Filling method and device of digital circuit, storage medium and electronic equipment

Abstract

The invention relates to a digital circuit filling method and device, a storage medium and electronic equipment, and relates to the technical field of semiconductor packaging, and the method comprises the steps: firstly obtaining the boundary information of a layout region of a digital circuit; then stretching and translating each voltage domain in the digital circuit based on the boundary information; based on the processed voltage domain, iteratively calculating the width of a filling unit and the width of a contact point unit required by the digital circuit to obtain a target filling result; and sequentially inserting a filling unit and a contact point unit into the digital circuit according to the target filling result. According to the technical scheme, through the space optimization strategy based on the voltage domain and the automatic filling process, it is ensured that the target filling result meets the design rule, meanwhile, space optimal utilization is achieved, the layout design period is effectively shortened, and meanwhile the overall efficiency and quality of integrated circuit design are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a filling method, device, storage medium, and electronic device for a digital circuit. Background Art

[0002] In the layout design of digital circuits, it is usually necessary to insert taps and fillers to meet design rules and optimize performance.

[0003] Currently, designers usually rely on manual work to complete the filling of contacts and fillers in digital circuits. This method is not only time-consuming and labor-intensive, but also inefficient, greatly increasing the time cost of layout design. Summary of the Invention

[0004] In view of this, the present application provides a filling method, device, storage medium and electronic device for a digital circuit, the main purpose of which is to improve the technical problem in the current existing technology that the filling work of contact points and fillers is time-consuming, labor-intensive, and inefficient, which greatly increases the time cost of layout design.

[0005] In a first aspect, the present application provides a method for filling a digital circuit, comprising:

[0006] Obtaining boundary information of a layout area of ​​a digital circuit;

[0007] Based on the boundary information, each voltage domain in the digital circuit is stretched and translated;

[0008] Based on the processed voltage domain, a target filling result is obtained by iteratively calculating a width of a filling unit and a width of a contact point unit required by the digital circuit;

[0009] The filling unit and the contact point unit are sequentially inserted into the digital circuit according to the target filling result.

[0010] Optionally, the stretching and translating each voltage domain in the digital circuit based on the boundary information includes:

[0011] Get the first width of each voltage domain;

[0012] determining, according to the first width, a weight corresponding to each voltage domain during the stretching process;

[0013] Based on the boundary information, uniformly stretch each voltage domain according to the weight, and determine a second width of each voltage domain after stretching;

[0014] Each voltage domain is shifted according to the second width.

[0015] Optionally, before obtaining the boundary information of the layout area of ​​the digital circuit, the method further includes:

[0016] Acquire a two-dimensional array composed of functional units in the digital circuit;

[0017] The two-dimensional array is divided into a plurality of sub-arrays according to a voltage domain of the digital circuit.

[0018] Optionally, obtaining a target filling result by iteratively calculating a width of a filling unit and a width of a contact point unit required by the digital circuit based on the processed voltage domain includes:

[0019] In each voltage domain, each row of the two-dimensional matrix is ​​used as a minimum processing unit to calculate the fillable width of the current row;

[0020] Determining a layout space available for the filling unit and the contact point unit according to the fillable width;

[0021] Based on the layout space, widths of the filling unit and the contact point unit are iteratively adjusted.

[0022] Optionally, the iteratively adjusting the widths of the filling unit and the contact point unit based on the layout space includes:

[0023] Determining, based on a current width of the filling cell and a current width of the contact point cell, whether all cells in the current row can be filled into the layout space while satisfying process design rules;

[0024] If all cells in the current row cannot be filled into the layout space while satisfying the process design rules, the width of the filling cell and the width of the contact point cell are further adjusted.

[0025] Optionally, the method further includes:

[0026] During each iteration, the number and positions of the contact point units are dynamically adjusted based on the placement order of the functional units, wherein the interval between adjacent contact point units is greater than a preset interval value.

[0027] Optionally, after sequentially inserting the filling unit and the contact point unit into the digital circuit according to the target filling result, the method further includes:

[0028] Verifying the filling layout of the digital circuit according to process design rules based on the boundary information and the spacing between the cells;

[0029] If the filling layout of the digital circuit does not meet the process design rules, the positions and quantities of the filling units and / or the contact point units are readjusted, and the filling process is re-executed.

[0030] In a second aspect, the present application provides a filling device for a digital circuit, comprising:

[0031] an acquisition module configured to acquire boundary information of a layout area of ​​a digital circuit;

[0032] A processing module is configured to perform stretching and translation processing on each voltage domain in the digital circuit based on the boundary information;

[0033] a calculation module configured to iteratively calculate the width of the filling unit and the width of the contact point unit required by the digital circuit based on the processed voltage domain to obtain a target filling result;

[0034] The filling module is configured to sequentially insert the filling unit and the contact point unit into the digital circuit according to the target filling result.

[0035] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the method described in the first aspect when the computer program is executed by a processor.

[0036] In a fourth aspect, the present application provides an electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor implements the method described in the first aspect when executing the computer program.

[0037] By means of the above technical solution, the present application provides a filling method, device, storage medium and electronic device for a digital circuit. Specifically, first, the boundary information of the layout area of ​​the digital circuit is obtained; then, based on the boundary information, each voltage domain in the digital circuit is stretched and translated; then, based on the processed voltage domain, the width of the filling unit and the width of the contact point unit required by the digital circuit are iteratively calculated to obtain the target filling result; according to the target filling result, the filling unit and the contact point unit are sequentially inserted into the digital circuit. Compared with the current existing technology, the present application uses a space optimization strategy based on the voltage domain and an automated filling process. On the basis of automatic layout, the voltage domain is stretched and translated in combination with the boundary information, making the filling space more reasonable and regular; and by iteratively calculating the width and number of each row of filling units and contact point units, it is ensured that the target filling result meets the design rules while achieving optimal space utilization, thereby effectively shortening the layout design cycle and improving the overall efficiency and quality of integrated circuit design.

[0038] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 A schematic flow chart of a method for filling a digital circuit provided in an embodiment of the present application is shown;

[0042] Figure 2 A schematic flow chart of another method for filling a digital circuit provided in an embodiment of the present application is shown;

[0043] Figure 3 A schematic diagram showing an application example provided by an embodiment of the present application is shown;

[0044] Figure 4 A schematic diagram showing an application example provided by an embodiment of the present application is shown;

[0045] Figure 5 A structural schematic diagram of a filling device for a digital circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0046] In order to more clearly understand the above-mentioned objectives, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0047] In order to improve the technical problem that the filling work of contact points and fillers in the existing technology is time-consuming and labor-intensive, and inefficient, which greatly increases the time cost of layout design, this embodiment provides a filling method for digital circuits, such as Figure 1 As shown, the method includes:

[0048] Step 101: Obtain boundary information of a layout area of ​​a digital circuit.

[0049] For example, boundary information is usually defined based on the overall size of the chip, functional module division and top-level layout planning, and can usually include the physical size of the entire digital circuit (such as the length and width of the rectangular area), the specific division range of the voltage domain, the non-routable area (such as the area occupied by macro units, power supply networks, etc.) and the constraints on edge spacing, alignment, etc. in the design rules.

[0050] Step 102: Based on the boundary information, stretch and translate each voltage domain in the digital circuit.

[0051] In some examples, a voltage threshold refers to a circuit region with the same supply voltage. A voltage threshold contains multiple standard cells (STD cells), which maintain the same height but may vary in width. When processing a voltage threshold, a two-dimensional matrix representing the layout of all standard cells in the region is input, where each element corresponds to a standard cell. Each row of this two-dimensional matrix represents a horizontally arranged group of standard cells in the physical layout and serves as the basic processing unit in the autofill flow.

[0052] For example, the stretching operation is usually used to adjust the height or spacing of the standard cell rows within the voltage domain to better adapt it to the alignment requirements of the overall layout or the power network wiring requirements. At the same time, it can increase the blank area that can be used to insert taps and fillers without affecting the logical function, thereby improving the integrity of the power network; while the translation operation is to move the entire voltage domain horizontally or vertically to avoid the non-routable area or maintain a reasonable relative position relationship with other voltage domains, which helps to avoid the existing non-routable areas in the chip, so that taps and fillers can be laid out in a more continuous and regular space, reducing filling difficulties or layout conflicts caused by irregular boundaries.

[0053] Step 103 : Based on the processed voltage domain, the width of the filling unit and the width of the contact point unit required by the digital circuit are iteratively calculated to obtain a target filling result.

[0054] In some examples, the number and location of fill cells and contacts can be dynamically adjusted based on the remaining blank space in each row and the design rule restrictions on cell spacing and density, ensuring that power network integrity and manufacturing process requirements are met. The resulting target fill result strikes a balance between space utilization efficiency, electrical performance, and design rule compliance, providing a reliable foundation for subsequent physical verification and routing processes.

[0055] Step 104: insert filling cells and contact point cells in sequence into the digital circuit according to the target filling result.

[0056] This process ensures that the remaining space in each row is properly utilized while meeting design rules, ensuring the integrity of the power network and the reliability of electrical connections. This orderly insertion not only improves chip area utilization but also enhances circuit stability and manufacturability.

[0057] This embodiment first obtains the boundary information of the layout area of ​​the digital circuit; then, based on the boundary information, stretches and translates each voltage domain in the digital circuit; then, based on the processed voltage domain, it iteratively calculates the width of the filler unit and the width of the contact point unit required for the digital circuit to obtain the target fill result; according to the target fill result, the filler unit and the contact point unit are sequentially inserted into the digital circuit. Compared with the current existing technology, this embodiment uniformly stretches the different voltage domains in the digital circuit within the layout boundary to optimize overall space utilization and improve subsequent fill efficiency; then, within a single voltage domain, based on a two-dimensional matrix composed of standard cells, each row is used as the minimum processing unit, and the total filler fill width required for each row is gradually calculated through a loop iteration method. Under the premise of meeting the design rules, a better automatic fill result is approached, and the global voltage domain layout adjustment and local fill optimization are effectively combined to improve the rationality of filler and tap insertion and layout quality.

[0058] Furthermore, as a refinement and extension of the above embodiment, in order to fully illustrate the specific implementation process of the method of this embodiment, this embodiment provides the following Figure 2 The specific method shown includes:

[0059] Step 201: Obtain boundary information of a layout area of ​​a digital circuit.

[0060] For example, the boundary information of the layout area of ​​the digital circuit can be extracted from the netlist or physical design tool (such as the Place and Route tool) and saved in the form of a data structure for subsequent layout filling, automatic insertion of filler / tap units, contact point layout and DRC (design rule checking) processes.

[0061] Step 202: Based on the boundary information, stretch and translate each voltage domain in the digital circuit.

[0062] Optionally, step 202 may specifically include: obtaining a first width of each voltage domain; determining the corresponding weight of each voltage domain during the stretching process based on the first width; based on the boundary information, uniformly stretching each voltage domain according to the weight, and determining the second width of each voltage domain after stretching; and performing translation processing on each voltage domain based on the second width.

[0063] The first width is the initial width of each voltage domain, and the second width is the width of each voltage domain after being uniformly stretched.

[0064] For example, when processing a design with multiple voltage domains, it is first necessary to adjust the position and size of each voltage domain according to the current physical design boundary (PRBoundary). First, the boundary of the current layout can be identified, and then the width of each voltage domain is used as a weight to stretch and translate it. This adjustment allows each voltage domain to expand or shrink evenly in a certain proportion, while ensuring that their relative positions in the entire layout are properly maintained. This process can not only adapt to new layout restrictions, but also make the space allocation within the voltage domain more reasonable, thereby providing a wider and optimized space for the subsequent arrangement of standard cells, filling cells, and contact point cells, so that they can fill the entire layout area as much as possible, thereby improving the overall efficiency and performance of the chip design.

[0065] For example, Figure 3 As shown in the figure, before stretching, voltage domains A, B, C, D, and E are arranged at specific spacings d1 to d5, forming a compact layout. To optimize space utilization, voltage domain A can be stretched using its initial layout width as a weight, increasing its width by D1. After stretching, the width of voltage domain A increases significantly, simultaneously expanding the entire layout boundary and adjusting the spacing between adjacent voltage domains. This not only increases the total width of the layout area but also provides more space for subsequent tap and filler cell filling, enabling more efficient circuit layout design.

[0066] Step 203 : In each voltage domain, each row of the two-dimensional matrix is ​​used as a minimum processing unit to calculate the fillable width of the current row.

[0067] For example, in the process of automatically filling tap and filler cells, in order to ensure that the set boundaries are not exceeded and the design rule requirements are met, the width of the current row to be filled needs to be accurately calculated. The width is equal to the total width of the current row minus the sum of the widths occupied by the arranged standard cells.

[0068] Optionally, the method of this embodiment may specifically include: obtaining a two-dimensional array composed of functional units in a digital circuit; and dividing the two-dimensional array into a plurality of sub-arrays according to a voltage domain of the digital circuit.

[0069] For example, a two-dimensional array of functional units (such as standard cells) is first obtained. This array reflects the arrangement and layout of all logic units in the circuit on the chip plane. Then, based on the voltage domain information defined in the circuit, the entire two-dimensional array is divided along the boundaries of different voltage domains to form multiple sub-arrays. Each sub-array corresponds to a specific voltage domain and contains all functional units within that voltage domain.

[0070] Step 204: Determine the layout space available for filling cells and contact point cells based on the fillable width.

[0071] For example, the available fill width determines the number of filler and tap units that can be inserted and their arrangement and combination. At the same time, space must be reserved for contact points to ensure that power or signals can be properly connected to the relevant network. Since contact points usually have specific position and density requirements, their layout may further limit the arrangement of filler units. Therefore, when determining the layout space, the algorithm needs to reasonably allocate the space ratio occupied by filler, tap, and contact units while meeting the design rules, and optimize their relative positions to maximize space utilization and optimize electrical performance.

[0072] In some examples, considering the restrictions on the distance between taps in the design rules, that is, the tap spacing in two horizontal directions cannot be greater than a certain set value, but is allowed to be smaller than this value, an iterative optimization method can be used to fill the blank area as much as possible.

[0073] Step 205 : Based on the layout space, iteratively adjust the widths of the filling units and the contact point units to obtain a target filling result.

[0074] For example, within a while loop, the algorithm repeatedly calculates and adjusts the placement of filler and tap cells until an optimal solution is found. This not only maximizes space utilization but also ensures that the circuit design meets electrical requirements, such as power integrity and signal integrity. This effectively addresses the space optimization challenges encountered during automatic layout while also meeting the design rule requirements for tap and filler cell distribution.

[0075] Optionally, step 205 may specifically include: based on the current width of the filling unit and the current width of the contact point unit, determining whether all the units in the current row can be filled into the layout space while satisfying the process design rules; if all the units in the current row cannot be filled into the layout space while satisfying the process design rules, then continue to adjust the width of the filling unit and the width of the contact point unit.

[0076] For example, in the initial state, an initial total fill width and the width of the tap cell can be set for the filler cell, and based on this input, it is calculated whether all cells in the current row (including std cells, tap cells, and filler cells) can be correctly placed within the specified voltage threshold range. If the calculation result shows that the position of the last cell in the current row exceeds the set boundary, it means that the layout scheme under the existing input conditions is not feasible, and the input value needs to be adjusted, usually by reducing the total fill width of the filler cell, and then calculating and judging again. In addition, since the placement of the tap cell must strictly comply with the design rules, that is, the distance between two taps must not exceed a certain value, the number and position of the taps will be affected by the placement order of the std cells.

[0077] For example, by iteratively optimizing input parameters and re-evaluating layout results, we can gradually approach an optimal solution that satisfies all design constraints. This process not only ensures that the circuit design meets electrical requirements such as signal integrity and power stability, but also effectively solves space utilization issues and improves overall layout efficiency.

[0078] Optionally, the method of this embodiment may specifically include: in each iteration process, dynamically adjusting the number and positions of the contact point units based on the placement order of the functional units, wherein the interval between adjacent contact point units is greater than a preset interval value.

[0079] For example, after the current row is filled, the distribution of the arranged functional units is analyzed, and the positions that can be used to insert or adjust contact units can be identified. According to the set spacing rules, the number of contacts can be dynamically increased or decreased or their positions can be moved to avoid excessive density or violation of spacing constraints, thereby improving the compliance of the layout.

[0080] Step 206: insert filling cells and contact point cells in sequence into the digital circuit according to the target filling result.

[0081] In some examples, fillers and taps can be inserted sequentially between standard cells in the current row or into the blank area at the end, based on the calculated width and number. This ensures that the spacing between taps does not exceed the preset maximum allowable distance to maintain power stability and signal integrity. Contact cells are then inserted at appropriate locations to establish electrical connections between the metal layer and the device.

[0082] For example, the insertion process of the filling unit and the contact point unit needs to ensure that the spacing between adjacent contact points is greater than a set minimum spacing to avoid manufacturing or electrical problems caused by excessive density.

[0083] Optionally, the method of this embodiment may specifically include: verifying the process design rules of the filling layout of the digital circuit based on the boundary information and the spacing between each unit; if the filling layout of the digital circuit does not meet the process design rules, readjusting the position and number of the filling unit and / or contact point unit, and re-executing the filling process.

[0084] For example, if the filling cells or contact point cells in certain areas are too dense or not spaced enough, the position and number of these cells need to be readjusted.

[0085] For example, the position of the tap / filler can be moved, the number of contacts can be increased or decreased, or the filling strategy of the blank area can be reallocated. After the adjustment is completed, the filling process is re-executed and the process design rule (DRC) verification is performed again until all layouts comply with the process design rules.

[0086] Illustratively, the core of the strategy for filling tap and filler cells in the digital circuit layout in this embodiment is to separate the layout of standard cells from the subsequent tap and filler filling process. The first step is the preliminary layout of the standard cells, which focuses on meeting the circuit functional requirements and basic physical design constraints. After completing this preliminary layout, a post-processing algorithm is used to analyze the laid out standard cell areas to identify the locations where taps and fillers need to be filled. This stage places special emphasis on checking and calculating the fillable width of each row according to the design rules to ensure that the spacing between taps meets specific requirements and does not exceed the voltage domain boundary. By iteratively adjusting the filling width of fillers and taps, and dynamically adjusting their number and position based on the actual placement of standard cells, the goal of meeting all electrical and physical design rules and using space as efficiently as possible is ultimately achieved.

[0087] In some examples, such as Figure 4As shown, first, a sequence containing only STD cells is input and divided into multiple groups based on the voltage domain boundaries. Then, based on the current physical design boundaries, each voltage domain is evenly stretched and translated with the voltage domain width as the weight to ensure that each voltage domain obtains a new position and range. Then, each voltage domain is looped through, and the cells in the same voltage domain are formed into a two-dimensional array. The fillable width of each row is checked row by row, while considering that the spacing between taps must meet specific circuit design rules. After the initial filler and tap widths are given, a while loop is used to iterate and calculate whether these cells can be legally filled within the voltage domain range. If the filler width of the current row is greater than 0, the filler and tap are filled in sequence, and the position of the last cell in the last row is checked to see if it exceeds the voltage domain boundary. If it does, the filler width is adjusted and reduced by a value equal to the width of the excess portion until the optimal or better filling solution is found, and the target filling result is output.

[0088] In some examples, users can first click the "Start Layout" function to initiate the first stage of the automatic layout process. During this stage, the system generates an initial layout result, which includes the placement of standard cells but does not yet include filler and tap cells. After the initial layout is completed, the user enters the automatic filling process of taps and fillers by clicking the corresponding function menu and setting the relevant parameters. The system automatically calculates and inserts the appropriate tap and filler cells based on the set design rules, voltage domain boundaries, and the distribution of standard cells in each row, and outputs the complete automatic filling result.

[0089] Compared with the current existing technology, this embodiment evenly stretches different voltage domains in the digital circuit within the layout boundary to optimize overall space utilization and improve subsequent filling efficiency; then, within a single voltage domain, based on a two-dimensional matrix composed of standard cells, each row is used as the minimum processing unit, and the total filler filling width required for each row is gradually calculated through a loop iteration method, approaching a better automatic filling result while meeting the design rules. It effectively combines global voltage domain layout adjustment with local filling optimization, and improves the rationality of filler and tap insertion and layout quality.

[0090] Further, as Figure 1 The specific implementation of the method shown in this embodiment provides a filling device for a digital circuit, such as Figure 5 As shown, the device includes: an acquisition module 31, a processing module 32, a calculation module 33, and a filling module 34.

[0091] An acquisition module 31 is configured to acquire boundary information of a layout area of ​​a digital circuit;

[0092] A processing module 32 is configured to perform stretching and translation processing on each voltage domain in the digital circuit based on the boundary information;

[0093] The calculation module 33 is configured to obtain a target filling result by iteratively calculating the width of the filling unit and the width of the contact point unit required by the digital circuit based on the processed voltage domain;

[0094] The filling module 34 is configured to sequentially insert the filling unit and the contact point unit into the digital circuit according to the target filling result.

[0095] In some examples, the processing module 32 is specifically configured to obtain a first width of each voltage domain; determine a weight corresponding to each voltage domain during the stretching process based on the first width; based on the boundary information, uniformly stretch each voltage domain according to the weight, and determine a second width of each voltage domain after stretching; and perform translation processing on each voltage domain based on the second width.

[0096] In some examples, the calculation module 33 is specifically configured to obtain a two-dimensional array composed of functional units in the digital circuit; and divide the two-dimensional array into multiple sub-arrays according to the voltage domain of the digital circuit.

[0097] In some examples, the calculation module 33 is further configured to calculate the fillable width of the current row within each voltage domain, using each row of the two-dimensional matrix as the minimum processing unit; determine the layout space available for the filling unit and the contact point unit based on the fillable width; and iteratively adjust the width of the filling unit and the contact point unit based on the layout space to obtain the target filling result.

[0098] In some examples, the calculation module 33 is further configured to determine, based on the current width of the filling unit and the current width of the contact point unit, whether all the units in the current row can be filled into the layout space while satisfying the process design rules; if all the units in the current row cannot be filled into the layout space while satisfying the process design rules, then continue to adjust the width of the filling unit and the width of the contact point unit.

[0099] In some examples, the calculation module 33 is further configured to dynamically adjust the number and position of the contact point units based on the placement order of the functional units during each iteration, wherein the interval between adjacent contact point units is greater than a preset interval value.

[0100] In some examples, the filling module 34 is further configured to verify the process design rules of the filling layout of the digital circuit based on the boundary information and the spacing between each unit; if the filling layout of the digital circuit does not meet the process design rules, the position and number of the filling unit and / or the contact point unit are readjusted, and the filling process is re-executed.

[0101] Based on the above Figure 1 and Figure 2 The method shown in FIG. 1 is a method for performing the above-mentioned steps. Accordingly, this embodiment further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program can realize the above-mentioned steps. Figure 1 and Figure 2 The method shown.

[0102] Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, USB flash drive, mobile hard disk, etc.), and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of the present application.

[0103] Based on the above Figure 1 and Figure 2 The method shown, and Figure 5 In order to achieve the above-mentioned purpose, the embodiment of the present application further provides an electronic device, which may include a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to achieve the above-mentioned Figure 1 and Figure 2 The method shown.

[0104] Optionally, the physical device may further include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a Wi-Fi module, and the like. The user interface may include a display, an input unit such as a keyboard, and the like. The optional user interface may also include a USB interface, a card reader interface, and the like. The network interface may optionally include a standard wired interface, a wireless interface (such as a Wi-Fi interface), and the like.

[0105] Those skilled in the art will understand that the above-mentioned physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or a combination of certain components, or different component arrangements.

[0106] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the physical device, supporting the execution of information processing programs and other software and / or programs. The network communication module is used to enable communication between components within the storage medium, as well as with other hardware and software within the physical information processing device.

[0107] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present application can be implemented by means of software plus the necessary general hardware platform, or by hardware. By applying the solution of this embodiment, the different voltage domains in the digital circuit are evenly stretched within the layout boundary to optimize the overall space utilization and improve the subsequent filling efficiency; then, within a single voltage domain, based on the two-dimensional matrix composed of standard cells, each row is used as the minimum processing unit, and the total filler filling width required for each row is gradually calculated through a loop iteration method. Under the premise of meeting the design rules, a better automatic filling result is approached, which effectively combines the global voltage domain layout adjustment with the local filling optimization, and improves the rationality of filler and tap insertion and the layout quality.

[0108] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article or device. In the absence of further limitations, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0109] The above are merely specific embodiments of the present application, which are intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but rather is intended to conform to the widest scope consistent with the principles and novel features of the present application.

Claims

1. A filling method for a digital circuit, characterized in that: include: Obtaining boundary information of a layout area of ​​a digital circuit; Based on the boundary information, each voltage domain in the digital circuit is stretched and translated; Based on the processed voltage domain, a target filling result is obtained by iteratively calculating a width of a filling unit and a width of a contact point unit required by the digital circuit; The filling unit and the contact point unit are sequentially inserted into the digital circuit according to the target filling result.

2. The method according to claim 1, characterized in that The stretching and translating each voltage domain in the digital circuit based on the boundary information includes: Get the first width of each voltage domain; determining, according to the first width, a weight corresponding to each voltage domain during the stretching process; Based on the boundary information, uniformly stretch each voltage domain according to the weight, and determine a second width of each voltage domain after stretching; Each voltage domain is shifted according to the second width.

3. The method according to claim 1, characterized in that Before obtaining the boundary information of the layout area of ​​the digital circuit, the method further includes: Acquire a two-dimensional array composed of functional units in the digital circuit; The two-dimensional array is divided into a plurality of sub-arrays according to a voltage domain of the digital circuit.

4. The method according to claim 3, characterized in that The step of obtaining a target filling result by iteratively calculating a width of a filling unit and a width of a contact point unit required by the digital circuit based on the processed voltage domain includes: In each voltage domain, each row of the two-dimensional matrix is ​​used as a minimum processing unit to calculate the fillable width of the current row; Determining a layout space available for the filling unit and the contact point unit according to the fillable width; Based on the layout space, the widths of the filling unit and the contact point unit are iteratively adjusted to obtain the target filling result.

5. The method according to claim 4, characterized in that The iteratively adjusting the widths of the filling unit and the contact point unit based on the layout space includes: Determining, based on a current width of the filling cell and a current width of the contact point cell, whether all cells in the current row can be filled into the layout space while satisfying process design rules; If all cells in the current row cannot be filled into the layout space while satisfying the process design rules, the width of the filling cell and the width of the contact point cell are further adjusted.

6. The method according to claim 4, characterized in that The method further comprises: During each iteration, the number and positions of the contact point units are dynamically adjusted based on the placement order of the functional units, wherein the interval between adjacent contact point units is greater than a preset interval value.

7. The method according to claim 1, characterized in that After sequentially inserting the filling unit and the contact point unit into the digital circuit according to the target filling result, the method further includes: Verifying the filling layout of the digital circuit according to process design rules based on the boundary information and the spacing between the cells; If the filling layout of the digital circuit does not meet the process design rules, the positions and quantities of the filling units and / or the contact point units are readjusted, and the filling process is re-executed.

8. A filling device for a digital circuit, characterized in that: include: an acquisition module configured to acquire boundary information of a layout area of ​​a digital circuit; A processing module is configured to perform stretching and translation processing on each voltage domain in the digital circuit based on the boundary information; a calculation module configured to iteratively calculate the width of the filling unit and the width of the contact point unit required by the digital circuit based on the processed voltage domain to obtain a target filling result; The filling module is configured to sequentially insert the filling unit and the contact point unit into the digital circuit according to the target filling result.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

10. An electronic device comprising a storage medium, a processor, and a computer program stored in the storage medium and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

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