Semiconductor device, manufacturing method thereof and electronic equipment
By using dielectric isolation layers made of different materials for selective etching in semiconductor devices, the problem of electrode damage during the etching process is solved, device performance is improved, and the process flow is simplified.
Patent Information
- Application Number
- CN202510882424.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-27
- Publication Date
- 2025-09-16
AI Technical Summary
During the etching process, the hole etching of the back-side source/drain contact structure is likely to damage the source/drain, affecting the performance of the semiconductor device.
A first dielectric isolation layer and a second dielectric isolation layer made of different materials are used to form the second dielectric isolation layer on the first surface of the base layer through selective etching technology, and a through hole is etched on the second surface of the base layer to avoid damage to the electrode.
The damage to the electrodes caused by etching is reduced, the performance of the semiconductor device is improved, the process flow is simplified, and time is saved.
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Figure CN120657000A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductors, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art
[0002] In the process of manufacturing semiconductor devices, in order to reduce the number of circuits on the front side of the wafer, free up space on the front side of the wafer, and thus reduce the size of the device, a backside source / drain contact (BSCON) structure can be set in the wafer to transfer the power supply network to the back side of the wafer where there is sufficient space resources, and interconnect the front and back sides of the wafer.
[0003] In related technology, a bottom dielectric isolation (BDI) layer is created during the front-side process flow. This layer improves the overlay process window when etching holes for back-side source / drain contacts. However, this process can easily damage the source / drain (S / D) electrodes, thereby impacting semiconductor device performance.
[0004] Therefore, how to solve the above technical problems should be the focus of those skilled in the art. Summary of the Invention
[0005] The present application discloses a semiconductor device and a manufacturing method thereof, and an electronic device, which are used to solve the problem of damage to electrodes during the etching process and improve the performance of the semiconductor device.
[0006] In a first aspect, the present application provides a method for manufacturing a semiconductor device, comprising:
[0007] Obtaining a basic structure of a semiconductor device, the basic structure consisting of a base layer, a first dielectric isolation layer, and a plurality of channel structures; wherein the first dielectric isolation layer is located on a first surface of the base layer, each of the channel structures is partially located on a surface of the first dielectric isolation layer facing away from the base layer, and electrode grooves are distributed between adjacent channel structures and the first dielectric isolation layer;
[0008] forming a second dielectric isolation layer on the first surface of the base layer; the first dielectric isolation layer and the second dielectric isolation layer are made of different materials so as to achieve selective etching of the first dielectric isolation layer and the second dielectric isolation layer;
[0009] An electrode material is grown in the electrode groove to form an electrode; the active area includes the electrode, the first dielectric isolation layer, the second dielectric isolation layer, and the plurality of channel structures; the electrode includes a first electrode that requires metal interconnection on one side of the second surface of the base layer; the second surface and the first surface are two opposite surfaces of the base layer;
[0010] thinning the base layer;
[0011] Etching the thinned base layer and the second dielectric isolation layer from the second surface of the base layer to form a through hole; the through hole corresponds to the first electrode;
[0012] An electrode contact structure is grown in the through hole; the electrode contact structure is in contact with the first electrode.
[0013] The manufacturing method of the semiconductor device of the present application, after obtaining the basic structure of the device, forms a second dielectric isolation layer on the first surface of the base layer, then forms the electrode. After completing the front-side process, the base layer is thinned, and then the second dielectric isolation layer is etched on the second surface of the thinned base layer to form a through hole for growing the electrode contact structure. The second dielectric isolation layer is made of a different material from the first dielectric isolation layer and the base layer, and the second dielectric isolation layer can act as an etching stop. The second dielectric isolation layer is grown on the first surface of the base layer, and the method of etching the second dielectric isolation layer from the second surface of the base layer is very simple and convenient, and does not affect the production of components such as the electrode. The first dielectric isolation layer and the second dielectric isolation layer are two different material layers located on the first surface of the base layer. When etching to form the through hole, the first dielectric isolation layer can reduce the alignment accuracy requirements and improve the photolithography process window. At the same time, because the second dielectric isolation layer is made of different materials from the first dielectric isolation layer, the electrode, and the base layer, selective etching of the second dielectric isolation layer can be achieved, reducing the damage caused by etching to the electrode, thereby improving the performance of the semiconductor device.
[0014] In a possible implementation, forming the second dielectric isolation layer on the first surface of the base layer includes:
[0015] The second dielectric isolation layer is directly grown on the first surface of the base layer by adopting a topologically selective atomic layer deposition method.
[0016] In this embodiment, the second dielectric isolation layer is directly formed on the first surface of the base layer and the upper surface of the channel structure. Only one step is required to grow the second dielectric layer on the first surface of the base layer, which can reduce process steps and save time.
[0017] In a possible implementation, forming the second dielectric isolation layer on the first surface of the base layer includes:
[0018] growing the second dielectric isolation layer on the surface of the basic structure;
[0019] The second dielectric isolation layer located on a side surface of each of the trench structures is removed.
[0020] In this embodiment, the second dielectric isolation layer is formed in two steps. First, the second dielectric isolation layer is formed on the entire surface, and then the second dielectric isolation layer located on the side of the channel structure is removed. It is possible to achieve selective growth of the second dielectric isolation layer on the front side of the substrate by relying solely on the deposition process or deposition plus EPI pretreatment.
[0021] In a possible implementation manner, growing the second dielectric isolation layer on the surface of the basic structure includes:
[0022] Plasma is injected into the surface of the basic structure, so that the plasma diffuses on the surface of the basic structure to form the second dielectric isolation layer.
[0023] In this embodiment, plasma diffusion is used. Due to the process characteristics, the thickness of the second dielectric isolation layer located on the side of the channel structure can be made thinner than the thickness of the second dielectric isolation layer located on the first surface of the base layer, making it easy to remove it with high selectivity. Therefore, the process flow can be simplified and the process window can be improved. It is possible to achieve selective growth of the second dielectric isolation layer located on the first surface of the base layer by relying solely on the diffusion process or diffusion plus EPI (epitaxial) pretreatment.
[0024] In a possible implementation manner, growing the second dielectric isolation layer on the surface of the basic structure includes:
[0025] A second dielectric isolation layer is deposited on the surface of the basic structure.
[0026] In this embodiment, the second dielectric isolation layer is formed by deposition, which is a simple method.
[0027] In a possible implementation manner, growing the second dielectric isolation layer on the surface of the basic structure includes:
[0028] The second dielectric isolation layer is grown on the surface of the basic structure by topologically selective atomic layer deposition; wherein the quality of the second dielectric isolation layer located on the side of each of the channel structures and the first dielectric isolation layer is different from the quality of the second dielectric isolation layer located on the first surface of the base layer.
[0029] This embodiment utilizes topologically selective atomic layer deposition (ALD). Due to process characteristics, the thickness of the second dielectric isolation layer located on the sides of the channel structure can be made thinner than that located on the first surface of the substrate layer. Furthermore, the quality of the second dielectric isolation layer located on the sides of the channel structure is inferior to that of the second dielectric isolation layer located on the first surface of the substrate layer, making subsequent removal of the second dielectric isolation layer located on the sides of the channel structure easier. Furthermore, this embodiment makes it possible to achieve selective growth of the second dielectric isolation layer on the first surface of the substrate layer through deposition alone or deposition plus epitaxial growth (EPI) pretreatment.
[0030] In a possible implementation, the thickness of the second dielectric isolation layer located on the side of the channel structure is smaller than the thickness of the second dielectric isolation layer located on the first surface of the base layer.
[0031] In this embodiment, the thickness of the second dielectric isolation layer on the side of the channel structure is smaller than the thickness of the second dielectric isolation layer on the first surface of the base layer, making it easier to remove the second dielectric isolation layer on the side of the channel structure.
[0032] In a possible implementation, removing the second dielectric isolation layer located on a side of the trench structure includes:
[0033] An isotropic dry etching process is used to etch back the second dielectric isolation layer located on the side of each of the channel structures.
[0034] The dry etching process used in this embodiment has the characteristics of high etching precision and easy control, so that the removal of the second dielectric isolation layer on the side of the trench structure can be accurately controlled.
[0035] In a possible implementation, removing the second dielectric isolation layer located on a side of the trench structure includes:
[0036] An isotropic wet etching process is used to etch back the second dielectric isolation layer located on the side of each of the channel structures.
[0037] The wet etching process used in this embodiment has the characteristics of low cost and mild etching, thereby reducing the manufacturing process cost and reducing etching damage.
[0038] In a possible implementation, the critical dimension of the electrode contact structure away from the first electrode is larger than the critical dimension of the side close to the first electrode, and the critical dimension of the electrode contact structure away from the first electrode is larger than the critical dimension of the first electrode.
[0039] In this embodiment, the critical dimension of the electrode contact structure is larger than the critical dimension of the electrode, which can reduce the contact resistance and ease the etching difficulty.
[0040] In a possible implementation, after etching the thinned base layer and the second dielectric isolation layer from the second surface of the base layer to form a through hole, and before growing an electrode contact structure in the through hole, the method further includes:
[0041] growing a silicide layer in the through hole; the silicide layer is in contact with the first electrode;
[0042] Accordingly, an electrode contact structure is grown in the through hole; and the electrode contact structure is in contact with the first electrode, comprising:
[0043] An electrode contact structure is grown in the through hole and on the surface of the silicide; the electrode contact structure is in contact with the silicide layer.
[0044] In this embodiment, a silicide layer is grown between the electrode contact structure and the electrode, which can reduce the contact resistance between the electrode contact structure and the electrode.
[0045] In a possible implementation manner, when the base layer is a silicon substrate, after growing the electrode contact structure in the through hole, the method further includes:
[0046] The silicon substrate is removed by etching, and an insulating dielectric material is grown to form an insulating dielectric substrate.
[0047] In this embodiment, the base layer adopts an insulating dielectric substrate, which can reduce the K value and leakage of the semiconductor device.
[0048] In a possible implementation, etching the thinned base layer and the second dielectric isolation layer from the second surface of the base layer to form the through hole includes:
[0049] depositing a hard mask layer on the second surface of the thinned base layer, and etching the hard mask layer to form a window;
[0050] Etching the base layer through the window to form a first through hole using a soft landing etching method, and stopping the etching on the surfaces of the first dielectric isolation layer and the second dielectric isolation layer;
[0051] The second dielectric isolation layer is etched to form a second through hole, and the etching stops at the surface of the first electrode; the first through hole and the second through hole constitute the through hole.
[0052] In this embodiment, a two-step etching method is used to form the through hole, which can reduce damage to devices such as electrodes and improve the uniformity of the manufacturing process.
[0053] In a possible implementation manner, the etching selectivity ratio of the second dielectric isolation layer to the first dielectric isolation layer, the base layer, and the shallow trench isolation is greater than 5:1.
[0054] In this embodiment, the second dielectric isolation layer has a high etching selectivity to the first dielectric isolation layer, the base layer and the shallow trench isolation, which can improve etching accuracy and reduce damage to the electrode.
[0055] In a second aspect, the present application provides a semiconductor device, comprising:
[0056] base layer;
[0057] an active area located on the first surface of the base layer, the active area comprising a plurality of channel structures, electrodes, a first dielectric isolation layer, and a second dielectric isolation layer, wherein the first dielectric isolation layer and the second dielectric isolation layer are located on the first surface of the base layer, and each of the channel structures is partially located on a surface of the first dielectric isolation layer facing away from the base layer; the electrodes are located on a surface of the second dielectric isolation layer facing away from the base layer and between adjacent channel structures and the first dielectric isolation layer, and no second dielectric isolation layer is provided between a first electrode of the electrodes and the base layer; the first dielectric isolation layer and the second dielectric isolation layer are made of different materials so as to achieve selective etching of the first dielectric isolation layer and the second dielectric isolation layer;
[0058] An electrode contact structure extends from the second surface of the base layer toward the first electrode and contacts the first electrode.
[0059] The semiconductor device in this embodiment has a second dielectric isolation layer disposed on the first surface of the substrate layer. When etching to form the through-holes where the electrode contact structures are located, the second dielectric isolation layer is etched from the second surface of the substrate layer without affecting the fabrication of components such as the electrodes. The first and second dielectric isolation layers, two different material layers, are both located on the first surface of the substrate layer. When etching to form the through-holes, the first dielectric isolation layer can reduce alignment accuracy requirements and increase the photolithography process window. Furthermore, because the second dielectric isolation layer, the first dielectric isolation layer, and the electrodes are made of different materials, selective etching of the second dielectric isolation layer is possible, reducing damage to the electrodes and thereby improving the performance of the semiconductor device.
[0060] In a possible implementation, the critical dimension of the electrode contact structure away from the first electrode is larger than the critical dimension of the side close to the first electrode, and the critical dimension of the electrode contact structure away from the first electrode is larger than the critical dimension of the electrode.
[0061] In this embodiment, the critical dimension of the electrode contact structure is larger than the critical dimension of the electrode, which can reduce the contact resistance.
[0062] In a possible implementation, the method further includes:
[0063] A shallow trench isolation is located in the base layer, and a side of the electrode contact structure away from the first electrode is flush with an end of the shallow trench isolation.
[0064] In this embodiment, the shallow trench isolation can play a self-alignment role during etching, thereby improving the photolithography process window, and at the same time has the effect of isolating devices to prevent mutual interference between devices.
[0065] In a possible implementation manner, the base layer includes a silicon substrate.
[0066] In this embodiment, the base layer adopts a silicon substrate, which does not require subsequent processing, can simplify the manufacturing process and reduce costs.
[0067] In a possible implementation manner, the base layer includes an insulating dielectric substrate.
[0068] In this embodiment, the base layer adopts an insulating dielectric substrate, which can reduce the K value and leakage of the device.
[0069] In a possible implementation, the method further includes:
[0070] A silicide layer is located between the first electrode and the electrode contact structure.
[0071] In this embodiment, a silicide layer is provided between the electrode and the electrode contact structure, which can reduce the contact resistance between the first electrode and the electrode contact structure.
[0072] In a third aspect, the present application provides a semiconductor device, which is manufactured using any of the above-mentioned methods for manufacturing a semiconductor device.
[0073] The semiconductor device in this embodiment has a second dielectric isolation layer disposed on the first surface of the substrate layer. When etching to form the through-holes where the electrode contact structures are located, the second dielectric isolation layer is etched from the second surface of the substrate layer without affecting the fabrication of components such as the electrodes. The first and second dielectric isolation layers, two different material layers, are both located on the first surface of the substrate layer. When etching to form the through-holes, the first dielectric isolation layer can reduce alignment accuracy requirements and increase the photolithography process window. Furthermore, because the second dielectric isolation layer, the first dielectric isolation layer, and the electrodes are made of different materials, selective etching of the second dielectric isolation layer is possible, reducing damage to the electrodes and thereby improving the performance of the semiconductor device.
[0074] In a fourth aspect, the present application provides an electronic device comprising the semiconductor device described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0075] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0076] Figure 1 A flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;
[0077] Figures 2 to 4 A flowchart of a manufacturing process of a basic structure provided in an embodiment of the present application;
[0078] Figure 5 A top view of a basic structure provided in an embodiment of the present application;
[0079] Figure 6 A top view of a basic structure after a second dielectric isolation layer is grown on the basic structure provided by an embodiment of the present application;
[0080] 7A to 15B A flowchart of a manufacturing process of a semiconductor device provided in an embodiment of the present application;
[0081] 16A to 17B A process flow chart for forming a second dielectric isolation layer on a first surface of a base layer provided in an embodiment of the present application;
[0082] Figures 18A to 19B The flowchart is a partial manufacturing process of a semiconductor device when an insulating dielectric substrate is used.
[0083] Description of reference numerals:
[0084] 10- basic structure;
[0085] 101 - base layer; 102 - first dielectric isolation layer; 103 - channel structure; 104 - electrode groove; 105 - SiGe layer; 106 - internal isolation layer; 107 - shallow trench isolation;
[0086] 1031 - first epitaxial layer; 1032 - second epitaxial layer;
[0087] 20- second dielectric isolation layer;
[0088] 30-electrode;
[0089] 301-first electrode; 302-second electrode;
[0090] 40-interlayer dielectric;
[0091] 50-through hole;
[0092] 501-first through hole; 502-second through hole
[0093] 60-silicide layer;
[0094] 70-electrode contact structure;
[0095] 80-insulating dielectric substrate;
[0096] 90-first interconnection layer;
[0097] 100-bonded slide;
[0098] 110-second interconnection layer;
[0099] 120 - hard mask layer. DETAILED DESCRIPTION
[0100] The manufacturing method in this application can be used in vertical interconnection scenarios in 3D integrated circuit architectures, mainly targeting logic, memory chips, and chiplets in advanced processes of 3nm and below. It can be used in semiconductor device structures such as GAA (Gate-All-Around) transistors, Fork sheets, and CFETs (Complementary Field-Effect Transistors).
[0101] Example 1
[0102] This embodiment provides a method for manufacturing a semiconductor device. Figure 1 、 Figure 4 , the method may include:
[0103] Step S101: Obtain a basic structure of a semiconductor device, wherein the basic structure 10 consists of a base layer 101, a first dielectric isolation layer 102, and a plurality of channel structures 103; wherein the first dielectric isolation layer 102 is located on a first surface of the base layer, each channel structure 103 is partially located on a surface of the first dielectric isolation layer 102 facing away from the base layer, and electrode grooves 104 are distributed between adjacent channel structures 103 and the first dielectric isolation layer.
[0104] In this application, the basic structure is the basic structure of the device obtained before forming the second dielectric isolation layer 20. The basic structure can be prepared by preparing a base layer, performing various processes on the base layer, forming the first dielectric isolation layer and the channel structure, and thus obtaining the basic structure.
[0105] See also Figure 4The base layer 101 may be a silicon substrate, including an etch stop layer, such as a SiGe layer, to control thinning accuracy. The material of the first dielectric isolation layer 102 is not specifically limited in this application and may be an insulating material. The material of the first dielectric isolation layer 102 includes, but is not limited to, any insulating material such as SiN, SiO, SiC, SiON, SiOC, SiCN, SiCON, SiBN, BN, BON, BCN, or BCON. The channel structure 103 includes a plurality of alternating first epitaxial layers 1031 (e.g., silicon layers) and a plurality of second epitaxial layers 1032 (e.g., SiGe layers).
[0106] Taking the semiconductor device as a GAA transistor as an example, the manufacturing process of the basic structure 10 includes: Figure 2 As shown, an electrode groove 104 is etched; Figure 3 As shown, the SiGe layer 105 at the bottom of the trench structure is then etched, and then an insulating dielectric material is deposited and etched back to form a first dielectric isolation layer 102. When etching the SiGe layer 105 at the bottom of the trench, etching is performed from the side of the SiGe layer 105, as shown in FIG. Figure 4 and Figure 5 As shown ( Figure 5 is a top view of the basic structure 10, Figures 2 to 4 for Figure 5 The cross-sectional view in the AA direction is shown), and then an inner spacer 106 is deposited and etched back to obtain the basic structure 10. The manufacturing process of the basic structure 10 is well known to those skilled in the art and will not be described in detail here.
[0107] Please refer to Figure 4 Part of the channel structure 103 is located on the surface of the first dielectric isolation layer 102 away from the base layer 101 , and the other part of the channel structure 103 is in direct contact with the base layer 101 (not shown in the figure).
[0108] For the convenience of description, the first surface of the base layer 101 (the surface where the first dielectric isolation layer is located) is referred to as the back surface, and correspondingly, the second surface of the base layer 101 opposite to the first surface is referred to as the front surface.
[0109] Step S102: forming a second dielectric isolation layer on the first surface of the base layer; the first dielectric isolation layer and the second dielectric isolation layer are made of different materials so that the first dielectric isolation layer and the second dielectric isolation layer can be selectively etched.
[0110] The material of the second dielectric isolation layer includes but is not limited to any insulating material such as SiN, SiO, SiC, SiON, SiOC, SiCN, SiCON, SiBN, BN, BON, BCN, and BCON.
[0111] like Figure 6 、 Figure 7A and Figure 7B As shown ( Figure 7A for Figure 6 Schematic diagram of the cross section in the AA direction, Figure 7B for Figure 6 Schematic diagram of the cross section in the BB direction, follow-up Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A All are cross-sectional diagrams in the AA direction. Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B 2 and 3. The second dielectric isolation layer can be formed by deposition. During the deposition process, a second dielectric isolation layer 20 is also formed on the upper surface of the channel structure 103. This part of the second dielectric isolation layer is removed in the subsequent process.
[0112] The present application does not limit the manufacturing process of the second dielectric isolation layer 20. For example, the second dielectric isolation layer 20 can be formed by the methods described in the following second and third embodiments.
[0113] Step S103: growing electrode material in the electrode groove to form an electrode; the active area includes an electrode, a first dielectric isolation layer, a second dielectric isolation layer, and multiple channel structures; the electrode includes a first electrode that needs to be metal-interconnected on one side of the second surface of the base layer.
[0114] like Figure 8A and Figure 8B As shown, the electrode 30 is the source / drain. Figure 6 The cross-sectional shape in the BB direction shown can be a hexagon or a rhombus, and the number of electrodes 30 includes two, which can be respectively referred to as a first electrode 301 and a second electrode 302. In one embodiment, one of the first electrode 301 and the second electrode 302 is a source electrode and the other is a drain electrode; in other embodiments, the first electrode 301 and the second electrode 302 can both be sources or both be drain electrodes. Figure 9A and Figure 9B As shown, after the electrode 30 is manufactured, the interlayer dielectric (ILD, full name InterlayerDielectric) 40 is manufactured according to the conventional process, and the upper surface of the channel structure 103 (the surface away from the first surface of the base layer 101, i.e. Figure 8A The second dielectric isolation layer 20 on the uppermost surface of the middle channel structure 103; Figure 10A and Figure 10B As shown, the contact hole preparation, MEOL (Middle End of Line) and BEOL (Back End of Line) and other structures on one side of the first surface are completed according to the existing conventional process flow to form a first interconnection layer 90. The contact hole preparation, MEOL and BEOL manufacturing process also includes the production of a gate in the channel structure area (not shown in the figure). Then, a bonding carrier 100 is formed on the first interconnection layer 90, wherein the second electrode 302 is metal-interconnected on one side of the first surface, the second electrode 302 is connected to the electrode contact structure in the first interconnection layer 90, and the electrode contact structure is connected to the metal layer, thereby realizing the metal interconnection of the second electrode 302 on the first surface side. A silicide layer 60 is formed on the upper surface of the second electrode 302 to reduce the contact resistance between the second electrode and the electrode contact structure in the first interconnection layer 90. For example, Figure 10A The middle electrode 30 may be a first electrode 301 .
[0115] Step S104: thinning the base layer.
[0116] For example Figure 10A and Figure 10B The structure in the embodiment is thinned, and the base layer 101 is thinned as shown in FIG. Figure 11A and Figure 11B As shown. For example, Figure 11A The middle electrode 30 may be a first electrode 301 .
[0117] Specifically, the substrate 101 can be thinned using grinding, CMP (Chemical Mechanical Polishing), dry or wet etching, and then stopped at the etch-stop layer 1011 of the substrate layer 101. Dry etching, wet etching, or CMP can then be used to stop at the surface of the STI (Shallow Trench Isolation) 107. The STI 107 is pre-fabricated in the substrate layer 101, and the specific fabrication process is well known to those skilled in the art. The shallow trench isolation 107 provides self-alignment during etching, increasing the lithography process window. It also isolates devices and prevents interference between them.
[0118] Step S105: etching the thinned base layer and the second dielectric isolation layer from the second surface of the base layer to form a through hole; the through hole corresponds to the first electrode.
[0119] As an implementation method, etching the thinned base layer and the second dielectric isolation layer from the second surface of the base layer to form the through hole includes:
[0120] Step S1051 : depositing a hard mask layer on the second surface of the thinned base layer, and etching the hard mask layer to form a window 1201 .
[0121] like Figure 12A and Figure 12B As shown, the hard mask layer 120 can be a composite layer of SiN layer and SiO layer or a TiN layer, etc., which is not limited in this embodiment. Figure 12A The middle electrode 30 may be a first electrode 301 .
[0122] The deposition process of the hard mask layer 120 includes but is not limited to chemical vapor deposition, sputtering deposition, etc.; the window on the hard mask layer 120 can be formed by spin-coating photoresist on the hard mask layer 120, then exposing and developing the photoresist, and then etching the hard mask layer 120 using the photoresist as a mask to form a window, and finally removing the photoresist.
[0123] Step S1052 : etching the base layer through the window to form a first through hole 501 by a soft landing etching method, and stopping the etching on the surfaces of the first dielectric isolation layer 102 and the second dielectric isolation layer 20 .
[0124] Soft landing etching is a technique used in semiconductor manufacturing to precisely control etching depth and avoid damaging underlying structures. In the present application, the soft landing etching method can gently stop at the surface of the second dielectric isolation layer 20 .
[0125] like Figure 12A and Figure 12B As shown, the etching in this step can be self-aligned based on the first dielectric isolation layer 102 and the shallow trench isolation 107, which can reduce the photolithography alignment accuracy requirements of the second surface of the base layer and improve the OVL (overlay alignment) process window. In addition, due to the presence of the first dielectric isolation layer 102, when the first through hole 501 is formed by etching in this step, it can also play a protective role to prevent damage to the channel structure.
[0126] Since the materials of the first dielectric isolation layer 102 and the second dielectric isolation layer 20 are different from the material of the base layer 101 , they can be selectively etched, so the etching can be stopped on the surface of the second dielectric isolation layer 20 .
[0127] Step S1053 : etching the second dielectric isolation layer 20 to form a second through hole 502 , and stopping the etching at the lower surface of the first electrode 301 ; the first through hole 501 and the second through hole 502 constitute a through hole 50 .
[0128] like Figure 13A and Figure 13B As shown, the second dielectric isolation layer 20 can block the etching of silicon and prevent the etching from damaging the first electrode 301. Since the material of the first electrode 301 is different from that of the second dielectric isolation layer 20, selective etching of the second dielectric isolation layer 20 can be achieved during etching, reducing the damage caused by etching to the first electrode 301, thereby improving the performance of the semiconductor device; at the same time, since the second dielectric isolation layer 20 and the first dielectric isolation layer 102 and the shallow trench isolation 107 are also made of different materials, damage to the first dielectric isolation layer 102 and the shallow trench isolation 107 can also be avoided. For example, Figure 13A The middle electrode 30 may be a first electrode 301 .
[0129] In this embodiment, a two-step etching method is used to form the through hole 50. First, a soft landing etching method is used to gently stop on the surface of the first dielectric isolation layer and the second dielectric isolation layer, and then the second dielectric isolation layer is selectively removed. This can reduce damage to devices such as the first electrode and improve the uniformity of the manufacturing process.
[0130] As an implementation method, the etching selectivity ratio of the second dielectric isolation layer 20 to the first dielectric isolation layer 102, the base layer 101 and the shallow trench isolation 107 is greater than 1, for example, it can be 5:1, so as to achieve high selective etching of the second dielectric isolation layer 20, improve etching accuracy, and reduce damage to the electrode.
[0131] Exemplarily, the etching selectivity ratio of the second dielectric isolation layer 20 to the first dielectric isolation layer 102 , the base layer 101 and the shallow trench isolation 107 may be 6:1, 7:1, 8:1, 9:1, 10:1 or the like.
[0132] Step S106: growing an electrode contact structure in the through hole; the electrode contact structure contacts the first electrode.
[0133] As an implementation method, before growing the electrode contact structure in the through hole, the method may further include:
[0134] Growing a silicide layer 60 in the through hole; the silicide layer 60 is in contact with the first electrode;
[0135] Accordingly, an electrode contact structure is grown in the through hole; and the electrode contact structure contacts the first electrode, including:
[0136] An electrode contact structure is grown in the through hole and on the surface of the silicide; the electrode contact structure is in contact with the silicide layer.
[0137] like Figure 14A and Figure 14B As shown, after the silicide layer 60 is grown, a metal material is filled in the through hole 50 to form an electrode contact structure 70. The material of the electrode contact structure 70 can be W, Co, Mo, Ru, etc., which is not specifically limited in this embodiment. Since the material of the electrode contact structure 70 is metal and the material of the electrode 30 is semiconductor material silicon, the Schottky barrier between the electrode contact structure 70 and the electrode 30 is relatively high, and the contact resistance is relatively large. The silicide layer 60 is located between the electrode contact structure 70 and the electrode 30. The work function of the silicide layer 60 is closer to that of silicon, which can reduce the barrier height, and thus reduce the contact resistance between the electrode contact structure 70 and the electrode 30. For example, Figure 14A The middle electrode 30 may be a first electrode 301 .
[0138] As an embodiment, the critical dimension of the electrode contact structure 70 away from the first electrode 301 is larger than the critical dimension of the side close to the first electrode 301, and the critical dimension of the electrode contact structure 70 away from the first electrode 301 is larger than the critical dimension of the first electrode 301, so as to reduce the contact resistance between the electrode contact structure 70 and the first electrode 301.
[0139] It should be noted that after the electrode contact structure 70 is grown, the process of manufacturing the BEOL structure on the second surface side of the base layer is completed according to the existing conventional process flow to form the second interconnection layer 110, such as Figure 15A and Figure 15B As shown. For example, Figure 15A The middle electrode 30 may be a first electrode 301 .
[0140] In the semiconductor device fabrication method of this embodiment, after obtaining the basic device structure, a second dielectric spacer is formed on the first surface of the substrate layer, followed by the electrode. After completing the front-side processing, the substrate layer is thinned, and the second dielectric spacer is etched on the second surface of the substrate layer to form a through hole for growing the electrode contact structure. The second dielectric spacer is made of a different material than the first dielectric spacer and the substrate layer, and thus serves as an etching stop. The second dielectric spacer is grown on the first surface of the substrate layer, and etching it from the second surface is simple and convenient, without affecting the fabrication of components such as the electrode. The first and second dielectric spacer layers, made of two different materials, are both located on the first surface of the substrate layer. When etching the through hole, the first dielectric spacer reduces alignment requirements and increases the photolithography process window. Furthermore, because the second dielectric spacer is made of different materials than the first dielectric spacer, the electrode, and the substrate layer, selective etching of the second dielectric spacer layer is achieved, minimizing damage to the electrode and thereby improving the performance of the semiconductor device. In addition, in this embodiment, by making an electrode contact structure on the second surface side of the substrate layer, the power supply network can be transferred to the second surface side, without occupying the active area of the first surface of the substrate layer, freeing up the space of the first surface of the substrate layer and reducing the voltage drop.
[0141] Example 2
[0142] Based on the above embodiments, this embodiment provides a method for forming a second dielectric isolation layer on the first surface of the base layer. This method may include: using topological selective atomic layer deposition to directly grow the second dielectric isolation layer on the first surface of the base layer.
[0143] In this embodiment, the second dielectric isolation layer is formed directly on the first surface of the base layer and the upper surface of the channel structure, without forming the second dielectric isolation layer on the side surfaces of the channel structure. This method only requires a single step to grow the second dielectric layer on the first surface of the base layer, which can reduce process steps and save time.
[0144] Example 3
[0145] Based on the above embodiments, this embodiment provides a method for forming a second dielectric isolation layer on the first surface of the base layer. The method may include:
[0146] Step S201: growing a second dielectric isolation layer on the surface of the basic structure.
[0147] like Figure 16A and Figure 16B As shown, a second dielectric isolation layer 20 is grown on the first surface of the base layer 101 and the upper surface and side surfaces of the channel structure 103 .
[0148] It should be noted that the present embodiment does not limit the growth method of the second dielectric isolation layer, and the method can be selected at will.
[0149] As an implementation method, growing a second dielectric isolation layer on the surface of the basic structure includes:
[0150] Plasma is injected into the surface of the basic structure so that the plasma diffuses on the surface of the basic structure to form a second dielectric isolation layer.
[0151] The plasma used may include N, O and C elements, such as Figure 17A and Figure 17B As shown, plasma bombards the basic structure from the front, injecting elements such as N, O and C into the base layer 101 at the bottom of the electrode groove 104 to form a second dielectric isolation layer 20 of a certain thickness.
[0152] When plasma diffusion is used to form the second dielectric isolation layer, due to process characteristics, the thickness of the second dielectric isolation layer 20 located on the side of each channel structure 103 is thinner than the thickness of the second dielectric isolation layer 20 located on the first surface of the base layer 101. The higher the collimation of the plasma, the better, which can make the thickness of the second dielectric isolation layer 20 on the side of the channel structure 103 relatively thin, making it easier to remove.
[0153] Because the second dielectric isolation layer 20 grown on the side of the channel structure 103 is thin and easy to remove with high selectivity, the process flow can be simplified and the process window can be improved. It is possible to achieve selective growth of the second dielectric isolation layer 20 located on the first surface of the base layer 101 by relying solely on a diffusion process or diffusion plus EPI (epitaxial) pretreatment.
[0154] As another possible implementation method, growing a second dielectric isolation layer on the surface of the basic structure includes:
[0155] A second dielectric isolation layer is deposited on the surface of the basic structure, wherein the deposition method may be CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition), etc., which is not limited in this embodiment.
[0156] For the deposition process, the CVD and PVD processes can have poor step coverage by adjusting parameters such as pressure, power, and bias, so that the thickness of the second dielectric isolation layer located on the side of each channel structure is less than the thickness of the second dielectric isolation layer located on the first surface of the base layer, that is, there is a thickness difference between the second dielectric isolation layer on the side of the channel structure and the first surface of the base layer.
[0157] This embodiment adopts PVD and CVD processes for deposition, which is a simple deposition method, and then removes the second dielectric isolation layer located on the side of the channel structure, and the process is easy to implement.
[0158] As another possible implementation method, growing a second dielectric isolation layer on the surface of the basic structure includes:
[0159] A second dielectric isolation layer is grown on the surface of the basic structure by topologically selective atomic layer deposition; wherein the quality of the second dielectric isolation layer located on the side of each channel structure and the first dielectric isolation layer is different from the quality of the second dielectric isolation layer located on the first surface of the base layer.
[0160] Due to the characteristics of the topological selective atomic layer deposition method, the thickness of the second dielectric isolation layer located on the side of the channel structure is less than the thickness of the second dielectric isolation layer located on the first surface of the base layer, which facilitates the subsequent removal of the second dielectric isolation layer on the side of the channel structure.
[0161] The second dielectric isolation layer located on the side of the channel structure is of lower quality than the second dielectric isolation layer located on the first surface of the base layer. This lower-quality second dielectric isolation layer is easier to remove, thereby facilitating subsequent removal of the second dielectric isolation layer located on the side of the channel structure. This embodiment makes it possible to selectively grow the second dielectric isolation layer located on the first surface of the base layer using only a deposition process or deposition plus EPI pretreatment.
[0162] Step S202: removing the second dielectric isolation layer located on the side of the trench structure.
[0163] After removing the second dielectric isolation layer on the side of the trench structure, Figure 7A and Figure 7B As shown, the second dielectric isolation layer 20 located on the first surface of the base layer 101 and the second dielectric isolation layer 20 located on the upper surface of the channel structure 103 are left.
[0164] It should be noted that, in this embodiment, there is no limitation on the method for removing the second dielectric isolation layer located on the side surface of the channel structure, and the method can be set arbitrarily.
[0165] As an implementation method, removing the second dielectric isolation layer located on the side of the trench structure includes:
[0166] An isotropic dry etching process is used to etch back the second dielectric isolation layer located on the side of each channel structure.
[0167] The dry etching process offers high etching precision and ease of control, enabling precise control over the removal of the second dielectric isolation layer located on the sides of the trench structure. Dry etching processes include, but are not limited to, reactive ion etching and inductively coupled plasma etching, and the specific dry etching process is user-selectable.
[0168] As another possible implementation method, removing the second dielectric isolation layer located on the side of the trench structure includes:
[0169] An isotropic wet etching process is used to etch back the second dielectric isolation layer located on the side of each channel structure.
[0170] When a wet etching process is used, the etching solution is selected according to the material type of the second dielectric isolation layer, and is not specifically limited in this application.
[0171] The wet etching process has the characteristics of low cost and mild etching, which can reduce the manufacturing process cost and reduce etching damage.
[0172] In this embodiment, the second dielectric isolation layer is formed in two steps. First, the second dielectric isolation layer is formed on the entire surface, and then the second dielectric isolation layer located on the side of the channel structure is removed. It is possible to achieve selective growth of the second dielectric isolation layer on the front side of the substrate by relying solely on the deposition process or deposition plus EPI pretreatment.
[0173] Example 4
[0174] Based on the above embodiments, this embodiment provides a method for manufacturing a semiconductor device. When the base layer is a silicon substrate, after growing the electrode contact structure in the through hole, the method may further include:
[0175] The silicon substrate is removed by etching, and an insulating dielectric material is grown to form an insulating dielectric substrate.
[0176] The silicon substrate may be etched by dry etching, such as reactive ion etching, inductively coupled plasma etching, etc., which is not specifically limited in this application.
[0177] The method of growing the insulating dielectric material is not specifically limited in this application and can be selected by the user, for example, chemical vapor deposition, physical vapor deposition, etc.
[0178] like Figure 18A and Figure 18B as well as Figure 19A and Figure 19B As shown, the silicon substrate is replaced with an insulating dielectric substrate 80 , the base layer becomes the insulating dielectric substrate 80 , and then the back-end process flow on the second surface side of the insulating dielectric substrate 80 is continued.
[0179] The insulating dielectric substrate 80 is made of an insulating dielectric material. Since the silicon substrate is conductive, replacing the silicon substrate with an insulating material is equivalent to increasing the thickness of the insulating layer, thereby reducing the K value of the device and reducing leakage. At the same time, since the silicon substrate is conductive, the silicon substrate is equivalent to a large capacitor with a very thin dielectric layer. Replacing it with the insulating dielectric substrate 80 can reduce the capacitance, thereby reducing RC delay (resistance-capacitance delay).
[0180] Example 5
[0181] This embodiment provides a semiconductor device such as Figure 15A and Figure 19A As shown, this may include:
[0182] Base layer 101;
[0183] An active area located on the first surface of the base layer 101, the active area including a plurality of channel structures 103, an electrode 30, a first dielectric isolation layer 102, and a second dielectric isolation layer 20, wherein the first dielectric isolation layer 102 and the second dielectric isolation layer 20 are located on the first surface of the base layer 101, and each channel structure 103 is partially located on a surface of the first dielectric isolation layer 102 facing away from the base layer 101; the electrode 30 is located on a surface of the second dielectric isolation layer 20 facing away from the base layer 101 and between adjacent channel structures 103 and the first dielectric isolation layer 102, and no second dielectric isolation layer 20 is provided between a first electrode 301 of the electrode 30 and the base layer 101; the first dielectric isolation layer 102 and the second dielectric isolation layer 20 are made of different materials to enable selective etching of the first dielectric isolation layer 102 and the second dielectric isolation layer 20;
[0184] The electrode contact structure 70 extends from the second surface of the base layer 101 toward the first electrode 301 and contacts the first electrode 301 .
[0185] The electrode 30 is a source / drain electrode and includes a first electrode 301 and a second electrode 302. One of the first electrode 301 and the second electrode 302 is a source electrode and the other is a drain electrode. The first electrode 301 is connected to the electrode contact structure 70, and the second electrode 302 is metal-interconnected on the first surface via a metal interconnect structure.
[0186] It should be noted that the semiconductor device further includes a gate, which is located in the region where the channel structure 103 is located.
[0187] The material of the first dielectric isolation layer 102 can be an insulating dielectric material such as SiN, SiO, SiCN, SiOC, etc., which is not specifically limited in this embodiment.
[0188] The material of the second dielectric isolation layer 20 can be an insulating dielectric material such as SiN, SiO, SiC, SiON, SiOC, SiCN, SiCON, SiBN, BN, BON, BCN, BCON, etc., which is not specifically limited in this embodiment.
[0189] The material of the electrode contact structure 70 may be metal, such as W, Co, Mo, Ru, etc.
[0190] When the semiconductor device is a P-type semiconductor device, the material of the electrode 30 may be SiGe, etc., and when the semiconductor device is an N-type semiconductor device, the material of the electrode 30 may be SiP, etc. To reduce the contact resistance between the first electrode 301 and the electrode contact structure 70, in one embodiment of the present application, the semiconductor device may further include a silicide layer 60 located between the first electrode 301 and the electrode contact structure 70.
[0191] As an embodiment, the critical dimension of the electrode contact structure 70 away from the first electrode 301 is larger than the critical dimension of the side close to the first electrode 301, and the critical dimension of the electrode contact structure 70 away from the first electrode 301 is larger than the critical dimension of the electrode 30, so as to reduce the contact resistance between the electrode contact structure 70 and the electrode 30.
[0192] It should be noted that the material of the base layer is not limited in this embodiment and depends on the circumstances.
[0193] As an implementation method, the base layer 101 includes a silicon substrate. Silicon is generally used as a substrate in conventional semiconductor processes and does not require subsequent processing, which can simplify the manufacturing process and reduce costs.
[0194] As another possible implementation, the base layer 101 includes an insulating dielectric substrate 80. The material of the insulating dielectric substrate 80 is an insulating material, which is equivalent to increasing the thickness of the insulating layer, which can reduce the K value and leakage of the device, and at the same time reduce the capacitance, thereby reducing the RC delay.
[0195] As an implementation method, the semiconductor device may further include: a shallow trench isolation 107 located in the base layer 101 , and a side of the electrode contact structure 70 away from the first electrode 301 is flush with an end of the shallow trench isolation 107 .
[0196] When manufacturing the through hole 50 where the electrode contact structure 70 is located, the shallow trench isolation 107 can play a self-alignment role during etching, improve the photolithography process window, and at the same time has the effect of isolating devices to prevent mutual interference between devices.
[0197] The types of semiconductor devices in this embodiment include but are not limited to GAA transistors, Fork sheets, CFET transistors, etc.
[0198] The semiconductor device provided in this embodiment has a second dielectric isolation layer 20 distributed on the first surface of the base layer 101. When etching to form the through hole 50 where the electrode contact structure 70 is located, the second dielectric isolation layer 20 is etched from the second surface of the base layer 101, which will not affect the production of components such as the electrode 30. The first dielectric isolation layer 102 and the second dielectric isolation layer 20, two different material layers, are both located on the first surface of the base layer 101. When etching to form the through hole 50, the first dielectric isolation layer 102 can reduce the alignment accuracy requirements and improve the photolithography process window. At the same time, because the second dielectric isolation layer 20 is made of different materials from the first dielectric isolation layer 102 and the electrode 30, selective etching of the second dielectric isolation layer 20 can be achieved, reducing the damage caused by etching to the electrode 30, thereby improving the performance of the semiconductor device.
[0199] Example 6
[0200] This embodiment provides a semiconductor device, which is manufactured using the method for manufacturing a semiconductor device according to any of the above embodiments.
[0201] The types of semiconductor devices in this embodiment include but are not limited to GAA transistors, Fork sheets, CFET transistors, etc.
[0202] The semiconductor device of this embodiment manufactures a second dielectric isolation layer on the first surface of the base layer, and etches the second dielectric isolation layer on the second surface of the base layer to form a through hole for growing an electrode contact structure. The second dielectric isolation layer is grown on the first surface of the base layer, and the method of etching the second dielectric isolation layer from the second surface of the base layer is very simple and convenient, and will not affect the production of components such as electrodes. The first dielectric isolation layer and the second dielectric isolation layer, two different material layers, are both located on the first surface of the base layer. When etching to form a through hole, the first dielectric isolation layer can reduce the alignment accuracy requirements and improve the photolithography process window. At the same time, since the second dielectric isolation layer, the first dielectric isolation layer, and the electrode are made of different materials, selective etching of the second dielectric isolation layer can be achieved, reducing the damage to the electrode caused by etching, thereby improving the performance of the semiconductor device.
[0203] Example 7
[0204] This embodiment provides an electronic device, including the semiconductor device of any of the above embodiments.
[0205] The above preferred embodiments further illustrate the objectives, technical solutions and advantages of the present invention in detail. It should be understood that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: Obtaining a basic structure of a semiconductor device, the basic structure consisting of a base layer, a first dielectric isolation layer, and a plurality of channel structures; wherein the first dielectric isolation layer is located on a first surface of the base layer, each of the channel structures is partially located on a surface of the first dielectric isolation layer facing away from the base layer, and electrode grooves are distributed between adjacent channel structures and the first dielectric isolation layer; forming a second dielectric isolation layer on the first surface of the base layer; the first dielectric isolation layer and the second dielectric isolation layer are made of different materials so as to achieve selective etching of the first dielectric isolation layer and the second dielectric isolation layer; An electrode material is grown in the electrode groove to form an electrode; the active area includes the electrode, the first dielectric isolation layer, the second dielectric isolation layer, and the plurality of channel structures; the electrode includes a first electrode that requires metal interconnection on one side of the second surface of the base layer; the second surface and the first surface are two opposite surfaces of the base layer; thinning the base layer; Etching the thinned base layer and the second dielectric isolation layer from the second surface of the base layer to form a through hole; the through hole corresponds to the first electrode; An electrode contact structure is grown in the through hole; the electrode contact structure is in contact with the first electrode.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a second dielectric isolation layer on the first surface of the base layer includes: The second dielectric isolation layer is directly grown on the first surface of the base layer by adopting a topologically selective atomic layer deposition method.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a second dielectric isolation layer on the first surface of the base layer includes: growing the second dielectric isolation layer on the surface of the basic structure; The second dielectric isolation layer located on a side surface of each of the trench structures is removed.
4. The method for manufacturing a semiconductor device according to claim 3, wherein: Growing the second dielectric isolation layer on the surface of the basic structure includes: Plasma is injected into the surface of the basic structure, so that the plasma diffuses on the surface of the basic structure to form the second dielectric isolation layer.
5. The method for manufacturing a semiconductor device according to claim 3, wherein: Growing the second dielectric isolation layer on the surface of the basic structure includes: A second dielectric isolation layer is deposited on the surface of the basic structure.
6. The method for manufacturing a semiconductor device according to claim 3, wherein: Growing the second dielectric isolation layer on the surface of the basic structure includes: The second dielectric isolation layer is grown on the surface of the basic structure by topologically selective atomic layer deposition; wherein the quality of the second dielectric isolation layer located on the side of each of the channel structures and the first dielectric isolation layer is different from the quality of the second dielectric isolation layer located on the first surface of the base layer.
7. The method for manufacturing a semiconductor device according to any one of claims 4 to 6, wherein: in, The thickness of the second dielectric isolation layer located on the side of each of the channel structures is smaller than the thickness of the second dielectric isolation layer located on the first surface of the base layer.
8. The method for manufacturing a semiconductor device according to any one of claims 3 to 7, wherein: Removing the second dielectric isolation layer located on a side of the trench structure includes: An isotropic dry etching process is used to etch back the second dielectric isolation layer located on the side of each of the channel structures.
9. The method for manufacturing a semiconductor device according to any one of claims 3 to 7, wherein: Removing the second dielectric isolation layer located on a side of the trench structure includes: An isotropic wet etching process is used to etch back the second dielectric isolation layer located on the side of each of the channel structures.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: The critical dimension of the electrode contact structure away from the first electrode is larger than the critical dimension of the side close to the first electrode, and the critical dimension of the electrode contact structure away from the first electrode is larger than the critical dimension of the first electrode.
11. The method for manufacturing a semiconductor device according to claim 1, wherein: After etching the thinned base layer and the second dielectric isolation layer from the second surface of the base layer to form a through hole, and before growing an electrode contact structure in the through hole, the method further includes: growing a silicide layer in the through hole; the silicide layer is in contact with the first electrode; Accordingly, an electrode contact structure is grown in the through hole; and the electrode contact structure is in contact with the first electrode, comprising: An electrode contact structure is grown in the through hole and on the surface of the silicide; the electrode contact structure is in contact with the silicide layer.
12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein: When the base layer is a silicon substrate, after growing the electrode contact structure in the through hole, the method further includes: The silicon substrate is removed by etching, and an insulating dielectric material is grown to form an insulating dielectric substrate.
13. The method for manufacturing a semiconductor device according to any one of claims 1 to 12, wherein: Etching the thinned base layer and the second dielectric isolation layer from the second surface of the base layer to form a through hole includes: depositing a hard mask layer on the second surface of the thinned base layer, and etching the hard mask layer to form a window; Etching the base layer through the window to form a first through hole using a soft landing etching method, and stopping the etching on the surfaces of the first dielectric isolation layer and the second dielectric isolation layer; The second dielectric isolation layer is etched to form a second through hole, and the etching stops at the surface of the first electrode; the first through hole and the second through hole constitute the through hole.
14. The method for manufacturing a semiconductor device according to claim 13, wherein: The etching selectivity ratio of the second dielectric isolation layer to the first dielectric isolation layer, the base layer and the shallow trench isolation is greater than 5:
1.
15. A semiconductor device, characterized in that: include: base layer; an active area located on the first surface of the base layer, the active area comprising a plurality of channel structures, electrodes, a first dielectric isolation layer, and a second dielectric isolation layer, wherein the first dielectric isolation layer and the second dielectric isolation layer are located on the first surface of the base layer, and each of the channel structures is partially located on a surface of the first dielectric isolation layer facing away from the base layer; the electrodes are located on a surface of the second dielectric isolation layer facing away from the base layer and between adjacent channel structures and the first dielectric isolation layer, and no second dielectric isolation layer is provided between a first electrode of the electrodes and the base layer; the first dielectric isolation layer and the second dielectric isolation layer are made of different materials so as to achieve selective etching of the first dielectric isolation layer and the second dielectric isolation layer; An electrode contact structure extends from the second surface of the base layer toward the first electrode and contacts the first electrode.
16. The semiconductor device according to claim 15, wherein The critical dimension of the electrode contact structure away from the first electrode is larger than the critical dimension of the side close to the first electrode, and the critical dimension of the electrode contact structure away from the first electrode is larger than the critical dimension of the electrode.
17. The semiconductor device according to claim 15, wherein Also includes: A shallow trench isolation is located in the base layer, and a side of the electrode contact structure away from the first electrode is flush with an end of the shallow trench isolation.
18. The semiconductor device according to any one of claims 15 to 17, wherein: The base layer includes a silicon substrate.
19. The semiconductor device according to any one of claims 15 to 17, wherein: The base layer includes an insulating dielectric substrate.
20. The semiconductor device according to any one of claims 15 to 19, wherein Also includes: A silicide layer is located between the first electrode and the electrode contact structure.
21. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 14.
22. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 15 to 20 or claim 21.