Substrate unit

Abstract

One embodiment of the present invention provides a substrate unit capable of suppressing the occurrence of manufacturing defects. According to one embodiment, a substrate unit includes an insulating base material, a first pad, a second pad, a solder resist layer, a first insulating portion, and an electronic component. The solder resist layer has an opening that exposes the first pad and the second pad. The first insulating portion is provided between the first pad and the second pad in the opening. The electronic component has a first terminal connected to the first pad via a bonding material, and a second terminal connected to the second pad via a bonding material. The solder resist layer contains a first insulating material. The first insulating portion includes a second insulating material different from the first insulating material. When a direction from the first pad toward the insulating substrate is a first direction, a length of the first insulating portion in the first direction is greater than a length of the first pad in the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a substrate unit. Background Art

[0002] A substrate unit is known that includes pads provided on an insulating base material, a solder resist layer having openings for exposing the pads, and electronic components connected to the pads. Summary of the Invention

[0003] One embodiment provides a substrate unit capable of suppressing the occurrence of manufacturing defects.

[0004] A substrate unit according to one embodiment includes an insulating substrate, a first solder pad, a second solder pad, a solder resist layer, a first insulating portion, and an electronic component. The first solder pad is provided on the insulating substrate. The second solder pad is provided on the insulating substrate. The solder resist layer includes a portion provided on the insulating substrate. The solder resist layer includes an opening that exposes the first solder pad and the second solder pad. The first insulating portion is provided within the opening between the first solder pad and the second solder pad. The electronic component includes a first terminal connected to the first solder pad via a bonding material, and a second terminal connected to the second solder pad via a bonding material. The solder resist layer includes a first insulating material. The first insulating portion includes a second insulating material different from the first insulating material. When the direction from the first solder pad toward the insulating substrate is defined as the first direction, the length of the first insulating portion in the first direction is greater than the length of the first solder pad in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 It is a perspective view showing the semiconductor memory device according to the first embodiment.

[0006] Figure 2 This is a cross-sectional view showing a portion of the substrate according to the first embodiment.

[0007] Figure 3 It is along Figure 2 A cross-sectional view of the substrate taken along line F3-F3 shown in FIG.

[0008] Figure 4 It is a cross-sectional view showing a part of the substrate unit according to the first embodiment.

[0009] Figure 5 (a) to (c) are cross-sectional views illustrating a method for manufacturing the substrate unit according to the first embodiment.

[0010] Figure 6 (d) to (e) are cross-sectional views illustrating the method for manufacturing the substrate unit according to the first embodiment.

[0011] Figure 7 It is a cross-sectional view showing a portion of the substrate according to the second embodiment.

[0012] Figure 8 It is a cross-sectional view showing a portion of the substrate according to the third embodiment.

[0013] Figure 9 It is along Figure 8 A cross-sectional view of the substrate taken along line F9-F9 is shown in FIG.

[0014] Figure 10 It is a cross-sectional view showing a part of the substrate unit according to the fourth embodiment.

[0015] Figure 11 It is along Figure 10 A cross-sectional view of the substrate taken along line F11-F11 is shown in FIG. DETAILED DESCRIPTION

[0016] Hereinafter, a substrate unit according to an embodiment will be described with reference to the drawings.

[0017] In the following description, the same symbols are used to mark the structures with the same or similar functions. In addition, there are cases where repeated descriptions of these structures are omitted. In the present application, "parallel", "orthogonal" or "same" may each include "approximately parallel", "approximately orthogonal" or "approximately the same". In the present application, "connection" is not limited to mechanical connection, and may include electrical connection. In other words, "connection" is not limited to the situation of direct connection with the object, and may also include the situation of connecting to the object with other elements interposed therebetween. In the present application, "overlap" means that the virtual projection images of two objects overlap with each other. In other words, "overlap" is not limited to the situation where two objects are in contact, and may also include the situation where two objects are not in contact (for example, the situation where there is space or other elements between the two objects).

[0018] In this application, the X direction, the Y direction, and the Z direction are defined as follows. The X direction and the Y direction are directions parallel to the first surface 21a of the substrate 21 described later (refer to Figure 1 The X direction is the direction from the first pad 42A to the second pad 42B (see Figure 3 ). The Y direction is a direction that intersects (e.g., is perpendicular to) the X direction (refer to Figure 3 The Z direction is a direction that intersects (for example, is perpendicular to) the X direction and the Y direction. The Z direction is a direction from the first pad 42A described later toward the insulating substrate 31 (refer to Figure 2 ). The Z direction is an example of the “first direction”. The X direction is an example of the “second direction”. The Y direction is an example of the “third direction”.

[0019] (First embodiment)

[0020] <1. Overall Structure of a Semiconductor Memory Device>

[0021] refer to Figures 1 to 6 A semiconductor memory device 1 including a substrate unit 20 according to the first embodiment will be described. The semiconductor memory device 1 is, for example, a storage device such as an SSD (Solid State Drive). The semiconductor memory device 1 is connected to a host device and functions as a storage device for the host device. The host device may be, but is not limited to, a server, a personal computer, a mobile device, a video recorder, or an in-vehicle device.

[0022] The semiconductor memory device 1 is an example of a "semiconductor device." The substrate unit 20 can also be applied to semiconductor devices other than semiconductor memory devices. Semiconductor devices other than semiconductor memory devices may be, for example, devices including semiconductor components (e.g., semiconductor integrated circuits) such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). They may also be devices including other types of semiconductor components such as diodes, transistors, or amplifiers. These semiconductor devices may be, for example, servers, personal computers, mobile devices, video recorders, or in-vehicle devices, but are not limited to these examples.

[0023] Figure 1 1 is a perspective view showing semiconductor memory device 1. Semiconductor memory device 1 includes, for example, a housing 10 and a substrate unit 20.

[0024] <1.1 Housing>

[0025] Housing 10 is a component that forms the outer shell of semiconductor storage device 1. Housing 10 houses substrate unit 20. Housing 10 includes, for example, base 11 and lid 12. Lid 12 faces substrate unit 20 from the side opposite base 11. Housing 10 is formed, for example, by combining base 11 and lid 12. Alternatively, semiconductor storage device 1 may not include housing 10. In this case, substrate unit 20 alone may constitute an example of a "semiconductor device."

[0026] <1.2 Substrate Unit>

[0027] Next, the substrate unit 20 will be described. The substrate unit 20 is an assembly including a substrate and semiconductor components. The substrate unit 20 includes, for example, a substrate 21, a connection connector 22, a controller 23, a plurality of NAND flash memories 24 (hereinafter referred to as "NAND 24"), and a plurality of electronic components 25.

[0028] The substrate 21 is a plate member extending in the X and Y directions. The substrate 21 is a printed wiring board, comprising an insulating base material 31 and a wiring pattern 32 (see FIG. Figure 2 The substrate 21 includes a first surface 21a and a second surface 21b located on the opposite side of the first surface 21a. The first surface 21a and the second surface 21b extend in the X direction and the Y direction, respectively.

[0029] The connection connector 22 is a connection portion capable of connecting to a connector of a host device. The connection connector 22 includes a plurality of metal terminals capable of connecting to the connector of the host device. The connection connector 22 is provided, for example, at an end of the substrate 21. The connection connector 22 is exposed to the outside of the housing 10 through the opening 10h of the housing 10.

[0030] Controller 23 is a component that comprehensively controls the entire semiconductor storage device 1. Controller 23 is, for example, a semiconductor package called a SoC (System on a Chip) that integrates a host interface circuit for a host device and a control circuit for controlling multiple NAND flash devices 24 into a single semiconductor chip. Controller 23 is, for example, provided on first surface 21a of substrate 21. Controller 23 is an example of a "semiconductor component."

[0031] NAND 24 is a semiconductor package that includes a nonvolatile semiconductor memory chip. For example, NAND 24 is provided on the first surface 21a and the second surface 21b of substrate 21. NAND 24 is an example of a "semiconductor memory" and an example of a "semiconductor component." Furthermore, the "semiconductor memory" or "semiconductor component" referred to in this application is not limited to NAND 24 and may also refer to other types of semiconductor memory, such as NOR memory, MRAM (Magnetoresistive Random Access Memory), or resistance change memory.

[0032] A plurality of electronic components 25 are provided on the first surface 21a and the second surface 21b of the substrate 21. The electronic components 25 include, for example, small components having a longitudinal length of 1 mm or less. The mounting structure of the electronic components 25 will be described below.

[0033] <2. Electronic Component Mounting Structure>

[0034] <2.1 Substrate Structure>

[0035] First, the structure of the substrate 21 will be described.

[0036] Figure 2 2 is a cross-sectional view showing a portion of a substrate 21. The substrate 21 is, for example, a multilayer circuit board and includes an insulating base material 31 and a wiring pattern 32.

[0037] The insulating substrate 31 is an insulating member that forms the base of the substrate 21. The insulating substrate 31 is formed, for example, from a hard insulating material such as epoxy glass. However, the material of the insulating substrate 31 is not limited to this example. The insulating substrate 31 may also be formed from a paper-phenol material, a composite material, a fluorine-based material, or a polyimide material.

[0038] In this embodiment, insulating substrate 31 includes core material 31A, adhesive sheet 31B, and prepreg 31C. Adhesive sheet 31B is laminated onto core material 31A. Prepreg 31C is integrated with core material 31A via adhesive sheet 31B. Prepreg 31C is located on the surface side of substrate 21 relative to core material 31A. Furthermore, substrate 21 is not limited to a multilayer circuit board and may also be a double-sided substrate. In other words, insulating substrate 31 may be formed solely of core material 31A without adhesive sheet 31B and prepreg 31C.

[0039] The insulating base material 31 has a surface 31s on which wiring 41 and pads 42 described later are provided. The surface 31s extends in the X direction and the Y direction. The surface 31s is an example of a "first surface."

[0040] The wiring pattern 32 is a conductive portion provided on the substrate 21. The wiring pattern 32 includes wiring 32L provided inside the insulating base material 31 and / or on the surface of the insulating base material 31. The wiring pattern 32 is formed of a metal material such as copper, for example.

[0041] <2.2 Structure of the Surface Layer of the Substrate>

[0042] Next, a description will be given of the surface layer portion of the substrate 21. The surface layer portion of the substrate 21 includes, for example, a conductive pattern 40, a solder resist layer 51, and an insulating portion 55.

[0043] <2.2.1 Conductive Pattern>

[0044] First, the conductive pattern 40 will be described. The conductive pattern 40 is a conductive portion provided on the surface layer portion as a part of the wiring pattern 32. The conductive pattern 40 includes wiring 41 and a plurality of pads 42.

[0045] (Wiring)

[0046] The wiring 41 is provided on the surface portion as a part of the wiring 32L. The wiring 41 is provided on the surface 31 s of the insulating base material 31 .

[0047] (pad)

[0048] The plurality of pads 42 are provided on the surface 31s of the insulating substrate 31. The plurality of pads 42 include, for example, a first pad 42A and a second pad 42B. The first pad 42A and the second pad 42B are arranged, for example, spaced apart in the X direction. When viewed from the Z direction, each of the first pad 42A and the second pad 42B is, for example, rectangular (see FIG. 1 ). Figure 3 However, each of the first pad 42A and the second pad 42B may be circular or have other shapes. Hereinafter, when the first pad 42A and the second pad 42B are not distinguished, they are simply referred to as "pads 42".

[0049] The pad 42 has a thickness (eg, maximum thickness) T42 as the thickness in the Z direction (length in the Z direction). Figure 2 When viewed in the cross section shown in FIG, the pad 42 has an end 42e located on the opposite side of the insulating substrate 31. The thickness T42 of the pad 42 corresponds to the height of the end 42e of the pad 42 relative to the surface 31s of the insulating substrate 31. The end 42e is an example of a "first end."

[0050] <2.2.2 Solder Resist Layer>

[0051] Next, the solder resist layer 51 will be described. The solder resist layer 51 is an insulating protective layer that protects the conductive pattern 40. The solder resist layer 51 has a surface 51s located opposite to the insulating base 31. The surface 51s of the solder resist layer 51 forms the first surface 21a of the substrate 21.

[0052] The solder resist layer 51 includes a first portion 51a and a second portion 51b. The first portion 51a is provided on the surface 31s of the insulating substrate 31 and is in contact with the insulating substrate 31. The second portion 51b covers the conductive pattern 40 from the Z direction. For example, the second portion 51b covers the wiring 41.

[0053] The solder resist layer 51 has an opening 51h that exposes the first pad 42A and the second pad 42B. When viewed from the Z direction, the opening 51h is, for example, rectangular (see FIG. 1 ). Figure 3 ).

[0054] The solder resist layer 51 has a thickness (eg, maximum thickness) T51 as the thickness in the Z direction. The thickness T51 is the thickness (eg, maximum thickness) of the first portion 51a of the solder resist layer 51 in the Z direction. Figure 2When viewed in the cross-section shown in FIG. 3 , the solder resist layer 51 has an end 51e located on the opposite side of the insulating substrate 31. The thickness T51 of the solder resist layer 51 in the Z direction corresponds to the height of the end 51e of the solder resist layer 51 relative to the surface 31s of the insulating substrate 31. The thickness T51 of the solder resist layer 51 in the Z direction is greater than the thickness T42 of the pad 42 in the Z direction.

[0055] The solder resist layer 51 includes a first insulating material. The first insulating material is a typical insulating material for forming a solder resist layer. For example, the first insulating material is an epoxy resin. The solder resist layer 51 is formed by applying the first insulating material to the insulating substrate 31 using, for example, a curtain coater, screen printing, or spray coating, and curing the applied first insulating material by heating or ultraviolet exposure.

[0056] <Insulation part>

[0057] Next, the insulating portion 55 will be described. The insulating portion 55 is an example of a "first insulating portion." The insulating portion 55 is provided on the surface 31s of the insulating substrate 31. The insulating portion 55 is provided within the opening 51h of the solder resist layer 51. For example, the insulating portion 55 is provided only within the opening 51h of the solder resist layer 51. The insulating portion 55 is provided between the first pad 42A and the second pad 42B in the X direction. The width W55x of the insulating portion 55 in the X direction is, for example, 0.1 mm or less.

[0058] Figure 3 It is along Figure 2 , a cross-sectional view of substrate 21 taken along line F3-F3 is shown in FIG. Insulating portion 55 extends in the Y direction between first pad 42A and second pad 42B. For example, insulating portion 55 extends linearly in the Y direction between first pad 42A and second pad 42B. In this embodiment, width W55y of insulating portion 55 in the Y direction is greater than width W42y of pad 42 in the Y direction. Width W55y of insulating portion 55 in the Y direction is greater than width W25y of electronic component 25, described later, in the Y direction.

[0059] In this embodiment, the edge 51he of the opening 51h of the solder resist layer 51 includes a first edge 51he1 and a second edge 51he2 located on the opposite side of the first edge 51he1, as a pair of edges in the Y direction. In this embodiment, the insulating portion 55 extends across the first edge 51he1 and the second edge 51he2 of the opening 51h of the solder resist layer 51.

[0060] In this embodiment, the insulating portion 55 has a first end 56e1 and a second end 56e2 located on the opposite side of the first end 56e1, forming a pair of ends in the Y direction. In this embodiment, the first end 56e1 and the second end 56e2 of the insulating portion 55 each contact the solder resist layer 51. For example, the first end 56e1 contacts the first edge 51he1 of the opening 51h of the solder resist layer 51. The first end 56e1 is an example of a "third end." Similarly, the second end 56e2 contacts the second edge 51he2 of the opening 51h of the solder resist layer 51.

[0061] Then, return Figure 2 , the thickness T55 of the insulating portion 55 in the Z direction will be described. The insulating portion 55 has a thickness (eg, maximum thickness) T55 as the thickness in the Z direction. Figure 2 When viewed in the cross-section shown in FIG, the insulating portion 55 has an end 55e located on the opposite side of the insulating substrate 31. The thickness T55 of the insulating portion 55 in the Z direction corresponds to the height of the end 55e of the insulating portion 55 relative to the surface 31s of the insulating substrate 31. The end 55e corresponds to an example of a "second end."

[0062] In this embodiment, the thickness (e.g., maximum thickness) T55 of the insulating portion 55 in the Z direction is greater than the thickness (e.g., maximum thickness) T42 of the pad 42 in the Z direction. In other words, the height of the end 55e of the insulating portion 55 relative to the surface 31s of the insulating substrate 31 is greater than the height of the end 42e of the pad 42 relative to the surface 31s of the insulating substrate 31.

[0063] On the other hand, the thickness (e.g., maximum thickness) T55 of the insulating portion 55 in the Z direction is smaller than the thickness (e.g., maximum thickness) T51 of the solder resist layer 51 in the Z direction. In other words, the height of the end 55 e of the insulating portion 55 relative to the surface 31 s of the insulating base material 31 is smaller than the height of the end 51 e of the solder resist layer 51 relative to the surface 31 s of the insulating base material 31.

[0064] The insulating portion 55 includes a second insulating material. The second insulating material is an insulating material different from the first insulating material. In this application, the term "insulating material different from the first insulating material" means that the insulating material differs from the first insulating material in at least one of its composition, composition, film quality, the presence or degree of internal bubbles, or other properties (e.g., viscosity before curing).

[0065] The second insulating material is, for example, an insulating material that can be applied by inkjet. For example, the second insulating material is an insulating material whose viscosity before curing (for example, viscosity at room temperature) is lower than that of the first insulating material. For example, the second insulating material is a resin-based insulating material adjusted in such a way that its viscosity at room temperature is lower than that of the first insulating material. The insulating portion 55 is formed by, for example, applying the second insulating material on the insulating substrate 31 by inkjet, and curing the applied second insulating material by ultraviolet exposure or the like. The second insulating material is, for example, an insulating material that is cured by ultraviolet exposure using a mercury lamp or an LED (Light Emitting Diode). In addition, the curing method of the second insulating material is not limited to the above-mentioned method, and may also be heating or the like.

[0066] <2.3 Electronic Components>

[0067] Next, the electronic component 25 will be described.

[0068] Figure 4 It is a cross-sectional view showing a portion of the substrate unit 20 . Figure 4 The electronic component 25 is exemplified as a chip capacitor, but is not limited thereto. The electronic component 25 may be a resistor, a diode, or other types of components. The electronic component 25 includes, for example, a component body 61 and a plurality of terminals 62.

[0069] The component body 61 is a portion responsible for the main function of the electronic component 25. For example, the component body 61 of the electronic component 25, such as a chip capacitor, is a portion that accumulates electric charge when a DC voltage is applied.

[0070] The plurality of terminals 62 include a first terminal 62A and a second terminal 62B. The first terminal 62A and the second terminal 62B are separately arranged on both sides of the component body 61 in the X direction. The first terminal 62A is one of the positive and negative terminals. When viewed from the Z direction, the first terminal 62A overlaps with the first solder pad 42A. The first terminal 62A is connected to the first solder pad 42A via a bonding material H such as solder. The second terminal 62B is the other of the positive and negative terminals. When viewed from the Z direction, the second terminal 62B overlaps with the second solder pad 42B. The second terminal 62B is connected to the second solder pad 42B via a bonding material H such as solder.

[0071] The component body 61 has an end 61e on the insulating base material 31 side. The end 61e of the component body 61 faces the insulating portion 55 in the Z direction. The end 61e of the component body 61 is located closer to the insulating base material 31 than the end 51e of the solder resist layer 51. The end 61e of the component body 61 may also be in contact with the end 55e of the insulating portion 55.

[0072] Next, refer to Figure 3An example of the dimensions of electronic component 25 will be described. When viewed from the Z direction, electronic component 25 is a rectangular component. The width of the long side of electronic component 25 (width W25x in the X direction) is, for example, 0.4 mm or less. The width of the short side of electronic component 25 (width W25y in the Y direction) is, for example, 0.2 mm or less.

[0073] <3. Method for Manufacturing Substrate Unit>

[0074] Next, a method for manufacturing the substrate unit 20 will be described.

[0075] Figure 5 and Figure 6 This is a cross-sectional view showing a method for manufacturing the substrate unit 20. First, an intermediate body 21M (see FIG. 1 ) is prepared in which a conductive layer 101 is attached to the surface 31s of the insulating substrate 31. Figure 5 Next, the unnecessary portion of the conductive layer 101 is removed by etching, and a conductive pattern 40 (eg, wiring 41 and pad 42) is formed from the conductive layer 101 (see Figure 5 (b) in the figure.

[0076] Next, a solder resist layer 51 (see FIG. 1 ) is provided on the surface 31s of the insulating substrate 31. Figure 5 (c)). For example, a first insulating material is supplied to the surface 31s of the insulating substrate 31 and the surface of the conductive pattern 40 and cured to form an insulating layer. Unnecessary portions of the insulating layer (e.g., portions corresponding to the openings 51h) are then removed by etching or the like. Thus, the solder resist layer 51 is formed from the insulating layer.

[0077] Next, an insulating portion 55 (see FIG. Figure 6 (d) in the figure). For example, the insulating portion 55 is formed by supplying a second insulating material to a position between the first pad 42A and the second pad 42B in the opening 51h of the solder resist layer 51 using an inkjet method and curing the second insulating material. Thus, the substrate 21 is completed.

[0078] In this embodiment, an insulating material having a lower viscosity than the first insulating material is used as the second insulating material to form the fine insulating portion 55. Therefore, it may be difficult to form an insulating portion 55 of sufficient height with a single application of the second insulating material using an inkjet method. In such cases, the insulating portion 55 can be formed by repeatedly applying the second insulating material using an inkjet method multiple times, or by alternately repeating the application and curing of the second insulating material using an inkjet method multiple times, thereby stacking multiple insulating layers 51sa, 51sb, and 51sc in the Z direction.

[0079] Next, the electronic component 25 is mounted on the substrate 21 (see Figure 6(e) in the figure). In this embodiment, the first terminal 62A of the electronic component 25 is placed on the first pad 42A via the bonding material H, and the second terminal 62B of the electronic component 25 is placed on the second pad 42B via the bonding material H. Then, by performing the reflow process, the second terminal 62B of the electronic component 25 is connected (bonded) to the first pad 42A via the bonding material H, and the second terminal 62B of the electronic component 25 is connected (bonded) to the second pad 42B via the bonding material H. Thus, the electronic component 25 is mounted on the substrate 21. Thus, the substrate unit 20 is completed.

[0080] <4. Advantages>

[0081] As a first comparative example, consider a configuration in which no insulating portion is provided between first pad 42A and second pad 42B. For example, the configuration of the first comparative example may occur in the following situation: electronic component 25 is small, making it difficult to form solder resist layer 51 between first pad 42A and second pad 42B, and providing opening 51h that exposes both first pad 42A and second pad 42B.

[0082] In the configuration of the first comparative example, when the first terminal 62A of the electronic component 25 is connected to the first pad 42A via the bonding material H, and the second terminal 62B of the electronic component 25 is connected to the second pad 42B via the bonding material H (for example, during a reflow process), the bonding material H used to connect the first terminal 62A to the first pad 42A and the bonding material H used to connect the second terminal 62B to the second pad 42B may melt and connect in close proximity, causing a short circuit between the first pad 42A and the second pad 42B. If a manufacturing defect caused by such a short circuit occurs, the manufacturing yield of the substrate unit 20 will decrease.

[0083] Therefore, in this embodiment, the substrate unit 20 includes an insulating base material 31, a first pad 42A, a second pad 42B, a solder resist layer 51, an insulating portion 55, and an electronic component 25. The solder resist layer 51 includes an opening 51h that exposes the first pad 42A and the second pad 42B. The insulating portion 55 is provided within the opening 51h between the first pad 42A and the second pad 42B. The electronic component 25 includes a first terminal 62A connected to the first pad 42A via a bonding material H, and a second terminal 62B connected to the second pad 42B via a bonding material H. The solder resist layer 51 includes a first insulating material. The insulating portion 55 includes a second insulating material different from the first insulating material. The thickness (e.g., maximum thickness) T55 of the insulating portion 55 in the Z direction is greater than the thickness (e.g., maximum thickness) T42 of the first pad 42A in the Z direction.

[0084] With this configuration, even when it is difficult to form the solder resist layer 51 between the first pad 42A and the second pad 42B, it is possible to provide the insulating portion 55 between the first pad 42A and the second pad 42B by other methods. Providing the insulating portion 55 between the first pad 42A and the second pad 42B can prevent the bonding material H connecting the first terminal 62A to the first pad 42A from being connected to the bonding material H connecting the second terminal 62B to the second pad 42B. This can help prevent manufacturing defects in the substrate unit 20.

[0085] In this embodiment, the thickness (e.g., maximum thickness) T55 of the insulating portion 55 in the Z direction is smaller than the thickness (e.g., maximum thickness) T51 of the first portion 51a of the solder resist layer 51 in the Z direction. This configuration limits the amount of protrusion of the insulating portion 55 from the surface 31s of the insulating substrate 31. For example, even when mounting a small electronic component 25, the insulating portion 55 can be prevented from becoming an obstacle and making it difficult to mount the electronic component 25 (e.g., increasing the mounting height of the electronic component 25). This improves the manufacturability of the substrate unit 20 and / or reduces the thickness of the substrate unit 20.

[0086] In this embodiment, the insulating portion 55 is formed by applying an insulating material using an inkjet method and curing it. This configuration makes it easier to form a fine insulating portion 55 than by forming a solder resist layer 51. Thus, even when it is difficult to form a solder resist layer 51 between the first pad 42A and the second pad 42B, it is easier to provide the insulating portion 55 between the first pad 42A and the second pad 42B.

[0087] Furthermore, when the insulating portion 55 is formed by inkjet printing, it is easy to achieve a thickness T55 of the insulating portion 55 that is different from the thickness T51 of the solder resist layer 51 in the Z direction. Therefore, when the insulating portion 55 is formed by inkjet printing, it is easy to make the thickness T55 of the insulating portion 55 in the Z direction smaller than the thickness T51 of the solder resist layer 51 in the Z direction.

[0088] In the present embodiment, at least one of the first end 56e1 and the second end 56e2 in the Y direction of the insulating portion 55 is in contact with the solder resist layer 51. With this configuration, it is possible to more reliably prevent the bonding material H for connecting the first terminal 62A to the first pad 42A and the bonding material H for connecting the second terminal 62B to the second pad 42B from being connected.

[0089] (Second embodiment)

[0090] Next, the second embodiment will be described. The second embodiment differs from the first embodiment in that the insulating portion 55 is spaced apart from the edge 51he of the opening 51h of the solder resist layer 51. The configuration other than that described below is the same as that of the first embodiment.

[0091] Figure 7 This is a cross-sectional view showing a portion of substrate 21 according to the second embodiment. In this embodiment, insulating portion 55 is located between first pad 42A and second pad 42B and extends in the Y direction. In this embodiment, width W55y of insulating portion 55 in the Y direction is smaller than width W42y of pad 42 in the Y direction. For example, width W55y of insulating portion 55 in the Y direction is at least half of width W42y of pad 42 in the Y direction, but smaller than width W42y of pad 42 in the Y direction.

[0092] In this embodiment, the insulating portion 55 has a first end 56e1 and a second end 56e2 located on the opposite side of the first end 56e1, forming a pair of ends in the Y direction. In this embodiment, the first end 56e1 and the second end 56e2 of the insulating portion 55 are each separated from the solder resist layer 51. For example, the first end 56e1 is separated from the first edge 51he1 of the opening 51h of the solder resist layer 51. Similarly, the second end 56e2 is separated from the second edge 51he2 of the opening 51h of the solder resist layer 51.

[0093] Even with this configuration, the provision of the insulating portion 55 makes it easier to prevent the bonding material H connecting the first terminal 62A to the first pad 42A and the bonding material H connecting the second terminal 62B to the second pad 42B from being connected via the insulating portion 55. This can help prevent manufacturing defects in the substrate unit 20.

[0094] In this embodiment, at least one of the first end 56e1 and the second end 56e2 in the Y direction of the insulating portion 55 is spaced from the edge 51he of the opening 51h of the solder resist layer 51. This configuration makes it easier to form the insulating portion 55 within the opening 51h of the solder resist layer 51. This improves the manufacturability of the substrate unit 20.

[0095] (Third embodiment)

[0096] Next, the third embodiment will be described. The third embodiment differs from the first embodiment in that an insulating portion 131 is provided instead of or in addition to the insulating portion 55. The configuration other than that described below is the same as that of the first embodiment.

[0097] Figure 83 is a cross-sectional view showing a portion of the substrate 21 according to the third embodiment. In this embodiment, the conductive pattern 40 on the surface portion of the substrate 21 includes a conductive layer 111 and second pads 42B.

[0098] (Conductive layer)

[0099] The conductive layer 111 is a conductive portion extending in a plate-like shape in the X and Y directions. The conductive layer 111 is provided on the surface 31s of the insulating substrate 31. The conductive layer 111 is, for example, a power supply layer or a ground layer. The conductive layer 111 includes a first region 111a and a second region 111b. The first region 111a is covered by the second portion 51b of the solder resist layer 51. On the other hand, the second region 111b is not covered by the solder resist layer 51. When viewed from the Z direction, the second region 111b is located within the opening 51h of the solder resist layer 51. The conductive layer 111 has a surface 111s located on the opposite side of the insulating substrate 31. The surface 111s extends in the X and Y directions.

[0100] The second region 111b includes the first pad 42A and a non-pad portion 121. The non-pad portion 121 is disposed between the first pad 42A and the first region 111a, and is a portion connecting the first pad 42A and the first region 111a.

[0101] Figure 9 It is along Figure 8 is a cross-sectional view of substrate 21 taken along line F9-F9 shown in FIG. In this embodiment, first region 111a of conductive layer 111 includes first portion 112a and second portion 112b. First portion 112a is a portion aligned with first pad 42A in the X direction. First portion 112a is located on the opposite side of second pad 42B relative to first pad 42A in the X direction. On the other hand, second portion 112b is a portion aligned with first pad 42A in the Y direction. In this embodiment, first portion 112a and second portion 112b are integrally formed. Alternatively, first region 111a may include only one of first portion 112a and second portion 112b.

[0102] As described above, second region 111b of conductive layer 111 includes first pad 42A and non-pad portion 121. First pad 42A is a region symmetrical to second pad 42B in second region 111b of conductive layer 111. Non-pad portion 121 is a region disposed between first pad 42A and first region 111a.

[0103] In this embodiment, the non-pad portion 121 includes a first portion 121a and a second portion 121b. The first portion 121a is located between the first portion 112a of the first region 111a of the conductive layer 111 and the first pad 42A in the X direction. The first portion 121a extends in the Y direction. Meanwhile, the second portion 121b is located between the second portion 112b of the first region 111a of the conductive layer 111 and the first pad 42A in the Y direction. The second portion 121b extends in the X direction. In this embodiment, the first portion 121a and the second portion 121b are integrally formed. This results in an L-shaped non-pad portion 121.

[0104] (Insulation part)

[0105] Next, the insulating portion 131 will be described. The insulating portion 131 is an example of a "second insulating portion." The insulating portion 131 is provided on the surface 111s of the conductive layer 111. The insulating portion 131 is provided on the non-pad portion 121. When viewed from the Z direction, the insulating portion 131 is provided between a portion of the edge 51he of the opening 51h of the solder resist layer 51 and the electronic component 25.

[0106] In this embodiment, the insulating portion 131 includes a first portion 131a and a second portion 131b. The first portion 131a is provided on the first portion 121a of the non-pad portion 121. The first portion 131a is provided in the X-direction between the edge 51he of the opening 51h of the solder resist layer 51 and the electronic component 25. The first portion 131a extends in the Y-direction. On the other hand, the second portion 131b is provided on the second portion 121b of the non-pad portion 121. The second portion 131b is provided in the Y-direction between the edge 51he (e.g., the first edge 51he1) of the opening 51h of the solder resist layer 51 and the electronic component 25. The second portion 131b extends in the X-direction. In this embodiment, the first portion 131a and the second portion 131b are formed integrally. Thus, an L-shaped insulating portion 131 is formed. By providing the insulating portion 131 , only the region corresponding to the first pad 42A in the non-pad portion 121 is exposed to the outside of the substrate 21 , and can be bonded to the bonding material H.

[0107] Then, return Figure 8 , the thickness T131 of the insulating portion 131 will be described. The insulating portion 131 has a thickness (eg, maximum thickness) T131 as a thickness in the Z direction. In a cross section taken along the Z direction ( Figure 8When viewed in the cross-section shown in FIG. 1 , the insulating portion 131 has an end 131e located on the opposite side of the insulating substrate 31. The thickness T131 of the insulating portion 131 in the Z direction corresponds to the height of the end 131e of the insulating portion 131 relative to the surface 111s of the conductive layer 111. In this embodiment, the thickness T131 of the insulating portion 131 in the Z direction (e.g., maximum thickness) is smaller than the thickness T51 of the solder resist layer 51 in the Z direction (e.g., maximum thickness). More specifically, the thickness T131 of the insulating portion 131 in the Z direction (e.g., maximum thickness) is smaller than the thickness T51b of the second portion 51b of the solder resist layer 51 in the Z direction (e.g., maximum thickness).

[0108] Insulating portion 131 includes the second insulating material. Similar to insulating portion 55, insulating portion 131 is formed by applying the second insulating material onto insulating substrate 31 using an inkjet method, for example, and curing the applied second insulating material by ultraviolet light exposure or the like. The curing method for the second insulating material is not limited to the method described above; heating or the like may also be used.

[0109] Here, as a second comparative example, a configuration without insulating portion 131 is considered. In the second comparative example, the shape of second region 111b of conductive layer 111 differs from the shape of second pad 42B when viewed from the Z direction. Therefore, during the reflow process, electronic component 25 may be displaced from its proper position (e.g., due to rotation).

[0110] Meanwhile, in this embodiment, the substrate 21 includes an insulating portion 131 made of a second insulating material, disposed between a portion of the edge 51he of the opening 51h of the solder resist layer 51 and the electronic component 25. With this configuration, for example, the positional deviation range of the electronic component 25 is limited by the insulating portion 131. This helps prevent manufacturing defects in the substrate unit 20.

[0111] In this embodiment, the conductive layer 111 includes a first region 111a covered by the solder resist layer 51, and a second region 111b disposed within the opening 51h of the solder resist layer 51 and including the first pad 42A. The insulating portion 131 is provided on the conductive layer 111 within the opening 51h of the solder resist layer 51. With this configuration, the provision of the insulating portion 131 limits the area of ​​the second region 111b of the conductive layer 111 that is bonded to the bonding material H. This allows the shapes of the first pad 42A and the second pad 42B to be aligned, further suppressing positional deviations of the electronic component 25. This further reduces manufacturing defects in the substrate unit 20.

[0112] In this embodiment, the thickness (e.g., maximum thickness) T131 of the insulating portion 131 in the Z direction is smaller than the thickness (e.g., maximum thickness) T51b of the second portion 51b of the solder resist layer 51 in the Z direction. This configuration prevents the insulating portion 131 from protruding from the surface 51s of the solder resist layer 51. This improves the manufacturability of the substrate unit 20 and / or reduces the thickness of the substrate unit 20.

[0113] (Fourth embodiment)

[0114] Next, the fourth embodiment will be described. The fourth embodiment differs from the first embodiment in that an insulating portion 55 is provided corresponding to the BGA (Ball Grid Array) pad 42. The configuration other than that described below is the same as that of the first embodiment.

[0115] Figure 10 This is a cross-sectional view showing a portion of substrate unit 20 according to the fourth embodiment. In this embodiment, electronic component 25 is a BGA-type semiconductor package. Electronic component 25 has multiple terminals 62. Terminals 62 are arranged in a grid pattern in the X and Y directions. Each terminal 62 is bonded to a solder ball, or bonding material H.

[0116] In this embodiment, the substrate 21 has a plurality of pads 42 corresponding to a BGA-type solder package. The pads 42 are provided on the surface 31s of the insulating substrate 31. The pads 42 are arranged in a grid pattern in the X and Y directions. Each pad 42 is connected to a terminal 62 of the electronic component 25 via a bonding material H.

[0117] Figure 11 It is along Figure 10 , a cross-sectional view of the substrate 21 taken along line F11-F11 is shown in FIG. In this embodiment, the insulating portion 55 is provided between the plurality of pads 42. The insulating portion 55 includes, for example, a plurality of insulating portions 55A and a plurality of insulating portions 55B. Each of the plurality of insulating portions 55A is arranged between two adjacent pads 42 in the X direction. Each of the plurality of insulating portions 55A extends in the Y direction between the plurality of pads 42 arranged in two rows. On the other hand, each of the plurality of insulating portions 55B is arranged between two adjacent pads 42 in the Y direction. Each of the plurality of insulating portions 55B extends in the X direction between the plurality of pads 42 arranged in two rows.

[0118] According to this configuration, it is possible to suppress the bonding material H from connecting between the plurality of pads 42 and causing a short circuit. This can thereby suppress the occurrence of manufacturing defects in the substrate unit 20.

[0119] Several embodiments have been described above. However, the embodiments are not limited to the examples described above. For example, the multiple embodiments described above can be combined to achieve the desired effect.

[0120] According to at least one embodiment described above, a substrate unit comprises an insulating base material, a first solder pad, a second solder pad, a solder resist layer, a first insulating portion, and an electronic component. The solder resist layer has an opening that exposes the first solder pad and the second solder pad. The first insulating portion is arranged between the first solder pad and the second solder pad within the opening. The solder resist layer comprises a first insulating material. The first insulating portion comprises a second insulating material that is different from the first insulating material. When the direction from the first solder pad toward the insulating base material is set as the first direction, the thickness of the first insulating portion in the first direction is greater than the thickness of the first solder pad in the first direction. According to this configuration, it is possible to suppress the occurrence of manufacturing defects in the substrate unit.

[0121] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, replaced, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are intended to be within the scope and spirit of the invention and are also intended to be within the scope of the invention as described in the claims and their equivalents.

[0122] [Explanation of Symbols]

[0123] 1 Semiconductor memory device

[0124] 10 Housing

[0125] 20 substrate units

[0126] 21 substrate

[0127] 25 electronic components

[0128] 31 Insulation substrate

[0129] 31s Surface of insulating substrate (first side)

[0130] 40 conductive pattern

[0131] 41 Wiring

[0132] 42 pads

[0133] 42A 1st pad

[0134] 42B 2nd pad

[0135] 51 solder resist layer

[0136] 51h Opening of solder resist layer

[0137] 51he Edge of the opening in the solder resist layer

[0138] 55 Insulation part (first insulation part)

[0139] 56e1 First end of the insulating portion in the Y direction

[0140] 56e2 Second end of the insulating portion in the Y direction

[0141] 61 Part body

[0142] 62 terminals

[0143] 62A Terminal 1

[0144] 62B 2nd terminal

[0145] 111 conductive layer

[0146] 111a: first region of the conductive layer

[0147] 111b Second region of the conductive layer

[0148] 131 Insulating portion (second insulating portion).

Claims

1. A substrate unit comprising: Insulation substrate; a first pad, disposed on the insulating substrate; a second pad, disposed on the insulating substrate; a solder resist layer including a portion provided on the insulating substrate and having an opening for exposing the first pad and the second pad; a first insulating portion provided between the first pad and the second pad in the opening; and an electronic component having a first terminal connected to the first pad via a bonding material, and a second terminal connected to the second pad via a bonding material; and The solder resist layer comprises a first insulating material; The first insulating portion includes a second insulating material different from the first insulating material; When a direction from the first pad toward the insulating substrate is defined as a first direction, a length of the first insulating portion in the first direction is greater than a length of the first pad in the first direction.

2. The substrate unit according to claim 1, wherein The insulating substrate has a first surface; The first pad and the first insulating portion are provided on the first surface; The first pad has a first end located on the opposite side of the first surface; The first insulating portion has a second end located on the opposite side of the first surface; and A height of the second end of the first insulating portion relative to the first surface is greater than a height of the first end of the first pad relative to the first surface.

3. The substrate unit according to claim 1 or claim 2, further comprising: wiring, disposed on the insulating substrate; and The solder resist layer includes a first portion in contact with the insulating base material and a second portion covering the wiring; The length of the first insulating portion in the first direction is smaller than the length of the first portion of the solder resist layer in the first direction.

4. The substrate unit according to claim 1 or claim 2, wherein The first insulating portion is formed by applying the second insulating material by inkjet method and curing the second insulating material.

5. The substrate unit according to claim 1 or claim 2, wherein When a direction from the first pad toward the second pad is defined as a second direction and a direction intersecting the first direction and the second direction is defined as a third direction, The first insulating portion has an end in the third direction, that is, a third end, and the third end is in contact with the solder resist layer.

6. The substrate unit according to claim 1 or claim 2, wherein When a direction from the first pad toward the second pad is defined as a second direction and a direction intersecting the first direction and the second direction is defined as a third direction, The first insulating portion has an end in the third direction, that is, a third end, and the third end is spaced apart from an edge of the opening.

7. The substrate unit according to claim 1 or claim 2, further comprising: The second insulating portion is provided between a portion of an edge of the opening and the electronic component when viewed from the first direction, and includes the second insulating material.

8. The substrate unit according to claim 7, further comprising: a conductive layer having a first region covered by the solder resist layer and a second region disposed in the opening and including the first pad; and The second insulating portion is provided on the conductive layer in the opening.

9. The substrate unit according to claim 8, wherein The solder resist layer includes a first portion in contact with the insulating base material and a second portion covering the first region of the conductive layer; and The length of the second insulating portion in the first direction is smaller than the length of the second portion of the solder resist layer in the first direction.

10. The substrate unit according to claim 1 or claim 2, wherein The electronic component is a rectangular component when viewed from the first direction; and The width of the long side of the electronic component is less than 0.4 mm; The width of the short side of the electronic component is 0.2 mm or less.

11. A substrate unit comprising: Insulation substrate; a first pad, disposed on the insulating substrate; a second pad, disposed on the insulating substrate; Wiring, disposed on the insulating substrate; a solder resist layer including a first portion in contact with the insulating base material and a second portion covering the wiring, and having an opening for exposing the first pad and the second pad; a first insulating portion provided between the first pad and the second pad in the opening; and an electronic component having a first terminal connected to the first pad via a bonding material, and a second terminal connected to the second pad via a bonding material; and When a direction from the first pad toward the insulating base is defined as a first direction, a length of the first insulating portion in the first direction is smaller than a length of the first portion of the solder resist layer in the first direction.

12. A substrate unit comprising: Insulation substrate; a first pad, disposed on the insulating substrate; a second pad, disposed on the insulating substrate; a solder resist layer including a portion provided on the insulating substrate and having an opening for exposing the first pad and the second pad; an electronic component having a first terminal connected to the first pad via a bonding material, and a second terminal connected to the second pad via a bonding material; and an insulating portion provided between a portion of an edge of the opening and the electronic component when viewed from a direction from the first pad toward the insulating substrate, that is, a first direction; and The solder resist layer comprises a first insulating material; The insulating portion includes a second insulating material different from the first insulating material; The length of the insulating portion in the first direction is smaller than the length of the solder resist layer in the first direction.

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