PAM4 signal automatic gain control circuit and automatic gain control method
By introducing a waveform generator and a second peak detector into the AGC circuit, the problem of insufficient gain control accuracy in PAM4 signal processing in traditional AGC systems is solved, achieving higher-precision gain control and reducing the bit error rate.
Patent Information
- Application Number
- CN202510869400.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-26
- Publication Date
- 2025-09-16
AI Technical Summary
Traditional AGC systems have difficulty maintaining stable gain control accuracy when processing PAM4 signals, resulting in system bit error rate degradation, mainly due to the nonlinear characteristics and temperature dependence of the peak detector.
A waveform generator and a second peak detector are introduced into the traditional AGC circuit to generate a PAM4 type high-speed AC signal equal to the input clock period. The outputs of the two peak detectors are compared through an operational amplifier to eliminate nonlinearity and temperature dependence.
The accuracy of PAM4 signal gain control is improved, the system bit error rate is reduced, and the stable performance of CDR is ensured.
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Figure CN120658223A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of communication technology, and in particular to a PAM4 signal automatic gain control circuit and an automatic gain control method. Background Art
[0002] With the rapid development of high-speed data communication technology, PAM4 (4-level Pulse Amplitude Modulation) signals are widely adopted in next-generation communication systems due to their high transmission efficiency. Compared to traditional NRZ (Non-Return-to-Zero) signals, PAM4 signals transmit data using four different levels, allowing two bits of information to be transmitted per symbol period, significantly increasing data rates. In high-speed scenarios such as optical modules and data center interconnects, PAM4 technology has become a key solution for achieving transmission rates of 100 Gbps and above.
[0003] In practical applications, PAM4 receivers typically include clock and data recovery (CDR) circuits, whose performance is directly affected by the input signal amplitude. Due to factors such as channel loss and transmission distance variations, the receiver may encounter input signals with a wide dynamic range, ranging from millivolts to volts. When the signal amplitude exceeds the CDR's optimal operating range, the symbol decision error rate increases, seriously affecting the system's bit error rate performance. Therefore, precise automatic gain control (AGC) technology is crucial to ensuring PAM4 system reliability.
[0004] Traditional AGC systems use a peak detector as a core feedback element. This device adjusts the gain of the variable-gain amplifier by detecting the peak-to-peak value of the input signal. However, peak detectors have inherent nonlinear characteristics: their output voltage is significantly non-proportional to the input amplitude, resulting in significant differences in conversion efficiency when processing signals of varying amplitudes. Consequently, traditional AGC systems struggle to maintain stable gain control accuracy when processing PAM4 signals, ultimately leading to a degradation in the system's bit error rate. Summary of the Invention
[0005] In view of this, the purpose of this application is to provide a PAM4 signal automatic gain control circuit and automatic gain control method. A waveform generator is introduced into a traditional automatic gain control circuit to generate a PAM4 type high-speed AC signal with a symbol period equal to (or proportional to) the input clock clk period. The signal generated by the waveform generator is used as a reference for the output signal of the variable gain amplifier, so that the amplitude of the variable gain amplifier output signal is equal to the amplitude of the signal generated by the waveform generator. In addition, a second peak detector is added to the automatic gain control loop. The conversion efficiency of the two peak detectors is equal, so their outputs can be directly compared, which can eliminate the nonlinearity and temperature dependence of a single peak detector and improve the accuracy of gain control for PAM4 signals.
[0006] In a first aspect, an embodiment of the present application provides a PAM4 signal automatic gain control circuit, the PAM4 signal automatic gain control circuit including a gain control initial circuit, the gain control initial circuit including a variable gain amplifier, a first peak detector, an operational amplifier, a digital-to-analog converter, and a clock data recovery module; the PAM4 signal automatic gain control circuit also includes a second peak detector and a waveform generator, the second peak detector and the waveform generator are both provided on the gain control initial circuit, wherein; The output of the variable gain amplifier is connected to the input of the first peak detector, the negative input of the operational amplifier is connected to the output of the first peak detector, the positive input of the operational amplifier is connected to the output of the second peak detector, the input of the second peak detector is connected to the output of the waveform generator, the input of the waveform generator is connected to the output of the digital-to-analog converter, the output of the operational amplifier is connected to the control end of the variable gain amplifier, and the clock data recovery module is connected to the waveform generator via a voltage-controlled oscillator.
[0007] Furthermore, the PAM4 signal automatic gain control circuit also includes a selector, a comparator and a digital calibration logic circuit; the selector, the comparator and the digital calibration logic circuit are all arranged on the gain control initial circuit; wherein, The output end of the variable gain amplifier and the first output end of the digital calibration logic circuit are respectively connected to the input end of the selector, the output end of the selector is connected to the input end of the first peak detector, the output end of the first peak detector is connected to the negative input end of the comparator, the output end of the digital-to-analog converter is connected to the positive input end of the comparator, the output end of the comparator is connected to the input end of the digital calibration logic circuit, and the second output end of the digital calibration logic circuit is connected to the input end of the digital-to-analog converter.
[0008] Furthermore, the selector controls the switching of the input signal source according to the selection signal output by the digital calibration logic circuit.
[0009] Furthermore, when the selection signal is logic 0, the selector selects the externally input PAM4 signal as the input signal of the first peak detector; when the selection signal is logic 1, the selector selects the output signal of the variable gain amplifier as the input signal of the first peak detector.
[0010] Furthermore, the digital calibration logic circuit also includes a temperature sensor and a temperature lookup table for recording calibration data under different ambient temperatures; The data in the temperature lookup table is used to adjust the output of the digital-to-analog converter in a normal operating mode to compensate for the effect of temperature changes on the first peak detector.
[0011] In a second aspect, an embodiment of the present application further provides a PAM4 signal automatic gain control method, which is applied to a PAM4 signal automatic gain control circuit. The PAM4 signal automatic gain control method includes: Controlling the variable gain amplifier to receive an input signal and adjust the amplitude of the input signal; controlling the first peak detector to detect the peak-to-peak value of the input signal and generate a first DC signal; Controlling the waveform generator to generate a reference signal corresponding to the peak-to-peak value; controlling the second peak detector to detect the peak-to-peak value of the reference signal and generate a second DC signal; The control operational amplifier compares a difference between the first DC signal and the second DC signal, and adjusts a gain of the variable gain amplifier according to the difference.
[0012] Furthermore, the symbol period of the reference signal generated by the waveform generator is equal to or in a preset proportion to the period of the clock signal of the clock data recovery module, and the conversion frequency of the first peak detector is the same as the conversion efficiency of the second peak detector.
[0013] Furthermore, the PAM4 signal automatic gain control method further includes: Obtaining a preset threshold voltage, and converting the input signal into a target signal based on the preset threshold voltage; Adjust the chip ambient temperature to the calibration temperature point through a high and low temperature box; Setting the output analog signal of the digital calibration logic circuit to a preset value, the reference voltage signal of the digital-to-analog converter to a minimum value, and the selector using the target signal as the input of the first peak detector; Using a linear search algorithm or a binary search algorithm to adjust the control word of the digital-to-analog converter so that the reference voltage signal output by the digital-to-analog converter is equal to the DC signal output by the first peak detector, and recording calibration data corresponding to the calibration temperature point; Changing the chip ambient temperature, and returning to the step of adjusting the chip ambient temperature to the calibration temperature point by using the high and low temperature box, until the calibration data recording of all calibration temperature points is completed to obtain a temperature lookup table; The output signal of the selector is switched, and the output of the digital-to-analog converter is controlled using the temperature lookup table to achieve automatic gain control.
[0014] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the above-mentioned PAM4 signal automatic gain control method are performed.
[0015] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned PAM4 signal automatic gain control method are executed.
[0016] The present application provides a PAM4 signal automatic gain control circuit and automatic gain control method. The PAM4 signal automatic gain control circuit includes a gain control initial circuit, a second peak detector, and a waveform generator. The second peak detector and the waveform generator are both arranged on the gain control initial circuit, wherein: the output end of the variable gain amplifier is connected to the input end of the first peak detector, the negative input end of the operational amplifier is connected to the output end of the first peak detector, the positive input end of the operational amplifier is connected to the output end of the second peak detector, the input end of the second peak detector is connected to the output end of the waveform generator, the input end of the waveform generator is connected to the output end of the digital-to-analog converter, the output end of the operational amplifier is connected to the control end of the variable gain amplifier, and the clock data recovery module is connected to the waveform generator through a voltage-controlled oscillator.
[0017] This application introduces a waveform generator into a conventional automatic gain control circuit, capable of generating a PAM4-type high-speed AC signal with a symbol period equal to (or proportional to) the input clock period (clk), and a peak-to-peak value equal to vref. The waveform generator's signal serves as a reference for the variable gain amplifier's output signal, ensuring that the amplitude of the variable gain amplifier's output signal is equal to the amplitude of the waveform generator's signal. Furthermore, a second peak detector is added to the automatic gain control loop. The conversion efficiencies Kpkd of the two peak detectors are equal, allowing their outputs to be directly compared. This eliminates the nonlinearity and temperature dependence of a single peak detector, improving the accuracy of gain control for PAM4 signals.
[0018] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.
[0020] Figure 1 Schematic diagram of the structure of a traditional automatic gain control circuit in the prior art; Figure 2 This is one of the structural diagrams of a PAM4 signal automatic gain control circuit provided in an embodiment of the present application; Figure 3 This is a second structural diagram of a PAM4 signal automatic gain control circuit provided in an embodiment of the present application; Figure 4 A flowchart of a PAM4 signal automatic gain control method provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work falls within the scope of protection of the present application.
[0022] First, the application scenarios to which this application is applicable are introduced. This application can be applied in the field of communication technology.
[0023] With the rapid development of high-speed data communication technology, PAM4 (4-level Pulse Amplitude Modulation) signals are widely adopted in next-generation communication systems due to their high transmission efficiency. Compared to traditional NRZ (Non-Return-to-Zero) signals, PAM4 signals transmit data using four different levels, allowing two bits of information to be transmitted per symbol period, significantly increasing data rates. In high-speed scenarios such as optical modules and data center interconnects, PAM4 technology has become a key solution for achieving transmission rates of 100 Gbps and above.
[0024] In practical applications, PAM4 receivers typically include clock and data recovery (CDR) circuits, whose performance is directly affected by the input signal amplitude. Due to factors such as channel loss and transmission distance variations, the receiver may encounter input signals with a wide dynamic range, ranging from millivolts to volts. When the signal amplitude exceeds the CDR's optimal operating range, the symbol decision error rate increases, seriously affecting the system's bit error rate performance. Therefore, precise automatic gain control (AGC) technology is crucial to ensuring PAM4 system reliability.
[0025] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the structure of a conventional automatic gain control circuit in the prior art. Figure 1As shown in the figure, in traditional automatic gain control implementations, the high-speed AC signal VA output by the VGA passes through a peak detector to generate a DC signal Vpkd. The magnitude of Vpkd is proportional to the peak-to-peak value (Vamp) of VA. Traditional AGC systems use a peak detector as a core feedback element, which adjusts the gain of the variable gain amplifier by detecting the peak-to-peak value of the input signal. However, the peak detector has inherent nonlinear characteristics: its output voltage is significantly non-proportional to the input amplitude, resulting in significant differences in conversion efficiency when processing signals of varying amplitudes. As a result, traditional AGC systems struggle to maintain stable gain control accuracy when processing PAM4 signals, ultimately leading to a degradation in the system's bit error rate.
[0026] Based on this, an embodiment of the present application provides a PAM4 signal automatic gain control circuit to improve the accuracy of gain control for PAM4 signals.
[0027] See also Figure 2 , Figure 2 This is one of the structural diagrams of a PAM4 signal automatic gain control circuit provided in an embodiment of the present application. Figure 2 As shown in , the PAM4 signal automatic gain control circuit 100 provided in an embodiment of the present application includes a gain control initial circuit 110, which includes a variable gain amplifier (VGA) 111, a first peak detector (PeakDetector1, PKD1) 112, an operational amplifier (OPA) 113, a digital-to-analog converter (DAC) 114 and a clock data recovery module (CDR) 115; the PAM4 signal automatic gain control circuit 100 also includes a second peak detector 120 (PeakDetector2, PKD2) and a waveform generator (Programable Wave Generator, PWG) 130, and the second peak detector 120 and the waveform generator 130 are both arranged on the gain control initial circuit 110.
[0028] Specifically, the output end of the variable gain amplifier 111 is connected to the input end of the first peak detector 112, the negative input end of the operational amplifier 113 is connected to the output end of the first peak detector 112, the positive input end of the operational amplifier 113 is connected to the output end 120 of the second peak detector, the input end of the second peak detector 120 is connected to the output end of the waveform generator 130, the input end of the waveform generator 130 is connected to the output end of the digital-to-analog converter 114, the output end of the operational amplifier 113 is connected to the control end of the variable gain amplifier 111, and the clock data recovery module 115 is connected to the waveform generator 130 through a voltage-controlled oscillator VCO.
[0029] Thus, the PAM4 signal automatic gain control circuit provided in this application replicates a second peak detector 120 based on a conventional automatic gain control circuit and adds a programmable waveform generator 130. Waveform generator 130 generates a PAM4-type high-speed AC signal with a symbol period equal to (or proportional to) the input clock clk period and a peak-to-peak value equal to vref. In this application, waveform generator 130 receives a clock signal from a VCO (or other clock signals) and a DC reference voltage Vdac from a digital-to-analog converter 114, and outputs a generated data signal (Generated Data) to the input port of the second peak detector 120.
[0030] Second peak detector 120 receives the high-speed AC signal from waveform generator 130 and converts it into a DC signal Vpkg. The conversion efficiency of second peak detector 120 is the same as that of first peak detector 112, which is Kpkd. Since first and second peak detectors 112 and 120 use the same circuitry and their input signals are PAM4 signals with similar rates, Vpkg = Kpkd * Vdac, where Vpkg is connected to the positive input of the operational amplifier. When the loop stabilizes, Vpkd and Vpkg become equal. At this point, Vpkd = Kpkd * Vamp = Vpkg = Kpkd * Vdac; Vamp = Vdac, thus making Vamp independent of Kpkd and eliminating the nonlinearity and temperature dependence introduced by the peak converter. Setting the threshold voltage Vth of clock-data recovery module 115 to one-third of Vdac allows for precise matching of the threshold voltage with the data signal amplitude, helping the comparator in clock-data recovery module 115 accurately discriminate the data signal level.
[0031] In specific implementations, waveform generator 130 generates a reference signal whose peak-to-peak value is set by Vdac. This reference signal is fed into the second peak detector (PeakDetector2), generating a DC signal, Vpkg. Simultaneously, the first peak detector (PeakDetector1) detects the peak-to-peak value of the VGA output signal, generating another DC signal, Vpkd. These two signals are fed into an operational amplifier for comparison, and the output of the operational amplifier serves as the VGA gain control signal, Vctrl. When the system is stable, Vpkd equals Vpkg, ensuring that the amplitude of the VGA output signal precisely matches the amplitude of the reference signal.
[0032] By introducing a waveform generator 130, this application can generate a PAM4-type high-speed AC signal with a symbol period equal to (or proportional to) the input clock clk period and a peak-to-peak value equal to vref. The signal generated by waveform generator 130 is used as a reference for the output signal of variable gain amplifier 111, so that the amplitude of the output signal of variable gain amplifier 111 is equal to the amplitude of the signal generated by waveform generator 130. In addition, a second peak detector 120 is added to the AGC control loop. The conversion efficiency Kpkd of the two peak detectors is equal, so their outputs can be directly compared. In this way, the nonlinearity and temperature dependence of a single peak detector can be eliminated, ensuring that the amplitude of the signal output by variable gain amplifier 111 is precisely equal to the amplitude of the reference signal, thereby improving the accuracy of gain control for PAM4 signals.
[0033] See also Figure 3 , Figure 3 This is a second structural diagram of a PAM4 signal automatic gain control circuit provided in an embodiment of the present application. Figure 3 As shown in , the PAM4 signal automatic gain control circuit 100 further includes a selector 140 (MUX), a comparator (CMP) 150 and a digital calibration logic circuit (Calibrate Logic) 160; the selector 140, the comparator 150 and the digital calibration logic circuit 160 are all arranged on the gain control initial circuit 110.
[0034] Specifically, the output end of the variable gain amplifier 111 and the first output end of the digital calibration logic circuit 160 are respectively connected to the input end of the selector 140, the output end of the selector 140 is connected to the input end of the first peak detector 112, the output end of the first peak detector 112 is connected to the negative input end of the comparator 150, the output end of the digital-to-analog converter 114 is connected to the positive input end of the comparator 150, the output end of the comparator 150 is connected to the input end of the digital calibration logic circuit 160, and the second output end of the digital calibration logic circuit 160 is connected to the input end of the digital-to-analog converter 114.
[0035] Thus, according to another embodiment of the present application, a PAM4 automatic gain control circuit 100 is provided, which adds a selector 140, a comparator 150, and a digital calibration logic circuit 160 to a conventional automatic gain control circuit. The selector 140 is used to switch between an ideal external PAM4 signal and an actual input signal.
[0036] Specifically, the selector 140 controls the switching of the input signal source according to the selection signal output by the digital calibration logic circuit 160. When the selection signal is logic 0, the selector 140 selects the externally input PAM4 signal as the input signal of the first peak detector 112; when the selection signal is logic 1, the selector 140 selects the output signal of the variable gain amplifier 111 as the input signal of the first peak detector 112.
[0037] Here, selector 140 is used to select the input signal of first peak detector 112. When signal sel is logic 0, selector 140 selects external input signal VI as the input of first peak detector 112. When signal sel is logic 1, selector 140 selects output signal VA of variable gain amplifier 111 (i.e., CDR input signal) as the input of first peak detector 112. Comparator 150 is used to compare Vpkd and Vdac. When Vdac is less than Vpkd, it outputs logic 0; otherwise, it outputs logic 1. Digital calibration logic circuit 160 receives the output signal of comparator 150 as an indicator of calibration completion. Digital calibration logic circuit 160 outputs selection signal sel, which is used to control selector 140.
[0038] Furthermore, the digital calibration logic circuit 160 also includes a temperature sensor and a temperature lookup table for recording calibration data under different ambient temperatures; the data in the temperature lookup table is used to adjust the output of the digital-to-analog converter in normal operating mode to compensate for the impact of temperature changes on the first peak detector.
[0039] Here, digital calibration logic circuit 160 includes a temperature sensor and a multi-byte temperature lookup table for recording calibration data at different ambient temperatures. Digital calibration logic circuit 160 outputs the control word from digital-to-analog converter 114, which, after digital-to-analog conversion, generates the positive input signal Vdac for variable gain amplifier 111 and comparator 150.
[0040] Thus, in the PAM4 automatic gain control circuit provided in another embodiment of the present application, when the chip is operating normally, the PAM4 automatic gain control circuit automatically adjusts the gain of the signal path so that the conversion result of the CDR input signal after passing through the first peak detector 112 is consistent with the result recorded in the temperature lookup table. At this time, the amplitude of the CDR input signal is equal to the amplitude of the external ideal PAM4 signal. This eliminates the nonlinearity and temperature dependence of the single peak detector and achieves precise control of the PAM4 CDR input signal. In addition, the introduction of the temperature lookup table adapts to temperature changes in different working environments, improves the performance of the CDR comparator, and significantly reduces the bit error rate of the system.
[0041] The PAM4 signal automatic gain control circuit provided in the present application includes a gain control initial circuit, and also includes a second peak detector and a waveform generator. The second peak detector and the waveform generator are both arranged on the gain control initial circuit, wherein; the output end of the variable gain amplifier is connected to the input end of the first peak detector, the negative input end of the operational amplifier is connected to the output end of the first peak detector, the positive input end of the operational amplifier is connected to the output end of the second peak detector, the input end of the second peak detector is connected to the output end of the waveform generator, the input end of the waveform generator is connected to the output end of the digital-to-analog converter, the output end of the operational amplifier is connected to the control end of the variable gain amplifier, and the clock data recovery module is connected to the waveform generator through a voltage-controlled oscillator.
[0042] This application introduces a waveform generator into a conventional automatic gain control circuit, capable of generating a PAM4-type high-speed AC signal with a symbol period equal to (or proportional to) the input clock period (clk), and a peak-to-peak value equal to vref. The waveform generator's signal serves as a reference for the variable gain amplifier's output signal, ensuring that the amplitude of the variable gain amplifier's output signal is equal to the amplitude of the waveform generator's signal. Furthermore, a second peak detector is added to the automatic gain control loop. The conversion efficiencies Kpkd of the two peak detectors are equal, allowing their outputs to be directly compared. This eliminates the nonlinearity and temperature dependence of a single peak detector, improving the accuracy of gain control for PAM4 signals.
[0043] See also Figure 4 , Figure 4 This is a flow chart of a PAM4 signal automatic gain control method provided in an embodiment of the present application. The PAM4 signal automatic gain control method is applied to the PAM4 signal automatic gain control circuit provided in the above embodiment, such as Figure 4 As shown in , the PAM4 signal automatic gain control method provided by the embodiment of the present application includes: S401 : Control a variable gain amplifier to receive an input signal and adjust the amplitude of the input signal.
[0044] Regarding the above step S401 , in a specific implementation, the variable gain amplifier receives an input signal, adjusts the amplitude of the received input signal, and transmits the input signal to the first peak detector.
[0045] S402: Control a first peak detector to detect the peak-to-peak value of the input signal and generate a first DC signal.
[0046] Regarding the above step S402, in a specific implementation, after receiving the input signal, the first peak detector detects the peak-to-peak value of the input signal to obtain a first DC signal.
[0047] S403: Control the waveform generator to generate a reference signal corresponding to the peak-to-peak value.
[0048] Regarding the above step S403, in a specific implementation, the waveform generator generates a corresponding reference signal based on the peak-to-peak value.
[0049] S404: Control the second peak detector to detect the peak-to-peak value of the reference signal and generate a second DC signal.
[0050] Regarding the above step S404, in a specific implementation, the second peak detector detects the peak-to-peak value of the reference signal generated by the waveform generator and generates a second DC signal.
[0051] S405 , controlling the operational amplifier to compare a difference between the first DC signal and the second DC signal, and adjusting a gain of the variable gain amplifier according to the difference.
[0052] Regarding the above step S405 , in a specific implementation, the operational amplifier compares the difference between the first DC signal and the second DC signal, and adjusts the gain of the variable gain amplifier according to the difference.
[0053] Furthermore, the symbol period of the reference signal generated by the waveform generator is equal to or in a preset proportion to the period of the clock signal of the clock data recovery module, and the conversion frequency of the first peak detector is the same as the conversion efficiency of the second peak detector.
[0054] As an optional embodiment, the PAM4 signal automatic gain control method provided in this application further includes: A: Obtain a preset threshold voltage, and convert the input signal into a target signal based on the preset threshold voltage.
[0055] Regarding step A above, during specific implementation, an appropriate CDR comparator threshold voltage Vth is selected, and the external input signal VI is set to an ideal PAM4 signal with an amplitude of 3·Vth to obtain the target signal.
[0056] B: Adjust the chip ambient temperature to the calibration temperature point through a high and low temperature box.
[0057] Regarding the above step B, during specific implementation, the chip ambient temperature is adjusted to the first calibration temperature point through a high and low temperature box.
[0058] C: setting the output analog signal of the digital calibration logic circuit to a preset value, the reference voltage signal of the digital-to-analog converter to a minimum value, and the selector using the target signal as the input of the first peak detector.
[0059] Regarding step C above, during the specific implementation, at the initial moment, the output dac of the calibration logic circuit is 0, and the output Vdac of the digital-to-analog converter is at the minimum value; the output sel of the calibration logic circuit is 0, and the selector MUX selects the external input signal VI as the input signal of the peak detector PKD. Since Vdac is at its minimum value, which is less than the DC voltage signal Vpkd generated after VI passes through PKD, the comparator CMP outputs a logic 0.
[0060] D: Use a linear search algorithm or a binary search algorithm to adjust the control word of the digital-to-analog converter so that the reference voltage signal output by the digital-to-analog converter is equal to the DC signal output by the first peak detector, and record the calibration data corresponding to the calibration temperature point.
[0061] Regarding the above step D, in the specific implementation, a linear search algorithm is used to adjust the control word of the digital-to-analog converter, and the control word of the DAC is scanned step by step from the least significant bit (LSB) to the most significant bit (MSB). Alternatively, a binary search algorithm is used to scan the control word of the DAC in sequence from the most significant bit (MSB) to the least significant bit (LSB). Ultimately, the reference voltage signal Vdac output by the digital-to-analog converter and the DC signal Vpkd output by the first peak detector are made equal. The calibration data at this temperature is recorded and written into the corresponding temperature lookup table register.
[0062] E: Change the chip ambient temperature, and return to the step of adjusting the chip ambient temperature to the calibration temperature point through the high and low temperature box until the calibration data recording of all calibration temperature points is completed to obtain a temperature lookup table.
[0063] For the above step E, during the specific implementation, change the chip ambient temperature and return to the step B above to adjust the chip ambient temperature to the calibration temperature point through the high and low temperature box until the calibration data records of all calibration temperature points are completed to obtain a complete temperature lookup table.
[0064] F: Switch the output signal of the selector and use the temperature lookup table to control the output of the digital-to-analog converter to achieve automatic gain control.
[0065] Regarding the above step F, in the specific implementation, after completing the above calibration, the output of the logic calibration circuit is controlled by the temperature lookup table, the output sel of the calibration logic circuit is 1, and the selector MUX selects the VGA output signal VA (i.e., the input signal of the CDR) as the input signal of the first peak detector PKD.
[0066] After completing the calibration, the automatic gain control (AGC) loop, aided by the temperature lookup table, automatically controls the VGA gain, ensuring that the CDR input signal amplitude is precisely equal to three times the threshold voltage (Vth). This digital calibration method introduces an external ideal PAM4 signal as the calibration target. The digital calibration logic records the PKD conversion result of an ideal PAM4 signal with an amplitude of 3 Vth using the temperature lookup table. After calibration, the AGC loop automatically adjusts the VGA gain to ensure that the CDR input signal amplitude is equal to that of the ideal PAM4 signal, eliminating the nonlinearity and temperature dependence introduced by the peak converter. During normal operation, the automatic gain control (AGC) circuit automatically adjusts the signal path gain to ensure that the CDR input signal's peak detector conversion result matches the result recorded in the temperature lookup table. At this point, the CDR input signal amplitude equals the external ideal PAM4 signal amplitude. This eliminates the nonlinearity and temperature dependence of a single peak detector and enables precise control of the PAM4 CDR input signal. The digital calibration logic records calibration data at different temperatures in the temperature lookup table.
[0067] The PAM4 signal automatic gain control method provided in the present application controls a variable gain amplifier to receive an input signal and adjust the amplitude of the input signal; controls a first peak detector to detect the peak-to-peak value of the input signal and generate a first DC signal; controls a waveform generator to generate a reference signal corresponding to the peak-to-peak value; controls a second peak detector to detect the peak-to-peak value of the reference signal and generate a second DC signal; and controls an operational amplifier to compare the difference between the first DC signal and the second DC signal, and adjust the gain of the variable gain amplifier according to the difference.
[0068] This application introduces a waveform generator into a conventional automatic gain control circuit, capable of generating a PAM4-type high-speed AC signal with a symbol period equal to (or proportional to) the input clock period (clk), and a peak-to-peak value equal to vref. The waveform generator's signal serves as a reference for the variable gain amplifier's output signal, ensuring that the amplitude of the variable gain amplifier's output signal is equal to the amplitude of the waveform generator's signal. Furthermore, a second peak detector is added to the automatic gain control loop. The conversion efficiencies Kpkd of the two peak detectors are equal, allowing their outputs to be directly compared. This eliminates the nonlinearity and temperature dependence of a single peak detector, improving the accuracy of gain control for PAM4 signals. See also Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 5As shown in FIG, the electronic device 500 includes a processor 510, a memory 520 and a bus 530.
[0069] The memory 520 stores machine-readable instructions executable by the processor 510. When the electronic device 500 is running, the processor 510 communicates with the memory 520 via the bus 530. When the machine-readable instructions are executed by the processor 510, the above-mentioned Figure 4 The steps of the PAM4 signal automatic gain control method in the method embodiment shown are specifically implemented in accordance with the method embodiment and will not be described in detail here.
[0070] The embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the computer program can execute the above-mentioned Figure 4 The steps of the PAM4 signal automatic gain control method in the method embodiment shown are specifically implemented in accordance with the method embodiment and will not be described in detail here.
[0071] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0072] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. There may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interface, indirect coupling or communication connection of devices or units, which may be electrical, mechanical or other forms.
[0073] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.
[0074] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0075] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0076] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-mentioned embodiments within the technical scope disclosed in the present application, or perform equivalent replacements for some of the technical features thereof. These modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A PAM4 signal automatic gain control circuit, characterized in that: The PAM4 signal automatic gain control circuit includes a gain control initial circuit, which includes a variable gain amplifier, a first peak detector, an operational amplifier, a digital-to-analog converter, and a clock data recovery module; the PAM4 signal automatic gain control circuit also includes a second peak detector and a waveform generator, and the second peak detector and the waveform generator are both arranged on the gain control initial circuit, wherein; The output of the variable gain amplifier is connected to the input of the first peak detector, the negative input of the operational amplifier is connected to the output of the first peak detector, the positive input of the operational amplifier is connected to the output of the second peak detector, the input of the second peak detector is connected to the output of the waveform generator, the input of the waveform generator is connected to the output of the digital-to-analog converter, the output of the operational amplifier is connected to the control end of the variable gain amplifier, and the clock data recovery module is connected to the waveform generator via a voltage-controlled oscillator.
2. The PAM4 signal automatic gain control circuit according to claim 1, characterized in that: The PAM4 signal automatic gain control circuit further includes a selector, a comparator and a digital calibration logic circuit; the selector, the comparator and the digital calibration logic circuit are all arranged on the gain control initial circuit; wherein, The output end of the variable gain amplifier and the first output end of the digital calibration logic circuit are respectively connected to the input end of the selector, the output end of the selector is connected to the input end of the first peak detector, the output end of the first peak detector is connected to the negative input end of the comparator, the output end of the digital-to-analog converter is connected to the positive input end of the comparator, the output end of the comparator is connected to the input end of the digital calibration logic circuit, and the second output end of the digital calibration logic circuit is connected to the input end of the digital-to-analog converter.
3. The PAM4 signal automatic gain control circuit according to claim 2, characterized in that: The selector controls the switching of the input signal source according to the selection signal output by the digital calibration logic circuit.
4. The PAM4 signal automatic gain control circuit according to claim 3, characterized in that: When the selection signal is logic 0, the selector selects the externally input PAM4 signal as the input signal of the first peak detector; when the selection signal is logic 1, the selector selects the output signal of the variable gain amplifier as the input signal of the first peak detector.
5. The PAM4 signal automatic gain control circuit according to claim 2, characterized in that: The digital calibration logic circuit also includes a temperature sensor and a temperature lookup table for recording calibration data under different ambient temperatures; The data in the temperature lookup table is used to adjust the output of the digital-to-analog converter in a normal operating mode to compensate for the effect of temperature changes on the first peak detector.
6. A PAM4 signal automatic gain control method, the PAM4 signal automatic gain control method being applied to the PAM4 signal automatic gain control circuit according to any one of claims 1 to 5, characterized in that: The PAM4 signal automatic gain control method includes: Controlling the variable gain amplifier to receive an input signal and adjust the amplitude of the input signal; controlling the first peak detector to detect the peak-to-peak value of the input signal and generate a first DC signal; Controlling the waveform generator to generate a reference signal corresponding to the peak-to-peak value; controlling the second peak detector to detect the peak-to-peak value of the reference signal and generate a second DC signal; The control operational amplifier compares a difference between the first DC signal and the second DC signal, and adjusts a gain of the variable gain amplifier according to the difference.
7. The PAM4 signal automatic gain control method according to claim 6, characterized in that: The symbol period of the reference signal generated by the waveform generator is equal to or in a preset proportion to the period of the clock signal of the clock data recovery module, and the conversion frequency of the first peak detector is the same as the conversion efficiency of the second peak detector.
8. The PAM4 signal automatic gain control method according to claim 6, wherein: The PAM4 signal automatic gain control method further includes: Obtaining a preset threshold voltage, and converting the input signal into a target signal based on the preset threshold voltage; Adjust the chip ambient temperature to the calibration temperature point through a high and low temperature box; Setting the output analog signal of the digital calibration logic circuit to a preset value, the reference voltage signal of the digital-to-analog converter to a minimum value, and the selector using the target signal as the input of the first peak detector; Using a linear search algorithm or a binary search algorithm to adjust the control word of the digital-to-analog converter so that the reference voltage signal output by the digital-to-analog converter is equal to the DC signal output by the first peak detector, and recording calibration data corresponding to the calibration temperature point; Changing the chip ambient temperature, and returning to the step of adjusting the chip ambient temperature to the calibration temperature point by using the high and low temperature box, until the calibration data recording of all calibration temperature points is completed to obtain a temperature lookup table; The output signal of the selector is switched, and the output of the digital-to-analog converter is controlled using the temperature lookup table to achieve automatic gain control.
9. An electronic device, characterized in that: include: A processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to perform the steps of the PAM4 signal automatic gain control method according to any one of claims 6 to 8.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the PAM4 signal automatic gain control method according to any one of claims 6 to 8 are executed.