Hysteresis voltage generation circuit used in low-voltage high-speed environment

Abstract

The invention discloses a hysteresis voltage generation circuit used in a low-voltage high-speed environment. The hysteresis voltage generation circuit comprises a low-voltage hysteresis comparator; the low-voltage hysteresis comparator comprises a main amplifier, a hysteresis voltage generating circuit, an electric leakage eliminating circuit and a Latch speed increasing circuit. The output end of the main amplifier is electrically connected with the input end of the hysteresis voltage generating circuit, and the output end of the hysteresis voltage generating circuit is electrically connected with the input end of the Latch speed increasing circuit; the input end of the main amplifier is used as the input end of the low-voltage hysteresis comparator, and the output end of the Latch speed boosting circuit is used as the output end of the low-voltage hysteresis comparator; the hysteresis voltage generating circuit generates hysteresis voltage of the low-voltage hysteresis comparator, and transmission delay of the low-voltage hysteresis comparator is considered on the premise of low power consumption. The electric leakage eliminating circuit eliminates electric leakage of a low-threshold tube in the main amplifier through pull-down current, and the Latch speed increasing circuit overcomes the defect that a low-power-consumption comparator cannot work in a low-voltage environment or the speed is very low.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a hysteresis voltage generating circuit used in a low-voltage and high-speed environment. Background Art

[0002] In comparator design, to avoid the uncertain effects of environmental noise on the chip, a hysteresis circuit is often incorporated into the comparator to mitigate these effects. In modern electronic systems, circuit design is gradually moving towards lower voltages and lower power consumption. However, low power consumption inevitably results in slower speeds, making it difficult to meet the requirements of some scenarios. Against this backdrop, research on low-voltage, low-power hysteresis comparators is crucial. In low-voltage applications, it is inevitable to use MOS transistors with lower thresholds. However, low-threshold transistors can have significant leakage currents in certain situations, which can significantly impact the circuit itself, especially low-power designs. Therefore, eliminating the impact of MOS transistor leakage current is a key issue. Summary of the Invention

[0003] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a hysteresis voltage generating circuit for use in a low-voltage, high-speed environment. The hysteresis voltage generating circuit is used to generate a hysteresis voltage under low voltage and low power consumption, and a newly constructed latch speed enhancement circuit is introduced. The transmission delay of the low-voltage hysteresis comparator is taken into account under the premise of low power consumption, thereby greatly improving the transmission speed of the comparator.

[0004] Technical solution: To achieve the above-mentioned objectives, the present invention provides a hysteresis voltage generating circuit for use in a low-voltage, high-speed environment, comprising a low-voltage hysteresis comparator; the low-voltage hysteresis comparator comprises a main amplifier, a hysteresis voltage generating circuit, a leakage elimination circuit, and a latch speed enhancement circuit; the output end of the main amplifier is electrically connected to the input end of the hysteresis voltage generating circuit, and the output end of the hysteresis voltage generating circuit is electrically connected to the input end of the latch speed enhancement circuit; the input end of the main amplifier serves as the input end of the low-voltage hysteresis comparator, and the output end of the latch speed enhancement circuit serves as the output end of the low-voltage hysteresis comparator; the hysteresis voltage generating circuit generates a hysteresis voltage for the low-voltage hysteresis comparator, and the leakage elimination circuit eliminates leakage of a low-threshold transistor in the main amplifier by a pull-down current.

[0005] Furthermore, the main amplifier includes an MN1 transistor, an MN2 transistor, an MP1 transistor, an MP2 transistor, an MP3 transistor and an MP4 transistor; the gate input of the MN1 transistor is INN, and the drain of the MN1 transistor is electrically connected to the gate and drain of the MP2 transistor; the gate input of the MN2 transistor is INP, and the drain of the MN2 transistor is electrically connected to the gate and drain of the MP3 transistor; the source of the MN1 transistor and the source of the MN2 transistor are grounded through a constant current source; the gate of the MP1 transistor is electrically connected to the gate of the MP2 transistor, and the gate of the MP4 transistor is electrically connected to the gate of the MP3 transistor.

[0006] Furthermore, the hysteresis voltage generating circuit includes an MN3 transistor, an MN4 transistor, an MN5 transistor, an MN6 transistor, an MN7 transistor and an MN8 transistor; the drain of the MN3 transistor and the drain of the MN6 transistor are electrically connected to the drain of the MP1 transistor, and the drain of the MN7 transistor and the drain of the MN5 transistor are electrically connected to the drain of the MP4 transistor.

[0007] Furthermore, the drain of the MN3 transistor is electrically connected to the gate of the MN3 transistor and the gate of the MN4 transistor, and the gate of the MN4 transistor is electrically connected to the gate of the MN5 transistor; the drain of the MN7 transistor is electrically connected to the gate of the MN7 transistor and the gate of the MN8 transistor, and the gate of the MN8 transistor is electrically connected to the gate of the MN6 transistor; the source of the MN3 transistor is electrically connected to the drain of the MN4 transistor, and the source of the MN7 transistor is electrically connected to the drain of the MN8 transistor.

[0008] Furthermore, the width-to-length ratio of the MN5 transistor is greater than the width-to-length ratio of the MN3 transistor and the MN4 transistor connected in series.

[0009] Furthermore, the leakage elimination circuit includes two groups of pull-down current branches; the drain of the MP1 transistor is grounded through one group of pull-down current branches, and the drain of the MP4 transistor is grounded through the other group of pull-down current branches.

[0010] Furthermore, the two groups of pull-down current branches each include several pull-down current circuits; the several pull-down current circuits each include a control switch and a current source; one end of the control switch is electrically connected to the MP1 transistor or the MP4 transistor, and the other end of the control switch is grounded through the current source.

[0011] Furthermore, the latch speed improvement circuit includes an MP5 transistor and an MP6 transistor; the gate of the MP5 transistor is electrically connected to the source of the MN3 transistor, and the drain of the MP5 transistor is electrically connected to the source of the MN7 transistor through the R1 resistor; the gate of the MP6 transistor is electrically connected to the source of the MN7 transistor, and the drain of the MP6 transistor is electrically connected to the source of the MN3 transistor through the R2 resistor; the drain of the MP6 transistor serves as the output end of the latch speed improvement circuit.

[0012] Beneficial effects: The present invention provides a hysteresis voltage generating circuit for use in a low-voltage, high-speed environment. The hysteresis voltage generating circuit cooperates with a main amplifier to generate a hysteresis voltage, and the leakage of a low-threshold tube in the main amplifier is eliminated through a leakage elimination circuit. The output structure of the newly constructed Latch speed enhancement circuit greatly improves the transmission speed of the comparator, and takes into account the transmission delay of the low-voltage hysteresis comparator under the premise of low power consumption, thereby solving the shortcomings of traditional low-power comparators that cannot work in a low-voltage environment or are very slow. At the same time, when a 5V device is used, it can work in a low-voltage environment of 1.4V, and does not require a large area, thereby saving the circuit area of ​​the low-voltage, low-power hysteresis comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the circuit block diagram of the low voltage hysteresis comparator;

[0014] Figure 2 This is the specific circuit diagram of the low-voltage hysteresis comparator. DETAILED DESCRIPTION

[0015] The present invention will be further described below with reference to the accompanying drawings.

[0016] like Figure 1As shown, a hysteresis voltage generating circuit for use in a low-voltage, high-speed environment includes a low-voltage hysteresis comparator; the low-voltage hysteresis comparator includes a main amplifier 1, a hysteresis voltage generating circuit 2, a leakage elimination circuit 3, and a latch speed enhancement circuit 4; the output end of the main amplifier 1 is electrically connected to the input end of the hysteresis voltage generating circuit 2, and the output end of the hysteresis voltage generating circuit 2 is electrically connected to the input end of the latch speed enhancement circuit 4; the input end of the main amplifier 1 serves as the input end of the low-voltage hysteresis comparator, and the output end of the latch speed enhancement circuit 4 serves as the output end of the low-voltage hysteresis comparator; the hysteresis voltage generating circuit 2 generates a hysteresis voltage for the low-voltage hysteresis comparator, and the leakage elimination circuit 3 eliminates leakage of the low-threshold transistor in the main amplifier 1 by pulling down current. The main amplifier 1 is composed of a symmetrical OTA transconductance operational amplifier, the hysteresis voltage generation circuit 2 is constructed by a cross-coupled MOS tube and a MOS diode in parallel, and the leakage cancellation circuit 3 uses a pair of two groups of pull-down fixed current sources to offset the leakage current of the low-threshold PMOS tube; the latch speed enhancement circuit 4 is used to pull the output voltage to the power supply and ground, and improve the signal transmission speed.

[0017] The low-voltage hysteresis comparator consists of a main amplifier 1, a hysteresis voltage generating circuit 2, a leakage elimination circuit 3 and a latch speed enhancement circuit 4. The hysteresis voltage generating circuit 2 is embedded in the main amplifier 1 and serves as the load of the main amplifier 1. The leakage elimination circuit 3 is used to eliminate leakage of the low-threshold tube in certain situations. The latch speed enhancement circuit 4 not only ensures that the output can generate stable high and low levels, but also uses pulse current to enhance the comparator speed. At the same time, when using 5V devices, it can operate in a low-voltage environment of 1.4V.

[0018] The main amplifier 1 includes an MN1 transistor 15, an MN2 transistor 16, an MP1 transistor 11, an MP2 transistor 12, an MP3 transistor 13 and an MP4 transistor 14; the gate input INN of the MN1 transistor 15, and the drain of the MN1 transistor 15 are electrically connected to the gate and drain of the MP2 transistor 12; the gate input INP of the MN2 transistor 16, and the drain of the MN2 transistor 16 are electrically connected to the gate and drain of the MP3 transistor 13; the source of the MN1 transistor 15 and the source of the MN2 transistor 16 are grounded through a constant current source 17; the gate of the MP1 transistor 11 is electrically connected to the gate of the MP2 transistor 12, and the gate of the MP4 transistor 14 is electrically connected to the gate of the MP3 transistor 13.

[0019] The sources of MP1 transistor 11, MP2 transistor 12, MP3 transistor 13, and MP4 transistor 14 are all electrically connected to the VDD power supply voltage. The drain of MP1 transistor 11 serves as the X connection point, and the drain of MP4 transistor serves as the Y connection point. MP1 transistor 11, MP2 transistor 12, MP3 transistor 13, and MP4 transistor 14 are all low-threshold MOS transistors to meet the requirements of low power supply voltage. The gate input of MN1 transistor 15 is INN, and the gate input of MN2 transistor 16 is INP. The gates of MN1 transistor 15 and MN2 transistor 16 serve as the two inputs of the low-voltage hysteresis comparator.

[0020] The hysteresis voltage generating circuit 2 includes an MN3 transistor 21, an MN4 transistor 22, an MN5 transistor 23, an MN6 transistor 24, an MN7 transistor 25, and an MN8 transistor 26. The drains of the MN3 transistor 21 and the MN6 transistor 24 are both electrically connected to the drain of the MP1 transistor 11, and the drains of the MN7 transistor 25 and the MN5 transistor 23 are both electrically connected to the drain of the MP4 transistor 14. The drains of the MN3 transistor 21 and the MN6 transistor 24 are electrically connected to the X connection point, and the drains of the MN7 transistor 25 and the MN5 transistor 23 are electrically connected to the Y connection point.

[0021] The drain of the MN3 transistor 21 is electrically connected to the gate of the MN3 transistor 21 and the gate of the MN4 transistor 22. The gate of the MN4 transistor 22 is electrically connected to the gate of the MN5 transistor 23. The drain of the MN7 transistor 25 is electrically connected to the gate of the MN7 transistor 25 and the gate of the MN8 transistor 26. The gate of the MN8 transistor 26 is electrically connected to the gate of the MN6 transistor 24. The source of the MN3 transistor 21 is electrically connected to the drain of the MN4 transistor 22. The source of the MN7 transistor 25 is electrically connected to the drain of the MN8 transistor 26. The source of the MN4 transistor 22, the source of the MN5 transistor 23, the source of the MN6 transistor 24, and the source of the MN8 transistor 26 are all electrically connected to VSS, i.e., ground. The source of the MN3 transistor 21 serves as the A connection point, and the source of the MN7 transistor 25 serves as the B connection point.

[0022] The MN3 transistor 21, MN4 transistor 22, MN5 transistor 23, MN6 transistor 24, MN7 transistor 25 and MN8 transistor 26 have a certain proportional relationship, so that the MN3 transistor 21, MN4 transistor 22 and MN5 transistor 23 on the left side are symmetrical with the MN6 transistor 24, MN7 transistor 25 and MN8 transistor 26 on the right side; and the width-to-length ratio of the MN5 transistor 23 is greater than the width-to-length ratio of the MN3 transistor 21 and the MN4 transistor 22 connected in series, so as to achieve the purpose of negative impedance and achieve the hysteresis effect.

[0023] Main amplifier 1's two inputs, INN and INP, initially flow through the left N transistor. MN5 is in its linear region, and the current flowing through it is greater than the current flowing through MN4 and MN3. As INP gradually increases to equal INN, MP1 and MP4 transistors have the same current, but MP4's current is insufficient to saturate MN5, and the circuit's output remains unchanged. When INP exceeds INN, MP4 draws more current, causing the low-voltage hysteresis comparator to change state, achieving hysteresis. Consequently, the comparator's output outputs a hysteresis voltage based on the magnitude of INP and INN.

[0024] The leakage elimination circuit 3 includes two groups of nA-level pull-down current branches; the drain of the MP1 transistor 11 is grounded through one group of nA-level pull-down current branches, and the drain of the MP4 transistor 14 is grounded through another group of nA-level pull-down current branches.

[0025] The two groups of nA-level pull-down current branches each include a plurality of pull-down current circuits; each of the plurality of pull-down current circuits includes a control switch and a current source; one end of the control switch is electrically connected to the MP1 transistor 11 or the MP4 transistor 14, and one end of the control switch is electrically connected to the X connection point or the Y connection point; the other end of the control switch is grounded through the current source.

[0026] Because the MP1 and MP4 transistors use low-threshold transistors, their turn-off leakage current can reach over 5nA at certain corner process angles. This causes the diode-connected MOS transistor at the bottom, which ideally should have no current, to not fully shut down when turned off. This results in minimal changes in the two outputs of the low-voltage hysteresis comparator, which in turn prevents the subsequent circuit from correctly identifying the signal and causing the low-voltage hysteresis comparator to erroneously state. To address this issue, a set of nA-level pull-down current branches are added to the drains of the MP1 and MP4 transistors. These nA-level pull-down currents offset the leakage currents generated by the MP1 and MP4 transistors. The pull-down current of the MP1 transistor is less than the current when the MP1 transistor is saturated, and the pull-down current of the MP4 transistor is less than the current when the MP4 transistor is saturated, thereby avoiding excessive interference with the normal operation of the circuit. At the same time, by adding control switches to several pull-down current circuits, the pull-down current is increased when the PMOS transistor leakage increases at certain process angles.

[0027] The latch speed boost circuit 4 includes an MP5 transistor 41 and an MP6 transistor 42. The gate of the MP5 transistor 41 is electrically connected to the source of the MN3 transistor 21, and the drain of the MP5 transistor 41 is electrically connected to the source of the MN7 transistor 25 via the R1 resistor. The gate of the MP5 transistor 41 is electrically connected to the A connection point, and the drain of the MP5 transistor 41 is electrically connected to the B connection point via the R1 resistor. The gate of the MP6 transistor 42 is electrically connected to the source of the MN7 transistor 25, and the drain of the MP6 transistor 42 is electrically connected to the source of the MN3 transistor 21 via the R2 resistor. The gate of the MP6 transistor 42 is electrically connected to the B connection point, and the drain of the MP6 transistor 42 is electrically connected to the A connection point via the R2 resistor. The drain of the MP6 transistor 42 serves as the output terminal of the latch speed boost circuit 4. The sources of the MP5 transistor 41 and the MP6 transistor 42 are electrically connected to the VDD power supply voltage. The output terminal of the latch speed boost circuit 4 serves as the output terminal OUT of the low-voltage hysteresis comparator, outputting a hysteresis voltage.

[0028] Traditional hysteresis comparators often use a common-source structure with a first-stage active current mirror as the load to achieve full signal swing. However, this approach relies on the circuit's own quiescent current to achieve large signal swings, resulting in very slow signal rise and fall times. Latch speed-boosting circuit 4 electrically connects its two input terminals to the middle of the NMOS transistors connected in series, MN3 and MN4, and to the middle of the NMOS transistors connected in series, MN7 and MN8. That is, latch speed-boosting circuit 4 electrically connects its two input terminals to connection points A and B, respectively. When the low-voltage hysteresis comparator flips, the voltages at connection points X and Y only need to change from 1 Vth to 0, resulting in a smaller swing and faster signal rise and fall times. The signal change speed at connection points A and B, which have large signal swings, is determined by the pulse current provided by transistors MP5 and MP6. In low-power designs, the current drawn by latch speed-boosting circuit 4 is much greater than the quiescent current provided by the previous active current mirror, resulting in faster signal rise and fall times, thus improving the speed of the low-power comparator.

[0029] By adding resistors R1 and R2, it can be ensured that when the input is a small signal, which makes it difficult for the low-voltage hysteresis comparator to distinguish and output an intermediate level, the MP6 transistor 42 is turned on, resulting in a certain voltage drop across the R2 resistor, so that the output end of the latch speed boost circuit 4 outputs a relatively high potential, avoiding the large leakage phenomenon that may occur in the subsequent inverter.

[0030] Example

[0031] By adding control switches to several pull-down current circuits, the pull-down current is increased when the leakage current of the PMOS transistor increases at certain process corners. Several pull-down current circuits in a group of nA-level pull-down current branches control the magnitude of the pull-down current by adding control switches. The greater the number of closed control switches in the pull-down current circuits, the greater the pull-down current. Simultaneously, a detection control circuit is provided at the drain of the MP1 transistor and the drain of the MP4 transistor. The detection control circuit detects the magnitude of the leakage current of the MP1 transistor or the MP4 transistor, and then controls the number of closed control switches in the pull-down current circuits in the group of nA-level pull-down current branches based on the magnitude of the leakage current of the MP1 transistor or the MP4 transistor. Taking the MP1 transistor, its corresponding detection control circuit, and the group of nA-level pull-down current branches as an example, multiple thresholds are set in the detection control circuit, where each threshold corresponds to the control switches of several pull-down current circuits. When the detection control circuit detects that the leakage current of the drain of the MP1 transistor is equal to or greater than a first threshold value, the control switch of one pull-down current circuit among the multiple pull-down current circuits is controlled to be closed; when the detection control circuit detects that the leakage current of the drain of the MP1 transistor is equal to or greater than a second threshold value, the control switches of two pull-down current circuits among the multiple pull-down current circuits are controlled to be closed; when the detection control circuit detects that the leakage current of the drain of the MP1 transistor is equal to or greater than a third threshold value, the control switches of three pull-down current circuits among the multiple pull-down current circuits are controlled to be closed; and so on. According to the detected leakage current of the drain of the MP1 transistor, the number of closed control switches in the multiple pull-down current circuits is automatically controlled to adjust the size of the pull-down current of the MP1 transistor according to the leakage current of the drain of the MP1 transistor.

[0032] The above is only a description of the preferred embodiment of the present invention. Ordinary technicians in this technical field can make several modifications and optimizations based on the above disclosure without departing from the above basic principles. These improvements and optimizations should be regarded as the scope of protection understood by the present invention.

Claims

1. A hysteresis voltage generating circuit for use in a low-voltage, high-speed environment, characterized in that: The invention comprises a low-voltage hysteresis comparator; the low-voltage hysteresis comparator comprises a main amplifier (1), a hysteresis voltage generating circuit (2), a leakage elimination circuit (3) and a latch speed enhancement circuit (4); the output end of the main amplifier (1) is electrically connected to the input end of the hysteresis voltage generating circuit (2), and the output end of the hysteresis voltage generating circuit (2) is electrically connected to the input end of the latch speed enhancement circuit (4); the input end of the main amplifier (1) serves as the input end of the low-voltage hysteresis comparator, and the output end of the latch speed enhancement circuit (4) serves as the output end of the low-voltage hysteresis comparator; the hysteresis voltage generating circuit (2) generates a hysteresis voltage of the low-voltage hysteresis comparator, and the leakage elimination circuit (3) eliminates leakage of a low-threshold transistor in the main amplifier (1) by pulling down current.

2. The hysteresis voltage generating circuit for use in a low-voltage and high-speed environment according to claim 1, wherein: The main amplifier (1) comprises an MN1 transistor (15), an MN2 transistor (16), an MP1 transistor (11), an MP2 transistor (12), an MP3 transistor (13) and an MP4 transistor (14); the gate input of the MN1 transistor (15) is INN, and the drain of the MN1 transistor (15) is electrically connected to the gate and drain of the MP2 transistor (12); the gate input of the MN2 transistor (16) is INP, and the drain of the MN2 transistor (16) is electrically connected to the gate and drain of the MP3 transistor (13); the source of the MN1 transistor (15) and the source of the MN2 transistor (16) are grounded via a constant current source (17); the gate of the MP1 transistor (11) is electrically connected to the gate of the MP2 transistor (12), and the gate of the MP4 transistor (14) is electrically connected to the gate of the MP3 transistor (13).

3. The hysteresis voltage generating circuit for use in a low-voltage and high-speed environment according to claim 1, wherein: The hysteresis voltage generating circuit (2) comprises an MN3 transistor (21), an MN4 transistor (22), an MN5 transistor (23), an MN6 transistor (24), an MN7 transistor (25) and an MN8 transistor (26); the drain of the MN3 transistor (21) and the drain of the MN6 transistor (24) are both electrically connected to the drain of the MP1 transistor (11), and the drain of the MN7 transistor (25) and the drain of the MN5 transistor (23) are both electrically connected to the drain of the MP4 transistor (14).

4. The hysteresis voltage generating circuit for use in a low-voltage and high-speed environment according to claim 3, wherein: The drain of the MN3 transistor (21) is electrically connected to the gate of the MN3 transistor (21) and the gate of the MN4 transistor (22), and the gate of the MN4 transistor (22) is electrically connected to the gate of the MN5 transistor (23); the drain of the MN7 transistor (25) is electrically connected to the gate of the MN7 transistor (25) and the gate of the MN8 transistor (26), and the gate of the MN8 transistor (26) is electrically connected to the gate of the MN6 transistor (24); the source of the MN3 transistor (21) is electrically connected to the drain of the MN4 transistor (22), and the source of the MN7 transistor (25) is electrically connected to the drain of the MN8 transistor (26).

5. The hysteresis voltage generating circuit for use in a low-voltage and high-speed environment according to claim 4, characterized in that: The width-to-length ratio of the MN5 transistor (23) is greater than the width-to-length ratio of the MN3 transistor (21) and the MN4 transistor (22) connected in series.

6. The hysteresis voltage generating circuit for use in a low-voltage and high-speed environment according to claim 1, wherein: The leakage elimination circuit (3) comprises two groups of pull-down current branches; the drain of the MP1 transistor (11) is grounded through one group of pull-down current branches, and the drain of the MP4 transistor (14) is grounded through the other group of pull-down current branches.

7. The hysteresis voltage generating circuit for use in a low-voltage and high-speed environment according to claim 6, characterized in that: The two groups of pull-down current branches each include a plurality of pull-down current circuits; each of the plurality of pull-down current circuits includes a control switch and a current source; one end of the control switch is electrically connected to the MP1 transistor (11) or the MP4 transistor (14), and the other end of the control switch is grounded through the current source.

8. The hysteresis voltage generating circuit for use in a low-voltage and high-speed environment according to claim 1, wherein: The latch speed boosting circuit (4) comprises an MP5 transistor (41) and an MP6 transistor (42); the gate of the MP5 transistor (41) is electrically connected to the source of the MN3 transistor (21), and the drain of the MP5 transistor (41) is electrically connected to the source of the MN7 transistor (25) via the R1 resistor; the gate of the MP6 transistor (42) is electrically connected to the source of the MN7 transistor (25), and the drain of the MP6 transistor (42) is electrically connected to the source of the MN3 transistor (21) via the R2 resistor; the drain of the MP6 transistor (42) serves as the output end of the latch speed boosting circuit (4).

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