Current-limiting turn-back circuit applied to power tube and control method of current-limiting turn-back circuit

Abstract

The invention discloses a current-limiting turn-back circuit applied to a power tube and a control method thereof.The current-limiting turn-back circuit comprises an LDO circuit, a current detection circuit, a reference voltage generating circuit, an operational amplifier A3 and an NMOS tube NM3, the LDO circuit generates stable output voltage VOUT, the current detection circuit detects current of a power tube NM1 of the LDO circuit and converts the current into detection voltage V2 in proportion, and the reference voltage generating circuit generates reference voltage; the reference voltage generation circuit generates a reference voltage V1 based on a voltage division signal V3 of an output voltage VOUT, an inverted input end of the operational amplifier A3 is connected with the reference voltage V1, a normal phase input end of the operational amplifier A3 is connected with a detection voltage V2, an output end of the operational amplifier A3 is connected with a grid electrode of the NMOS tube NM3, a drain electrode of the NMOS tube NM3 is connected with a grid electrode of a power tube NM1 of the LDO circuit, and a source electrode of the NMOS tube NM3 is grounded. The power consumption of the power tube is reduced, and heating is reduced.

Description

Technical Field

[0001] The present invention relates to a current limiting foldback circuit and a control method thereof, in particular to a current limiting foldback circuit and a control method thereof applied to a power tube, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] In power management systems and power electronics, over-current protection (OCP) is a core mechanism for ensuring safe system operation. As core components for energy conversion, power transistors (such as MOSFETs and IGBTs) must provide over-current protection that balances fast response, power consumption control, and thermal reliability.

[0003] Traditional current limiting protection technology mainly uses a fixed current limiting threshold. Therefore, when the power tube is in a high voltage difference environment, its power increases, which is not conducive to power consumption control and thermal management. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a current limiting foldback circuit applied to a power tube and a control method thereof, so as to reduce the power consumption of the power tube and reduce the heat generation.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A current limiting foldback circuit for a power tube includes an LDO circuit, a current detection circuit, a reference voltage generation circuit, an operational amplifier A3, and an NMOS tube NM3. The LDO circuit generates a stable output voltage VOUT. The current detection circuit detects the current of the power tube NM1 of the LDO circuit and converts it proportionally into a detection voltage V2. The reference voltage generation circuit generates a reference voltage V1 based on a voltage-divided signal V3 of the output voltage VOUT. The inverting input of the operational amplifier A3 is connected to the reference voltage V1, the non-inverting input of the operational amplifier A3 is connected to the detection voltage V2, the output of the operational amplifier A3 is connected to the gate of the NMOS tube NM3, the drain of the NMOS tube NM3 is connected to the gate of the power tube NM1 of the LDO circuit, and the source of the NMOS tube NM3 is grounded.

[0006] Furthermore, the LDO circuit includes an operational amplifier A1, a power tube NM1 and resistors R1 to R3, the non-inverting input terminal of the operational amplifier A1 is connected to the reference voltage VREF, the output terminal of the operational amplifier A1 is connected to the gate of the power tube NM1, the drain of the power tube NM1 is connected to the power supply VIN, the source of the NMOS tube NM1 is connected to one end of the resistor R1 and generates a stable output voltage VOUT, the other end of the resistor R1 is connected to one end of the resistor R2 and the inverting input terminal of the operational amplifier A1, the other end of the resistor R2 is connected to one end of the resistor R3 and generates a voltage division signal V3, and the other end of the resistor R3 is grounded.

[0007] Furthermore, the current detection circuit includes a sampling tube NM2, resistors R4 to R7, a PMOS tube PM1, a PMOS tube PM2, a current source I1, a current source I2 and an NMOS tube NM4, one end of the resistor R4 and one end of the resistor R6 are connected to the power supply VIN, the other end of the resistor R4 is connected to the drain of the sampling tube NM2 and one end of the resistor R5, the gate of the sampling tube NM2 is connected to the gate of the power tube NM1 of the LDO circuit, the source of the sampling tube NM2 is connected to the output voltage VOUT, the other end of the resistor R5 is connected to the PMOS tube PM The source of the PMOS transistor PM1 is connected to the source of the PMOS transistor PM2, the other end of the resistor R6 is connected to the source of the PMOS transistor PM2 and the drain of the NMOS transistor NM4, the gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM1, and one end of the current source I1, the drain of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM4 and one end of the current source I2, the source of the NMOS transistor NM4 is connected to one end of the resistor R7 and generates a detection voltage V2, and the other end of the current source I1, the other end of the current source I2, and the other end of the resistor R7 are grounded.

[0008] Furthermore, the reference voltage generating circuit includes an operational amplifier A2, a resistor R8 and a current source I3, the non-inverting input terminal of the operational amplifier A2 is connected to the voltage divided signal V3, the output terminal of the operational amplifier A2 is connected to the inverting input terminal of the operational amplifier A2 and one end of the resistor R8, the other end of the resistor R8 is connected to one end of the current source I3 and generates a reference voltage V1, and the other end of the current source I3 is connected to the power supply VIN.

[0009] Furthermore, the operational amplifier A3 and the NMOS transistor NM3 form an error amplifier stage for amplifying the difference between the reference voltage V1 and the detection voltage V2.

[0010] A control method for a current limiting foldback circuit applied to a power tube comprises the following steps: Operational amplifier A1, power transistor NM1, and resistors R1 to R3 form an LDO circuit. The non-inverting input of operational amplifier A1 is connected to the reference voltage VREF, and the inverting input of operational amplifier A1 is connected to the voltage-divided signal VFB of the output voltage VOUT. When the voltage-divided signal VFB is greater than the reference voltage VREF, operational amplifier A1 amplifies the error signal and pulls down the voltage at the output of operational amplifier A1. The source voltage of power transistor NM1 is pulled down following the gate voltage of power transistor NM1, and the voltage-divided signal VFB is pulled down following the source voltage of power transistor NM1, forming negative feedback. When stable, VREF=VFB, so the output voltage VOUT is expressed as: ; The sampling transistor NM2, resistors R4 to R7, PMOS transistors PM1 and PM2, current sources I1 and I2, and NMOS transistor NM4 form a current detection circuit. The width-to-length ratio of the power transistor NM1 and the sampling transistor NM2 is K:1. The current flowing through the power transistor NM1 is IOUT, and the current flowing through the sampling transistor NM2 is ISEN. Resistors R4, R5, and R6 have the same resistance value R. The power transistor NM1 and the sampling transistor NM2 have the same gate-source voltage and drain-source voltage. The relationship between the current IOUT and the current ISEN is: ; The voltage drop V4 across resistor R4 is expressed as: ; PMOS transistors PM1 and PM2, current sources I1 and I2, NMOS transistor NM4, and resistor R7 form a negative feedback clamping loop. Current sources I1 and I2 have the same current magnitude, and PMOS transistors PM1 and PM2 have the same width-to-length ratio. When the source voltage of PMOS transistor PM2 is higher than the source voltage of PMOS transistor PM1, the drain voltage of PMOS transistor PM2 increases and the source voltage of PMOS transistor PM2 decreases, forming negative feedback. When stable, PMOS transistors PM1 and PM2 have the same source voltage. Therefore, the detection voltage V2 is expressed as: ; Operational amplifier A2, resistor R8, and current source I3 form a reference voltage generation circuit. The inverting input terminal of operational amplifier A2 is connected to the output terminal to form negative feedback. In steady state, the output terminal voltage of operational amplifier A2 is equal to the non-inverting input terminal voltage. The voltage of the non-inverting input terminal of the operational amplifier is the voltage-divided signal V3. The voltage-divided signal V3 is the divided voltage of the output voltage VOUT. The voltage-divided signal V3 is expressed as: ; Therefore, the reference voltage V1 related to the output voltage VOUT is expressed as: ; Operational amplifier A3 and transistor NM3 form an error amplifier stage for amplifying the difference between the reference voltage V1 and the detection voltage V2; When the load current driven by the LDO circuit is much smaller than the current limit threshold, the detection voltage V2 is much smaller than the reference voltage V1. Therefore, the operational amplifier A3 works in the comparator state, the output is 0V, and the NMOS tube NM3 is turned off, which does not affect the LDO circuit. When the load current driven by the LDO circuit gradually increases and exceeds the current limit threshold, the detection voltage V2 begins to rise and exceeds the reference voltage V1. The output voltage of the operational amplifier A3 rises, the gate voltage of the power tube NM1 drops, and the current IOUT decreases, causing the detection voltage V2 to decrease, forming a negative feedback. In steady state, the detection voltage V2 is equal to the reference voltage V1, so ; ; Therefore, the current limit threshold decreases as the output voltage VOUT decreases.

[0011] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a current limiting foldback circuit and a control method for a power tube. By generating a reference voltage that decreases with the output voltage, when the current limiting loop is working, the current limiting value decreases as the reference voltage decreases, thereby realizing the current limiting foldback function, thereby reducing the power consumption of the power tube and reducing heat generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of a current limiting foldback circuit applied to a power tube according to the present invention.

[0013] Figure 2 This is a simulation waveform diagram of a current limiting foldback circuit applied to a power tube according to the present invention. DETAILED DESCRIPTION

[0014] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0015] like Figure 1As shown, a current limiting and foldback circuit for a power transistor of the present invention includes an LDO circuit, a current detection circuit, a reference voltage generation circuit, an operational amplifier A3, and an NMOS transistor NM3. The LDO circuit generates a stable output voltage VOUT. The current detection circuit detects the current of the power transistor NM1 of the LDO circuit and converts it proportionally into a detection voltage V2. The reference voltage generation circuit generates a reference voltage V1 based on a voltage-divided signal V3 of the output voltage VOUT. The inverting input of the operational amplifier A3 is connected to the reference voltage V1, the non-inverting input of the operational amplifier A3 is connected to the detection voltage V2, the output of the operational amplifier A3 is connected to the gate of the NMOS transistor NM3, the drain of the NMOS transistor NM3 is connected to the gate of the power transistor NM1 of the LDO circuit, and the source of the NMOS transistor NM3 is grounded. When the output current of the power transistor is greater than a preset value, the power transistor begins to limit current, and the current limiting threshold decreases as the output voltage decreases, thereby reducing power consumption and heat generation of the power transistor.

[0016] The LDO circuit includes an operational amplifier A1, a power transistor NM1, and resistors R1 to R3. The non-inverting input terminal of the operational amplifier A1 is connected to a reference voltage VREF, the output terminal of the operational amplifier A1 is connected to the gate of the power transistor NM1, the drain of the power transistor NM1 is connected to a power supply VIN, the source of the NMOS transistor NM1 is connected to one end of the resistor R1 and generates a stable output voltage VOUT, the other end of the resistor R1 is connected to one end of the resistor R2 and the inverting input terminal of the operational amplifier A1, the other end of the resistor R2 is connected to one end of the resistor R3 and generates a voltage divided signal V3, and the other end of the resistor R3 is grounded.

[0017] The current detection circuit includes a sampling tube NM2, resistors R4 to R7, a PMOS tube PM1, a PMOS tube PM2, a current source I1, a current source I2, and an NMOS tube NM4. One end of the resistor R4 and one end of the resistor R6 are connected to the power supply VIN, the other end of the resistor R4 is connected to the drain of the sampling tube NM2 and one end of the resistor R5, the gate of the sampling tube NM2 is connected to the gate of the power tube NM1 of the LDO circuit, the source of the sampling tube NM2 is connected to the output voltage VOUT, and the other end of the resistor R5 is connected to the source of the PMOS tube PM1. The other end of the resistor R6 is connected to the source of the PMOS transistor PM2 and the drain of the NMOS transistor NM4. The gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM1, and one end of the current source I1. The drain of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM4 and one end of the current source I2. The source of the NMOS transistor NM4 is connected to one end of the resistor R7 to generate a detection voltage V2. The other end of the current source I1, the other end of the current source I2, and the other end of the resistor R7 are grounded.

[0018] The reference voltage generating circuit includes an operational amplifier A2, a resistor R8, and a current source I3. The non-inverting input terminal of the operational amplifier A2 is connected to the voltage divided signal V3. The output terminal of the operational amplifier A2 is connected to the inverting input terminal of the operational amplifier A2 and one end of the resistor R8. The other end of the resistor R8 is connected to one end of the current source I3 to generate a reference voltage V1. The other end of the current source I3 is connected to the power supply VIN.

[0019] The operational amplifier A3 and the NMOS transistor NM3 form an error amplifier stage for amplifying the difference between the reference voltage V1 and the detection voltage V2.

[0020] A control method for a current limiting foldback circuit applied to a power tube comprises the following steps: Operational amplifier A1, power transistor NM1, and resistors R1-R3 form an LDO circuit. The non-inverting input of operational amplifier A1 is connected to a reference voltage VREF, which can be generated by a bandgap reference or a bandgap reference plus a preceding LDO. The inverting input of operational amplifier A1 is connected to a voltage-divided signal VFB of the output voltage VOUT. When the voltage-divided signal VFB is greater than the reference voltage VREF, operational amplifier A1 amplifies the error signal, pulling down the voltage at the output of operational amplifier A1. The source voltage of power transistor NM1 is pulled down along with the gate voltage of power transistor NM1, and the voltage-divided signal VFB is pulled down along with the source voltage of power transistor NM1, forming negative feedback. When stable, VREF = VFB, so the output voltage VOUT is expressed as: .

[0021] Sampling transistor NM2, resistors R4-R7, PMOS transistors PM1 and PM2, current sources I1 and I2, and NMOS transistor NM4 form a current detection circuit, which detects the current in power transistor NM1 and converts it proportionally into a detection voltage V2. The width-to-length ratio of power transistor NM1 and sampling transistor NM2 is K:1. The current flowing through power transistor NM1 is IOUT, and the current flowing through sampling transistor NM2 is ISEN. Resistors R4, R5, and R6 have the same resistance value R. Since the K value is generally increased, ISEN is relatively small. By designing resistor R4 to have a smaller resistance value, the voltage drop across resistor R4 can be kept small. As a result, power transistor NM1 and sampling transistor NM2 have the same gate-source voltage and nearly equal drain-source voltage. The relationship between current IOUT and current ISEN is: .

[0022] The voltage drop V4 across resistor R4 is expressed as: .

[0023] PMOS transistors PM1 and PM2, current sources I1 and I2, NMOS transistor NM4, and resistor R7 form a negative feedback clamping loop. Current sources I1 and I2 have the same current magnitude, and PMOS transistors PM1 and PM2 have the same width-to-length ratio. When the source voltage of PMOS transistor PM2 is higher than the source voltage of PMOS transistor PM1, the drain voltage of PMOS transistor PM2 increases and the source voltage of PMOS transistor PM2 decreases, forming negative feedback. When stable, PMOS transistors PM1 and PM2 have the same source voltage. Therefore, the detection voltage V2 is expressed as: .

[0024] Operational amplifier A2, resistor R8, and current source I3 form a reference voltage generation circuit. The inverting input terminal of operational amplifier A2 is connected to the output terminal to form negative feedback. In steady state, the output terminal voltage of operational amplifier A2 is equal to the non-inverting input terminal voltage. The voltage of the non-inverting input terminal of the operational amplifier is the voltage-divided signal V3. The voltage-divided signal V3 is the divided voltage of the output voltage VOUT. The voltage-divided signal V3 is expressed as: .

[0025] Therefore, the reference voltage V1 related to the output voltage VOUT is expressed as: .

[0026] Operational amplifier A3 and transistor NM3 form an error amplifier stage for amplifying the difference between the reference voltage V1 and the detection voltage V2.

[0027] When the load current driven by the LDO circuit is much smaller than the current limit threshold, the detection voltage V2 is much smaller than the reference voltage V1. Therefore, the operational amplifier A3 works in the comparator state, the output is close to 0V, and the NMOS tube NM3 is turned off, which does not affect the LDO circuit.

[0028] When the load current driven by the LDO circuit gradually increases and exceeds the current limit threshold, the detection voltage V2 begins to rise and exceeds the reference voltage V1. The output voltage of the operational amplifier A3 rises, the gate voltage of the power tube NM1 drops, and the current IOUT decreases, causing the detection voltage V2 to decrease, forming a negative feedback. In steady state, the detection voltage V2 is equal to the reference voltage V1, so ; ; Therefore, the current limit threshold decreases as the output voltage VOUT decreases.

[0029] like Figure 2The figure shows the simulated waveform of a current limiting foldback circuit applied to a power tube according to the present invention. The waveform diagram has two curves: output voltage VOUT and current IOUT. The horizontal axis is the resistance value of the load resistor. When the load resistance is large, the LDO circuit operates normally and maintains an output close to 1.8V. When the load resistance gradually decreases, the load current gradually increases until the load current increases to a preset value of 2A. The current limiting loop starts to operate and the output voltage decreases. As the output voltage decreases, the current limiting value also begins to decrease. Finally, when the output voltage VOUT is 0V, the current limiting value is maintained at 420mA.

[0030] The present invention provides a current limiting foldback circuit for a power tube and a control method thereof. By generating a reference voltage that decreases with the output voltage, when the current limiting loop is operating, the current limiting value decreases as the reference voltage decreases, thereby realizing the current limiting foldback function, thereby reducing the power consumption of the power tube and reducing heat generation.

[0031] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A current limiting foldback circuit for a power tube, characterized in that: The invention comprises an LDO circuit, a current detection circuit, a reference voltage generation circuit, an operational amplifier A3 and an NMOS transistor NM3. The LDO circuit generates a stable output voltage VOUT. The current detection circuit detects the current of the power transistor NM1 of the LDO circuit and converts it into a detection voltage V2 in proportion. The reference voltage generation circuit generates a reference voltage V1 based on a voltage-divided signal V3 of the output voltage VOUT. The inverting input terminal of the operational amplifier A3 is connected to the reference voltage V1, the non-inverting input terminal of the operational amplifier A3 is connected to the detection voltage V2, the output terminal of the operational amplifier A3 is connected to the gate of the NMOS transistor NM3, the drain of the NMOS transistor NM3 is connected to the gate of the power transistor NM1 of the LDO circuit, and the source of the NMOS transistor NM3 is grounded.

2. The current limiting foldback circuit for a power tube according to claim 1, characterized in that: The LDO circuit includes an operational amplifier A1, a power tube NM1, and resistors R1 to R3. The non-inverting input terminal of the operational amplifier A1 is connected to a reference voltage VREF, the output terminal of the operational amplifier A1 is connected to the gate of the power tube NM1, the drain of the power tube NM1 is connected to a power supply VIN, the source of the NMOS tube NM1 is connected to one end of the resistor R1 and generates a stable output voltage VOUT, the other end of the resistor R1 is connected to one end of the resistor R2 and the inverting input terminal of the operational amplifier A1, the other end of the resistor R2 is connected to one end of the resistor R3 and generates a voltage division signal V3, and the other end of the resistor R3 is grounded.

3. The current limiting foldback circuit for a power tube according to claim 1, characterized in that: The current detection circuit includes a sampling tube NM2, resistors R4 to R7, a PMOS tube PM1, a PMOS tube PM2, a current source I1, a current source I2, and an NMOS tube NM4. One end of the resistor R4 and one end of the resistor R6 are connected to the power supply VIN, the other end of the resistor R4 is connected to the drain of the sampling tube NM2 and one end of the resistor R5, the gate of the sampling tube NM2 is connected to the gate of the power tube NM1 of the LDO circuit, the source of the sampling tube NM2 is connected to the output voltage VOUT, the other end of the resistor R5 is connected to the source of the PMOS tube PM1, and the output voltage VOUT is VOUT. The gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM1, and one end of the current source I1. The drain of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM4 and one end of the current source I2. The source of the NMOS transistor NM4 is connected to one end of the resistor R7 and generates a detection voltage V2. The other end of the current source I1, the other end of the current source I2, and the other end of the resistor R7 are grounded.

4. The current limiting foldback circuit for a power tube according to claim 1, wherein: The reference voltage generating circuit includes an operational amplifier A2, a resistor R8 and a current source I3. The non-inverting input terminal of the operational amplifier A2 is connected to the voltage divided signal V3, the output terminal of the operational amplifier A2 is connected to the inverting input terminal of the operational amplifier A2 and one end of the resistor R8, the other end of the resistor R8 is connected to one end of the current source I3 to generate a reference voltage V1, and the other end of the current source I3 is connected to the power supply VIN.

5. The current limiting foldback circuit for a power tube according to claim 1, characterized in that: The operational amplifier A3 and the NMOS transistor NM3 form an error amplifier stage for amplifying the difference between the reference voltage V1 and the detection voltage V2.

6. A control method for a current limiting foldback circuit applied to a power tube according to any one of claims 1 to 5, characterized in that The following steps are involved: Operational amplifier A1, power transistor NM1, and resistors R1 to R3 form an LDO circuit. The non-inverting input of operational amplifier A1 is connected to the reference voltage VREF, and the inverting input of operational amplifier A1 is connected to the voltage-divided signal VFB of the output voltage VOUT. When the voltage-divided signal VFB is greater than the reference voltage VREF, operational amplifier A1 amplifies the error signal and pulls down the voltage at the output of operational amplifier A1. The source voltage of power transistor NM1 is pulled down following the gate voltage of power transistor NM1, and the voltage-divided signal VFB is pulled down following the source voltage of power transistor NM1, forming negative feedback. When stable, VREF=VFB, so the output voltage VOUT is expressed as: ； The sampling transistor NM2, resistors R4 to R7, PMOS transistors PM1 and PM2, current sources I1 and I2, and NMOS transistor NM4 form a current detection circuit. The width-to-length ratio of the power transistor NM1 and the sampling transistor NM2 is K:

1. The current flowing through the power transistor NM1 is IOUT, and the current flowing through the sampling transistor NM2 is ISEN. Resistors R4, R5, and R6 have the same resistance value R. The power transistor NM1 and the sampling transistor NM2 have the same gate-source voltage and drain-source voltage. The relationship between the current IOUT and the current ISEN is: ； The voltage drop V4 across resistor R4 is expressed as: ； PMOS transistors PM1 and PM2, current sources I1 and I2, NMOS transistor NM4, and resistor R7 form a negative feedback clamping loop. Current sources I1 and I2 have the same current magnitude, and PMOS transistors PM1 and PM2 have the same width-to-length ratio. When the source voltage of PMOS transistor PM2 is higher than the source voltage of PMOS transistor PM1, the drain voltage of PMOS transistor PM2 increases and the source voltage of PMOS transistor PM2 decreases, forming negative feedback. When stable, PMOS transistors PM1 and PM2 have the same source voltage. Therefore, the detection voltage V2 is expressed as: ； Operational amplifier A2, resistor R8, and current source I3 form a reference voltage generation circuit. The inverting input terminal of operational amplifier A2 is connected to the output terminal to form negative feedback. In steady state, the output terminal voltage of operational amplifier A2 is equal to the non-inverting input terminal voltage. The voltage of the non-inverting input terminal of the operational amplifier is the voltage-divided signal V3. The voltage-divided signal V3 is the divided voltage of the output voltage VOUT. The voltage-divided signal V3 is expressed as: ； Therefore, the reference voltage V1 related to the output voltage VOUT is expressed as: ； Operational amplifier A3 and transistor NM3 form an error amplifier stage for amplifying the difference between the reference voltage V1 and the detection voltage V2; When the load current driven by the LDO circuit is much smaller than the current limit threshold, the detection voltage V2 is much smaller than the reference voltage V1. Therefore, the operational amplifier A3 works in the comparator state, the output is 0V, and the NMOS tube NM3 is turned off, which does not affect the LDO circuit. When the load current driven by the LDO circuit gradually increases and exceeds the current limit threshold, the detection voltage V2 begins to rise and exceeds the reference voltage V1. The output voltage of the operational amplifier A3 rises, the gate voltage of the power tube NM1 drops, and the current IOUT decreases, causing the detection voltage V2 to decrease, forming a negative feedback. In steady state, the detection voltage V2 is equal to the reference voltage V1, so ； ； Therefore, the current limit threshold decreases as the output voltage VOUT decreases.

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