A current-limiting return circuit applied to a power tube and a control method thereof

Abstract

The application discloses a current-limiting return circuit applied to a power tube and a control method thereof, and comprises an LDO circuit, a current detection circuit, a reference voltage generation circuit, an operational amplifier A3 and an NMOS tube NM3. The LDO circuit generates a stable output voltage VOUT. The current detection circuit detects the current of a power tube NM1 of the LDO circuit and converts the current into a detection voltage V2 in proportion. The reference voltage generation circuit generates a reference voltage V1 based on a voltage division signal V3 of the output voltage VOUT. The inverting input end of the operational amplifier A3 is connected with the reference voltage V1. The non-inverting input end of the operational amplifier A3 is connected with the detection voltage V2. The output end of the operational amplifier A3 is connected with the gate of the NMOS tube NM3. The drain of the NMOS tube NM3 is connected with the gate of the power tube NM1 of the LDO circuit. The source of the NMOS tube NM3 is grounded. The application reduces the power consumption of the power tube and reduces heat generation.

Description

Technical Field

[0001] This invention relates to a current-limiting foldback circuit and its control method, particularly a current-limiting foldback circuit and its control method applied to power transistors, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] In power management systems and power electronic devices, over-current protection (OCP) is one of the core mechanisms to ensure the safe operation of the system. As the core devices for energy conversion, power transistors (such as MOSFETs and IGBTs) require over-current protection that balances fast response, power consumption control, and thermal reliability.

[0003] Traditional current limiting protection technology mainly uses a fixed current limiting threshold. Therefore, when the power transistor is in a high voltage differential environment, its power increases, which is not conducive to power consumption control and thermal management. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a current-limiting foldback circuit and its control method for power transistors, so as to reduce the power consumption of power transistors and reduce heat generation.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0006] A current-limiting foldback circuit for power transistors includes an LDO circuit, a current detection circuit, a reference voltage generation circuit, an operational amplifier A3, and an NMOS transistor NM3. The LDO circuit generates a stable output voltage VOUT. The current detection circuit detects the current of the power transistor NM1 in the LDO circuit and converts it into a detection voltage V2 proportionally. The reference voltage generation circuit generates a reference voltage V1 based on the voltage divider signal V3 of the output voltage VOUT. The inverting input terminal of the operational amplifier A3 is connected to the reference voltage V1, and the non-inverting input terminal of the operational amplifier A3 is connected to the detection voltage V2. The output terminal of the operational amplifier A3 is connected to the gate of the NMOS transistor NM3. The drain of the NMOS transistor NM3 is connected to the gate of the power transistor NM1 in the LDO circuit, and the source of the NMOS transistor NM3 is grounded.

[0007] Furthermore, the LDO circuit includes an operational amplifier A1, a power transistor NM1, and resistors R1 to R3. The non-inverting input of the operational amplifier A1 is connected to the reference voltage VREF. The output of the operational amplifier A1 is connected to the gate of the power transistor NM1. The drain of the power transistor NM1 is connected to the power supply VIN. The source of the NMOS transistor NM1 is connected to one end of resistor R1 and generates a stable output voltage VOUT. The other end of resistor R1 is connected to one end of resistor R2 and the inverting input of the operational amplifier A1. The other end of resistor R2 is connected to one end of resistor R3 and generates a voltage divider signal V3. The other end of resistor R3 is grounded.

[0008] Furthermore, the current detection circuit includes a sampling transistor NM2, resistors R4-R7, PMOS transistors PM1 and PM2, current source I1, current source I2, and NMOS transistor NM4. One end of resistor R4 and one end of resistor R6 are connected to the power supply VIN. The other end of resistor R4 is connected to the drain of sampling transistor NM2 and one end of resistor R5. The gate of sampling transistor NM2 is connected to the gate of power transistor NM1 in the LDO circuit. The source of sampling transistor NM2 is connected to the output voltage VOUT. The other end of resistor R5 is connected to PMOS transistor PM1. The source of transistor I1 is connected, and the other end of resistor R6 is connected to the source of PMOS transistor PM2 and the drain of NMOS transistor NM4. The gate of PMOS transistor PM1 is connected to the gate of PMOS transistor PM2, the drain of PMOS transistor PM1 and one end of current source I1. The drain of PMOS transistor PM2 is connected to the gate of NMOS transistor NM4 and one end of current source I2. The source of NMOS transistor NM4 is connected to one end of resistor R7 and generates detection voltage V2. The other ends of current source I1, current source I2 and resistor R7 are grounded.

[0009] Furthermore, the reference voltage generation circuit includes an operational amplifier A2, a resistor R8, and a current source I3. The non-inverting input terminal of the operational amplifier A2 is connected to the voltage divider signal V3. The output terminal of the operational amplifier A2 is connected to the inverting input terminal of the operational amplifier A2 and one end of the resistor R8. The other end of the resistor R8 is connected to one end of the current source I3 to generate a reference voltage V1. The other end of the current source I3 is connected to the power supply VIN.

[0010] Furthermore, the operational amplifier A3 and the NMOS transistor NM3 form an error amplification stage to amplify the difference between the reference voltage V1 and the detection voltage V2.

[0011] A control method for a current-limiting foldback circuit applied to a power transistor includes the following steps:

[0012] Operational amplifier A1, power transistor NM1, and resistors R1-R3 constitute an LDO circuit. The non-inverting input of operational amplifier A1 is connected to the reference voltage VREF, and the inverting input is connected to the voltage divider signal VFB of the output voltage VOUT. When the voltage divider signal VFB is greater than the reference voltage VREF, operational amplifier A1 amplifies the error signal, pulling down the output voltage of operational amplifier A1. The source voltage of power transistor NM1 is pulled down along with the gate voltage of power transistor NM1, and the voltage divider signal VFB is pulled down along with the source voltage of power transistor NM1, forming negative feedback. When stable, VREF = VFB. Therefore, the output voltage VOUT can be expressed as:

[0013] ;

[0014] The current detection circuit consists of sampling transistor NM2, resistors R4-R7, PMOS transistors PM1 and PM2, current sources I1 and I2, and NMOS transistor NM4. The width-to-length ratio of power transistor NM1 to sampling transistor NM2 is K:1. The current flowing through power transistor NM1 is IOUT, and the current flowing through sampling transistor NM2 is ISEN. Resistors R4, R5, and R6 have the same resistance value R. Power transistor NM1 and sampling transistor NM2 have the same gate-source voltage and drain-source voltage. The relationship between current IOUT and current ISEN is:

[0015] ;

[0016] The voltage drop V4 across resistor R4 is expressed as:

[0017] ;

[0018] PMOS transistors PM1 and PM2, current sources I1 and I2, NMOS transistor NM4, and resistor R7 form a negative feedback clamping loop. Current sources I1 and I2 have the same current magnitude, and PMOS transistors PM1 and PM2 have the same width-to-length ratio. When the source voltage of PMOS transistor PM2 is higher than that of PMOS transistor PM1, the drain voltage of PMOS transistor PM2 increases, and the source voltage of PMOS transistor PM2 decreases, forming negative feedback. When stable, PMOS transistors PM1 and PM2 have the same source voltage. Therefore, the detected voltage V2 is expressed as:

[0019] ;

[0020] Operational amplifier A2, resistor R8, and current source I3 constitute a reference voltage generation circuit. The inverting input terminal of operational amplifier A2 is connected to its output terminal to form negative feedback. In steady state, the output voltage of operational amplifier A2 is equal to the non-inverting input voltage. The voltage at the non-inverting input terminal of the operational amplifier is a voltage divider signal V3, which is a voltage divider of the output voltage VOUT. The voltage divider signal V3 is expressed as:

[0021] ;

[0022] Therefore, the reference voltage V1 related to the output voltage VOUT is expressed as:

[0023] ;

[0024] Operational amplifier A3 and transistor NM3 form an error amplification stage to amplify the difference between the reference voltage V1 and the detection voltage V2;

[0025] When the load current driven by the LDO circuit is much less than the current limiting threshold, the detection voltage V2 is much less than the reference voltage V1. Therefore, the operational amplifier A3 operates in comparator mode and outputs 0V. The NMOS transistor NM3 is turned off, which does not affect the LDO circuit.

[0026] When the load current driven by the LDO circuit gradually increases and exceeds the current limiting threshold, the detection voltage V2 starts to rise and exceeds the reference voltage V1. The output voltage of operational amplifier A3 rises, the gate voltage of power transistor NM1 drops, and the current IOUT decreases, causing the detection voltage V2 to decrease, forming negative feedback. In steady state, the detection voltage V2 equals the reference voltage V1.

[0027] ;

[0028] ;

[0029] Therefore, the current limiting threshold decreases as the output voltage VOUT decreases.

[0030] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a current limiting foldback circuit and its control method for power transistors. By generating a reference voltage that decreases with the output voltage, when the current limiting loop is working, the current limiting value decreases as the reference voltage decreases, thereby realizing the current limiting foldback function, thereby reducing the power consumption of the power transistor and reducing heat generation. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a current-limiting foldback circuit applied to a power transistor according to the present invention.

[0032] Figure 2 This is a simulation waveform diagram of a current-limiting foldback circuit applied to a power transistor according to the present invention. Detailed Implementation

[0033] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0034] like Figure 1As shown, this invention provides a current-limiting foldback circuit for power transistors, comprising an LDO circuit, a current detection circuit, a reference voltage generation circuit, an operational amplifier A3, and an NMOS transistor NM3. The LDO circuit generates a stable output voltage VOUT. The current detection circuit detects the current of the power transistor NM1 in the LDO circuit and proportionally converts it into a detection voltage V2. The reference voltage generation circuit generates a reference voltage V1 based on a voltage divider signal V3 of the output voltage VOUT. The inverting input of the operational amplifier A3 is connected to the reference voltage V1, and the non-inverting input of the operational amplifier A3 is connected to the detection voltage V2. The output of the operational amplifier A3 is connected to the gate of the NMOS transistor NM3, the drain of the NMOS transistor NM3 is connected to the gate of the power transistor NM1 in the LDO circuit, and the source of the NMOS transistor NM3 is grounded. When the output current of the power transistor exceeds a preset value, the power transistor begins current limiting, and the current limiting threshold decreases as the output voltage decreases, thereby reducing the power consumption of the power transistor and reducing heat generation.

[0035] The LDO circuit includes an operational amplifier A1, a power transistor NM1, and resistors R1 to R3. The non-inverting input of operational amplifier A1 is connected to the reference voltage VREF. The output of operational amplifier A1 is connected to the gate of power transistor NM1. The drain of power transistor NM1 is connected to the power supply VIN. The source of NMOS transistor NM1 is connected to one end of resistor R1 and generates a stable output voltage VOUT. The other end of resistor R1 is connected to one end of resistor R2 and the inverting input of operational amplifier A1. The other end of resistor R2 is connected to one end of resistor R3 and generates a voltage divider signal V3. The other end of resistor R3 is grounded.

[0036] The current detection circuit includes a sampling transistor NM2, resistors R4-R7, PMOS transistors PM1 and PM2, current sources I1 and I2, and an NMOS transistor NM4. One end of resistor R4 and one end of resistor R6 are connected to the power supply VIN. The other end of resistor R4 is connected to the drain of sampling transistor NM2 and one end of resistor R5. The gate of sampling transistor NM2 is connected to the gate of power transistor NM1 in the LDO circuit. The source of sampling transistor NM2 is connected to the output voltage VOUT. The other end of resistor R5 is connected to the source of PMOS transistor PM1. The connection is as follows: the other end of resistor R6 is connected to the source of PMOS transistor PM2 and the drain of NMOS transistor NM4; the gate of PMOS transistor PM1 is connected to the gate of PMOS transistor PM2, the drain of PMOS transistor PM1 and one end of current source I1; the drain of PMOS transistor PM2 is connected to the gate of NMOS transistor NM4 and one end of current source I2; the source of NMOS transistor NM4 is connected to one end of resistor R7 and generates detection voltage V2; the other ends of current source I1, current source I2 and resistor R7 are grounded.

[0037] The reference voltage generation circuit includes an operational amplifier A2, a resistor R8, and a current source I3. The non-inverting input of the operational amplifier A2 is connected to the voltage divider signal V3. The output of the operational amplifier A2 is connected to the inverting input of the operational amplifier A2 and one end of the resistor R8. The other end of the resistor R8 is connected to one end of the current source I3 to generate the reference voltage V1. The other end of the current source I3 is connected to the power supply VIN.

[0038] Operational amplifier A3 and NMOS transistor NM3 form an error amplification stage used to amplify the difference between the reference voltage V1 and the detection voltage V2.

[0039] A control method for a current-limiting foldback circuit applied to a power transistor includes the following steps:

[0040] Operational amplifier A1, power transistor NM1, and resistors R1-R3 constitute an LDO circuit. The non-inverting input of operational amplifier A1 is connected to a reference voltage VREF, which can be generated by a bandgap reference or by adding the bandgap reference to the preceding LDO stage. The inverting input of operational amplifier A1 is connected to the voltage divider signal VFB of the output voltage VOUT. When the voltage divider signal VFB is greater than the reference voltage VREF, operational amplifier A1 amplifies the error signal, pulling down the output voltage of operational amplifier A1. The source voltage of power transistor NM1 is pulled down along with its gate voltage, and the voltage divider signal VFB is pulled down along with its source voltage, forming negative feedback. When stable, VREF = VFB. Therefore, the output voltage VOUT can be expressed as:

[0041] .

[0042] The sampling transistor NM2, resistors R4-R7, PMOS transistors PM1 and PM2, current sources I1 and I2, and NMOS transistor NM4 constitute a current detection circuit used to detect the current of power transistor NM1 and convert it proportionally to a detection voltage V2. The width-to-length ratio of power transistor NM1 to sampling transistor NM2 is K:1. The current flowing through power transistor NM1 is IOUT, and the current flowing through sampling transistor NM2 is ISEN. Resistors R4, R5, and R6 have the same resistance value R. Since the value of K is generally larger, ISEN is relatively small. By designing the resistance value of resistor R4 to be smaller, the voltage drop across resistor R4 can be ensured to be very small. Therefore, power transistor NM1 and sampling transistor NM2 have the same gate-source voltage and almost equal drain-source voltage. The relationship between current IOUT and current ISEN is:

[0043] .

[0044] The voltage drop V4 across resistor R4 is expressed as:

[0045] .

[0046] PMOS transistors PM1 and PM2, current sources I1 and I2, NMOS transistor NM4, and resistor R7 form a negative feedback clamping loop. Current sources I1 and I2 have the same current magnitude, and PMOS transistors PM1 and PM2 have the same width-to-length ratio. When the source voltage of PMOS transistor PM2 is higher than that of PMOS transistor PM1, the drain voltage of PMOS transistor PM2 increases, and the source voltage of PMOS transistor PM2 decreases, forming negative feedback. When stable, PMOS transistors PM1 and PM2 have the same source voltage. Therefore, the detected voltage V2 is expressed as:

[0047] .

[0048] Operational amplifier A2, resistor R8, and current source I3 constitute a reference voltage generation circuit. The inverting input terminal of operational amplifier A2 is connected to its output terminal to form negative feedback. In steady state, the output voltage of operational amplifier A2 is equal to the non-inverting input voltage. The voltage at the non-inverting input terminal of the operational amplifier is a voltage divider signal V3, which is a voltage divider of the output voltage VOUT. The voltage divider signal V3 is expressed as:

[0049] .

[0050] Therefore, the reference voltage V1 related to the output voltage VOUT is expressed as:

[0051] .

[0052] Operational amplifier A3 and transistor NM3 form an error amplification stage used to amplify the difference between reference voltage V1 and detection voltage V2.

[0053] When the load current driven by the LDO circuit is much less than the current limiting threshold, the detection voltage V2 is much less than the reference voltage V1. Therefore, the operational amplifier A3 operates in comparator mode, and the output is close to 0V. The NMOS transistor NM3 is turned off, which does not affect the LDO circuit.

[0054] When the load current driven by the LDO circuit gradually increases and exceeds the current limiting threshold, the detection voltage V2 starts to rise and exceeds the reference voltage V1. The output voltage of operational amplifier A3 rises, the gate voltage of power transistor NM1 drops, and the current IOUT decreases, causing the detection voltage V2 to decrease, forming negative feedback. In steady state, the detection voltage V2 equals the reference voltage V1.

[0055] ;

[0056] ;

[0057] Therefore, the current limiting threshold decreases as the output voltage VOUT decreases.

[0058] like Figure 2 The diagram shows a simulation waveform of a current-limiting foldback circuit applied to a power transistor according to the present invention. The waveform has two curves: output voltage VOUT and current IOUT. The horizontal axis represents the resistance value of the load resistor. When the load resistance is large, the LDO circuit works normally, maintaining an output close to 1.8V. As the load resistance gradually decreases, the load current gradually increases until the load current increases to the preset value of 2A. At this point, the current-limiting loop starts to work, and the output voltage drops. As the output voltage drops, the current-limiting value also begins to decrease. Finally, when the output voltage VOUT is 0V, the current-limiting value is maintained at 420mA.

[0059] This invention provides a current-limiting foldback circuit and its control method for power transistors. By generating a reference voltage that decreases with the output voltage, the current-limiting value decreases as the reference voltage decreases when the current-limiting loop is working, thereby realizing the current-limiting foldback function, reducing the power consumption of the power transistor and reducing heat generation.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A current-limiting foldback circuit applied to a power transistor, characterized in that: The current detection circuit comprises a sampling transistor NM2, resistors R4-R7, a PMOS transistor PM1, a PMOS transistor PM2, a current source I1, a current source I2 and an NMOS transistor NM4, one end of the resistor R4 and one end of the resistor R6 are connected to the power supply VIN, the other end of the resistor R4 is connected to the drain of the sampling transistor NM2 and one end of the resistor R5, the gate of the sampling transistor NM2 is connected to the gate of the power transistor NM1 of the LDO circuit, the source of the sampling transistor NM2 is connected to the output voltage VOUT, the other end of the resistor R5 is connected to the source of the PMOS transistor PM1, the other end of the resistor R6 is connected to the source of the PMOS transistor PM2 and the drain of the NMOS transistor NM4, the gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM1 and one end of the current source I1, the drain of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM4 and one end of the current source I2, the source of the NMOS transistor NM4 is connected to one end of the resistor R7 and generates the detection voltage V2, the other end of the current source I1, the other end of the current source I2 and the other end of the resistor R7 are grounded.

2. The current limiting return circuit for a power tube according to claim 1, wherein: The reference voltage generating circuit comprises an operational amplifier A2, a resistor R8 and a current source I3, the non-inverting input terminal of the operational amplifier A2 is connected to the voltage division signal V3, the output terminal of the operational amplifier A2 is connected to the inverting input terminal of the operational amplifier A2 and one end of the resistor R8, the other end of the resistor R8 is connected to one end of the current source I3 and generates the reference voltage V1, the other end of the current source I3 is connected to the power supply VIN.

3. The current limiting return circuit for a power tube according to claim 1, wherein: The operational amplifier A3 and the NMOS transistor NM3 constitute an error amplification stage for amplifying the difference between the reference voltage V1 and the detection voltage V2. The current detection circuit comprises a sampling transistor NM2, resistors R4-R7, a PMOS transistor PM1, a PMOS transistor PM2, a current source I1, a current source I2 and an NMOS transistor NM4, one end of the resistor R4 and one end of the resistor R6 are connected to the power supply VIN, the other end of the resistor R4 is connected to the drain of the sampling transistor NM2 and one end of the resistor R5, the gate of the sampling transistor NM2 is connected to the gate of the power transistor NM1 of the LDO circuit, the source of the sampling transistor NM2 is connected to the output voltage VOUT, the other end of the resistor R5 is connected to the source of the PMOS transistor PM1, the other end of the resistor R6 is connected to the source of the PMOS transistor PM2 and the drain of the NMOS transistor NM4, the gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM1 and one end of the current source I1, the drain of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM4 and one end of the current source I2, the source of the NMOS transistor NM4 is connected to one end of the resistor R7 and generates the detection voltage V2, the other end of the current source I1, the other end of the current source I2 and the other end of the resistor R7 are grounded. The reference voltage generating circuit comprises an operational amplifier A2, a resistor R8 and a current source I3, the non-inverting input terminal of the operational amplifier A2 is connected to the voltage division signal V3, the output terminal of the operational amplifier A2 is connected to the inverting input terminal of the operational amplifier A2 and one end of the resistor R8, the other end of the resistor R8 is connected to one end of the current source I3 and generates the reference voltage V1, the other end of the current source I3 is connected to the power supply VIN. The operational amplifier A3 and the NMOS transistor NM3 constitute an error amplification stage for amplifying the difference between the reference voltage V1 and the detection voltage V2.

4. A control method for a current-limiting return circuit applied to a power tube according to any one of claims 1 to 3, characterized in that Comprising the following steps: The operational amplifier A1, power tube NM1 and resistance R1~R3 constitute the LDO circuit, the positive input terminal of the operational amplifier A1 is connected with the reference voltage VREF, the inverting input terminal of the operational amplifier A1 is connected with the voltage division signal VFB of the output voltage VOUT, when the voltage division signal VFB is greater than the reference voltage VREF, the operational amplifier A1 amplifies the error signal to pull down the voltage at the output terminal of the operational amplifier A1, the source voltage of the power tube NM1 follows the gate voltage of the power tube NM1 and is pulled down, the voltage division signal VFB follows the source voltage of the power tube NM1 and is pulled down, forming a negative feedback, and when stable, VREF=VFB, therefore the output voltage VOUT is expressed as: ； The sampling tube NM2, resistance R4~R7, PMOS tube PM1, PMOS tube PM2, current source I1, current source I2 and NMOS tube NM4 constitute the current detection circuit, the width-length ratio of the power tube NM1 and the sampling tube NM2 is K:1, the current flowing through the power tube NM1 is IOUT, the current flowing through the sampling tube NM2 is ISEN, the resistance R4, the resistance R5 and the resistance R6 have the same resistance R, the power tube NM1 and the sampling tube NM2 have the same gate-source voltage and drain-source voltage, and the relationship between the current IOUT and the current ISEN is: ； The voltage drop V4 on the resistance R4 is expressed as: ； The PMOS tube PM1, the PMOS tube PM2, the current source I1, the current source I2, the NMOS tube NM4 and the resistance R7 constitute a negative feedback clamping loop, the current source I1 and the current source I2 have the same current size, the PMOS tube PM1 and the PMOS tube PM2 have the same width-length ratio, when the source voltage of the PMOS tube PM2 is higher than the source voltage of the PMOS tube PM1, the drain voltage of the PMOS tube PM2 rises, the source voltage of the PMOS tube PM2 decreases, forming a negative feedback, and when stable, the PMOS tube PM1 and the PMOS tube PM2 have the same source voltage, therefore the detection voltage V2 is expressed as: ； The operational amplifier A2, the resistance R8 and the current source I3 constitute the reference voltage generation circuit, the inverting input terminal of the operational amplifier A2 is connected with the output terminal to form a negative feedback, and when stable, the output terminal voltage of the operational amplifier A2 is equal to the voltage of the positive input terminal, the voltage of the positive input terminal of the operational amplifier is the voltage division signal V3, the voltage division signal V3 is the voltage division of the output voltage VOUT, and the voltage division signal V3 is expressed as: ； Therefore, the reference voltage V1 related to the output voltage VOUT is expressed as: ； The operational amplifier A3 and the transistor NM3 constitute an error amplifier stage for amplifying the difference between the reference voltage V1 and the detection voltage V2; When the load current driven by the LDO circuit is much smaller than the current limiting threshold, the detection voltage V2 is much smaller than the reference voltage V1, therefore the operational amplifier A3 works in the comparator state, the output is 0V, the NMOS tube NM3 is turned off, and the LDO circuit is not affected; When the load current driven by the LDO circuit gradually increases and exceeds the current limit threshold, the detection voltage V2 begins to rise and exceeds the reference voltage V1, the output voltage of the operational amplifier A3 rises, the gate voltage of the power transistor NM1 drops, and the current IOUT decreases, resulting in a decrease in the detection voltage V2, forming a negative feedback. In the steady state, the detection voltage V2 is equal to the reference voltage V1, and thus ； ； Therefore, the current limit threshold decreases as the output voltage VOUT decreases.

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