Power switch integrated with temperature sensor and preparation method thereof

Abstract

The invention belongs to the technical field of power switches, and particularly discloses a power switch integrated with a temperature sensor and a preparation method of the power switch. According to the power switch device, the two identical temperature sensing diodes are integrated, the nonlinear influence of saturation current and diode parasitic series resistance on the characteristics of the sensor can be overcome by utilizing the linear relation that the voltage drop difference is in direct proportion to absolute temperature, and the detection precision is improved. Besides, a current mirror structure is integrated, and two constant currents can be copied to bias the two identical temperature sensing diodes only by providing a constant current externally. Meanwhile, the current mirror structure is close to the temperature sensing diode, so that the error of current multiples of the current mirror structure and the temperature sensing diode is reduced, and the detection precision is improved. In addition, a power switch device and a control circuit are integrated together, so that the problems of occupied area, transmission delay and the like of a PCB (Printed Circuit Board) can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power switches and relates to a power switch with an integrated temperature sensor and a preparation method thereof. Background Art

[0002] With the development of consumer electronics, industrial electronics, automotive, and other fields, society's requirements for electronic device performance are becoming increasingly stringent. Power MOSFETs, due to their low power consumption, light weight, and easy control, are widely used in electronic terminals in industrial, automotive, and communications fields. When power switching devices operate at high frequencies and high powers, they generate significant heat. This is especially true for highly integrated chips. The increased power density within the chip and the resulting temperature rise can lead to chip degradation or even outright failure. Therefore, on-chip temperature sensing is essential.

[0003] Traditional solutions include using discrete temperature sensor chips or thermally conducting temperature sensors on the surface of power MOS chips. However, these solutions suffer from low accuracy and slow detection speeds. Other solutions utilize integrated temperature detection circuits with a single transistor or diode, leveraging the quasi-linear relationship between the voltage drop (VD) across a forward-biased diode and temperature. However, these circuits exhibit limited linearity and lack accuracy at high temperatures. Summary of the Invention

[0004] The purpose of the present invention is to propose a power switching device with an integrated temperature sensor. By using two identical integrated diodes with different currents that remain constant within the temperature range to bias them, a configuration proportional to absolute temperature is achieved. This can overcome the nonlinear effects of saturation current and diode parasitic series resistance on sensor characteristics, thereby improving temperature detection accuracy.

[0005] A power switch device with an integrated temperature sensor, comprising:

[0006] An LDMOS power device, a temperature sensor integrated with the LDMOS power device and consisting of two diodes, and a bias circuit integrated with the LDMOS power device and used to provide different currents to the two diodes;

[0007] The LDMOS power device, temperature sensor, and bias circuit are formed on the same substrate and epitaxial layer;

[0008] The temperature sensor is located between the bias circuit and the LDMOS power device; an isolation region is provided on the epitaxial layer for isolating the LDMOS power device from the temperature sensor and the temperature sensor from the bias circuit;

[0009] The depth of the isolation region is less than the thickness of the epitaxial layer, and the opening of the isolation region is located on the upper surface of the epitaxial layer;

[0010] The bias circuit includes a first PMOS device, a second PMOS device and a third PMOS device;

[0011] The first PMOS device forms a current mirror structure with the second PMOS device and the third PMOS device respectively, and the number ratio of the first PMOS device, the second PMOS device and the third PMOS device is 1:M:N, where M and N are both natural numbers and M≠N;

[0012] The second PMOS device and the third PMOS device are respectively used to provide current to a diode constituting the temperature sensor;

[0013] An insulating layer is provided above the epitaxial layer, and a plurality of contact holes are provided on the insulating layer;

[0014] The LDMOS power device, the two diodes, and the first PMOS device, the second PMOS device, and the third PMOS device are respectively led out through corresponding contact hole electrodes; wherein each contact hole electrode passes through a corresponding contact hole.

[0015] In addition, based on the above power switching device, the present invention also proposes a method for preparing a corresponding power switching device with an integrated temperature sensor, the method comprising the following steps:

[0016] Step 1. providing a substrate;

[0017] Step 2: using an epitaxial growth process to grow an epitaxial layer on the substrate;

[0018] Step 3. Using photolithography, etching, and thermal oxidation processes to form an isolation region in the epitaxial layer;

[0019] Step 4. Using ion implantation, forming the deep N-well, N-well, P-type base region and drift region of the first PMOS device, the second PMOS device, the third PMOS device, the diode and the LDMOS power device;

[0020] Step 5. Thermally oxidize to form a gate oxide layer, deposit polysilicon and etch to form a gate;

[0021] Step 6. Ion implantation to form heavily doped N / P type low resistivity regions, and N / P type source and drain regions;

[0022] Step 7. Complete the contact hole process and make the contact hole electrode.

[0023] In addition, based on the above power switch device, the present invention also proposes a power switch with an integrated temperature sensor. The power switch adopts the above power switch device with an integrated temperature sensor, and its technical solution is as follows:

[0024] A power switch with an integrated temperature sensor comprises a control circuit and a power switch device; wherein the power switch device adopts the power switch device with an integrated temperature sensor as described above.

[0025] Preferably, the control circuit is integrated with the LDMOS power device, the temperature sensor and the bias circuit; wherein the LDMOS power device, the temperature sensor, the bias circuit and the control circuit are formed on the same substrate and epitaxial layer.

[0026] On the basis of the above-mentioned power switch device, the present invention integrates the control circuit with the LDMOS power device, the temperature sensor, and the bias circuit, thereby reducing the occupied area of ​​the PCB board, transmission delay, and other problems.

[0027] The present invention has the following advantages:

[0028] 1. The two identical temperature sensing diodes integrated into the power switching device of the present invention are manufactured using the same process and are closely positioned in design, resulting in nearly identical device parameters such as area, junction depth, doping type, and doping concentration. Consequently, changes in electrical characteristics are nearly identical, and the effects of temperature, voltage, and process angle are identical. This ensures that the voltage drop difference between the two temperature sensing diodes is proportional to the absolute temperature, overcoming the nonlinear effects of saturation current and diode parasitic series resistance on sensor characteristics and improving temperature detection accuracy. Furthermore, the present invention further enhances the electrical characteristics of the two temperature sensing diodes by adding redundant components (i.e., redundant diodes) or by employing interdigital matching, further improving temperature detection accuracy.

[0029] 2. The power switch device in the present invention integrates a temperature sensor, which allows the power switch device and the temperature sensor to be placed very close together, enabling faster detection of excessive chip temperature caused by the switching of the power device.

[0030] 3. The integrated current mirror of the present invention is very close to the temperature sensing diode, which makes the current ratio of the two temperature sensing diodes more accurate. At the same time, only a constant current needs to be provided externally, which simplifies the design.

[0031] 4. This invention eliminates the soldering wires and solder points between the power device and the discrete or surface mount temperature sensor, reducing additional inductance, capacitance, and resistance. This not only improves system reliability and stability, but also reduces transmission delay and power loss, thereby increasing system integration and power density. Furthermore, since the power switching components of the entire integrated temperature sensor are integrated on a single chip, potential defects and damage during the packaging process are also reduced.

[0032] 5. There is trench isolation between the power switching device and the temperature sensing diode, which can make the cell very small.

[0033] 6. Using integrated LDMOS power devices can reduce dependence on different suppliers and simplify procurement and inventory management.

[0034] 7. The integrated solution reduces design complexity and the time required for component testing, which helps to speed up the product development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic structural diagram of a power switch device with an integrated temperature sensor in Example 1 of the present invention;

[0036] Figure 2 The schematic diagram of the temperature sensor in Example 1 of the present invention is shown in FIG. Figure 2 (a) is a schematic diagram of the structure of two temperature sensing diodes that constitute the temperature sensor; Figure 2 (b) is a curve diagram of pressure drop and temperature;

[0037] Figure 3 is an equivalent circuit diagram of a power switch device with an integrated temperature sensor in an embodiment of the present invention;

[0038] Figure 4 This is a schematic structural diagram of a power switch device with an integrated temperature sensor in Example 2 of the present invention;

[0039] Figure 5 This is a circuit structure block diagram of a power switch with an integrated temperature sensor in Example 3 of the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0041] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two or three, unless otherwise specifically defined.

[0043] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0044] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0045] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0046] Example 1

[0047] Traditionally, temperature monitoring is achieved using discrete temperature sensor chips or through heat conduction, using temperature sensor patches on the surface of power MOS chips. However, such solutions have low temperature detection accuracy and slow detection speed. There are also integrated temperature detection circuits with a single transistor or diode, which use the quasi-linear relationship between the voltage drop VD across the forward-biased diode and temperature. However, their linearity is limited, and the measurement accuracy is not high enough under high temperature conditions.

[0048] An embodiment of the present invention proposes a power switch device with an integrated temperature sensor. This power switch device incorporates two identical temperature sensing diodes. By leveraging the linear relationship between voltage drop and absolute temperature, the device overcomes the nonlinear effects of saturation current and diode parasitic series resistance on sensor characteristics, thereby improving detection accuracy. Furthermore, the present invention can further enhance temperature detection accuracy by adding redundant components (i.e., redundant diodes) or implementing interdigital matching.

[0049] Furthermore, the power switch device of Example 1 of the present invention incorporates a current mirror structure. By simply supplying a constant current externally, two constant currents can be replicated to bias two identical temperature sensing diodes. Furthermore, the current mirror structure's proximity to the temperature sensing diodes helps minimize errors in the current multiples between the two, improving detection accuracy. Externally applying two different constant currents can introduce errors, such as current fluctuations, differences in solder joints, and wire lengths, which can affect the actual current ratio. Furthermore, this external addition increases complexity and PCB footprint.

[0050] like Figure 1 As shown, the power switching device with an integrated temperature sensor in this embodiment includes an LDMOS power device, a temperature sensor integrated with the LDMOS power device and composed of two diodes D1 and D2, and a bias circuit integrated with the LDMOS power device and used to provide different currents to the two diodes.

[0051] The bias circuit, temperature sensor and LDMOS power device are formed on the same substrate and epitaxial layer, such as Figure 1 On the P-type substrate 1 and the P-type epitaxial layer 2 shown in the figure, the three are arranged in sequence from left to right.

[0052] The P-type epitaxial layer 2 is disposed above the P-type substrate 1 .

[0053] An isolation region is provided on the P-type epitaxial layer 2 for isolating the LDMOS power device from the temperature sensor, and isolating the temperature sensor from the bias circuit. Figure 1 The first isolation region 9 and the second isolation region 9a.

[0054] The first isolation region 9 is used to isolate the temperature sensor from the bias circuit, and the second isolation region 9a is used to isolate the LDMOS power device from the temperature sensor.

[0055] The depths of the first isolation region 9 and the second isolation region 9 a are smaller than the thickness of the P-type epitaxial layer 2 , and the openings of the first isolation region 9 and the second isolation region 9 a are located on the upper surface of the P-type epitaxial layer 2 .

[0056] Corresponding dielectric layers are provided inside the first isolation region 9 and the second isolation region 9a.

[0057] In this embodiment, the first isolation region 9 and the second isolation region 9a are deep trench isolations, which can effectively isolate the active regions of semiconductor devices, thereby reducing harmful interactions between devices and improving the integration of the chip.

[0058] The bias circuit is used to provide different currents to the two diodes D1 and D2 constituting the temperature sensor. The bias circuit includes a first PMOS device, a second PMOS device and a third PMOS device.

[0059] The first PMOS device forms a current mirror structure with the second PMOS device and the third PMOS device respectively, and the number ratio of the first PMOS device, the second PMOS device and the third PMOS device is 1:M:N, M and N are both natural numbers, and M≠N.

[0060] The second PMOS device and the third PMOS device are respectively used to provide current for a diode constituting the temperature sensor.

[0061] A first N-type well region 4 is provided on the P-type epitaxial layer 2 in the region corresponding to the bias circuit formation. The depth of the first N-type well region 4 on the P-type epitaxial layer 2 is smaller than the depths of the first isolation region 9 and the second isolation region 9a on the P-type epitaxial layer 2 .

[0062] The right side surface of the first N-type well region 4 and the left side surface of the first isolation region 9 are in contact with each other.

[0063] The top area of ​​the first N-type well region 4 is formed with an N-type low resistivity region 8, a first P-type source region 7, a first P-type drain region 7a, a second P-type source region 7b, a second P-type drain region 7c, a third P-type source region 7d and a third P-type drain region 7e in sequence from left to right.

[0064] There is one first P-type source region 7 and one first P-type drain region 7a.

[0065] A first gate oxide layer 10 is formed above the region between the first P-type source region 7 and the first P-type drain region 7 a . The first gate oxide layer 10 partially contacts the upper surfaces of the first P-type source region 7 and the first P-type drain region 7 a .

[0066] A first gate 11 is disposed above the first gate oxide layer 10 .

[0067] There are M second P-type source regions 7b and M second P-type drain regions 7c, and 7b and 7c are in one-to-one correspondence.

[0068] A second gate oxide layer 10a is formed above the region between each second P-type source region 7b and each second P-type drain region 7c; the second gate oxide layer 10a partially contacts the upper surfaces of the second P-type source region 7b and the second P-type drain region 7c.

[0069] A second gate 11 a is disposed above the second gate oxide layer 10 a .

[0070] There are N third P-type source regions 7d and N third P-type drain regions 7e, and 7d and 7e are in one-to-one correspondence.

[0071] A third gate oxide layer 10b is formed above the region between each third P-type source region 7d and each third P-type drain region 7e. The third gate oxide layer 10b partially contacts the upper surfaces of the third P-type source region 7d and the third P-type drain region 7e.

[0072] A third gate 11 b is disposed above the third gate oxide layer 10 b .

[0073] The first PMOS device is composed of the first P-type source region 7, the first P-type drain region 7a, the first gate oxide layer 10 and the first gate 11. The number of the first PMOS device is one.

[0074] Each corresponding second P-type source region 7b, each second P-type drain region 7c, each second gate oxide layer 10a and each second gate 11a constitutes a second PMOS device, and the number of the second PMOS devices is M.

[0075] Each corresponding third P-type source region 7d, each third P-type drain region 7e, each third gate oxide layer 10b and each third gate 11b constitute a third PMOS device, and the number of the third PMOS devices is N.

[0076] Figure 1 Only one second PMOS device is shown, and an ellipsis is used behind it to indicate the second PMOS device not shown. Similarly, only one third PMOS device is shown, and an ellipsis is used behind it to indicate the third PMOS device not shown.

[0077] The areas, junction depths, doping types, and doping concentrations of the components of the first PMOS device, the second PMOS device, and the third PMOS device are the same to ensure the same performance.

[0078] For the sake of convenience, the first PMOS device, the second PMOS device and the third PMOS device are replaced by PMOS1, PMOS2 and PMOS3 respectively. Figure 3 shown.

[0079] A second deep N well 3 a is provided on the P-type epitaxial layer 2 in the region corresponding to the temperature sensor. The depth of the second deep N well 3 a on the P-type epitaxial layer 2 is less than the depth of the isolation region on the P-type epitaxial layer 2 .

[0080] The left side of the second deep N well 3a contacts the right side of the first isolation region 9. The right side of the second deep N well 3a contacts the left side of the second isolation region 9a.

[0081] A first P-type base region 6 and a second P-type base region 6 a are formed in the second deep N-well 3 a .

[0082] The first P-type base region 6 is located at the left area of ​​the top of the second deep N-well, and the second P-type base region 6a is located at the right area of ​​the top of the second deep N-well, with a certain distance between them.

[0083] Two first P-type positive regions 7 f and one first N-type negative region 8 a are formed in the first P-type base region 6 .

[0084] The two first P-type positive regions 7 f are respectively located at the left and right regions of the top of the first P-type base region 6 , and the first N-type negative region 8 a is located at the center region of the top of the first P-type base region 6 .

[0085] The distances between the two first P-type positive regions 7f and the first N-type negative region 8a are the same.

[0086] Two second P-type positive regions 7g and one second N-type negative region 8b are formed in the second P-type base region 6a.

[0087] The two second P-type positive regions 7g are respectively located at the left and right regions of the top of the second P-type base region 6a, and the second N-type negative region 8b is located at the top center region of the second P-type base region 6a.

[0088] The distances between the two second P-type positive regions 7g and the second N-type negative region 8b are the same.

[0089] The first temperature sensor D1 is composed of the first P-type base region 6, the first P-type positive region 7f and the first N-type negative region 8a; the second temperature sensor D2 is composed of the second P-type base region 6a, the second P-type positive region 7g and the second N-type negative region 8b.

[0090] The areas, junction depths, doping types, and doping concentrations of the components of the first temperature sensor D1 and the second temperature sensor D2 are respectively the same, so as to ensure that the structures of D1 and D2 are completely identical.

[0091] A first deep N-well 3 is provided on the P-type epitaxial layer 2 in the region corresponding to the formation of the LDMOS power device. The depth of the first deep N-well 3 on the P-type epitaxial layer 2 is less than the depth of the isolation region on the P-type epitaxial layer 2 .

[0092] The left side of the first deep N well 3 and the right side of the second isolation region 9 a are in contact with each other.

[0093] The first N-type well region 4 , the first isolation region 9 , the first P-type base region 6 , the second P-type base region 6 a , the second isolation region 9 a and the first deep N-well 3 are arranged in sequence from left to right and are all located in the top area of ​​the P-type epitaxial layer 2 .

[0094] A third P-type base region 6 b and an N-type drift region 5 are sequentially formed in the first deep N-well 3 from left to right, wherein the third P-type base region 6 b and the N-type drift region 5 are both located in the top region of the first deep N-well 3 .

[0095] A P-type low resistivity region 7h and an N-type source region 8c are formed in the third P-type base region 6b from left to right. The P-type low resistivity region 7h and the N-type source region 8c are both the top left area of ​​the third P-type base region 6b and the sides of the two are in contact with each other.

[0096] An N-type drain region 8 d is formed in the N-type drift region 5 , and the N-type drain region 8 d is located at the top right region of the N-type drift region 5 .

[0097] A fourth gate oxide layer 10c is formed on the top right area of ​​the third P-type base region 6b and partially contacts the N-type source region 8c and the upper surface of the N-type drift region 5. A fourth gate 11c is provided above the fourth gate oxide layer 10c.

[0098] The LDMOS power device is composed of the third P-type base region 6b, the N-type drift region 5, the P-type low-resistivity region 7h, the N-type source region 8c, the N-type drain region 8d, the fourth gate oxide layer 10c and the fourth gate 11c.

[0099] An insulating layer 12 is provided above the P-type epitaxial layer 2 . In this embodiment, the insulating layer 12 may be made of, for example, borophosphosilicate glass, silicon dioxide, benzocyclobutene, aluminum oxide, sapphire, or hafnium oxide.

[0100] A plurality of contact holes are provided on the insulating layer 12, such as Figure 1 The contact hole 13 is shown in FIG.

[0101] Above the insulating layer 12 is a metal layer, and the material of the metal layer can be one or more of aluminum, copper, gold or silver.

[0102] The LDMOS power device, the two diodes, and the first PMOS device, the second PMOS device, and the third PMOS device are respectively led out through corresponding contact hole electrodes; wherein each contact hole electrode passes through the corresponding contact hole 13 .

[0103] Specifically, the N-type low resistivity region 8, the first P-type source region 7, the first gate 11, the first P-type drain region 7a, the second P-type source region 7b, the second gate 11a, the second P-type drain region 7c, the third P-type source region 7d, the third gate 11b, the third P-type drain region 7e, the first P-type positive region 7f, the first N-type negative region 8a, the second P-type positive region 7g, the second N-type negative region 8b, the P-type low resistivity region 7h, the N-type source region 8c, the fourth gate 11c and the N-type drain region 8d are connected to the metal layer through the contact hole 13.

[0104] Among them, the metal electrodes connected to the N-type low resistivity region 8, the first P-type source region 7, the second P-type source region 7b and the third P-type source region 7d are short-circuited to form a first metallized source 14; the metal electrodes connected to the first gate 11, the first P-type drain region 7a, the second gate 11a and the third gate 11b are short-circuited to form a first metallized gate 15; the metal electrode connected to the second P-type drain region 7c and the first P-type positive region 7f is short-circuited to form a first metallized drain 16; the metal electrode connected to the third P-type drain region 7e and the second P-type positive region 7g is short-circuited to form a second metallized drain 17; the metal electrode connected to the first N-type negative region 8a and the second N-type negative region 8b is short-circuited to form a metallized negative electrode 18; the metal electrode connected to the P-type low resistivity region 7h and the N-type source region 8c is short-circuited to form a second metallized source 19; the metal electrode connected to the fourth gate 11c is a second metallized gate 20; and the metal electrode connected to the N-type drain region 8d is a third metallized drain 21. Figure 1 Marked 14, 15, 16, 17, 18, 19, 20, 21 are all contact hole electrodes.

[0105] The working mechanism of the temperature measurement of the power switch with integrated temperature sensor in this embodiment is: keep constant different current biasing two identical integrated temperature sensing diodes within the temperature range to achieve the voltage drop difference between the two diodes proportional to the absolute temperature, such as Figure 2 As shown in (a) of the figure, this overcomes the nonlinear effects of saturation current and diode parasitic series resistance on sensor characteristics. The theory is to use two diodes D1 and D2 to monitor temperature changes by the difference in their conduction voltage drops.

[0106] According to the I_V characteristic of the diode, Id=Is[exp(qVD / KT)-1].

[0107] Where Is is the saturation current, VD is the forward voltage drop, q is the charge of the electron, K is the Boltzmann constant, and T is the thermodynamic temperature. Therefore, we get: ΔV D =VD1-VD2=(KT / q)ln(ID1 / ID2).

[0108] Where ID1 and ID2 are the currents flowing through diodes D1 and D2 respectively. When ID1 = ID2, the voltage drop ΔV between the two diodes D1 and D2 is D It has a linear relationship with temperature T, such as Figure 2 As shown in (b), the temperature can be accurately monitored.

[0109] PMOS1 forms a current mirror structure with PMOS2 and PMOS3 respectively to realize current replication. If the number ratio of PMOS2 to PMOS1 is M:1, then the current replication ratio is M:1. Similarly, the current replication ratio of PMOS3 to PMOS1 is N:1.

[0110] At this time, a constant current can be input externally to achieve two different constant currents through the current mirror structure, and then biased to two identical diodes. The external drive circuit realizes the switching effect of LDMOS. The port number in the figure is the same as Figure 1 Serial number corresponding.

[0111] Traditional integrated temperature sensor diodes are single devices. Device parameters such as doping concentration and doping area may not be identical across different chips, resulting in varying temperature values. Furthermore, the detected values ​​can fluctuate slightly depending on the process angle, power supply voltage, and ambient temperature. The two temperature sensor diodes fabricated in this embodiment are manufactured using the same process and are closely positioned. This ensures that device parameters such as area, junction depth, doping type, and doping concentration are nearly identical, resulting in nearly identical changes in electrical characteristics.

[0112] In particular, matching can be used in the design to further improve the similarity of the electrical characteristics of the two temperature sensing diodes, such as adding redundant components or interdigital matching. Figure 1 Place another identical temperature sensing diode on both sides of the two middle temperature sensing diodes. The spacing between the four temperature sensing diodes is the same. The metal electrodes of the two middle temperature sensing diodes are connected to the Figure 1 The metal electrodes of the two temperature sensing diodes on both sides are short-circuited together. Figure 1 Place two more identical temperature sensing diodes on the left or right of the two temperature sensing diodes. The spacing between the four temperature sensing diodes is the same. The metal electrodes of the first and third temperature sensing diodes from left to right are connected to the Figure 1 The first temperature sensor D1 is the same as the second and fourth temperature sensor diodes. Figure 1 The second temperature sensor D2 is the same.

[0113] At this time, the metal potentials of the two temperature sensing diodes D1 and D2 are connected to PMOS2 and PMOS3, and the current of the temperature sensing diodes is provided by the current mirror structure. Only a constant current needs to be provided externally. Since the current mirror structure is relatively close to the diodes, it helps to reduce the error in the current multiples between the two, thereby improving the accuracy of temperature detection.

[0114] Based on the structure of the power switch device with integrated temperature sensor, this embodiment 1 further proposes a method for preparing the power switch device with integrated temperature sensor, which includes the following steps:

[0115] Step 1. Providing a P-type substrate 1;

[0116] Step 2: Using an epitaxial growth process, a P-type epitaxial layer 2 is grown on the P-type substrate 1;

[0117] Step 3. Using photolithography, etching, and thermal oxidation processes, a first isolation region 9 and a second isolation region 9d are formed in the P-type epitaxial layer 2;

[0118] Step 4. Using ion implantation, forming the deep N-well, N-well, P-type base region and drift region of the first PMOS device, the second PMOS device, the third PMOS device, the diode and the LDMOS power device;

[0119] Step 5. Thermally oxidize to form a gate oxide layer, deposit polysilicon and etch to form a gate;

[0120] Step 6. Ion implantation to form heavily doped N / P type low resistivity regions, and N / P type source and drain regions;

[0121] Step 7. Complete the contact hole 13 process and make the contact hole electrode.

[0122] Example 2

[0123] This embodiment 2 also describes a power switch device with an integrated temperature sensor. Except for the following technical features, the power switch device is different from the above embodiment 1. The rest of the technical features can refer to the above embodiment 1.

[0124] Based on the structure of the above embodiment 1, the PN junction diode is converted into a triode structure. Figure 4 Taking the NPN transistor as an example, the collector and base are connected to realize the diode effect. The transistor has low noise and relatively good temperature linearity.

[0125] like Figure 4 As shown, a third deep N well 3b and a fourth deep N well 3c are provided on the P-type epitaxial layer 2 in the region corresponding to the formation of the temperature sensor, wherein a certain distance exists between the third deep N well 3b and the fourth deep N well 3c.

[0126] The depths of the third deep N-well 3 b and the fourth deep N-well 3 c on the P-type epitaxial layer 2 are smaller than the depth of the isolation region.

[0127] The third deep N well 3b is located on the left side of the fourth deep N well 3c. The left side of the third deep N well 3b contacts the right side of the first isolation region 9, and the right side of the fourth deep N well 3c contacts the left side of the second isolation region 9a.

[0128] Two second N-type well regions 4 a and a first P-type base region 6 are formed in the third deep N-well 3 b.

[0129] The two second N-type well regions 4a are respectively located at two side regions (ie, left and right regions) of the top of the third deep N-well 3b, and the first P-type base region 6 is located in the middle region of the top of the third deep N-well 3b.

[0130] The distances between the two second N-type well regions 4 a and the first P-type base region 6 are the same.

[0131] The structures in the two second N-type well regions 4a are the same. A third N-type negative region 8e is formed in each second N-type well region 4a. The third N-type negative region 8e is located in the top middle area of ​​the second N-type well region 4a.

[0132] Two first P-type positive regions 7 f and one first N-type negative region 8 a are formed in the first P-type base region 6 .

[0133] The two first P-type positive regions 7f are respectively located at two side regions (ie, left and right regions) of the top of the first P-type base region 6 , and the first N-type negative region 8a is located in the middle region of the top of the first P-type base region 6 .

[0134] The distances between the two first P-type positive regions 7f and the first N-type negative region 8a are the same.

[0135] Two third N-type well regions 4b and a second P-type base region 6a are formed in the fourth deep N-well 3c.

[0136] The two third N-type well regions 4b are respectively located at two side regions (ie, left and right regions) of the top of the fourth deep N-well 3c, and the second P-type base region 6a is located in the middle region of the top of the fourth deep N-well 3c.

[0137] The distances between the two third N-type well regions 4 b and the second P-type base region 6 a are the same.

[0138] The two third N-type well regions 4b have the same structure. A fourth N-type negative region 8f is formed in each third N-type well region 4b. The fourth N-type negative region 8f is located in the top middle area of ​​the third N-type well region 4b.

[0139] Two second P-type positive regions 7g and one second N-type negative region 8b are formed in the second P-type base region 6a.

[0140] The two second P-type positive regions 7g are respectively located at the top two side regions (ie, the left and right regions) of the second P-type base region 6a, and the second N-type negative region 8b is located at the top middle region of the second P-type base region 6a.

[0141] The distances between the two second P-type positive regions 7g and the second N-type negative region 8b are the same.

[0142] The first temperature sensor D1 is composed of the third deep N-well 3b, the second N-type well region 4a, the third N-type negative region 8e, the first P-type base region 6, the first P-type positive region 7f and the first N-type negative region 8a.

[0143] The second temperature sensor D2 is composed of the fourth deep N-well 3c, the third N-type well region 4b, the fourth N-type negative region 8f, the second P-type base region 6a, the second P-type positive region 7g and the second N-type negative region 8b.

[0144] The areas, junction depths, doping types, and doping concentrations of the components of the first temperature sensor D1 and the second temperature sensor D2 are respectively the same, so as to ensure that the structures of D1 and D2 are completely identical.

[0145] Specifically, the N-type low resistivity region 8, the first P-type source region 7, the first gate 11, the first P-type drain region 7a, the second P-type source region 7b, the second gate 11a, the second P-type drain region 7c, the third P-type source region 7d, the third gate 11b, the third P-type drain region 7e, the third N-type negative region 8e, the first P-type positive region 7f, the first N-type negative region 8a, the fourth N-type negative region 8f, the second P-type positive region 7g, the second N-type negative region 8b, the P-type low resistivity region 7h, the N-type source region 8c, the fourth gate 11c and the N-type drain region 8d are connected to the metal layer through the contact hole 13; the metal layer is arranged above the insulating layer 13.

[0146] Among them, the metal electrodes connected to the N-type low resistivity region 8, the first P-type source region 7, the second P-type source region 7b and the third P-type source region 7d are short-circuited to form a first metallized source 14; the metal electrodes connected to the first gate 11, the first P-type drain region 7a, the second gate 11a and the third gate 11b are short-circuited to form a first metallized gate 15; the metal electrodes connected to the second P-type drain region 7c, the third N-type negative region 8e and the first P-type positive region 7f are short-circuited to form a first metallized drain 16; the metal electrodes connected to the third P-type drain region 7e, the fourth N-type negative region 8f and the second P-type positive region 7g are short-circuited to form a second metallized drain 17; the metal electrodes connected to the first N-type negative region 8a and the second N-type negative region 8b are short-circuited to form a metallized negative electrode 18; the metal electrodes connected to the P-type low resistivity region 7h and the N-type source region 8c are short-circuited to form a second metallized source 19; the metal electrode connected to the fourth gate 11c is a second metallized gate 20; and the metal electrode connected to the N-type drain region 8d is a third metallized drain 21.

[0147] The method for preparing the power switch device in this embodiment 2 is the same as that in the above embodiment 1 and will not be described again here.

[0148] Of course, the NPN transistor in this embodiment 2 can also be manufactured as a PNP transistor.

[0149] Example 3

[0150] This embodiment 3 proposes a power switch with an integrated temperature sensor, such as Figure 5 As shown, the power switch includes a power switch device 110 and a control circuit. The power switch device 110 is the power switch device in the above-mentioned embodiment 1 or 2.

[0151] like Figure 5 As shown, the control circuit includes a power detection circuit 101, a reference circuit 102, a chip logic and protection circuit 103, an active clamping circuit 109, and the output device described therein, namely a power switch device 110 with an integrated temperature sensor.

[0152] This device schematic depicts an N-type MOSFET device used as the output device.

[0153] The power detection circuit 101 is used to detect whether the VDD voltage is lower than the normal working threshold to prevent functional errors caused by undervoltage.

[0154] The reference circuit 102 is used to provide a reference voltage to the remaining circuits and to provide different constant currents to the two temperature sensing diodes, so that the voltage drop difference between the two diodes is proportional to the absolute temperature. This overcomes the nonlinear effects of the saturation current and the parasitic series resistance of the diodes on the sensor characteristics and achieves highly linear temperature detection.

[0155] The chip logic and protection circuit 103 includes an input interface circuit 105 and a driving logic and protection circuit 104 .

[0156] The input interface circuit 105 is used to be compatible with 3.3V or 5V input signals provided by the CPU or DSP.

[0157] The driving logic and protection circuit 104 includes an over-temperature protection circuit 106 , an over-current protection circuit 107 , and a driving circuit 108 .

[0158] The over-temperature protection circuit 106 is used to detect the difference between the two diodes to detect the temperature, and will turn off the transistor if it exceeds a set threshold.

[0159] The overcurrent protection circuit 107 is used to prevent the transistor from being damaged by excessive current. If the current exceeds a set threshold, the threshold current will be maintained or the transistor will be turned off.

[0160] The driving circuit 108 is used for logic processing and provides a large driving capability to drive the subsequent power MOS, ie, the low-side device M1 .

[0161] The active clamping circuit 109 is used to suppress the surge voltage generated when the power device is turned off, protecting the power device from high voltage breakdown, thereby extending its service life and improving the reliability of the system.

[0162] The power switch device 110 includes a power device M1 and diodes D1 and D2 .

[0163] In a preferred embodiment, the control circuit is integrated with the power device M1, the temperature sensor composed of diodes D1 and D2, and the bias circuit; wherein the LDMOS power device, the temperature sensor composed of diodes D1 and D2, the bias circuit, and the control circuit are formed on the same substrate 1 and epitaxial layer 2.

[0164] In this embodiment, the power switch device with integrated temperature sensor and the control circuit are integrated on the same substrate and electrically connected, which greatly reduces the area occupied by the PCB board, improves the integration level, improves the temperature detection accuracy, reduces transmission delay, electromagnetic interference and power loss, etc., and forms an efficient and compact power switch chip solution with integrated temperature sensor.

[0165] It should be noted that, in the above description, NLDMOS is used, but it can also be manufactured as PLDMOS.

[0166] Of course, the above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above-mentioned embodiments. It should be noted that all equivalent substitutions and obvious deformation forms made by any technician familiar with this field under the guidance of this specification fall within the substantive scope of this specification and should be protected by the present invention.

Claims

1. A power switch device with an integrated temperature sensor, characterized in that: include: An LDMOS power device, a temperature sensor integrated with the LDMOS power device and consisting of two diodes, and a bias circuit integrated with the LDMOS power device and used to provide different currents to the two diodes; The LDMOS power device, temperature sensor and bias circuit are formed on the same substrate and epitaxial layer; The temperature sensor is located between the bias circuit and the LDMOS power device; an isolation region is provided on the epitaxial layer for isolating the temperature sensor from the LDMOS power device and the temperature sensor from the bias circuit; The depth of the isolation region is less than the thickness of the epitaxial layer, and the opening of the isolation region is located on the upper surface of the epitaxial layer; The bias circuit includes a first PMOS device, a second PMOS device and a third PMOS device; The first PMOS device forms a current mirror structure with the second PMOS device and the third PMOS device respectively, and the number ratio of the first PMOS device, the second PMOS device and the third PMOS device is 1:M:N, where M and N are both natural numbers and M≠N; The second PMOS device and the third PMOS device are respectively used to provide current to a diode constituting the temperature sensor; An insulating layer is provided above the epitaxial layer, and a plurality of contact holes are provided on the insulating layer; The LDMOS power device, the two diodes, and the first PMOS device, the second PMOS device, and the third PMOS device are respectively led out through corresponding contact hole electrodes; wherein each contact hole electrode passes through a corresponding contact hole.

2. The power switch device with integrated temperature sensor according to claim 1, characterized in that: A first N-type well region is provided on the epitaxial layer in a region corresponding to the formation of the bias circuit; wherein the depth of the first N-type well region on the epitaxial layer is less than the depth of the isolation region on the epitaxial layer; The top area of ​​the first N-type well region is sequentially formed with an N-type low resistivity region, a first P-type source region, a first P-type drain region, a second P-type source region, a second P-type drain region, a third P-type source region, and a third P-type drain region; There is one first P-type source region and one first P-type drain region; forming a first gate oxide layer above the region between the first P-type source region and the first P-type drain region, wherein the first gate oxide layer partially contacts upper surfaces of the first P-type source region and the first P-type drain region; and disposing a first gate electrode above the first gate oxide layer; There are M second P-type source regions and M second P-type drain regions, and they are in one-to-one correspondence; forming a second gate oxide layer above the region between each second P-type source region and each second P-type drain region; the second gate oxide layer partially contacts the upper surfaces of the second P-type source region and the second P-type drain region; and disposing a second gate electrode above the second gate oxide layer; There are N third P-type source regions and N third P-type drain regions, and they are in one-to-one correspondence; forming a third gate oxide layer above the region between each third P-type source region and each third P-type drain region, wherein the third gate oxide layer partially contacts the upper surfaces of the third P-type source region and the third P-type drain region; and disposing a third gate electrode above the third gate oxide layer; A first PMOS device is formed by a first P-type source region, a first P-type drain region, a first gate oxide layer and a first gate; Each corresponding second P-type source region, each second P-type drain region, each second gate oxide layer, and each second gate constitute a second PMOS device, and the number of the second PMOS devices is M; Each corresponding third P-type source region, each third P-type drain region, each third gate oxide layer, and each third gate constitute a third PMOS device, and the number of the third PMOS devices is N; The areas, junction depths, doping types, and doping concentrations of the components of the first PMOS device, the second PMOS device, and the third PMOS device are the same, so as to ensure the same performance of the PMOS devices.

3. The power switch device with integrated temperature sensor according to claim 1, characterized in that: A second deep N-well is provided on the epitaxial layer in a region corresponding to the formation of the temperature sensor; wherein the depth of the second deep N-well on the epitaxial layer is less than the depth of the isolation region on the epitaxial layer; A first P-type base region and a second P-type base region are formed in the second deep N-well; the first P-type base region is located in the left area of ​​the top of the second deep N-well, and the second P-type base region is located in the right area of ​​the top of the second deep N-well, with a gap between the first P-type base region and the second P-type base region; Two first P-type positive regions and one first N-type negative region are formed in the first P-type base region; The two first P-type positive regions are respectively located in the left and right regions of the top of the first P-type base region, and the first N-type negative region is located in the middle region of the top of the first P-type base region; the two first P-type positive regions and the first N-type negative region are spaced the same distance apart; Two second P-type positive regions and one second N-type negative region are formed in the second P-type base region; The two second P-type positive regions are respectively located in the left and right regions of the top of the second P-type base region, and the second N-type negative region is located in the middle region of the top of the second P-type base region; the two second P-type positive regions and the second N-type negative region are spaced the same distance apart; The first temperature sensor D1 is composed of a first P-type base region, a first P-type positive region, and a first N-type negative region; the second temperature sensor D2 is composed of a second P-type base region, a second P-type positive region, and a second N-type negative region; The areas, junction depths, doping types, and doping concentrations of the components of the first temperature sensor D1 and the second temperature sensor D2 are identical to ensure that the structures of D1 and D2 are completely identical.

4. The power switch device with integrated temperature sensor according to claim 1, characterized in that: A first deep N-well is provided on the epitaxial layer in a formation area corresponding to the LDMOS power device; wherein the depth of the first deep N-well on the epitaxial layer is less than the depth of the isolation region on the epitaxial layer; A third P-type base region and an N-type drift region are formed in sequence from left to right in the top area of ​​the first deep N-well; A P-type low resistivity region and an N-type source region are sequentially formed in the third P-type base region from left to right, both of which are located in the top left area of ​​the third P-type base region and contact each other on the side; An N-type drain region is formed in the N-type drift region, and the N-type drain region is located in the top right area of ​​the N-type drift region; A fourth gate oxide layer is formed above the top right area of ​​the third P-type base region, the fourth gate oxide layer partially contacts the upper surfaces of the N-type source region and the N-type drift region, and a fourth gate is provided above the fourth gate oxide layer; The LDMOS power device is composed of a third P-type base region, an N-type drift region, a P-type low resistivity region, an N-type source region, an N-type drain region, a fourth gate oxide layer and a fourth gate.

5. The power switch device with integrated temperature sensor according to claim 1, characterized in that: The insulating layer is made of borophosphosilicate glass, silicon dioxide, benzocyclobutene, aluminum oxide, sapphire or hafnium oxide.

6. The power switch device with integrated temperature sensor according to claim 1, characterized in that: A third deep N-well and a fourth deep N-well are provided on the epitaxial layer in a region corresponding to the temperature sensor, wherein the depth of the third deep N-well and the fourth deep N-well on the epitaxial layer is less than the depth of the isolation region, and there is a gap between the third deep N-well and the fourth deep N-well; Two second N-type well regions and a first P-type base region are formed in the third deep N-well; The two second N-type well regions are respectively located on the left and right sides of the top of the third deep N-well, and the first P-type base region is located in the center of the top of the third deep N-well; the two second N-type well regions are spaced the same distance from the first P-type base region; A third N-type negative region is formed in the second N-type well region, and the third N-type negative region is located in the middle area of ​​the top of the second N-type well region; Two first P-type positive regions and one first N-type negative region are formed in the first P-type base region; The two first P-type positive regions are respectively located in the left and right regions of the top of the first P-type base region, and the first N-type negative region is located in the middle region of the top of the first P-type base region; the two first P-type positive regions and the first N-type negative region are spaced the same distance apart; Two third N-type well regions and a second P-type base region are formed in the fourth deep N-well; The two third N-type well regions are respectively located at the left and right regions of the top of the fourth deep N-well, and the second P-type base region is located in the middle region of the top of the fourth deep N-well; the two third N-type well regions are spaced the same distance from the second P-type base region; A fourth N-type negative region is formed in the third N-type well region, and the fourth N-type negative region is located in the middle area of ​​the top of the third N-type well region; Two second P-type positive regions and one second N-type negative region are formed in the second P-type base region; The two second P-type positive regions are respectively located in the left and right regions of the top of the second P-type base region, and the second N-type negative region is located in the middle region of the top of the second P-type base region; the two second P-type positive regions and the second N-type negative region are spaced the same distance apart; The first temperature sensor D1 is composed of a third deep N-well, a second N-type well region, a third N-type negative region, a first P-type base region, a first P-type positive region and a first N-type negative region; The second temperature sensor D2 is composed of a fourth deep N-well, a third N-type well region, a fourth N-type negative region, a second P-type base region, a second P-type positive region, and a second N-type negative region; The areas, junction depths, doping types, and doping concentrations of the components of the first temperature sensor D1 and the second temperature sensor D2 are identical to ensure that the structures of D1 and D2 are completely identical.

7. The power switch device with integrated temperature sensor according to claim 1, characterized in that: When designing the structure of the temperature sensor integrated with the LDMOS power device, redundant diodes are added or interdigital matching is adopted to further improve the similarity of the electrical characteristics of the two diodes constituting the temperature sensor.

8. A method for preparing a power switch device with an integrated temperature sensor, wherein the method is directed to the power switch device with an integrated temperature sensor according to claim 1, characterized in that: The preparation method comprises the following steps: Step 1. providing a substrate; Step 2: using an epitaxial growth process to grow an epitaxial layer on the substrate; Step 3. Using photolithography, etching, and thermal oxidation processes to form an isolation region in the epitaxial layer; Step 4. Using ion implantation, forming the deep N-well, N-well, P-type base region and drift region of the first PMOS device, the second PMOS device, the third PMOS device, the diode and the LDMOS power device; Step 5. Thermally oxidize to form a gate oxide layer, deposit polysilicon and etch to form a gate; Step 6. Ion implantation to form heavily doped N / P type low resistivity regions, and N / P type source and drain regions; Step 7. Complete the contact hole process and make the contact hole electrode.

9. A power switch with an integrated temperature sensor, comprising a control circuit and a power switch device; characterized in that: The power switching device is a power switching device with an integrated temperature sensor as claimed in any one of claims 1 to 7.

10. The power switch with integrated temperature sensor according to claim 9, characterized in that: The control circuit is integrated with the LDMOS power device, the temperature sensor and the bias circuit; wherein the control circuit, the LDMOS power device, the temperature sensor and the bias circuit are formed on the same substrate and epitaxial layer.

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