Clock calibration method and time-interleaved analog-to-digital converter
By calculating the correlation value of the ADC in TIADC and calibrating the clock phase, the sampling time mismatch problem of TIADC is solved, low-complexity and high-precision clock calibration is achieved, and the performance of TIADC is improved.
Patent Information
- Application Number
- CN202410377599.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-28
- Publication Date
- 2025-09-16
AI Technical Summary
In the existing technology, the time-interleaved analog-to-digital converter (TIADC) has the problem of sampling time mismatch, which leads to high calibration complexity, low accuracy and inability to perform effective calibration in the foreground, affecting the receiver performance.
By calculating the correlation value between each ADC and its two adjacent ADCs in sampling order, the mismatch size at the sampling time is estimated, and the ADC clock phase is calibrated based on the correlation value. The LMS algorithm is used to adjust the delay line to calibrate the clock phase. This supports foreground and background calibration and reduces computational complexity.
It achieves low-complexity, high-precision clock calibration, improves the overall performance of TIADC, supports foreground and background calibration, reduces sampling time mismatch error, and improves system linearity.
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Figure CN120658265A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of signal processing technology, and in particular to a clock calibration method and a time-interleaved analog-to-digital converter. Background Art
[0002] The rapidly developing fields of AI (Artificial Intelligence) and data-intensive applications are driving high-performance interconnect technologies. AI applications, with their massive data sets and complex algorithms, are driving unprecedented demands for data transmission speeds. To support newer, faster data interfaces, transceiver speeds need to be significantly increased. Consequently, receiver architectures based on TIADC (Time-Interleaved Analog Digital Converter) are becoming mainstream. The performance of each ADC (Analog Digital Converter) in the TIADC is a key factor influencing receiver performance.
[0003] Affected by various physical and electrical characteristics, ADC has the problem of sampling time mismatch, which is the key difficulty in calibrating TIADC. Summary of the Invention
[0004] In view of the above-mentioned deficiencies in the prior art, the present disclosure provides a clock calibration method and a time-interleaved analog-to-digital converter.
[0005] In a first aspect, an embodiment of the present disclosure provides a clock calibration method, comprising:
[0006] Obtaining an output value of each analog-to-digital converter ADC in a time-interleaved analog-to-digital converter TIADC; wherein the TIADC includes at least two ADCs connected in parallel, and each ADC performs sampling in sequence according to a sampling order;
[0007] For each ADC, calculating a first correlation value and a second correlation value of the ADC according to an output value of the ADC and output values of two ADCs adjacent to the ADC in sampling order;
[0008] The clock phase of the ADC is calibrated according to the first correlation value and the second correlation value.
[0009] In a second aspect, an embodiment of the present disclosure provides a time-interleaved analog-to-digital converter, comprising:
[0010] At least two ADCs in parallel;
[0011] a processing module configured to obtain an output value of each analog-to-digital converter (ADC) in a time-interleaved analog-to-digital converter (TIADC); wherein each of the ADCs performs sampling in sequence; and, for each ADC, calculate a first correlation value and a second correlation value of the ADC based on the output value of the ADC and output values of two ADCs adjacent to the ADC in the sampling sequence;
[0012] A calibration module is configured to calibrate a clock phase of the ADC according to the first correlation value and the second correlation value.
[0013] Embodiments of the present disclosure provide a clock calibration method and a time-interleaved analog-to-digital converter. In this embodiment, by calculating the correlation value between each ADC and its two sequentially adjacent ADCs, this correlation value reflects the relationship between the sampling times of the ADC and its two sequentially adjacent ADCs. This correlation value can be used to estimate the magnitude of the sampling time mismatch and calibrate the ADC's clock phase. This calibration process reduces computational complexity and improves the overall performance of the ADC. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 A schematic diagram of the structure of a TIADC provided in an embodiment of the present disclosure;
[0015] Figure 2 A flowchart of a clock calibration method provided in an embodiment of the present disclosure;
[0016] Figure 3 This is a flowchart of a specific implementation method of step S3 in the embodiment of the present disclosure;
[0017] Figure 4 This is a flowchart of a specific implementation method of step S32 in the embodiment of the present disclosure;
[0018] Figure 5 This is a flowchart of a specific implementation method of step S321 in the embodiment of the present disclosure;
[0019] Figure 6 A schematic structural diagram of a time-interleaved analog-to-digital converter provided in an embodiment of the present disclosure;
[0020] Figure 7 A schematic diagram of the structure of the TIADC provided in the first embodiment of the present disclosure;
[0021] Figure 8 A schematic diagram of the output spectrum of the TIADC before clock calibration provided in the second embodiment of the present disclosure;
[0022] Figure 9 A schematic diagram of the output spectrum of the TIADC after clock calibration provided in the second embodiment of the present disclosure;
[0023] Figure 10 This is a schematic diagram of the change in the output spectrum of the TIADC during the clock calibration process provided in the second embodiment of the present disclosure. DETAILED DESCRIPTION
[0024] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the clock calibration method of the control and the time-interleaved analog-to-digital converter provided by the present disclosure are described in detail below with reference to the accompanying drawings.
[0025] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.
[0026] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.
[0027] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0028] The terms used herein are used only to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.
[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.
[0030] In this disclosure, unless otherwise specified, the following technical terms should be understood as follows:
[0031] TIADC connects multiple ADCs in parallel, staggering the sampling clocks of each ADC so that they can sample the same signal in a staggered manner. The sampling results of each ADC are then combined, thereby achieving high-speed sampling. This approach offers advantages such as high sampling speed, low power consumption, and low cost. However, the ADCs connected in parallel in a TIADC may experience sampling time mismatches. The embodiments of the present disclosure do not restrict the type of ADC in the TIADC. The TIADC can be single-stage, dual-stage, or triple-stage, and the present disclosure is not limited thereto.
[0032] Sampling time mismatch refers to the situation where the actual sampling time of the ADC does not match the actual changes in the signal it samples. Although each ADC samples at a fixed frequency, if the signal changes faster than the sampling frequency, the sampling time may be inconsistent with the signal changes, resulting in mismatch, which in turn introduces errors and affects signal reconstruction and analysis.
[0033] Figure 1 A schematic diagram of the structure of a TIADC provided by an embodiment of the present disclosure. Figure 1 In some embodiments, the TIADC includes a first analog-to-digital converter (ADC1), a second analog-to-digital converter (ADC2), a third analog-to-digital converter (ADC3), and a fourth analog-to-digital converter (ADC4) connected in parallel. The output values sampled by ADC1, ADC2, ADC3, and ADC4 are synchronized and output in parallel, thereby generating the output result of the TIADC. If there is a mismatch in the sampling times of ADC1, ADC2, ADC3, and ADC4, calibration of ADC1, ADC2, ADC3, and ADC4 is required.
[0034] Some related technologies pre-input a single-tone sinusoidal or quasi-sinusoidal signal into the TIADC. Then, an algorithm is used to estimate the sampling time mismatch between each ADC in the TIADC before calibration. However, this calibration method requires interrupting the normal operation of each ADC in the TIADC, making it impossible to perform calibration while the ADC is operating normally. This means that it can only be used for foreground calibration. This can lead to problems such as being unable to calibrate the TIADC even when a sampling time mismatch has occurred, or frequent foreground calibration leading to reduced TIADC efficiency.
[0035] In other related technologies, an additional sampling channel of the ADC is designed for reference, and the sampling channels of other ADCs are aligned with this additional channel. However, this increases the design complexity of the overall analog circuit, increases the power consumption of the sampling, and has low calibration accuracy.
[0036] Therefore, there is an urgent need for a TIADC clock calibration method that can support foreground and background calibration, has low computational complexity and higher calibration accuracy.
[0037] Figure 2 A flowchart of a clock calibration method provided by an embodiment of the present disclosure. Figure 2 , an embodiment of the present disclosure provides a clock calibration method, comprising:
[0038] S1. Obtain an output value of each analog-to-digital converter (ADC) in a time-interleaved analog-to-digital converter (TIADC); wherein the TIADC includes at least two ADCs connected in parallel, and each ADC performs sampling in sequence;
[0039] S2. For each ADC, calculate a first correlation value and a second correlation value of the ADC according to an output value of the ADC and output values of two ADCs adjacent to the ADC in sampling order;
[0040] S3. Calibrate a clock phase of the ADC according to the first correlation value and the second correlation value.
[0041] In an embodiment of the present disclosure, by calculating the correlation value (first correlation value, second correlation value) between the output value of each ADC and the output values of two ADCs adjacent to its sampling order, the correlation value can reflect the sampling time relationship between the ADC and the adjacent ADCs. In some embodiments, in the absence of a sampling time mismatch, the correlation value between the ADC and the two adjacent ADCs before and after its sampling order should be the same or similar. Therefore, the sampling time mismatch size of the ADC can be estimated by the correlation value, and the clock phase of the ADC can be calibrated. The computational complexity of the calibration process is low, and it will not affect the sampling process of the TIADC. It can support foreground and background calibration, and can effectively improve the overall performance of the ADC.
[0042] In some embodiments, a TIADC includes at least two parallel ADCs. The sampling sequence refers to multiple rounds of cyclic sampling performed by a limited number of parallel ADCs, with each round of cyclic sampling involving each ADC performing a sample once in a fixed order. For example, a TIADC with three sampling channels includes three sampling switches and three parallel ADCs: ADC1, ADC2, and ADC3. These three ADCs perform multiple rounds of cyclic sampling, with each round of cyclic sampling performing a sample once in the fixed order of ADC1, ADC2, and ADC3.
[0043] Two ADCs adjacent to an ADC in a sampling order refer to an ADC that performs sampling before the ADC and an ADC that performs sampling after the ADC.
[0044] In some embodiments, S2 includes:
[0045] The output value of the ADC is multiplied by the output values of two adjacent ADCs respectively to obtain a first correlation value and a second correlation value of the ADC; wherein the sampling order of the two adjacent ADCs is adjacent to the sampling order of the ADC.
[0046] As an example, an N-channel TIADC includes N sampling switches and N parallel ADCs. The N ADCs are named ADC1 to ADC1 in the fixed order of each round of sampling in the sampling sequence. N , wherein, for ADC2, its adjacent ADCs are ADC1 and ADC3 respectively, the first correlation value between ADC2 and ADC1 is Y1=ADC1*ADC2, and the second correlation value between ADC2 and ADC3 is Y2=ADC2*ADC3.
[0047] Figure 3 This is a flow chart of a specific implementation method of step S3 in the embodiment of the present disclosure. Figure 3 In some embodiments, S3 includes:
[0048] S31. Calculating a clock position deviation value between the ADC and two adjacent ADCs based on the first correlation value and the second correlation value;
[0049] S32: Calibrate the clock phase of the ADC according to the clock position deviation value.
[0050] In the embodiments of the present disclosure, since the TIADC includes at least two parallel ADCs, the correlation values between ADCs in adjacent sampling sequences should be the same or similar, that is, the first correlation value and the second correlation value should be the same or similar. Therefore, by calculating the difference between the first correlation value and the second correlation value, the clock position deviation value between the ADC and the two adjacent ADCs can be obtained, where the clock position deviation value can reflect the direction and magnitude of the clock position deviation of the ADC. In some embodiments, the absolute value of the difference between the first correlation value and the second correlation value can reflect the magnitude of the clock position deviation, that is, the magnitude of the error value of the sampling time mismatch; the positive or negative value of the difference between the first correlation value and the second correlation value can reflect the direction of the clock position deviation. Therefore, the clock phase of the ADC can be calibrated based on the clock position deviation value.
[0051] In some embodiments, when the clock position deviation value is within a preset deviation range (indicating that the first correlation value is close to the second correlation value), the clock phase of the ADC does not need to be calibrated.
[0052] It is worth noting that the difference between the first correlation value and the second correlation value can be the first correlation value minus the second correlation value, or the second correlation value minus the first correlation value. The calculation method can be unified in each ADC of the same TIADC, and the present disclosure is not limited to this.
[0053] As an example, for ADC2, its adjacent ADCs are ADC1 and ADC3, the first correlation value between ADC2 and ADC1 is Y1=ADC1*ADC2, and the second correlation value between ADC2 and ADC3 is Y2=ADC2*ADC3, then the clock position deviation value of ADC2 is D=Y1-Y2.
[0054] In some embodiments, S2 may further include:
[0055] Subtracting the output value of the ADC from the output values of two adjacent ADCs to obtain a first difference and a second difference; wherein the sampling order of the two adjacent ADCs is adjacent to the sampling order of the ADCs;
[0056] An absolute value of the first difference is determined as a first correlation value of the ADC, and an absolute value of the second difference is determined as a second correlation value of the ADC.
[0057] As an example, an N-channel TIADC includes N sampling switches and N parallel ADCs. The N ADCs are named ADC1 to ADC1 in the fixed order of each round of sampling in the sampling sequence. N , where for ADC2, its adjacent ADCs are ADC1 and ADC3 respectively, the first correlation value between ADC2 and ADC1 is Y1 = |ADC1-ADC2|, and the second correlation value between ADC2 and ADC3 is Y2 = |ADC2-ADC3|.
[0058] In some embodiments, when the correlation value is the absolute value of the difference between two adjacent ADC values, S3 includes:
[0059] Calculating a clock position deviation value between the ADC and two adjacent ADCs based on the first correlation value and the second correlation value;
[0060] The ADC clock phase is calibrated according to the clock position deviation value.
[0061] In the embodiments of the present disclosure, since the TIADC includes at least two parallel ADCs, the correlation values between ADCs in adjacent sampling sequences should be the same or similar, that is, the first correlation value and the second correlation value should be the same or similar. Therefore, by calculating the difference between the first correlation value and the second correlation value, the clock position deviation value between the ADC and the two adjacent ADCs can be obtained. The clock position deviation value can reflect the direction and magnitude of the clock position deviation of the ADC. In some embodiments, the magnitude of the difference between the first correlation value and the second correlation value can reflect the magnitude of the clock position deviation, that is, the magnitude of the sampling time mismatch error; the positive or negative value of the difference between the first correlation value and the second correlation value can reflect the direction of the clock position deviation.
[0062] It is worth noting that the difference between the first correlation value and the second correlation value can be the first correlation value minus the second correlation value, or the second correlation value minus the first correlation value. The calculation method can be unified in each ADC of the same TIADC, and the present disclosure is not limited to this.
[0063] As an example, for ADC2, its adjacent ADCs are ADC1 and ADC3, the first correlation value between ADC2 and ADC1 is Y1 = |ADC1-ADC2|, and the second correlation value between ADC2 and ADC3 is Y2 = |ADC2-ADC3|, then the clock position deviation value of ADC2 is D = Y1-Y2.
[0064] Figure 4 This is a flowchart of a specific implementation method of step S32 in the embodiment of the present disclosure. Figure 4 In some embodiments, S32 includes:
[0065] S321, determining a control word of the ADC according to the clock position deviation value;
[0066] S322: Calibrate the clock phase of the ADC according to the control word of the ADC.
[0067] In this embodiment, the delay line can be adjusted by the control word to change the sampling clock phase of the ADC. The embodiment of the present disclosure does not impose any special restrictions on the method of determining the control word, which can be LMS (Least Mean Squares) or other methods.
[0068] Figure 5 This is a flowchart of a specific implementation method of step S321 in the embodiment of the present disclosure. Figure 5 In some embodiments, S321 includes:
[0069] S3211, obtaining a first control word of an ADC whose sampling order is the previous ADC of the ADC;
[0070] S3212: Subtract the first control word from the product of the clock position deviation value of the ADC and a preset control coefficient to obtain a control word corresponding to the ADC.
[0071] In the embodiment of the present disclosure, the clock position deviation values corresponding to different sampling moments of the ADC obtained in the sampling order are iteratively calculated by LMS to obtain the control word of the ADC. As an example, LMS uses formula D skew(ck1),n+1 =D skew(ck1),n -μ*d1 calculates the control word of ADC, where D skew(ck1),n is the first control word, D skew(ck1),n+1 is the control word, d1 is the clock position deviation value, and μ is the convergence coefficient. The embodiments of the present disclosure do not impose any specific restrictions on the value of the convergence coefficient μ, which can be determined based on actual needs. The value of μ affects the convergence speed: a larger μ results in faster convergence and poorer calibration results, while a smaller μ results in slower convergence and better calibration results.
[0072] In the embodiments of the present disclosure, there is no special restriction on the method of calibrating the clock phase of the ADC according to the control word. It can be parallel calibration before the start of each round of sampling in accordance with the sampling order, or it can be calibrated once each time the control word corresponding to an ADC is calculated, or it can be calibrated based on one of the ADCs in the TIADC.
[0073] In some embodiments, S322 includes: calibrating clock phases of all ADCs in parallel according to control words of all ADCs in the TIADC within a preset period; wherein, within the preset period, all ADCs in the TIADC perform one sampling.
[0074] In this embodiment, the preset period refers to a plurality of sampling rounds corresponding to the sampling sequence, and before each round of sampling begins, all ADCs are calibrated in parallel according to their corresponding control words. The embodiment of the present disclosure does not impose any special restrictions on the length of the preset period.
[0075] In some further embodiments, S322 includes: calibrating the clock phase of each ADC in the TIADC in sequence according to the control word of each ADC in the TIADC.
[0076] In this embodiment, based on the control word of each ADC in the TIADC, the clock phase of each ADC may be calibrated in a different order for each sampling round, rather than in the sampling order. As an example, the TIADC includes parallel ADC1, ADC2, ADC3, and ADC4, where the clock of ADC1 is ck1, the clock of ADC2 is ck2, the clock of ADC3 is ck3, and the clock of ADC4 is ck4. The clock phases of ck1, ck2, ck3, and ck4 may be calibrated in sequence in the sampling order, or ck3 may be calibrated first, followed by ck1, ck2, and ck4.
[0077] In some embodiments, S322 includes: acquiring a control word of a preset ADC, wherein the preset ADC is one of the ADCs of the TIADC; and calibrating other ADCs except the preset ADC according to the control word of the preset ADC.
[0078] The embodiments of the present disclosure do not impose any special restrictions on specifying an ADC in the TIADC as a preset ADC. The designated preset ADC does not perform clock phase calibration, but uses the clock of the preset ADC as a reference to calibrate other ADCs except the preset ADC.
[0079] The embodiments of the present disclosure can calibrate the sampling time mismatch error of the ADC in the TIADC. By calculating the correlation value between each ADC and the two ADCs adjacent to it in the sampling order, the correlation value can reflect the sampling time relationship between the ADC and the two ADCs adjacent to it in the sampling order. Therefore, the sampling time mismatch size can be estimated by the correlation value, and the clock phase of the ADC is calibrated to improve the linearity of the TIADC system. At the same time, the sampling time error (i.e., the clock position deviation value) is extracted in the digital domain. The algorithm is simple and clear, does not require other additional reference channels, is easy to implement, and the computational complexity of the calibration process is low. It is not affected by PVT (Pressure-Temperature-Voltage, pressure-temperature-humidity) factors, has good compatibility, supports TIADCs with any number of channels, and supports foreground and background calibration.
[0080] Secondly, refer to Figure 6 , an embodiment of the present disclosure provides a time-interleaved analog-to-digital converter 600, comprising:
[0081] at least two ADCs 601 connected in parallel;
[0082] A processing module 602 is configured to obtain an output value of each analog-to-digital converter (ADC) in a time-interleaved analog-to-digital converter (TIADC); wherein each of the ADCs performs sampling in sequence; and for each ADC, calculate a first correlation value and a second correlation value of the ADC based on the output value of the ADC and output values of two ADCs adjacent to the ADC in the sampling sequence.
[0083] The calibration module 603 is configured to calibrate a clock phase of the ADC according to the first correlation value and the second correlation value.
[0084] Among them, the specific embodiments of how the processing module 602 calculates the first correlation value and the second correlation value of the ADC, and the specific embodiments of how the calibration module 603 calibrates the clock phase of the ADC, please refer to the corresponding parts of the clock calibration method embodiment described in the first aspect. To avoid repetition, they will not be repeated here.
[0085] The time-interleaved analog-to-digital converter provided in the embodiments of the present disclosure is capable of implementing the various processes of the various embodiments of the above-mentioned clock calibration method. The technical features correspond one to one and can achieve the same technical effects. To avoid repetition, they will not be described here.
[0086] In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the technical solutions provided by the embodiments of the present disclosure are described in detail below through specific examples:
[0087] Example 1: Figure 7 This is a schematic diagram of the structure of the TIADC provided in the first embodiment of the present disclosure. Figure 7 In one embodiment, the TIADC includes a four-channel ADC (ADC1, ADC2, ADC3, ADC4). The output values of two ADCs in adjacent channels are connected to a multiplier so that the output values of the two ADCs are multiplied to obtain a correlation value. The outputs of the two adjacent multipliers are connected to an adder-subtractor for performing addition or subtraction operations on the correlation values obtained by multiplication. The control word obtained by LMS calculation controls the clock phase of each ADC through a delay line. The clock calibration method corresponding to this TIADC is described below:
[0088] In ADC4_0, ADC1_1, ADC2_1, ADC3_1, ADC4_1, and ADC1_2, the number after the underscore "_" indicates the corresponding sampling round information, that is, the number of cycles in the preset period. Specifically, the sampling order of ADC4 in round 0 is adjacent to the sampling order of ADC1 in round 1, the sampling order of ADC1 in round 1 is adjacent to the sampling order of ADC2 in round 1, the sampling order of ADC2 in round 1 is adjacent to the sampling order of ADC3 in round 1, the sampling order of ADC3 in round 1 is adjacent to the sampling order of ADC4 in round 1, and the sampling order of ADC1 in round 2 is adjacent to the sampling order of ADC4 in round 1.
[0089] Multiply the output value of ADC4 in round 0 by the output value of ADC1 in round 1 to obtain the first correlation value y1 = ADC4_0 * ADC1_1 of ADC1 in round 1;
[0090] Multiply the output value of ADC1 in the first round by the output value of ADC2 in the first round to obtain the second correlation value y2 = ADC1_1 * ADC2_1 of ADC1 in the first round (that is, the first correlation value of ADC2 in the first round);
[0091] Multiply the output value of ADC2 in the first round by the output value of ADC3 in the first round to obtain the second correlation value y3 = ADC2_1 * ADC3_1 of ADC2 in the first round (that is, the first correlation value of ADC3 in the first round);
[0092] Multiply the output value of ADC3 in the first round by the output value of ADC4 in the first round to obtain the second correlation value y4 of ADC3 in the first round = ADC3_1*ADC4_1 (that is, the first correlation value of ADC4 in the first round);
[0093] The output value of ADC4 in the first round is multiplied by the output value of ADC1 in the second round to obtain a second correlation value y5 = ADC4_1 * ADC1_2 of ADC4 in the first round.
[0094] Then, the first correlation value corresponding to each ADC is subtracted from the second correlation value to obtain the clock position deviation value. The clock position deviation value of ADC1_1 is d1 = y1 - y2, the clock position deviation value of ADC2_1 is d2 = y2 - y3, the clock position deviation value of ADC3_1 is d3 = y3 - y4, and the clock position deviation value of ADC4_1 is d4 = y4 - y5.
[0095] Substitute the clock position deviation values d1, d2, d3, d4 and d5 into the LMS calculation formula to obtain D skew(ck1),n+1=D skew(ck1),n -μ*d1、D skew(ck2),n+1 =D skew(ck2),n -μ*d2、D skew(ck3),n+1 =D skew(ck3),n -μ*d3、D skew(ck4),n+1 =D skew(ck4),n -μ*d4.
[0096] Among them, D skew(ck1),n+1 It is the control word of ADC1 delay line in the first round, D skew(ck2),n+1 It is the control word of ADC2 delay line in the first round, D skew(ck3),n+1 It is the control word of ADC3 delay line in the first round, D skew(ck4),n+1 is the control word for ADC4's delay line in the first round. μ is the convergence coefficient, which controls the rate of change of the calibration control word and can be set to 2e-6. The control word of each ADC sequentially affects the control word of the next ADC in the sampling order. The delay line controls the clock phase, shifting it forward or backward, completing a single calibration.
[0097] Among them, each round of 4-phase clocks is calibrated in parallel. After several cycles, the sampling time mismatch of the 4-phase clocks can be calibrated, thereby achieving the effect of calibrating the sampling time mismatch error of the TIADC.
[0098] Example 2: By detecting the output spectrum of the TIADC before and after clock calibration, the state of the sampling time mismatch error before and after clock calibration can be more intuitively observed. Figure 8 Schematic diagram of the output spectrum of the TIADC before clock calibration provided in the second embodiment of the present disclosure; Figure 8 ,It can be seen that before the TIADC performs clock calibration, there are obvious harmonics of the sampling time mismatch error, and the ENOB (effective number of bits) of the ADC is 4.7.
[0099] Figure 9 Schematic diagram of the output spectrum of the TIADC after clock calibration provided in the second embodiment of the present disclosure; Figure 9 ,It can be seen that after the TIADC performs clock calibration, the ADC's ENOB is reduced to 6.8, and the harmonics of the original obvious sampling time mismatch error are effectively reduced.
[0100] Figure 10 The schematic diagram of the change of the output spectrum of TIADC during the clock calibration process provided in the second embodiment of the present disclosure is shown in FIG. Figure 10 ,It can be seen that during the calibration process of each ADC (i.e., ADC1, ADC2, ADC3, and ADC4) of the TIADC, the sampling time mismatch error gradually decreases.
[0101] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
[0102] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.
Claims
1. A clock calibration method, comprising: Obtaining an output value of each analog-to-digital converter ADC in a time-interleaved analog-to-digital converter TIADC; wherein the TIADC includes at least two ADCs connected in parallel, and each ADC performs sampling in sequence according to a sampling order; For each ADC, calculating a first correlation value and a second correlation value of the ADC according to an output value of the ADC and output values of two ADCs adjacent to the ADC in sampling order; The clock phase of the ADC is calibrated according to the first correlation value and the second correlation value.
2. The clock calibration method according to claim 1, wherein: The calculating, according to the output value of the ADC and the output values of two ADCs adjacent to the ADC in sampling order, a first correlation value and a second correlation value of the ADC, comprises: The output value of the ADC is multiplied by the output values of two adjacent ADCs respectively to obtain a first correlation value and a second correlation value of the ADC; wherein the sampling order of the two adjacent ADCs is adjacent to the sampling order of the ADC.
3. The clock calibration method according to claim 1, wherein: The calculating, according to the output value of the ADC and the output values of two ADCs adjacent to the ADC in sampling order, a first correlation value and a second correlation value of the ADC, comprises: Subtracting the output value of the ADC from the output values of two adjacent ADCs to obtain a first difference and a second difference; wherein the sampling order of the two adjacent ADCs is adjacent to the sampling order of the ADCs; An absolute value of the first difference is determined as a first correlation value of the ADC, and an absolute value of the second difference is determined as a second correlation value of the ADC.
4. The clock calibration method according to claim 2 or 3, wherein: The calibrating the clock phase of the ADC according to the first correlation value and the second correlation value includes: Calculating a clock position deviation value between the ADC and two adjacent ADCs according to the first correlation value and the second correlation value; The clock phase of the ADC is calibrated according to the clock position deviation value.
5. The clock calibration method according to claim 4, wherein: The step of calibrating the clock phase of the ADC according to the clock position deviation value includes: Determining a control word of the ADC according to the clock position deviation value; The clock phase of the ADC is calibrated according to the control word of the ADC. The clock calibration method according to claim 5 , wherein: The determining the control word of the ADC according to the clock position deviation value includes: Obtaining a first control word of an ADC whose sampling order is preceding the ADC of the ADC; The first control word is subtracted from the product of the clock position deviation value of the ADC and a preset control coefficient to obtain a control word corresponding to the ADC.
7. The clock calibration method according to claim 5, wherein: The step of calibrating a clock phase of the ADC according to a control word of the ADC includes: The clock phases of all ADCs are calibrated in parallel according to the control words of all ADCs in the TIADC within a preset period; wherein, within the preset period, all ADCs in the TIADC perform one sampling.
8. The clock calibration method according to claim 5, wherein: The step of calibrating a clock phase of the ADC according to a control word of the ADC includes: According to the control word of each ADC in the TIADC, the clock phase of each ADC is calibrated in sequence according to the sampling order.
9. The clock calibration method according to claim 5, wherein: The step of calibrating a clock phase of the ADC according to a control word of the ADC includes: Obtaining a control word of a preset ADC, wherein the preset ADC is one of the ADCs of the TIADC; According to the control word of the preset ADC, other ADCs except the preset ADC are calibrated.
10. A time-interleaved analog-to-digital converter, comprising: At least two ADCs in parallel; a processing module configured to obtain an output value of each analog-to-digital converter (ADC) in a time-interleaved analog-to-digital converter (TIADC); wherein each of the ADCs performs sampling in sequence; and, for each ADC, calculate a first correlation value and a second correlation value of the ADC based on the output value of the ADC and output values of two ADCs adjacent to the ADC in the sampling sequence; A calibration module is configured to calibrate a clock phase of the ADC according to the first correlation value and the second correlation value.