Time domain analog-to-digital converter, communication system and vehicle

Abstract

The invention discloses a time domain analog-to-digital converter, a communication system and a vehicle. The analog-to-digital converter comprises a plurality of channels; each channel comprises a sampling switch, a voltage-time converter, a first-stage time-to-digital converter, a residual error generator, a second-stage time-to-digital converter, a binary code converter and a digital code aligner; the voltage-time converter is used for converting a sampled voltage signal into a time signal, the first-stage time-to-digital converter is used for carrying out coarse quantization on the time signal to obtain a first thermometer code, and the residual error generator is used for obtaining a time residual error according to the thermometer code; the second-stage time-to-digital converter is used for finely quantizing the time residual error to obtain a second thermometer code; and the binary code converter and the digital code aligner are used for obtaining the output of the time domain analog-to-digital converter. The conversion speed and the conversion precision can be improved. The invention can be widely applied to the technical field of ultra-high-speed communication.

Description

Technical Field

[0001] The present invention relates to the field of ultra-high-speed communication technology, and in particular to a time-domain analog-to-digital converter, a communication system, and a vehicle. Background Art

[0002] The rapid development of smart cars requires analog-to-digital converters (ADCs) that combine high speed and low power consumption while adapting to complex battery environments. Compared to voltage-domain ADCs, time-domain ADCs offer advantages such as simpler structure, faster conversion speed, lower input capacitance, and the benefits of advanced process technology. They hold great potential in the high-speed ADC field.

[0003] In related technologies, flash-based time-to-digital converters (TDCs) have limited accuracy and are unable to achieve finer time-domain quantization (time steps <10ps). Vernier-based TDCs, on the other hand, have conversion times determined by the delay of a slow delay chain, resulting in slow conversion speeds and making high-speed applications difficult. Summary of the Invention

[0004] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0005] To this end, an object of the present invention is to provide a high-precision, high-speed time-domain analog-to-digital converter, a communication system, and a vehicle.

[0006] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include the following aspects:

[0007] On the one hand, an embodiment of the present invention provides a time-domain analog-to-digital converter, comprising: a plurality of time-interleaved channels; each channel comprising: a sampling switch, a voltage-to-time converter, a first-stage time-to-digital converter, a residual generator, a second-stage time-to-digital converter, a binary code converter, and a digital code aligner; the sampling switch is used to sample an input signal, the voltage-to-time converter is used to convert the sampled voltage signal into a time signal, the first-stage time-to-digital converter is used to coarsely quantize the time signal to obtain a first thermometer code, the residual generator is used to obtain a time residual based on the first thermometer code; the second-stage time-to-digital converter is a multi-path flash time-to-digital converter based on the vernier principle, the second-stage time-to-digital converter is used to finely quantize the time residual to obtain a second thermometer code, the binary code converter and the digital code aligner are used to convert the first thermometer code and the second thermometer code into a binary code to obtain the output of the time-domain analog-to-digital converter. The multi-path parallel time-to-digital converter based on the vernier principle of the present application effectively combines the advantages of flash-type and vernier-type time-to-digital converters, generates a fine minimum quantizable time step based on the buoy principle, and improves conversion speed. This application is beneficial to improving the conversion speed and conversion accuracy of the analog-to-digital converter.

[0008] In addition, the time domain analog-to-digital converter according to the above embodiment of the present invention may also have the following additional technical features:

[0009] Furthermore, in the time domain analog-to-digital converter of an embodiment of the present invention, the second-stage time-to-digital converter includes a step size generator and a signal converter. The step size generator is a multi-path minimum quantizable time step size generator based on the vernier principle. The step size generator includes several first delay paths and one second delay path. The first delay paths include fast buffers or slow buffers, and the number of slow buffers in each first delay path increases with the sorting position of the first delay path; the second delay path includes several fast buffers connected in sequence; the signal converter includes several parallel flash time-to-digital converters; the flash time-to-digital converters are used to quantize the first time signal and the second time signal; the first time signal is a signal generated by the first delay path corresponding to the sorting position of the flash time-to-digital converter, and the second time signal is a signal generated by the second delay path.

[0010] Furthermore, in one embodiment of the present invention, the step size generator includes four first delay paths and one second delay path, the first delay path with the first sorting position includes three fast buffers connected in sequence, the first delay path with the second sorting position includes two fast buffers and one slow buffer connected in sequence, the first delay path with the third sorting position includes one fast buffer and two slow buffers connected in sequence, and the first delay path with the fourth sorting position includes three slow buffers connected in sequence; the second delay path includes three fast buffers connected in sequence.

[0011] Furthermore, in one embodiment of the present invention, the delay time difference between the fast buffer and the slow buffer is the first minimum quantizable time step of the flash time-to-digital converter, and the rising edge difference of the first time signal of the first delay path at adjacent positions is related to the first minimum quantizable time step; the minimum quantizable time step of the signal converter is the first minimum quantizable time step.

[0012] Furthermore, in one embodiment of the present invention, the first-stage time-to-digital converter, the signal converter, and the delay unit of the step size generator follow each other, and the delay unit includes a buffer with unbalanced PMOS and NMOS sizes.

[0013] Further, in one embodiment of the present invention, the first delay unit of the first-stage time-to-digital converter includes a 2 / 1 unbalanced buffer;

[0014] The second delay unit of the signal converter includes a 2 / 1 unbalanced buffer;

[0015] The fast buffer or slow buffer in the step size generator is a third delay unit, and the third delay unit includes an m / 1 unbalanced buffer or a 1 / 1 balanced buffer, wherein m is related to the quantization time step of the step size generator.

[0016] Furthermore, in one embodiment of the present invention, the first-stage time-to-digital converter is configured to divide the input range into a plurality of first intervals using a first quantization time step, the signal converter is configured to divide the first interval into a plurality of second intervals using a second quantization time step, and the step size generator is configured to divide the second interval into a plurality of third intervals using a third quantization time step, so as to obtain an output with a preset accuracy.

[0017] The first quantization time step is the quantization time step of the first-stage time-to-digital converter, the second quantization time step is the quantization time step of the signal converter, and the third quantization time step is the quantization time step of the step generator; the first quantization time step is greater than the second quantization time step, and the second quantization time step is greater than the third quantization time step;

[0018] As process temperature and voltage change, the ratio of the first ratio to the second ratio remains stable; the first ratio is the ratio of the first delay time to the second delay time, and the second ratio is the ratio of the second delay time to the third delay time.

[0019] Furthermore, the sampling switch includes a bootstrap circuit.

[0020] On the other hand, an embodiment of the present invention provides a communication system including the above-mentioned time domain analog-to-digital converter.

[0021] On the other hand, an embodiment of the present invention provides a vehicle, including the above-mentioned time-domain analog-to-digital converter, or including the above-mentioned communication system.

[0022] The analog-to-digital converter provided in an embodiment of the present invention includes: a plurality of time-interleaved channels; each of the channels includes: a sampling switch, a voltage-to-time converter, a first-stage time-to-digital converter, a residual generator, a second-stage time-to-digital converter, a binary code converter, and a digital code aligner; the sampling switch is used to sample an input signal, the voltage-to-time converter is used to convert the sampled voltage signal into a time signal, the first-stage time-to-digital converter is used to coarsely quantize the time signal to obtain a first thermometer code, and the residual generator is used to obtain a time residual based on the first thermometer code; the second-stage time-to-digital converter is a multi-path flash time-to-digital converter based on the vernier principle, the second-stage time-to-digital converter is used to finely quantize the time residual to obtain a second thermometer code, the binary code converter and the digital code aligner are used to convert the first thermometer code and the second thermometer code into a binary code to obtain the output of the time domain analog-to-digital converter. The multi-path parallel time-to-digital converter based on the vernier principle of the present application effectively combines the advantages of flash-type and vernier-type time-to-digital converters, generates a fine minimum quantizable time step based on the buoy principle, and improves conversion speed. The present application is conducive to improving conversion speed and conversion accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following introduction is made to the drawings of the embodiments of the present invention or the related technical solutions in the prior art. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 A schematic structural diagram of an embodiment of a time domain analog-to-digital converter provided by the present invention;

[0025] Figure 2 A schematic structural diagram of an embodiment of a step size generator provided by the present invention;

[0026] Figure 3 This is a structural diagram of an embodiment of the delay unit provided by the present invention. DETAILED DESCRIPTION

[0027] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided for ease of explanation only and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0028] Targeting the rapidly developing smart cars, the IEEE 802.3cz-2023 standard defines 50GBASE-AU, requiring analog-to-digital converters (ADCs) to combine high speed and low power consumption while adapting to complex battery environments. Compared to voltage-domain ADCs, time-domain ADCs offer significant advantages, including simpler structure, faster conversion speed, lower input capacitance, and the benefits of advanced process technology. They hold great potential in the high-speed ADC field. Currently, there are two mainstream architectures for high-speed time-to-digital converters: flash-based and vernier-based. A flash time-to-digital converter (TDC) consists of a delay chain formed by a buffer and a comparator array. Taking a single-ended converter as an example, its operating principle is as follows: the "fast" time signal with the earlier rising edge in the differential input time signal is connected to the input of a multi-stage delay chain, while the "slow" time signal with the later rising edge is connected to the negative input of each comparator. The fixed delay of the delay unit in the multi-stage delay chain determines the minimum quantizable time step of the TDC. The output of each stage of the delay chain is connected to the positive input of a parallel comparator array. The "fast" signal is compared with the "slow" signal after each delay stage. When the rising edge of the delayed "fast" signal is later than that of the "slow" signal, the comparator output changes from a high level to a low level. The thermometer code output by the comparator array is converted into binary code to obtain the output of the flash time-to-digital converter. A vernier time-to-digital converter (TDC) consists of a fast delay chain, a slow delay chain, and a comparator array. Its operating principle is as follows: the "fast" time signal with the earlier rising edge in the differential input time signal is connected to the negative input of each comparator after a unit delay T. S The slow delay chain, the "slow" time signal with a later rising edge is connected to the unit delay T F The fast delay chain, the unit delay difference of the two delay chains (T S -T F ) determines the minimum quantizable time step of the time-to-digital converter; when the rising edge of the "fast" signal passing through the slow delay chain is later than the rising edge of the "slow" signal passing through the fast delay chain, the comparator changes from outputting a high level to outputting a low level; the thermometer code output by the comparator array is converted into a binary code to obtain the output result of the vernier-type time-to-digital converter.

[0029] For flash-based time-to-digital converters: 1. Their minimum quantizable time step is determined by the delay time of a buffer. In a 28nm CMOS process, the minimum delay of a buffer is typically 10ps. Therefore, the accuracy of flash-based time-to-digital converters is limited, and finer time-domain quantization (time step <10ps) is not possible. 2. The delay time of the buffer-based delay unit varies significantly with changes in process temperature and voltage (PVT), making the flash-based time-to-digital converter very sensitive to PVT changes and unable to adapt to the complex automotive battery environment. For vernier-based time-to-digital converters: 1. Their conversion time is determined by the delay time of the slow delay chain, resulting in slow conversion speeds and difficulty in high-speed applications. 2. The minimum quantizable time step, determined by the delay difference between the slow and fast delay chains, is affected by the cumulative errors of the two delay chains, resulting in quantization errors and affecting overall accuracy.

[0030] The time domain analog-to-digital converter and the communication system proposed in the embodiments of the present invention are described in detail below with reference to the accompanying drawings. First, a time domain analog-to-digital converter proposed in the embodiments of the present invention is described with reference to the accompanying drawings.

[0031] Figure 1 FIG. 1 is a schematic diagram of the structure of a time domain analog-to-digital converter according to an embodiment of the present invention. The system specifically includes:

[0032] Several time-interwoven channels;

[0033] Each channel includes: a sampling switch, a voltage-to-time converter, a first-stage time-to-digital converter, a residue generator, a second-stage time-to-digital converter, a binary code converter, and a digital code aligner;

[0034] The sampling switch is used to sample the input signal, the voltage-to-time converter is used to convert the sampled voltage signal into a time signal, the first-stage time-to-digital converter is used to coarsely quantize the time signal to obtain a first thermometer code, and the residual generator is used to obtain a time residual based on the first thermometer code; the second-stage time-to-digital converter is a multi-path flash time-to-digital converter based on the vernier principle, the second-stage time-to-digital converter is used to finely quantize the time residual to obtain a second thermometer code, the binary code converter and the digital code aligner are used to convert the first thermometer code and the second thermometer code into binary code to obtain the output of the time domain analog-to-digital converter.

[0035] In some embodiments, the first stage time-to-digital converter is used to perform 3-bit coarse quantization on the time signal to obtain a 7-bit first thermometer code, and the second stage time-to-digital converter is used to perform 4-bit fine quantization on the time residual to obtain a 15-bit second thermometer code.

[0036] Furthermore, in the time domain analog-to-digital converter of an embodiment of the present invention, the second-stage time digital converter includes a step size generator and a signal converter. The step size generator is a multi-path minimum quantizable time step size generator based on the vernier principle. The step size generator includes several first delay paths and one second delay path. The first delay path includes fast buffers or slow buffers, and the number of slow buffers in each first delay path increases with the sorting position of the first delay path; the second delay path includes several fast buffers connected in sequence; the signal converter includes several parallel flash time digital converters; the flash time digital converter is used to quantize the first time signal and the second time signal; the first time signal is the signal generated by the first delay path corresponding to the sorting position of the flash time digital converter, and the second time signal is the signal generated by the second delay path.

[0037] The number of flash time-to-digital converters in the signal converter is the same as the total number of fast buffers or slow buffers in the first delay path. In other embodiments, the number of the slow buffers in each of the first delay paths decreases with the sorting position of the first delay path. It should be noted that the present application does not limit the specific number of time-interleaved channels, the number of step generators in the first delay path, the number of fast buffers in the second delay path, etc. The structure in the drawings of the present application is only the number under one embodiment, and those skilled in the art can adjust any number in the present application according to actual needs.

[0038] Furthermore, in one embodiment of the present invention, the step size generator includes four first delay paths and one second delay path, the first delay path with the first sorting position includes three fast buffers connected in sequence, the first delay path with the second sorting position includes two fast buffers and one slow buffer connected in sequence, the first delay path with the third sorting position includes one fast buffer and two slow buffers connected in sequence, and the first delay path with the fourth sorting position includes three slow buffers connected in sequence; the second delay path includes three fast buffers connected in sequence.

[0039] Correspondingly, the signal converter includes four parallel flash time-to-digital converters.

[0040] Furthermore, in one embodiment of the present invention, the delay time difference between the fast buffer and the slow buffer is the first minimum quantizable time step of the flash time-to-digital converter, and the rising edge difference of the first time signal of the first delay path at adjacent positions is related to the first minimum quantizable time step; the minimum quantizable time step of the signal converter is the first minimum quantizable time step.

[0041] Furthermore, in one embodiment of the present invention, the delay unit of the first-stage time-to-digital converter, the signal converter, and the step size generator follows each other, and the delay unit includes a buffer with unbalanced PMOS and NMOS sizes.

[0042] Furthermore, in one embodiment of the present invention, the first delay unit of the first-stage time-to-digital converter includes a 2 / 1 unbalanced buffer;

[0043] The second delay unit of the signal converter includes a 2 / 1 unbalanced buffer;

[0044] The fast buffer or slow buffer in the step generator is a third delay unit, which includes an m / 1 unbalanced buffer or a 1 / 1 balanced buffer, where m is related to the quantization time step of the step generator.

[0045] Furthermore, in one embodiment of the present invention, the first-stage time-to-digital converter is configured to divide the input range into a plurality of first intervals using a first quantization time step, the signal converter is configured to divide the first interval into a plurality of second intervals using a second quantization time step, and the step size generator is configured to divide the second interval into a plurality of third intervals using a third quantization time step, so as to obtain an output with a preset accuracy.

[0046] The first quantization time step is the quantization time step of the first-stage time-to-digital converter, the second quantization time step is the quantization time step of the signal converter, and the third quantization time step is the quantization time step of the step generator; the first quantization time step is greater than the second quantization time step, and the second quantization time step is greater than the third quantization time step;

[0047] As process temperature and voltage change, the ratio of the first ratio to the second ratio remains stable; the first ratio is the ratio of the first delay time to the second delay time, and the second ratio is the ratio of the second delay time to the third delay time.

[0048] The first delay time is the delay time of the first delay unit, the second delay time is the delay time of the second delay unit, and the third delay time is the delay time of the third delay unit.

[0049] Furthermore, the sampling switch includes a bootstrap circuit.

[0050] The time domain analog-to-digital converter provided by this application is described in detail below using a specific embodiment:

[0051] The technical problems to be solved by the present invention are as follows: 1. In response to the problem that the minimum quantizable time step of the flash-type time digitizer is too long and the conversion time of the vernier-type time digitizer is too long, the present invention proposes a multi-path parallel time digitizer technology based on the vernier principle, which effectively combines the advantages of the flash-type and vernier-type time digitizers, generates a fine minimum quantizable time step (<2ps) based on the buoy principle, and significantly improves the conversion speed by using a multi-channel parallel flash-type time digitizer; 2. In response to the problem that the delay time of the delay unit will change with the change of PVT, the present invention proposes delay units that can follow each other. When the PVT changes, although the delay time of the delay unit will change, the delay time ratio of the coarse quantization delay unit and the fine quantization delay unit that follow each other remains unchanged, so that the entire ADC achieves PVT robustness.

[0052] Figure 1 This is a diagram of the structure of a two-step time-domain analog-to-digital converter implemented by the present invention using a multipath parallel time-to-digital converter based on the vernier principle. Structurally, the ADC of the present invention is composed of four channels that are time-interleaved, achieving a sampling rate of 16 GS / s. The number of channels can be further expanded to achieve even faster speeds. Each single-channel ADC consists of a bootstrap sampling switch, a voltage-to-time converter (VTC), a first-stage time-to-digital converter (TDC), a residual generator, a second-stage vernier-based multipath flash time-to-digital converter (VMF TDC), a thermometer code binary code converter, and a digital code aligner. In terms of the operating process, first, the sampling circuit composed of the bootstrap switch samples the differential input signal. Next, the VTC converts the sampled voltage signal into a time signal. The first-stage TDC performs 3-bit coarse quantization on the time signal to obtain a 7-bit thermometer code. The time residual is then generated based on the quantization result. Finally, the second stage VMF TDC performs 4-bit fine quantization on the time difference to obtain a 15-bit thermometer code, and then converts the two-stage thermometer code into a binary code to obtain the ADC output. The circuit structure of the second stage VMF TDC is as follows: Figure 2 As shown, it consists of a multipath T based on the vernier principle. LSB Generator (Vernier-based Multipath T LSBThe VMTG is composed of a step size generator (VMTG) and a flash TDC (signal converter). In the VMTG, "F" represents a "fast" buffer with a shorter delay time, and "S" represents a "slow" buffer with a longer delay time. The delay time difference between a "fast" buffer and a "slow" buffer corresponds to the minimum quantizable time step of the TDC, T LSB The time signal input from the P terminal passes through four delay paths composed of different numbers of "fast" buffers and "slow" buffers. The first path consists of three "fast" buffers with a delay time of T0; the second path consists of two "fast" buffers and one "slow" buffer. Compared with the first path, the delay time of the second path will be more than the delay difference between the "slow" buffer and the "fast" buffer, that is, T0+T LSB The third path consists of one "fast" buffer and two "slow" buffers, with a delay of T0+2T LSB ; The fourth path consists of 3 "slow" buffers with a delay of T0+3T LSB The delay time difference of each path is T LSB , so the rising edges are T LSB The time signal T P <0:3> (i.e. the first time signal). The time signal input from the N terminal passes through the delay path (i.e. the second delay path) composed of three "fast" buffers to generate the time signal T N (ie, the second time signal) to match the delay of the time signal at the P end. Time signal T P <0:3> and T N The quantization is performed by four parallel flash TDCs. For each flash TDC, the minimum quantizable time step is T D (T D =4T LSB ), for four parallel flash TDCs, the minimum quantizable time step can be reduced to T LSB The four paths in this architecture can be expanded to more paths in parallel to achieve a smaller quantization time step and a faster conversion speed. However, more paths will lead to increased power consumption and design difficulty. Under the trade-off between energy efficiency, speed and complexity, the present invention adopts 4 paths in parallel to meet application requirements. In different application contexts, the number of multiple paths can be flexibly selected. The delay unit used in the present invention is as follows: Figure 3As shown in the figure, since the edge of the time signal transmitted in the delay chain is determined, the transmission speed can be increased by increasing the size of the MOS tube on the transmission path. Therefore, the present invention uses buffers with unbalanced PMOS and NMOS sizes to form a delay unit. The first delay unit in the figure is the delay unit in the first stage flash TDC, which is composed of four 2 / 1 unbalanced buffers with a delay time of T D1 The second delay unit is the delay unit in the second-stage flash TDC (i.e., signal converter), which is composed of a 2 / 1 unbalanced buffer. The delay time T D2 It is about 7ps, that is, the quantization time step of the second-level TDC is 7ps; the third delay unit is the "fast" buffer and "slow" buffer in VMTG, which are composed of m / 1 unbalanced buffer and 1 / 1 balanced buffer respectively. By selecting the appropriate m value, the delay difference T of the "fast" and "slow" buffers can be achieved. LSB It is about 1.75ps, that is, the quantization time step of VMTG is 1.75ps. The overall 7-bit ADC needs to divide the quantization range of 224ps into 128 intervals. First, the first-stage 3-bit flash TDC divides the input range into 8 intervals through a quantization time step of 28ps, and generates a time residual that is less than or equal to one time step; the second-stage 2-bit flash TDC on one path divides the residual range into 4 intervals through a quantization time step of 7ps; the parallel flash TDC on the 4 paths through VMTG subdivides a quantization interval of 7ps into 4 intervals through a quantization time step of 1.75ps, thereby achieving an overall 7-bit accuracy. 128 quantization intervals. In this ADC, the time step accuracy of each part directly determines the overall accuracy of the ADC. Therefore, the present invention adopts the same structure to design the delay unit of each part, so that each delay unit can track changes with each other, which is manifested as T changes with the change of PVT. D1 / T D2 and T D2 / T LSB The ratio remains stable.

[0053] Compared with the existing technology, the technical solution of the present invention has the following advantages: 1. For the traditional vernier-type TDC, the conversion speed is limited by the lengthy "slow" delay chain. This technology significantly improves the conversion speed by using four-path TDC working in parallel. 2. For the traditional flash-type TDC, the minimum quantizable time step is determined by the delay of a buffer, which is usually about 10ps. The minimum quantizable time step generated by the VMTG of this technology is 1.75ps, which is significantly smaller than the traditional flash-type TDC. The time step of 1.75ps not only speeds up the conversion speed of the second-stage TDC, but also shortens the unit delay time required for the first-stage TDC. In addition, the VMTG composed entirely of inverters in this technology only introduces very little power consumption. Therefore, under the 28nm CMOS process, the present invention realizes an ultra-high-speed ADC of 4GS / s per channel and 16GS / s overall, while having an excellent energy efficiency ratio. 3. For traditional two-step time-domain ADCs, the time steps of coarse and fine quantization vary with changes in PVT, requiring extensive calibration of the entire system to correct these deviations. The delay units in this technology are based on the same structure and can intrinsically track each other's changes. As PVT changes, the ratio of the time steps of each quantization level remains stable, achieving good robustness and reducing calibration overhead.

[0054] This application innovatively combines vernier-type TDCs with flash-type TDCs to propose a multipath parallel TDC based on the vernier principle, achieving both a precise minimum quantifiable time step and a fast conversion speed. The sampling circuit design in this application is the most critical and challenging aspect of high-speed multi-channel ADCs, as its quality directly determines the overall accuracy of the ADC. The delay units in this application, designed to track each other and maintain a stable time step ratio with PVT changes, are key to the invention.

[0055] On the other hand, an embodiment of the present invention provides a communication system, including the above-mentioned time domain analog-to-digital converter.

[0056] It can be seen that the contents of the above-mentioned analog-to-digital converter embodiments are applicable to the present system embodiments. The functions specifically implemented by the present system embodiments are the same as those of the above-mentioned analog-to-digital converter embodiments, and the beneficial effects achieved are also the same as those achieved by the above-mentioned analog-to-digital converter embodiments.

[0057] On the other hand, an embodiment of the present invention provides a vehicle, including the above-mentioned time-domain analog-to-digital converter, or including the above-mentioned communication system.

[0058] It can be seen that the contents of the above-mentioned analog-to-digital converter embodiment are all applicable to the present vehicle embodiment. The functions specifically implemented by the present vehicle embodiment are the same as those of the above-mentioned analog-to-digital converter embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned analog-to-digital converter embodiment.

[0059] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0060] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the ordinary skill of an engineer. Therefore, a person skilled in the art will be able to implement the present invention set forth in the claims using ordinary skill without undue experimentation. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0061] The logic and / or steps represented in a flowchart or otherwise described herein, for example, may be considered as an ordered list of executable programs for implementing the logical functions, and may be embodied in any computer-readable medium for use by, or in conjunction with, a program execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can retrieve and execute a program from a program execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, a program execution system, apparatus, or device.

[0062] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0063] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0064] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A time domain analog-to-digital converter, characterized in that The analog-to-digital converter includes: a plurality of time-interleaved channels; Each of the channels includes: a sampling switch, a voltage-to-time converter, a first-stage time-to-digital converter, a residue generator, a second-stage time-to-digital converter, a binary code converter, and a digital code aligner; The sampling switch is used to sample an input signal, the voltage-to-time converter is used to convert the sampled voltage signal into a time signal, the first-stage time-to-digital converter is used to coarsely quantize the time signal to obtain a first thermometer code, and the remainder generator is used to obtain a time remainder based on the first thermometer code; the second-stage time-to-digital converter is a multi-path flash time-to-digital converter based on the vernier principle, the second-stage time-to-digital converter is used to finely quantize the time remainder to obtain a second thermometer code, and the binary code converter and digital code aligner are used to convert the first thermometer code and the second thermometer code into binary code to obtain the output of the time domain analog-to-digital converter.

2. The time domain analog-to-digital converter according to claim 1, wherein: The second-stage time-to-digital converter includes a step size generator and a signal converter. The step size generator is a multi-path minimum quantizable time step size generator based on the vernier principle. The step size generator includes several first delay paths and one second delay path. The first delay path includes a fast buffer or a slow buffer, and the number of the slow buffers in each first delay path increases with the sorting position of the first delay path; the second delay path includes several fast buffers connected in sequence; the signal converter includes several parallel flash time-to-digital converters; the flash time-to-digital converters are used to quantize the first time signal and the second time signal; the first time signal is the signal generated by the first delay path corresponding to the sorting position of the flash time-to-digital converter, and the second time signal is the signal generated by the second delay path.

3. The time domain analog-to-digital converter according to claim 2, wherein: The step size generator includes four first delay paths and one second delay path. The first delay path with the first sorting position includes three fast buffers connected in sequence. The first delay path with the second sorting position includes two fast buffers and one slow buffer connected in sequence. The first delay path with the third sorting position includes one fast buffer and two slow buffers connected in sequence. The first delay path with the fourth sorting position includes three slow buffers connected in sequence. The second delay path includes three fast buffers connected in sequence.

4. The time domain analog-to-digital converter according to claim 3, wherein: The delay time difference between the fast buffer and the slow buffer is the first minimum quantizable time step of the flash time-to-digital converter, and the rising edge difference of the first time signal of the first delay path at adjacent positions is related to the first minimum quantizable time step; the minimum quantizable time step of the signal converter is the first minimum quantizable time step.

5. The time domain analog-to-digital converter according to claim 2, wherein: The first-stage time-to-digital converter, the signal converter, and the delay unit of the step size generator follow each other, and the delay unit includes a buffer with unbalanced PMOS and NMOS sizes.

6. The time domain analog-to-digital converter according to claim 5, characterized in that The first delay unit of the first-stage time-to-digital converter includes a 2 / 1 unbalanced buffer; The second delay unit of the signal converter includes a 2 / 1 unbalanced buffer; The fast buffer or slow buffer in the step size generator is a third delay unit, and the third delay unit includes an m / 1 unbalanced buffer or a 1 / 1 balanced buffer, wherein m is related to the quantization time step of the step size generator.

7. The time domain analog-to-digital converter according to claim 6, wherein: The first-stage time-to-digital converter is used to divide the input range into a plurality of first intervals using a first quantization time step, the signal converter is used to divide the first interval into a plurality of second intervals using a second quantization time step; the step size generator is used to divide the second interval into a plurality of third intervals using a third quantization time step, so as to obtain an output with a preset accuracy; The first quantization time step is the quantization time step of the first-stage time-to-digital converter, the second quantization time step is the quantization time step of the signal converter, and the third quantization time step is the quantization time step of the step generator; the first quantization time step is greater than the second quantization time step, and the second quantization time step is greater than the third quantization time step; As process temperature and voltage change, the ratio of the first ratio to the second ratio remains stable; the first ratio is the ratio of the first delay time to the second delay time, and the second ratio is the ratio of the second delay time to the third delay time.

8. The time domain analog-to-digital converter according to claim 1, wherein: The sampling switch includes a bootstrap circuit.

9. A communication system, characterized in that: The communication system comprises the time domain analog-to-digital converter according to any one of claims 1 to 8.

10. A vehicle, characterized in that: The vehicle comprises the time domain analog-to-digital converter according to any one of claims 1 to 8 , or the vehicle comprises the communication system according to claim 9 .

Images