Interconnection interface, data transmission method, chip and electronic equipment

Abstract

The embodiment of the invention provides an interconnection interface, a data transmission method, a chip and electronic equipment. The interconnection interface comprises a data link layer and a physical layer, and the data link layer and the physical layer communicate with each other; the physical layer comprises a plurality of physical layer channels and is configured to transmit bit streams through the plurality of physical layer channels; the data link layer is configured to determine at least one target physical channel in the plurality of physical layer channels based on a bandwidth switching decision so as to execute a bandwidth switching operation, and the bandwidth switching operation comprises the step of directly switching the target physical layer channel from a current working state to a target working state. According to the interconnection interface, the continuity and reliability of data transmission can be ensured and the resource utilization efficiency can be optimized through a method of directly adjusting the normal working states of a plurality of physical layer channels to the target working state.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an interconnection interface, a data transmission method, a chip, and an electronic device. Background Art

[0002] An interconnect interface is a key component for data transmission and communication between computer systems, communication devices, or other electronic devices. It is responsible for transferring data from the source device to the destination device, ensuring the accurate delivery and reception of information.

[0003] Existing interconnect interfaces typically use a fixed number of transmission lanes to handle varying bandwidth requirements. This results in wasted resources and high power consumption when bandwidth requirements are low. Furthermore, traditional methods for dynamically adjusting lanes often involve frequent and complex state transitions, increasing the complexity of the system's control logic and power consumption. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides an interconnection interface, comprising: a data link layer and a physical layer; wherein the data link layer and the physical layer communicate with each other; the physical layer comprises a plurality of physical layer channels and is configured to transmit a bit stream through the plurality of physical layer channels; the data link layer is configured to determine at least one target physical channel among the plurality of physical layer channels based on a bandwidth switching decision to perform a bandwidth switching operation, wherein the bandwidth switching operation comprises directly switching the target physical layer channel from a current working state to a target working state.

[0005] For example, in an interconnection interface provided in at least one embodiment of the present disclosure, the bandwidth switching operation includes switching the interconnection interface to a lower power consumption state, and the target working state includes a non-working state having lower power consumption than the current working state.

[0006] For example, at least one embodiment of the present disclosure provides an interconnection interface, which also includes a protocol layer, wherein the protocol layer is communicatively connected with the data link layer to transmit data to each other; the protocol layer includes a system bus and is configured to provide the bandwidth switching decision to the data link layer through the system bus.

[0007] For example, in an interconnection interface provided by at least one embodiment of the present disclosure, the protocol layer further includes: a status monitoring module, which is communicatively connected to the system bus and is configured to generate the bandwidth switching decision based on the status monitoring result of the bit stream.

[0008] For example, in an interconnection interface provided by at least one embodiment of the present disclosure, the status monitoring module is further configured to monitor the target dimension of the bit stream and generate the bandwidth switching decision based on the monitoring result.

[0009] For example, in at least one embodiment of the present disclosure, the interconnection interface is provided, wherein the status monitoring module is further configured to predict the target dimension of the bit stream, and generate the bandwidth switching decision based on the prediction result and the monitoring result.

[0010] For example, in an interconnection interface provided by at least one embodiment of the present disclosure, the data link layer includes multiple link layer channels, and the multiple link layer channels are communicatively connected to the multiple physical layer channels.

[0011] For example, in an interconnection interface provided in at least one embodiment of the present disclosure, the data link layer further includes a bandwidth switching control module and a channel status management module; wherein the bandwidth switching control module is configured to receive the bandwidth switching decision and control the bandwidth switching operation; the channel status management module is communicatively connected to the multiple link layer channels, and is configured to receive the bandwidth switching decision and manage the multiple link layer channels during the bandwidth switching operation.

[0012] For example, in an interconnection interface provided by at least one embodiment of the present disclosure, the channel management module is communicatively connected to the multiple physical layer channels and is further configured to control clocks of the multiple physical layer channels.

[0013] For example, in an interconnection interface provided by at least one embodiment of the present disclosure, the data link layer further includes: a main state machine, which is communicatively connected to the bandwidth switching module and the channel state management module, and is configured to receive the bandwidth switching decision from the bandwidth switching control module, manage information state synchronization in the bandwidth switching operation, generate a request based on the bandwidth switching decision, and provide the request and the bandwidth switching decision to the channel state management module.

[0014] For example, in an interconnection interface provided by at least one embodiment of the present disclosure, the data link layer also includes a link function module, wherein the link function module is communicatively connected to the main state machine and the multiple link layer channels, and is configured to perform data encoding and decoding error correction, data packet assembly or unpacking; wherein the multiple physical layer channels include at least one sending physical layer channel and at least one receiving physical layer channel, and the multiple link layer channels include at least one sending link layer channel and at least one receiving link layer channel, and the at least one sending link layer channel and the at least one receiving link layer channel correspond to the at least one sending physical layer channel and the at least one receiving physical layer channel, respectively, and receive data packets to be sent from the link function module, or provide the received data packets to the link function module.

[0015] For example, in an interconnection interface provided in at least one embodiment of the present disclosure, the sending link layer channel is configured to scramble the data packets to be sent received from the link function module, and provide the scrambled data packets to be sent to the corresponding sending physical layer channel; the receiving link layer channel is configured to perform symbol alignment and descrambling on the data packets received from the corresponding receiving physical layer channel, and provide the aligned and descrambled received data packets to the link function module.

[0016] For example, in an interconnection interface provided by at least one embodiment of the present disclosure, the link function module is also configured to perform the information status synchronization operation, and includes a link sending submodule and a link receiving submodule; wherein, the link sending submodule is configured to perform the information status synchronization operation in the sending link layer channel; the link receiving submodule is configured to perform the information status synchronization operation in the receiving link layer channel.

[0017] At least one embodiment of the present disclosure further provides a data transmission method for an interconnected interface, wherein the interconnected interface includes a data link layer and a physical layer, the data link layer and the physical layer communicate with each other, and the data transmission method includes: transmitting a bit stream through multiple physical layer channels of the physical layer; determining at least one target physical channel among the multiple physical layer channels based on a bandwidth switching decision at the data link layer to perform a bandwidth switching operation; wherein the bandwidth switching operation includes directly switching the target physical layer channel from a current working state to a target working state.

[0018] At least one embodiment of the present disclosure further provides a chip, comprising the interconnection interface provided by any embodiment of the present disclosure.

[0019] For example, at least one embodiment of the present disclosure provides a chip including a first core particle and a second core particle, wherein each of the first core particle and the second core particle includes the interconnection interface to communicate with each other through the interconnection interface.

[0020] At least one embodiment of the present disclosure further provides an electronic device, comprising the chip provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0022] Figure 1 A schematic block diagram of an interconnection interface framework;

[0023] Figure 2A schematic diagram of an interconnection interface provided by at least one embodiment of the present disclosure;

[0024] Figure 3 A schematic block diagram of an interconnection interface provided in at least one embodiment of the present disclosure;

[0025] Figure 4 A schematic block diagram of another interconnection interface provided for at least one embodiment of the present disclosure;

[0026] Figure 5 A schematic block diagram of another interconnection interface provided for at least one embodiment of the present disclosure;

[0027] Figure 6 A schematic flow chart of a data transmission method of an interconnected interface provided in at least one embodiment of the present disclosure;

[0028] Figure 7 A schematic block diagram of a chip provided in at least one embodiment of the present disclosure;

[0029] Figure 8 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure; and

[0030] Figure 9 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that the disclosure is not intended to be limited to the described embodiments. On the contrary, it is intended to cover variations, modifications, and equivalents within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0032] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of the present disclosure to the specific configurations, hardware, connections, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct further embodiments not described herein by reading this specification.

[0034] The terms used in this disclosure are those commonly used in the art currently in consideration of the functions of the present disclosure, but these terms may vary according to the intentions of those skilled in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as a general description based on the meaning of the terms and the present disclosure.

[0035] Flowcharts are used in this disclosure to illustrate the operations performed by the systems according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the various steps may be processed in reverse order or simultaneously, as needed. Furthermore, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0036] Figure 1 This is a schematic block diagram of an interconnection interface framework. Figure 1 In [1], the interconnection interface 100 comprises a protocol layer, a data link layer, and a physical layer. The protocol layer is related to the specific service type being carried and can support SoC (System on Chip) bus protocols, high-bandwidth storage services, and custom protocols. The data link layer provides reliable data transmission between the communicating parties. The physical layer provides bitstream transmission services that conform to the characteristics of the physical channel.

[0037] For example, in the chiplet interconnect interface, the physical layer is primarily implemented through packaging technology and hardware circuits. For example, electrical connections are achieved using microbumps, high-density wires in silicon interposers, or substrate wiring. High-speed transceivers (such as SerDes) or through-silicon vias (TSVs) rely on packaging technologies to transmit electrical or optical signals while ensuring timing synchronization and physical channel stability. The data link layer, based on this foundation, uses control modules or dedicated controllers (such as link training circuits and error correction units) integrated into the physical layer chip (PHY) to achieve reliable transmission of data frames. Its functions include low-power state switching management, error detection and correction, flow control, and link initialization. It typically requires the coordinated design of hardware logic and firmware to ensure low latency and high reliability. The protocol layer, as the top-level architecture, defines packet formats, transaction types (such as memory reads and writes, cache coherence operations), and routing rules through standardized protocol stacks (such as PCIe, CXL, or proprietary protocols). Its implementation relies on the logic units of the main control chip (such as the CPU or protocol controller in the SoC) or the network-on-chip (NoC), converting complex interaction rules into hardware-executable instructions while also being compatible with the heterogeneous communication requirements of different chiplets. For example, the data link layer implements data transmission between the protocol layer and the physical layer. The data link layer is typically directly connected to the physical layer and connected to the protocol layer via the system bus.

[0038] Low-power state transition management is a key function of the data link layer. Its purpose is to reduce energy consumption and extend device life by properly controlling device transitions between different power states while ensuring normal network communication. In actual network communications, devices are not always operating at full speed, which requires high power consumption. For example, when a device has no data transmission tasks for a period of time, the data link layer's low-power state transition management function can switch the device from normal operation to low-power mode. In low-power mode, the device shuts down non-essential hardware modules or reduces their transmission bandwidth, significantly reducing energy consumption.

[0039] To increase data transmission speed and bandwidth, interconnect interfaces often adopt multi-lane technology. This means that data is transmitted (sent or received) simultaneously through multiple parallel channels, each of which can transmit data independently. This design significantly improves the overall data transmission rate, but it also brings new challenges, such as power management and dynamic bandwidth adjustment. The demand for data transmission bandwidth varies greatly in different application scenarios. For example, video streaming may require high bandwidth to support the real-time transmission of HD or 4K video streams, while simple text file transfers have relatively low bandwidth requirements. Therefore, the ability to dynamically adjust data transmission bandwidth based on actual needs becomes particularly important.

[0040] The inventors of this disclosure have noted that current multi-channel interconnect interfaces often face problems such as resource waste, high power consumption, and data transmission interruptions. For example, even when bandwidth requirements are low, all channels are still used for data transmission, resulting in energy waste. For example, frequent state transitions and unnecessary channel activation during bandwidth switching increase the power consumption of the data transmission system. In another example, during the process of dynamically adjusting the number of channels, brief data transmission interruptions may occur, affecting data continuity and reliability.

[0041] At least one embodiment of the present disclosure provides an interconnection interface, a data transmission method for the interconnection interface, a chip, and an electronic device.

[0042] The interconnection interface of at least one embodiment of the present disclosure includes a data link layer and a physical layer, and the data link layer and the physical layer communicate with each other; the physical layer includes multiple physical layer channels and is configured to transmit bit streams through the multiple physical layer channels; the data link layer is configured to determine at least one target physical channel among the multiple physical layer channels based on a bandwidth switching decision to perform a bandwidth switching operation, wherein the bandwidth switching operation includes directly switching the target physical layer channel from a current working state to a target working state.

[0043] This interconnect interface directly adjusts the normal operating states of multiple physical layer channels to the target operating state, reducing unnecessary state transitions, lowering power consumption, and optimizing resource utilization. It also avoids brief data transmission interruptions that may occur during the dynamic adjustment of the number of channels, thereby ensuring data continuity and reliability. Furthermore, in at least one example, the number of channels can be dynamically adjusted based on real-time monitored data transmission bandwidth requirements, thereby optimizing resource utilization.

[0044] In the data transmission method of the interconnected interface of at least one embodiment of the present disclosure, the interconnected interface includes a data link layer and a physical layer, the data link layer and the physical layer communicate with each other, and the data transmission method includes: transmitting a bit stream through multiple physical layer channels of the physical layer; determining at least one target physical channel among the multiple physical layer channels based on a bandwidth switching decision at the data link layer to perform a bandwidth switching operation; wherein the bandwidth switching operation includes directly switching the target physical layer channel from the current working state to the target working state. The data transmission method of the interconnected interface reduces unnecessary state transitions, reduces power consumption loss, optimizes resource utilization efficiency, and can also avoid brief data transmission interruptions that may occur during the process of dynamically adjusting the number of channels, thereby ensuring data continuity and reliability.

[0045] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0046] Figure 2 A schematic diagram of an interconnection interface provided in at least one embodiment of the present disclosure. Figure 2 The bandwidth switching operation during data transmission between device A and device B is described.

[0047] For example, Figure 2 As shown, devices A and B each include an interconnection interface 200, and devices A and B transmit data to each other via the physical layer 220 of the interconnection interface 200. For example, devices A and B can be any two devices that need to communicate via a physical medium and a data link protocol. For example, A and B can be hardware devices, chip components, virtual entities, etc. This disclosure does not impose any restrictions on the application scenarios of the interconnection interface.

[0048] For example, in Figure 2 In the upper part, device A and device B are interconnected through physical layer channels 1-N (N is a positive integer greater than 1), and each physical layer channel transmits data independently. Figure 2 The lower half of the "" indicates that after a bandwidth switch operation is triggered, the target physical layer channel selected by the system from multiple physical layer channels will be directly switched to the target operating state. For example, after the bandwidth switch operation is completed, data between devices A and B will be transmitted over the remaining physical layer channels except the target physical layer channel.

[0049] For example, Figure 2 As shown, physical layer channel 2 can be determined as the target physical layer channel. In this case, physical layer channel 2 is directly switched to the target working state, and the other channels such as physical layer channel 1 and physical layer channels 3-N maintain the current working state.

[0050] like Figure 2 As shown, the interconnection interface 200 includes a data link layer 210 and a physical layer 220, and the data link layer 210 and the physical layer 220 communicate with each other. The physical layer 220 includes multiple physical layer channels and is configured to transmit bit streams through multiple physical layer channels. Here, bit stream is the smallest unit of physical layer transmission, which refers to a binary digital signal sequence transmitted through the physical layer channel, that is, the original data stream encoded in the form of "0" and "1". For example, a binary digital signal can directly correspond to an electrical signal in a hardware circuit (such as a high level is "1" and a low level is "0") or an optical signal (such as a light pulse represents "1" and no light represents "0"). The data link layer 210 is configured to make a bandwidth switching decision based on the bandwidth switching decision ( Figure 2(not shown) determines at least one target physical channel among multiple physical layer channels to perform a bandwidth switching operation, wherein the bandwidth switching operation includes directly switching the target physical layer channel from a current working state to a target working state to reduce unnecessary state transitions and reduce power consumption losses, thereby ensuring data continuity and reliability and optimizing resource utilization efficiency.

[0051] For example, Figure 2 As shown, the multiple physical layer lanes can be physical layer lanes 1-N (N is a positive integer greater than 1), and the target physical layer lane can be one or more selected from these. For example, a physical layer lane is the smallest physical unit for data transmission in high-speed digital communications, and its core consists of a pair of differential signal lines (positive and negative terminals). For example, each physical layer lane can function as an independent transmission unit, and the total bandwidth can be multiplied by aggregating multiple lanes (e.g., x4, x8, or x16). For example, a PCIe (PCI Express) x16 physical layer interface consists of 16 lanes, with a total bandwidth equal to the single lane rate multiplied by 16. For example, when the interconnect interface is a PCIe interface, the physical layer can have multiple physical layer interface groups (Phy Groups). Each physical layer interface group can serve as a logical grouping of serializer / deserializer (SerDes) physical interfaces, and can be configured with x4 or x8 SerDes lanes to meet different bandwidth requirements. For example, the target physical layer lanes can be multiple, such as all physical layer lanes configured for a physical layer interface group.

[0052] For example, a bandwidth switching decision may indicate the target physical channel to be operated, which may be any one or more channels. For example, the bandwidth switching decision may specify the number, location, and parameters (e.g., bandwidth) of the target physical layer channels via protocol signaling or control instructions, thereby guiding the bandwidth switching operation. For example, the location of the target physical layer channels may be indicated by information such as channel identifiers.

[0053] For example, a bandwidth switching operation includes directly switching a target physical layer channel from a current operating state to a target operating state. For example, the target physical layer channel is directly switched from the current operating state to the target operating state without passing through other states (such as a reset). In other words, during the bandwidth switching operation, the target physical layer channel only exists in two states: the current operating state and the target operating state.

[0054] For example, the operating state of an interconnect interface can be full-power, low-power, or off. For example, in the full-power state, all physical layer channels are active, transmitting bit streams and providing maximum bandwidth. For example, in the low-power state, only some physical layer channels remain active, while the remaining physical layer channels enter a low-power or off state, and bandwidth is reduced as needed. For another example, in the off state, all physical layer channels are powered off, the link is completely disconnected, and reinitialization is required to restore communication. Here, for the same interconnect interface, the power consumption state is directly correlated with the number of channels in operation.

[0055] For example, in at least one embodiment of the present disclosure, the bandwidth switching operation includes switching the interconnect interface to a lower power consumption state, and the target working state includes a non-working state with lower power consumption than the current working state. For example, after the bandwidth switching operation is completed, the interconnect interface can now be in the above-mentioned low power consumption state, and the target working state can now be a low power consumption state or an off state. In this case, after the bandwidth switching operation is completed, the interconnect interface will be in a lower power consumption state. For another example, the bandwidth switching operation can include switching the interconnect interface to a higher power consumption state, and the target working state can also be a working state with higher power consumption than the current working state. For example, after the bandwidth switching operation is completed, the interconnect interface can now be in the above-mentioned full power consumption state, and the target working state can now be an activated state. That is, the bandwidth switching operation of the interconnect interface of at least one embodiment of the present disclosure can be a reversible bidirectional process.

[0056] The interconnect interface provided by at least one embodiment of the present disclosure avoids the need to shut down all physical layer channels, enter a reset state, restart, and then open the required physical layer channels (e.g., channels other than the target physical layer channel). It directly adjusts from a normal multi-channel operating state to a target operating state, avoiding unnecessary intermediate states. This direct adjustment method significantly reduces the time required for adjustment and improves the system's response speed. It also effectively reduces overall energy consumption, which helps extend the battery life of the device.

[0057] In addition, during the bandwidth switching process that requires entering a reset state, all physical layer channels will be closed and then restarted. Since the physical layer is composed of analog circuits, analog circuits are easily interfered with by physical environmental factors such as power supply, resulting in unstable operation. This state of complete disconnection of the physical layer may affect the stability of the system, especially in high-frequency bandwidth adjustment scenarios. The interconnection interface provided by at least one embodiment of the present disclosure can provide a more stable data transmission environment because the physical layer channels remain connected at all times. Even during the bandwidth switching process, the data link layer and the physical layer will not be completely disconnected, thereby ensuring the continuity and reliability of data transmission.

[0058] Figure 3A schematic block diagram of an interconnection interface provided by at least one embodiment of the present disclosure, compared to Figure 2 The provided embodiments add a protocol layer.

[0059] like Figure 3 As shown, the interconnection interface 300 includes a data link layer 310 and a physical layer 320, and the data link layer 310 and the physical layer 320 communicate with each other. The physical layer 320 includes multiple physical layer channels 1-N. Figure 3 As shown, the interconnection interface 300 may further include a protocol layer 330, which is connected to the data link layer 310 for mutual data transmission. Figure 3 As shown, the protocol layer 330 may include a system bus 331 , and may be configured to provide a bandwidth switching decision to the data link layer 310 via the system bus 331 .

[0060] The interconnection interface provided by at least one embodiment of the present disclosure can dynamically adjust the number of physical layer channels according to the data transmission bandwidth demand monitored in real time, thereby optimizing resource utilization efficiency.

[0061] For example, bandwidth switching decisions can be made at the software control level or at the hardware component level. For example, software can generate bandwidth switching decisions based on global status (e.g., network load, service priority, policy configuration, etc.) and transmit them to the data link layer 310 via the system bus 331. Alternatively, a hardware module can generate bandwidth switching decisions based on physical layer status (e.g., data bandwidth, bit error rate, etc.) and transmit them to the data link layer 310 via the system bus 331 to directly trigger bandwidth switching.

[0062] For example, in at least one embodiment of the present disclosure, Figure 3 As shown, the protocol layer 330 may further include a status monitoring module 332. The status monitoring module 332 is communicatively connected to the system bus 331 and is configured to generate a bandwidth switching decision based on the status monitoring result of the bit stream. The above bit stream is a bit stream transmitted between multiple physical layer channels, for example, Figure 2 The bit stream transmitted between devices A and B on multiple physical layer channels. That is, the transmitted bit stream includes both the bit stream sent by device A to B and the bit stream received by device A from B.

[0063] For example, in at least one embodiment of the present disclosure, the status monitoring module 332 can be further configured to monitor the target dimension of the bitstream and generate a bandwidth switching decision based on the monitoring results. For example, the target dimension of the bitstream can be one or more dimensions such as the bandwidth, delay or packet loss rate of the bitstream. In other words, the bandwidth switching decision can be generated based on the above-mentioned single dimension, or based on a combination of the above-mentioned multiple dimensions, such as by assigning weights to each dimension. For example, the status monitoring module 332 can be configured to monitor the bandwidth of the bitstream in real time and generate a bandwidth switching decision based on the monitoring results of the bitstream bandwidth. By comprehensively considering multiple factors, the current network status can be judged more accurately, and the number of physical layer channels can be adjusted accordingly, thereby improving the comprehensiveness and accuracy of the test.

[0064] For another example, in at least one embodiment of the present disclosure, the status monitoring module 332 may be further configured to predict the target dimension of the bitstream and generate a bandwidth switching decision based on the prediction result and the monitoring result. For example, the status monitoring module 332 may introduce a machine learning algorithm to predict the bandwidth of the bitstream based on the historical bandwidth of the bitstream, and generate a bandwidth switching decision based on the predicted bandwidth result and the monitored bandwidth result.

[0065] Figure 4 A schematic block diagram of an interconnection interface provided in at least one embodiment of the present disclosure is provided. Figure 4 The data link layer and physical layer in Figure 3 A specific example of the data link layer and physical layer in .

[0066] For example, Figure 4 As shown, in at least one embodiment of the present disclosure, the data link layer 410 includes multiple link layer channels 415, and the physical layer 420 includes multiple physical layer channels 421. The multiple link layer channels 415 and the multiple physical layer channels 421 correspond to communication connections respectively. The link layer channel can be a logical communication path or a virtual channel established in the data link layer. For example, the link layer channel can send or receive a logical bit stream to the physical layer channel. For example, Figure 4 As shown, the link layer channel and the physical layer channel can have a one-to-one correspondence. For another example, one physical layer channel can correspond to multiple link layer channels, or multiple physical layer channels can be aggregated into a high-bandwidth link layer channel.

[0067] For example, Figure 4As shown, in at least one embodiment of the present disclosure, the data link layer 410 may further include a bandwidth switching control module 411 and a channel state management module 412. For example, the bandwidth switching control module 411 is configured to receive a bandwidth switching decision and control the bandwidth switching operation. For example, the bandwidth switching module 411 may receive a bandwidth switching decision through the system bus of the protocol layer, and decode the bandwidth switching decision to obtain relevant information such as the channel identifier of the target physical layer channel and the corresponding link layer channel. For example, the bandwidth switching control module 411 controlling the bandwidth switching operation may include the bandwidth switching control module 411 directing the main state machine 413 to complete the device (for example Figure 2 The information and status between A and B in the figure are synchronized, and the bandwidth switching control module 411 instructs the channel status management module 412 to complete the bandwidth switching.

[0068] For example, Figure 4 As shown, in at least one embodiment of the present disclosure, the channel state management module 412 is communicatively connected to multiple link layer channels 415 and is configured to receive bandwidth switching decisions and manage the multiple link layer channels 415 during bandwidth switching operations. For example, the channel state management module 412 can be connected to the main state machine 413 to receive requests for information state synchronization operations and bandwidth switching decisions provided by the main state machine 413. For example, the channel state management module 412 can be connected to each link layer channel and, based on requests provided by the bandwidth switching control module 411 and the main state machine 413, complete hardware management during bandwidth switching operations. Hardware management can include clock reset and state switching management. For example, the request can include bandwidth switching instructions, state synchronization instructions, state switching requests, and error detection requests.

[0069] For example, Figure 4 As shown, in at least one embodiment of the present disclosure, the channel state management module 412 can be communicatively connected to multiple physical layer channels 421 and can be further configured to control the clocks of the multiple physical layer channels 421. For example, each physical layer channel can be directly communicatively connected to the channel state management module 412, and the channel state management module 412 can independently control the clock of each physical layer channel.

[0070] For example, Figure 4As shown, in at least one embodiment of the present disclosure, the data link layer 410 may further include a master state machine 413. For example, the master state machine 413 is in communication with the bandwidth switching module 411 and the channel state management module 412, and is configured to receive bandwidth switching decisions from the bandwidth switching control module 411, manage information state synchronization during bandwidth switching operations, generate requests based on the bandwidth switching decisions, and provide the requests and bandwidth switching decisions to the channel state management module 412. For example, the master state machine 413 may control the transmission of synchronization sequences. For example, the master state machine 413 may pre-allocate physical resources (such as time slots and buffer areas) required for the target bandwidth to ensure sufficient transmission resources after bandwidth switching. For another example, the master state machine 413 may suspend data transmission at the moment of bandwidth switching to avoid packet loss through caching or retransmission mechanisms.

[0071] For example, Figure 4 As shown, in at least one embodiment of the present disclosure, the data link layer 410 may further include a link function module 414, which is communicatively connected to the main state machine 413 and multiple link layer channels 415 and is configured to perform data encoding and decoding error correction, data packet assembly or unpacking.

[0072] For example, Figure 4 As shown, in at least one embodiment of the present disclosure, the multiple physical layer channels 421 may include at least one transmitting physical layer channel and at least one receiving physical layer channel, and the multiple link layer channels 415 may include at least one transmitting link layer channel and at least one receiving link layer channel. The transmitting link layer channels correspond to the transmitting physical layer channels, and the receiving link layer channels correspond to the receiving physical layer channels, thereby receiving data packets to be transmitted from the link function module 414 or providing received data packets to the link function module 414.

[0073] For example, in at least one embodiment of the present disclosure, a transmitting link layer channel is configured to scramble a data packet to be transmitted received from a link function module and provide the scrambled data packet to be transmitted to a corresponding transmitting physical layer channel. For example, a receiving link layer channel is configured to perform symbol alignment and descrambling on a data packet received from a corresponding receiving physical layer channel and provide the aligned and descrambled received data packet to the link function module 414.

[0074] Figure 5 A schematic block diagram of another interconnection interface provided by at least one embodiment of the present disclosure is Figure 4 A specific example of an embodiment is provided.

[0075] like Figure 5As shown, the interconnection interface may include a data link layer 510, a physical layer 520, and a protocol layer 530. The data link layer 510 and the physical layer 520 communicate with each other, and the data link layer 510 and the protocol layer 530 communicate with each other. Figure 5 As shown, the protocol layer 530 includes a system bus 531 and a status monitoring module 532; the data link layer 510 includes a bandwidth switching control module 511, a channel status management module 512, multiplexers 5121a and 5121b, a main state machine 513, a link function module ( Figure 5 Not shown) and multiple link layer channels ( Figure 5 For example, the plurality of link layer channels may include a receiving link layer channel 5151 and a sending link layer channel 5152; the physical layer 520 includes a plurality of physical layer channels ( Figure 5 (not shown in the figure), for example, the multiple physical layer channels may include a receiving physical layer channel 5211 and a sending physical layer channel 5212.

[0076] For example, Figure 5 As shown, the link function module ( Figure 5 5141). For example, the link transmission submodule 5142 may be configured to perform information state synchronization operations in the transmission link layer channel 5152. For example, the link reception submodule 5141 may be configured to perform information state synchronization operations in the reception link layer channel 5151. For example, the information state synchronization operations in the transmission link layer channel 5152 may include hardware synchronization management of the transmission link layer channel 5152 before and after the bandwidth switching process, such as operations such as scrambling and level balancing. For example, the information state synchronization operations in the reception link layer channel 5151 may include hardware synchronization management of the reception link layer channel 5151 before and after the bandwidth switching process, such as operations such as descrambling and symbol alignment.

[0077] For example, the link transmission submodule 5142 may receive the first data from the protocol layer 530 via the system bus 531 and provide the first logical bit stream to the transmission link layer channel 5152. Figure 5 As shown, the link sending submodule 5142 may include a buffer module 5142a, an error correction coding module 5142b, a packetization module 5142c and a sequence generator 5142d.

[0078] For example, the buffer module 5142a can be configured to cache untransmitted first data during a bandwidth switching operation and provide the untransmitted first data to the packetization module 5142c. For example, when the system needs to perform a bandwidth switching operation, that is, switch from one bandwidth mode to another, data transmission may be temporarily interrupted or discontinuous. At this time, the buffer module 5142a can ensure that the untransmitted first data is not lost due to the bandwidth switching operation. When the bandwidth switching operation is completed and the system enters a new working state, the buffer module 5142a can provide these cached untransmitted first data to the packetization module 5142c. The packetization module 5142c can reorganize this data into a data packet format suitable for the new bandwidth mode and then continue transmission.

[0079] For example, the error correction coding module 5142b can be configured to receive the first data from the system bus 531, perform error correction coding on the first data, and provide the error correction coded first data to the packetization module 5142c. For example, the error correction coding module 5142b can add redundant check information to the synchronization process to improve the reliability of state synchronization.

[0080] For example, sequencer 5142d can be configured to generate a synchronization training sequence based on the bandwidth switching decision and provide the synchronization training sequence to each transmitting link layer channel. For example, a synchronization training sequence is a special signal or data pattern predefined in the communication system. It is used to achieve timing alignment and state synchronization when dynamically adjusting transmission parameters (such as bandwidth and rate) between communicating entities. This ensures that the clocks of the sender and receiver are consistent and the channel parameters match during the switching process, thereby avoiding data misalignment or loss. For example, the synchronization training sequence can be the TS1 / TS2 training sequence in the PCIe protocol. Physical layer parameters can be negotiated by continuously sending an ordered character set containing link width and rate identifiers.

[0081] For example, the packetization module 5142c can be configured to packetize the first data according to the bandwidth switching decision, obtain a first logical bit stream, and provide the first logical bit stream to each transmit link layer channel 5152. For example, the packetization module 5142c can packetize the data according to the new data packet format indicated by the bandwidth switching decision.

[0082] For example, the transmitting link layer channel 5152 may receive the first data from the link transmitting submodule 5142 and provide the first bit stream to the transmitting physical layer channel 5212. Figure 5As shown, the transmission link layer channel 5152 includes a scrambling module 5152a and a level balancing module 5152b. For example, the scrambling module 5152a can be configured to receive a first logical bit stream from the link transmission submodule 5142, perform scrambling on the first logical bit stream under the control of the channel state management module 512, and provide the scrambled first logical bit stream to the level balancing module 5152b. For example, the level balancing module 5152b can be configured to adjust the voltage intensity of the scrambled first logical bit stream under the control of the channel state management module 512 to provide the first bit stream to each transmission physical layer channel 5212.

[0083] For example, the channel state management module 512 can be connected to multiplexers 5121a and 5121b to control the various channels in the data link layer. For example, the channel state management module 512 can generate control signals to control the specific channel switching state of the receiving link layer channel 5151 or the transmitting link layer channel 5152 connected to the multiplexer. For example, the multiplexer 5121a can be connected to the receiving link layer channel 5151 and the link receiving submodule 5141, such as the descrambling module 5151a and the depacketizing module 5141c. Upon receiving the control signal from the channel state management module 512, the multiplexer 5121a can control the specific channel switching state of the receiving link layer channel 5151. For another example, the multiplexer 5121b can be connected to the transmitting link layer channel 5152 and the link transmitting submodule 5142, such as the scrambling module 5152a, the sequencer 5142d, and the packetization module 5142c. When receiving a control signal from the channel state management module 512, the multiplexer 5121b can control the specific channel switch state of the transmission link layer channel 5152. For example, when the multiplexers 5121a and 5121b are two-or-one multiplexers, the corresponding control signal can be a logic value of 0 / 1.

[0084] For example, the receiving link layer channel 5151 can receive the second bit stream from the receiving physical layer channel 5211 and provide the second logical bit stream to the link receiving submodule 5141. For example, the receiving link layer channel 5151 can include a descrambling module 5151a, a flexible buffer module 5151b, and a symbol alignment module 5151c. For example, the symbol alignment module 5151c can be configured to receive the second bit stream from each receiving physical layer channel 5211, calibrate the symbol timing between the multiple receiving physical layer channels, and provide the untransmitted second logical bit stream to the flexible buffer module 5151b. For example, the flexible buffer module 5151b can be configured to buffer the untransmitted second logical bit stream and provide the unscrambled second logical bit stream to the descrambling module 5151a. For example, the descrambling module 5151a can be configured to descramble the unscrambled second logical bit stream to provide the second logical bit stream to the link receiving submodule 5141.

[0085] For example, the link receiving submodule 5141 may receive the second logical bit stream from the receiving link layer channel 5151 and provide the second data to the protocol layer 530 via the system bus 531. Figure 5 As shown, the link receiving submodule 5141 may include an error correction decoding module 5141a, a de-skew module 5141b, and a depacketization module 5141c. For example, the depacketization module 5141c may be configured to receive the second logical bit stream from each receiving link layer channel 5151, and depacketize the second logical bit stream according to the data packet format indicated by the bandwidth switching decision, to provide the second data before error correction decoding to the error correction decoding module 5141a. For example, the de-skew module 5141b may be configured to eliminate the transmission skew of the second logical bit stream between multiple receiving physical layer channels during the depacketization process. For example, the error correction decoding module 5141a may be configured to perform error correction decoding on the second data before error correction decoding to provide the second data to the system bus 531. For example, the error correction decoding module 5141a may verify the integrity of the data during the synchronization process and correct possible transmission errors.

[0086] At least one embodiment of the present disclosure further provides a data transmission method of an interconnection interface. Figure 6 A schematic flow chart of a data transmission method of an interconnected interface provided in at least one embodiment of the present disclosure, which method may correspond to Figure 2-Figure 5 Any of the interconnect interfaces shown.

[0087] like Figure 6 As shown, the data transmission method provided by at least one embodiment of the present disclosure includes at least steps S610 to S620. For example, the data transmission method can be applied to the interconnection interface provided by any of the above embodiments of the present disclosure.

[0088] Step S610: Transmitting a bit stream through multiple physical layer channels of the physical layer.

[0089] Step S620: Determine at least one target physical channel among multiple physical layer channels based on the bandwidth switching decision at the data link layer to perform a bandwidth switching operation; wherein the bandwidth switching operation includes directly switching the target physical layer channel from the current working state to the target working state.

[0090] For example, in at least one embodiment of the data transmission method of the interconnect interface, the bandwidth switching operation includes switching the interconnect interface to a lower power consumption state, and the target working state includes a non-working state having lower power consumption than the current working state.

[0091] For example, in at least one embodiment of the data transmission method of the interconnection interface, the interconnection interface may further include a protocol layer, and the protocol layer and the data link layer are communicatively connected to transmit data to each other. In this case, step S620 may further include step S621.

[0092] Step S621: The data link layer receives a bandwidth switching decision from the protocol layer via the system bus.

[0093] For example, in at least one embodiment of the data transmission method of the interconnected interface, the protocol layer may further include a status monitoring module, which is communicatively connected to the system bus. In this case, step S621 may further include: the status monitoring module generating a bandwidth switching decision based on the status monitoring result of the bit stream.

[0094] For example, in at least one embodiment of the data transmission method of the interconnected interface, step S621 may further include: a status monitoring module monitoring the target dimension of the bit stream and generating a bandwidth switching decision based on the monitoring result.

[0095] For example, in at least one embodiment of the data transmission method of the interconnected interface, step S621 may further include: the status monitoring module predicts the target dimension of the bit stream, and generates a bandwidth switching decision based on the prediction result and the monitoring result.

[0096] For example, in at least one embodiment of the data transmission method of the interconnection interface, the data link layer includes multiple link layer channels, and the multiple link layer channels are communicatively connected to the multiple physical layer channels.

[0097] For example, in at least one embodiment of the data transmission method of the interconnect interface, the data link layer may further include a bandwidth switching control module and a channel status management module. Step S620 may further include steps S622 to S623.

[0098] Step S622: The bandwidth switching control module receives the bandwidth switching decision and controls the bandwidth switching operation.

[0099] Step S623: The channel state management module receives the bandwidth switching decision and manages multiple link layer channels in the bandwidth switching operation.

[0100] For example, in at least one embodiment of the data transmission method of the interconnect interface, the channel management module is communicatively connected to the multiple physical layer channels. Step S623 may further include: the channel management module controlling the clocks of the multiple physical layer channels.

[0101] For example, in at least one embodiment of the data transmission method for an interconnected interface, the data link layer may further include a master state machine. Step S622 may further include: the master state machine receiving a bandwidth switching decision from the bandwidth switching control module, managing information state synchronization during the bandwidth switching operation, generating a request based on the bandwidth switching decision, and providing the request and the bandwidth switching decision to the channel state management module.

[0102] For example, in at least one embodiment of the data transmission method of the interconnect interface, the data link layer may further include a link function module that is communicatively connected to the main state machine and the plurality of link layer channels. Step S622 may further include step S6221.

[0103] Step S6221: The link function module performs data encoding and decoding error correction, data packet assembly or unpacking; wherein, the multiple physical layer channels include at least one sending physical layer channel and at least one receiving physical layer channel, the multiple link layer channels include at least one sending link layer channel and at least one receiving link layer channel, the at least one sending link layer channel and the at least one receiving link layer channel correspond to the at least one sending physical layer channel and the at least one receiving physical layer channel respectively, and receives the data packet to be sent from the link function module, or provides the received data packet to the link function module.

[0104] For example, in at least one embodiment of the data transmission method of the interconnection interface, step S6221 includes: the sending link layer channel scrambles the data packet to be sent received from the link function module, and provides the scrambled data packet to be sent to the corresponding sending physical layer channel; the receiving link layer channel is configured to perform symbol alignment and descrambling on the data packet received from the corresponding receiving physical layer channel, and provides the aligned and descrambled received data packet to the link function module.

[0105] For example, in at least one embodiment of the data transmission method of the interconnection interface, step S6221 includes: the link sending submodule performs the information status synchronization operation in the sending link layer channel; the link receiving submodule performs the information status synchronization operation in the receiving link layer channel.

[0106] It should be noted that, for the relevant content of the functions or beneficial effects of each step in the data transmission method of the interconnection interface provided in any embodiment of the present disclosure, for example, reference can be made to the relevant description of the interconnection interface provided in any embodiment of the present disclosure, and no further details will be given here.

[0107] It should also be noted that in the various embodiments of the present disclosure, the order in which the various steps of the interconnected interface data transmission method are executed is not limited. Although the execution process of the various steps is described above in a specific order, this does not constitute a limitation on the embodiments of the present disclosure. The various steps in the interconnected interface data transmission method can be executed serially or in parallel, which can be determined according to actual needs.

[0108] For example, compared with the above description, the data transmission method of the interconnection interface provided in at least one embodiment of the present disclosure may also include more or fewer steps, and the embodiments of the present disclosure are not limited to this.

[0109] Figure 7 A schematic block diagram of a chip provided in accordance with at least one embodiment of the present disclosure.

[0110] like Figure 7 As shown, the chip 700 includes an interconnection interface 710. The interconnection interface 710 can be the interconnection interface provided by any of the above embodiments of the present disclosure.

[0111] For example, Figure 7 As shown, in at least one embodiment of the present disclosure, a chip 700 may include multiple chiplets, such as a first chiplet 720 and a second chiplet 730. For example, each of the first chiplet 720 and the second chiplet 730 includes an interconnection interface 710, so as to communicate with each other through the interconnection interface 710. A chiplet refers to a pre-manufactured, unpackaged die with a specific function, which is integrated with other chiplets through standardized interfaces and advanced packaging technology to form a high-performance system-on-chip. For example, the first chiplet and the second chiplet may have the same or different functions. For example, the first chiplet may be a computing chiplet, and the second chiplet may be a storage chiplet, which communicate with each other through an interconnection interface.

[0112] For example, the first chiplet 720 and the second chiplet 730 can achieve communication connection through package-level physical interconnection and protocol collaboration. For example, in terms of physical interconnection, the first chiplet 720 and the second chiplet 730 can achieve direct physical layer connection by means of high-density copper interconnection or through-silicon vias (TSV) of a silicon interposer. The interface forms a multi-channel parallel link through an array of microbumps, and each channel transmits the original bit stream using high-speed electrical signals or optical pulses. For example, in terms of protocol collaboration, the interconnection interface 710 can use a standardized protocol stack (such as UCIe and AIB) to define the data packet format and transaction rules. For example, by being compatible with the CXL protocol, it supports memory read and write and cache consistency operations. At the same time, the data link layer controllers within the first chiplet 720 and the second chiplet 730 complete operations such as link training, traffic scheduling, and error recovery (such as CRC check and dynamic channel resynchronization).

[0113] At least some embodiments of the present disclosure further provide an electronic device comprising the chip of any of the above embodiments.

[0114] Figure 8 A schematic block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure.

[0115] like Figure 8 As shown, the electronic device 800 includes a chip 810. The chip 810 is a chip according to any embodiment of the present disclosure, for example Figure 7 Chip 700 is shown.

[0116] Figure 9 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0117] The electronic devices in the embodiments of the present disclosure may include mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), vehicle-mounted terminals (e.g., vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc. Figure 9 The electronic device 900 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0118] For example, Figure 9As shown, in some examples, electronic device 900 includes a processor 901 (e.g., a central processing unit, a graphics processing unit, etc.). Processor 901 can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 902 or programs loaded from storage device 908 into random access memory (RAM) 903. For example, processor 901 can be the chip provided in any of the above embodiments, such as chip 810 or chip 700. RAM 903 also stores various programs and data required for computer system operation. Processor 901, ROM 902, and RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to bus 904.

[0119] For example, the following components can be connected to the I / O interface 905: an input device 906 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 907 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device including, for example, a magnetic tape, a hard disk, etc.; and a communication device 909 which can also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 909 can allow the electronic device 900 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. Removable media 911, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 910 as needed so that the computer program read therefrom can be installed into the storage device as needed. Although Figure 9 The electronic device 900 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0120] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 909 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0121] For example, the electronic device 900 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure do not limit this.

[0122] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0123] There are a few points to note:

[0124] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0125] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0126] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An interconnection interface, comprising: A data link layer and a physical layer; wherein the data link layer and the physical layer communicate with each other; The physical layer includes a plurality of physical layer channels and is configured to transmit a bit stream through the plurality of physical layer channels; The data link layer is configured to determine at least one target physical channel among the multiple physical layer channels based on the bandwidth switching decision to perform a bandwidth switching operation, wherein the bandwidth switching operation includes directly switching the target physical layer channel from a current working state to a target working state.

2. The interconnection interface according to claim 1, wherein: The bandwidth switching operation includes switching the interconnect interface to a lower power consumption state, and the target working state includes a non-working state having lower power consumption than the current working state.

3. The interconnection interface according to claim 1 further comprises a protocol layer, wherein: The protocol layer is communicatively connected with the data link layer to transmit data to each other; The protocol layer includes a system bus and is configured to provide the bandwidth switching decision to the data link layer through the system bus.

4. The interconnection interface according to claim 3, wherein: The protocol layer also includes: The status monitoring module is communicatively connected to the system bus and is configured to generate the bandwidth switching decision according to a status monitoring result of the bit stream.

5. The interconnection interface according to claim 4, wherein: The status monitoring module is further configured to monitor the target dimension of the bit stream and generate the bandwidth switching decision based on the monitoring result.

6. The interconnection interface according to claim 5, wherein: The status monitoring module is further configured to predict the target dimension of the bitstream, and generate the bandwidth switching decision based on the prediction result and the monitoring result.

7. The interconnection interface according to any one of claims 3 to 5, wherein: The data link layer includes multiple link layer channels, and the multiple link layer channels are correspondingly communicated with the multiple physical layer channels.

8. The interconnection interface according to claim 7, wherein: The data link layer also includes a bandwidth switching control module and a channel status management module; wherein, The bandwidth switching control module is configured to receive the bandwidth switching decision and control the bandwidth switching operation; The channel state management module is in communication with the multiple link layer channels, and is configured to receive the bandwidth switching decision and manage the multiple link layer channels during the bandwidth switching operation.

9. The interconnection interface according to claim 8, wherein: The channel management module is communicatively connected to the multiple physical layer channels and is further configured to control clocks of the multiple physical layer channels.

10. The interconnection interface according to claim 8, wherein: The data link layer also includes: a main state machine, communicatively connected to the bandwidth switching module and the channel state management module, and configured to receive the bandwidth switching decision from the bandwidth switching control module, manage information state synchronization during the bandwidth switching operation, generate a request based on the bandwidth switching decision, and provide the request and the bandwidth switching decision to the channel state management module.

11. The interconnection interface according to claim 10, wherein: The data link layer also includes a link function module, wherein: The link function module is communicatively connected to the main state machine and the plurality of link layer channels, and is configured to perform data encoding and decoding error correction, and data packet assembly or depacketization; Among them, the multiple physical layer channels include at least one sending physical layer channel and at least one receiving physical layer channel, the multiple link layer channels include at least one sending link layer channel and at least one receiving link layer channel, the at least one sending link layer channel and the at least one receiving link layer channel correspond to the at least one sending physical layer channel and the at least one receiving physical layer channel respectively, and receive data packets to be sent from the link function module, or provide the received data packets to the link function module.

12. The interconnection interface according to claim 11, wherein: The transmitting link layer channel is configured to scramble the data packets to be transmitted received from the link function module, and provide the scrambled data packets to be transmitted to the corresponding transmitting physical layer channel; The receiving link layer channel is configured to perform symbol alignment and descrambling on data packets received from the corresponding receiving physical layer channel, and provide the aligned and descrambled received data packets to the link function module.

13. The interconnection interface according to claim 12, wherein: The link function module is further configured to perform the information state synchronization operation, and includes a link sending submodule and a link receiving submodule; wherein, The link sending submodule is configured to perform the information state synchronization operation in the sending link layer channel; The link receiving submodule is configured to perform the information status synchronization operation in the receiving link layer channel.

14. A data transmission method for an interconnected interface, wherein: The interconnection interface includes a data link layer and a physical layer, the data link layer and the physical layer communicate with each other, and the data transmission method includes: transmitting a bit stream via a plurality of physical layer channels of the physical layer; Determining, at the data link layer, at least one target physical channel among the plurality of physical layer channels based on the bandwidth switching decision, to perform a bandwidth switching operation; The bandwidth switching operation includes directly switching the target physical layer channel from a current working state to a target working state.

15. A chip comprising the interconnection interface according to any one of claims 1 to 13.

16. The chip according to claim 15, comprising a first core particle and a second core particle, wherein: Each of the first core particle and the second core particle includes the interconnection interface, so as to be communicatively connected to each other through the interconnection interface.

17. An electronic device comprising the chip according to claim 15 or 16.

Images