Ferroelectric tunnel junction and ferroelectric field effect transistor function coupled computing storage chip

Abstract

The invention discloses a ferroelectric tunnel junction and ferroelectric field effect transistor function coupled calculation storage chip, a design method and a preparation method, the calculation storage chip is in an out-of-plane vertical direction, a two-dimensional material is combined with an upper electrode and a lower electrode to form a ferroelectric tunnel junction structure, and the heights of upper and lower Schottky barriers are changed by turning over a ferroelectric polarization state, so that the ferroelectric field effect transistor function coupled calculation storage chip is obtained. Therefore, the tunneling resistance is regulated and controlled, and high-performance nonvolatile storage is realized by utilizing multiple resistance state characteristics of the ferroelectric tunneling junction; in the in-plane transverse direction, the two-dimensional material serves as a conductive channel, a ferroelectric polarization depolarization field serves as equivalent grid voltage, the carrier concentration in a channel is regulated and controlled, then dynamic adjustment of on-resistance is achieved, and the efficient calculation function is completed. And by realizing an integrated structure of calculation and storage, excellent performance is shown in large-scale matrix operation and exponential function calculation. The characteristics of high integration level and low power consumption provide a new solution for generative artificial intelligence hardware acceleration.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic devices and artificial intelligence technology, and specifically relates to a computing storage chip with a ferroelectric tunneling junction and a ferroelectric field effect transistor functionally coupled, and a design and preparation method thereof. Background Art

[0002] Generative AI technology has made significant progress in recent years, particularly in large language models (LLMs), multimodal models, and image and video generation models. This has driven the widespread application of AI in areas such as text, images, audio, and video. The core of generative AI technology lies in neural network-based generative models (such as generative adversarial networks (GANs), variational autoencoders (VAEs), and the Transformer architecture. These models require extensive matrix operations and nonlinear function calculations during runtime, exponentially increasing computational complexity and placing higher demands on hardware performance. The traditional von Neumann architecture, currently the dominant architecture for generative AI hardware implementations, has a separate architecture for computing and storage units, leading to a "memory wall" problem: frequent data transfers during computation, resulting in high power consumption, latency, and hardware complexity. This architectural bottleneck is particularly pronounced when faced with the high-frequency computational demands of generative AI models. Especially when handling large-scale generative tasks, the data transfer and storage access overhead significantly limit model performance. Therefore, optimizing hardware architecture to meet the demands of generative AI has become a hot topic of research.

[0003] In-memory computing is an emerging computing paradigm that aims to embed computational operations within the storage process, improving efficiency by reducing data transfer between computing and storage units. By performing linear algebra operations such as addition and multiplication, as well as nonlinear function calculations, directly in memory, in-memory computing significantly reduces power consumption and latency, significantly improving computing performance. This makes it an effective means of addressing the "memory wall" problem, particularly in computationally intensive, data-intensive applications such as generative AI.

[0004] Despite the enormous potential of in-memory computing technology, existing implementations still face several technical difficulties. First, traditional memory components such as SRAM or Flash lack the sensitive multi-resistance properties, making it difficult to meet the high-precision weight representation requirements of generative AI. Second, current in-memory computing hardware has limited support for nonlinear operations and cannot efficiently implement exponential operations such as the Softmax function, which significantly restricts further improvements in generative AI performance. Furthermore, many in-memory computing architectures still have shortcomings in power-off data integrity, long-term data retention, and energy optimization, making it difficult to meet the high reliability and low energy requirements of generative AI.

[0005] Therefore, developing an in-memory computing solution that combines new materials, new devices, and new architectures to improve the computing efficiency and hardware adaptability of generative artificial intelligence is an important topic in the current research field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a computing storage chip, design and preparation method that couples the functions of a ferroelectric tunneling junction and a ferroelectric field-effect transistor, thereby solving the problem in the prior art that in-memory computing is difficult to meet the requirements of generative artificial intelligence for high-precision weight representation, as well as the problem of limited support for nonlinear operations.

[0007] The present invention adopts the following technical solutions to solve the above technical problems: A computing memory chip with a functional coupling of a ferroelectric tunneling junction and a ferroelectric field effect transistor includes a bottom electrode arranged on an insulating substrate, a two-dimensional ferroelectric semiconductor material layer arranged above the bottom electrode, and a pair of top electrodes symmetrically arranged at both ends above the two-dimensional ferroelectric semiconductor material layer.

[0008] The two-dimensional ferroelectric semiconductor material layer realizes the ferroelectric tunneling junction function in the out-of-plane vertical direction, generating multiple stable resistance states for storage; in the in-plane lateral direction, the adjustable computing function of the ferroelectric field effect transistor is realized by automatically controlling the carrier concentration in the channel.

[0009] The multiple resistance states of the ferroelectric tunneling junction are negatively correlated with the on-resistance of the ferroelectric field effect transistor, and are controlled by regulating the ferroelectric polarization intensity and direction.

[0010] A method for designing a computing memory chip, characterized by comprising the following steps: Step 1: Select a two-dimensional ferroelectric semiconductor material that has both ferroelectric and semiconductor mechanisms; Step 2: Design the pattern and specifications of the bottom electrode, with a minimum line width of 500 nanometers; Step 3: Design the pattern and specifications of the top electrode, with a minimum line width of 500 nanometers; Step 4: On the simulation platform, prepare a computing memory chip with ferroelectric tunneling junction performance and ferroelectric field effect transistor performance, and verify its performance.

[0011] The test method for ferroelectric tunneling junction performance is as follows: Applying a gradually changing external voltage between the top electrode and the bottom electrode to obtain a tunneling current-voltage characteristic curve of the ferroelectric tunneling junction; Different write pulse voltages are applied between the top electrode and the bottom electrode to regulate the ferroelectric polarization state, so that the tunnel junction exhibits multiple stable current states and obtains multiple stable resistance state characteristic curves of the tunnel junction.

[0012] The test method for the performance of ferroelectric field effect transistors is as follows: By applying different gate voltages, the corresponding drain-source current variation curves are obtained; by increasing the gate voltage scanning range, the control range of the depolarization field is obtained, and the non-volatile switching behavior and control characteristics of the ferroelectric field-effect transistor are determined; A series of gate pulses of different amplitudes are applied to observe the switching process between the low-resistance state and the high-resistance state. By recording the changes in the drain-source current, the multi-resistance state characteristics and state retention time of the device are determined, and its stability in multiple adjustable states is verified.

[0013] It also includes testing the coupling performance and nonlinear computing performance of the computing memory chip. The specific methods are as follows: First, the polarization state of the computing memory chip is controlled by applying an external electric field to verify the mapping relationship between the multi-resistance state characteristics of the ferroelectric tunneling junction and the on-resistance of the ferroelectric field-effect transistor. The resistance change of the ferroelectric tunneling junction is used to construct the exponential basis function. At the same time, the dynamic adjustment of the weight parameters by the ferroelectric field-effect transistor is combined to perform nonlinear calculations and determine the degree of match between the calculated results and the theoretical results.

[0014] The steps include: Step a, selecting a two-dimensional ferroelectric semiconductor material as a functional material and preparing a two-dimensional material film by a mechanical exfoliation method; Step b: preparing a two-dimensional material layer on an insulating substrate and defining an electrode pattern using electron beam lithography and dry etching techniques; Step c, depositing the bottom electrode platinum material by magnetron sputtering and performing annealing treatment; Step d: accurately transferring the prepared two-dimensional material film onto the insulating substrate using a dry transfer technique, and removing the material in the redundant area using a dry etching technique to ensure that only the two-dimensional material in the required functional area remains; Step e: On the two-dimensional material after the transfer is completed, the top electrode pattern is redefined using electron beam lithography technology, and the top electrode gold material is deposited by magnetron sputtering.

[0015] Prepare a two-dimensional material layer with a size of 30 microns x 30 microns or more; prepare a bottom electrode with a thickness of 20 nanometers; prepare a top electrode with a thickness of 70 nanometers A computer storage medium stores computer instructions, which are used to execute all or part of the steps of the method when called.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. Through the integrated design of storage and computing, it breaks through the traditional storage bottleneck and significantly reduces the delay and energy consumption of data transmission.

[0017] 2. By leveraging the resistance-state mapping relationship between ferroelectric tunneling junctions and ferroelectric field-effect transistors, this invention can efficiently perform softmax functions and other exponential computations, accelerating exponential calculations. With its low-power and high-performance design, the energy efficiency of hardware operation is significantly improved.

[0018] 3. The universal approach of this invention can adapt to a wide range of generative artificial intelligence application scenarios, including text generation, image generation, and multimodal intelligent computing, showing extremely high adaptability and scalability.

[0019] 4. This invention provides an efficient hardware solution for the development of generative artificial intelligence, which is both innovative and practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the structure of the ferroelectric coupling device of the present invention; Figure 2 Schematic diagram of the structure of the ferroelectric tunneling junction in the ferroelectric coupling device of the present invention; Figure 3 is a planar optical diagram of the ferroelectric coupling device of the present invention; Figure 4 Graphs showing the functional test of the ferroelectric tunneling junction of the present invention, (a) a tunneling junction switching current-voltage graph, and (b) a ferroelectric multistable retention characteristic graph; Figure 5 Graphs showing the functional test of the ferroelectric field-effect transistor of the present invention, (a) a transfer characteristic curve of the field-effect transistor, (b) a ferroelectric multistable retention characteristic graph, and (c) a cyclic pulse resistance switching response graph; Figure 6 The coupling characteristics of the ferroelectric tunneling junction and the ferroelectric field effect transistor of the present invention are shown in FIG. (a) is a coupling switch performance diagram, (b) is a nonlinear correlation characteristic diagram, and (c) is an exponential operation performance test diagram of the coupling characteristics. Figure 7 This is a planar optical diagram of a 3×9 array device of the present invention; Figure 8 This is an example of a text generation task based on an array device of the present invention; Among them, 1-insulating substrate; 2-bottom electrode; 3-top electrode; 4-two-dimensional ferroelectric semiconductor material layer. DETAILED DESCRIPTION

[0021] The structure and working process of the present invention will be further described below with reference to the accompanying drawings.

[0022] Generative AI hardware based on traditional von Neumann architecture has bottleneck problems in data transmission, such as high latency and high energy consumption. To address this problem, the present invention proposes a computing and storage integrated device architecture based on two-dimensional ferroelectric semiconductor materials. Figure 1 As shown, efficient storage and computing functions are achieved through functionally coupled ferroelectric tunneling junctions and ferroelectric field-effect transistors. In the out-of-plane vertical direction, the multiple resistance-state characteristics of the ferroelectric tunneling junction are utilized to achieve high-performance non-volatile storage. In the in-plane lateral direction, the depolarization field of the ferroelectric polarization acts as an equivalent gate voltage to regulate the carrier concentration in the channel, thereby achieving dynamic adjustment of the on-resistance and completing efficient computing functions. The ferroelectric tunneling junction and ferroelectric field-effect transistor achieve functional coupling through a self-regulated polarization mechanism. In addition, the resistance-state mapping relationship between the two achieves efficient fitting of exponential operations, further addressing the core computing requirements in generative artificial intelligence.

[0023] A computing memory chip with a functional coupling of a ferroelectric tunneling junction and a ferroelectric field effect transistor includes a bottom electrode arranged on an insulating substrate, a two-dimensional ferroelectric semiconductor material layer arranged above the bottom electrode, and a pair of top electrodes symmetrically arranged at both ends above the two-dimensional ferroelectric semiconductor material layer.

[0024] Specific embodiment 1, as Figure 1 、 Figure 2 、 Figure 3 As shown, A computing memory chip with a functional coupling of a ferroelectric tunneling junction and a ferroelectric field effect transistor includes a bottom electrode 2 arranged on an insulating substrate 1, a two-dimensional ferroelectric semiconductor material layer 4 arranged above the bottom electrode 2, and a pair of top electrodes 3 symmetrically arranged at both ends above the two-dimensional ferroelectric semiconductor material layer 4.

[0025] The two-dimensional ferroelectric semiconductor material layer generates multiple stable resistance states in the out-of-plane vertical direction, realizing the ferroelectric tunneling junction function; in the in-plane lateral direction, the adjustable computing function of the ferroelectric field effect transistor is realized by automatically controlling the carrier concentration in the channel.

[0026] The multiple resistance states of the ferroelectric tunneling junction are negatively correlated with the on-resistance of the ferroelectric field effect transistor, and are controlled by regulating the ferroelectric polarization intensity and direction.

[0027] A method for designing a computing memory chip with functional coupling of a ferroelectric tunneling junction and a ferroelectric field effect transistor comprises the following steps: Step 1: Select a two-dimensional ferroelectric semiconductor material that has both ferroelectric and semiconductor mechanisms; Step 2: Design the pattern and specifications of the bottom electrode, with a minimum line width of 500 nanometers; Step 3: Design the pattern and specifications of the top electrode, with a minimum line width of 500 nanometers; Step 4: Verification test.

[0028] A method for preparing a computing memory chip with a ferroelectric tunneling junction and a ferroelectric field effect transistor functionally coupled comprises the following steps: Step a, selecting a two-dimensional ferroelectric semiconductor material as a functional material and preparing a two-dimensional thin film by a mechanical exfoliation method; Step b: preparing a two-dimensional material layer on an insulating substrate and defining an electrode pattern using electron beam lithography and dry etching techniques; Step c, depositing the bottom platinum electrode material by magnetron sputtering and performing annealing treatment; Step d: accurately transferring the prepared two-dimensional material film to the target substrate using a dry transfer technique, and using a dry etching technique to remove the material in the excess area to ensure that only the two-dimensional material in the required functional area remains; Step e: On the two-dimensional material after the transfer is completed, the electrode pattern is redefined using electron beam lithography technology, and the top gold electrode material is deposited by magnetron sputtering.

[0029] Specific embodiment 2, as Figures 1 to 8 As shown, A method for preparing a computing memory chip with a ferroelectric tunneling junction and a ferroelectric field effect transistor functionally coupled comprises the following steps: Step a: Select a two-dimensional ferroelectric semiconductor material as the functional material and prepare a two-dimensional thin film by a mechanical exfoliation method; the material has excellent ferroelectric properties and semiconductor properties, meeting the needs of high-performance computing and storage integrated devices.

[0030] Step b: preparing a two-dimensional material layer on an insulating substrate (such as silicon oxide / silicon) and defining an electrode pattern using electron beam lithography and dry etching techniques; Step c, depositing the bottom platinum electrode material by magnetron sputtering, and optimizing the contact characteristics by annealing; Step d: accurately transferring the prepared two-dimensional material film to the target substrate using a dry transfer technique, and using a dry etching technique to remove the material in the excess area to ensure that only the two-dimensional material in the required functional area remains; Step e: On the two-dimensional material after the transfer is completed, the electrode pattern is redefined using electron beam lithography technology, and the top gold electrode material is deposited by magnetron sputtering.

[0031] In order to achieve the functional integration of ferroelectric tunneling junction and ferroelectric field-effect transistor, the interface engineering between the upper and lower electrodes and the two-dimensional material was specially designed during the device preparation process to enhance the Schottky barrier control capability.

[0032] Finally, through standard micro-nano processing technology, a ferroelectric tunneling junction-ferroelectric field effect transistor coupling device with multi-resistance state storage and dynamic computing capabilities was successfully prepared.

[0033] In order to further verify the performance of the ferroelectric tunneling junction-ferroelectric field effect transistor coupling device of this scheme, a series of performance tests were carried out, mainly including: 1. Ferroelectric tunneling junction performance test Verify the tunneling current switching characteristics and multi-stability retention performance of ferroelectric tunneling junctions, and provide support for their application in information storage and reconfigurable logic circuits. Figure 4 (a) Shows the tunneling current-voltage (IV) characteristic curve of the ferroelectric tunneling junction, demonstrating distinct switching behavior with changes in applied voltage. Under forward and reverse voltage modulation, the current exhibits asymmetric changes, with clear visible switching between the high resistance state (HRS) and low resistance state (LRS). This is due to the change in the tunneling barrier caused by the polarization reversal of the ferroelectric material. The current span exceeds 100 times, demonstrating an excellent on-off ratio and validating its potential as a data write and erase unit in nonvolatile memory. Figure 4 (b) further verifies the multi-stable state maintenance capability of the ferroelectric tunnel junction. By applying different write voltages to control the ferroelectric polarization state, the tunnel junction exhibits multiple stable current states (S1 to S16) and maintains a stable state for up to 10 7 The multistable state property of the ferroelectric tunneling junction not only enables traditional binary storage but also has the potential for multistable storage, making it possible for high-density information storage and multifunctional information processing.

[0034] 2. Ferroelectric field effect transistor performance test We tested the performance of the ferroelectric field-effect transistor, including its transfer characteristics, multistability retention capability, and cyclic pulse switching response capability. Figure 5 (a) shows the transfer characteristic curve of a ferroelectric field-effect transistor. The drain-source current (Ids) changes significantly with the application of different gate voltages (Vg). As the gate voltage sweep range increases (from ±20 V to ±50 V), the hysteresis of the curve gradually increases. This is due to the electric field control effect caused by the polarization switching of the ferroelectric material, fully demonstrating the nonvolatile switching behavior and controllable characteristics of the ferroelectric field-effect transistor. Figure 5 (b) shows the transistor's retention capability under multistable storage conditions. By applying different write voltages, the device can stably exhibit 128 discrete states from S1 to S128 and remain stable within 1000 seconds, indicating that it has good multistable storage characteristics and time stability. Figure 5(c) further verifies the transistor's cyclic resistance switching response under pulse control. After applying 20 pulses, the switching between the low resistance state (LRS) and high resistance state (HRS) is highly repeatable, with stable current values ​​and significant separation. These test results demonstrate that ferroelectric field-effect transistors not only possess excellent transfer characteristics and storage capacity, but also remain reliable under highly repeated operation, demonstrating their broad application prospects in non-volatile storage, reconfigurable logic devices, and neuromorphic computing.

[0035] 3. Coupling performance and nonlinear calculation performance test like Figure 6 As shown in the figure, we tested the coupling performance of the ferroelectric tunneling junction and the ferroelectric field-effect transistor and its performance in nonlinear calculations. First, by adjusting the polarization state of the device by applying an external electric field, we verified the mapping relationship between the multi-resistance state characteristics of the ferroelectric tunneling junction and the on-resistance of the ferroelectric field-effect transistor. The results show that under different polarization states, the change amplitude of the tunneling resistance shows a high nonlinear correlation with the change of the channel resistance of the field-effect transistor, confirming the effectiveness of the self-regulated polarization mechanism. We further tested the device's ability to fit typical exponential operations, using the resistance state change of the ferroelectric tunneling junction to complete the construction of the exponential basis function. At the same time, combined with the dynamic adjustment of the weight parameters by the ferroelectric field-effect transistor, efficient nonlinear calculations were achieved.

[0036] 4. Prepare a 3×9 hardware array and implement text generation function like Figure 7 As shown, a 3×9 hardware array was prepared based on two-dimensional ferroelectric semiconductor materials to verify the actual application performance of the device in generative artificial intelligence.

[0037] First, the array is prepared and packaged through high-precision lithography, thin film deposition and annealing processes to ensure that each array unit has the coupling function of ferroelectric tunneling junction and ferroelectric field-effect transistor, and has multi-resistance state storage characteristics.

[0038] The array was then used in hardware implementation of a text generation task, using the classic Transformer model as the core computing module. Leveraging Ohm's and Kirchhoff's laws, it efficiently performs linear algebraic operations such as weighted summation and matrix multiplication, while leveraging its nonlinear coupling properties to efficiently perform exponential operations (such as the Softmax function).

[0039] Specifically, the weighted summation and exponential transformation of the input matrix are mapped into hardware for efficient computation through the nonlinear coupling characteristics of the array.

[0040] Experimental results show that the array can achieve high-precision text generation with low power consumption (less than 1 μJ / bit per operation), and the logical accuracy of the generated results reaches 99.6%, which is highly consistent with the software simulation results.

[0041] Furthermore, the device's stability and consistency in actual operation were verified. Even after long periods of operation, the array's resistance state distribution and exponential calculation accuracy remained stable. This experiment further demonstrates the potential of integrated computing and storage arrays based on two-dimensional ferroelectric materials in the field of generative artificial intelligence, providing strong support for low-power, high-performance hardware acceleration technology.

[0042] A computer storage medium stores computer instructions, which are used to execute all or part of the steps of the method when called.

[0043] If the above functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0044] Through the above-mentioned specific embodiments, the design and performance advantages of the present invention have been fully verified, laying the foundation for the realization of efficient generative artificial intelligence hardware.

[0045] In summary, this solution provides a functionally coupled integrated computing and storage architecture and its applications. This architecture is designed based on the unique coupling mechanism of a ferroelectric tunneling junction and a ferroelectric field-effect transistor (FFET) in a two-dimensional ferroelectric semiconductor material. In the vertical direction, the two-dimensional material combines with upper and lower electrodes to form a FTT structure. By flipping the ferroelectric polarization state, the upper and lower Schottky barrier heights are altered, thereby regulating the tunneling resistance. This multi-resistance state characteristic of the FTT is leveraged to achieve high-performance non-volatile storage. In the lateral direction, the two-dimensional material acts as a conductive channel, using the depolarization field of the ferroelectric polarization to act as an equivalent gate voltage, regulating the carrier concentration in the channel and enabling dynamic adjustment of the on-resistance, thus achieving efficient computing. The FTT and FFET achieve functional coupling through a self-regulated polarization mechanism. Furthermore, the resistance mapping relationship between the two enables efficient fitting of exponential operations, providing hardware acceleration support for the core computing requirements of generative artificial intelligence (GAI). By achieving an integrated computing and storage architecture, the storage bottleneck in GAI computing is significantly reduced, demonstrating exceptional performance in large-scale matrix operations and exponential function calculations. Its high integration and low power consumption provide new solutions for generative artificial intelligence hardware acceleration, laying the technical foundation for the next generation of intelligent computing devices.

[0046] While the present invention has been disclosed above with reference to preferred embodiments, this is not intended to limit the present invention. Persons skilled in the art will readily appreciate that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A computing memory chip with a ferroelectric tunneling junction and a ferroelectric field-effect transistor functionally coupled, characterized in that: including a bottom electrode disposed on an insulating substrate; a two-dimensional ferroelectric semiconductor material layer disposed above the bottom electrode; a pair of top electrodes symmetrically arranged at both ends above the two-dimensional ferroelectric semiconductor material layer; The two-dimensional ferroelectric semiconductor material layer realizes the ferroelectric tunneling junction function in the out-of-plane vertical direction, generating multiple stable resistance states for storage; in the in-plane lateral direction, the adjustable computing function of the ferroelectric field effect transistor is realized by automatically controlling the carrier concentration in the channel.

2. The computing memory chip with a ferroelectric tunneling junction and a ferroelectric field effect transistor functionally coupled according to claim 1, characterized in that: The multiple resistance states of the ferroelectric tunneling junction are negatively correlated with the on-resistance of the ferroelectric field effect transistor, and are controlled by regulating the ferroelectric polarization intensity and direction.

3. A method for designing a computing memory chip based on the functional coupling of a ferroelectric tunneling junction and a ferroelectric field effect transistor according to any one of claims 1 to 2, characterized in that: The steps include: Step 1: Select a two-dimensional ferroelectric semiconductor material that has both ferroelectric and semiconductor mechanisms; Step 2: Design the pattern and specifications of the bottom electrode, with a minimum line width of 500 nanometers; Step 3: Design the pattern and specifications of the top electrode, with a minimum line width of 500 nanometers; Step 4: On the simulation platform, prepare a computing memory chip with ferroelectric tunneling junction performance and ferroelectric field effect transistor performance, and verify its performance.

4. The method for designing a computing memory chip according to claim 3, wherein: The test method for ferroelectric tunneling junction performance is as follows: Applying a gradually changing external voltage between the top electrode and the bottom electrode to obtain a tunneling current-voltage characteristic curve of the ferroelectric tunneling junction; Different write pulse voltages are applied between the top electrode and the bottom electrode to regulate the ferroelectric polarization state, so that the tunnel junction exhibits multiple stable current states and obtains multiple stable resistance state characteristic curves of the tunnel junction.

5. The method for designing a computing memory chip according to claim 3, wherein: The test method for the performance of ferroelectric field effect transistors is as follows: By applying different gate voltages, the corresponding drain-source current variation curves are obtained; by increasing the gate voltage scanning range, the control range of the depolarization field is obtained, and the non-volatile switching behavior and control characteristics of the ferroelectric field-effect transistor are determined; A series of gate pulses of different amplitudes are applied to observe the switching process between the low-resistance state and the high-resistance state. By recording the changes in the drain-source current, the multi-resistance state characteristics and state retention time of the device are determined, and its stability in multiple adjustable states is verified.

6. The method for designing a computing memory chip according to claim 3, wherein: It also includes testing the coupling performance and nonlinear computing performance of the computing memory chip. The specific methods are as follows: By applying an external electric field to control the polarization state of the computing memory chip, the mapping relationship between the multi-resistance state characteristics of the ferroelectric tunneling junction and the on-resistance of the ferroelectric field-effect transistor was verified. The resistance change of the ferroelectric tunneling junction is used to construct the exponential basis function. At the same time, the dynamic adjustment of the weight parameters by the ferroelectric field-effect transistor is combined to perform nonlinear calculations and determine the degree of match between the calculated results and the theoretical results.

7. A method for preparing a computing memory chip with a ferroelectric tunneling junction and a ferroelectric field effect transistor functionally coupled, for implementing a method for designing a computing memory chip with a ferroelectric tunneling junction and a ferroelectric field effect transistor functionally coupled as claimed in any one of claims 1 to 6, characterized in that: The steps include: Step a, selecting a two-dimensional ferroelectric semiconductor material as a functional material and preparing a two-dimensional material film by a mechanical exfoliation method; Step b: preparing a two-dimensional material layer on an insulating substrate and defining an electrode pattern using electron beam lithography and dry etching techniques; Step c, depositing the bottom electrode platinum material by magnetron sputtering and performing annealing treatment; Step d: accurately transferring the prepared two-dimensional material film onto the insulating substrate using a dry transfer technique, and removing the material in the redundant area using a dry etching technique to ensure that only the two-dimensional material in the required functional area remains; Step e: On the two-dimensional material after the transfer is completed, the top electrode pattern is redefined using electron beam lithography technology, and the top electrode gold material is deposited by magnetron sputtering.

8. The method for preparing a computing memory chip according to claim 7, wherein: Prepare a two-dimensional material layer with a size of 30 microns × 30 microns or more; prepare a bottom electrode with a thickness of 20 nanometers; prepare a top electrode with a thickness of 70 nanometers.

9. A computer storage medium, characterized in that: The computer storage medium stores computer instructions, which are used to execute all or part of the steps of the method according to any one of claims 1 to 6 when called.

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