Manufacturing method of power element with double polycrystalline silicon gates
The double polysilicon gate structure solves the problems of high on-resistance and sharp gate angle caused by the LOCOS field oxide region, achieves precise control of the shape and thickness of the field plate region, and improves the performance and reliability of power components.
Patent Information
- Application Number
- CN202410299147.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-15
- Publication Date
- 2025-09-16
AI Technical Summary
In the prior art, high on-resistance caused by the LOCOS field oxide region and process problems caused by the sharp angle between the gate and the field oxide region affect device characteristics and reliability.
A double polysilicon gate structure is adopted, and etching and impurity injection are performed through the photoresist layer as a shield to form field plate trenches and enhance the drift region, avoid damage to the LOCOS field oxide region, and eliminate the sharp angle between the gate and the field oxide region interface.
Precisely control the profile and thickness of the field plate area to reduce on-resistance, improve device characteristics and reliability, and avoid oxide damage and purity issues.
Smart Images
Figure CN120659349A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a power element with a double polysilicon gate, in particular to a method for manufacturing a power element with a double polysilicon gate capable of eliminating the acute angle of the interface between the gate and the field oxidation region. Background Art
[0002] Please refer to Figure 1 , which is a cross-sectional schematic diagram showing a power element 10 in the prior art. Figure 1 As shown, the power device 10 is formed in a substrate 11 and includes a gate oxide region 12 , a gate 13 , a field oxide region 17 , a spacer region 19 , a body region 20 , a source 21 , a drain 22 and a shallow trench isolation region 23 .
[0003] The power device 10 is a lateral double diffused metal oxide semiconductor (LDMOS) device. In a typical LDMOS device, the most effective way to improve the device breakdown voltage and the hot carrier injection problem near the gate edge is to use a field plate structure, which can alleviate the local electric field crowding that causes early device breakdown. Although the traditional LOCOS field oxide region (such as Figure 1 The field oxide region 17 shown is the simplest way to implement the field plate structure without the need for additional shielding definition, but the LOCOS field oxide region may cause some serious problems, such as high on-resistance and the diffusion of impurities (boron, phosphorus) in the LDMOS element into the field oxide region during high-temperature heat treatment.
[0004] Furthermore, the gate 13 and the gate oxide region 12 form a sharp angle at the interface with the field oxide region 17, which can cause process problems such as voids or seams. Furthermore, various oxide etching and re-deposition steps can exacerbate the recessing of the shallow trench isolation region 23. Furthermore, the diffusion of the aforementioned impurities (boron and phosphorus) in the field oxide region affects device performance and reliability.
[0005] In view of this, the present invention proposes a method for manufacturing a power element with a double polysilicon gate, which can avoid damage to the shallow trench insulation region or the LOCOS field oxide region, eliminate the sharp angle at the interface between the gate and the field oxide region, reduce the on-resistance, and improve the problems affecting the characteristics and reliability of the device. Summary of the Invention
[0006] In one aspect, the present invention provides a method for manufacturing a power element having a double polysilicon gate, comprising: forming a well region in a substrate; forming a gate oxide layer directly connected to and completely covering the substrate; forming a first polysilicon gate layer directly connected to and completely covering the gate oxide layer; forming a first photoresist layer on the first polysilicon gate layer by a first lithography process step to simultaneously define a reduced surface electric field region, an enhanced drift region and a field plate groove; etching the first polysilicon gate layer using the first photoresist layer as a shield to form the field plate groove; using the first photoresist layer as a shield, injecting a plurality of first conductive type impurities into the substrate to form the reduced surface electric field region; using the first photoresist layer as a shield , implanting a plurality of second conductive type impurities into the substrate to form the enhanced drift region, wherein the electrical properties of the plurality of first conductive type impurities are opposite to those of the plurality of second conductive type impurities; forming a field plate region in the field plate trench by a self-aligned process step; forming a second polysilicon gate layer directly connected to and completely covering the first polysilicon gate layer and the field plate region; and etching the first polysilicon gate layer and the second polysilicon gate layer to form a first polysilicon gate region and a second polysilicon gate region, thereby forming the double polysilicon gate; wherein a portion of the second polysilicon gate region is directly connected to and completely covers the first polysilicon gate region, and another portion of the second polysilicon gate region is directly connected to and covers a portion of the field plate region.
[0007] In one embodiment, the step of etching the first polysilicon gate layer through the first photoresist layer as a shield to form the field plate trench is performed before the step of implanting a plurality of first conductive type impurities into the substrate using the first photoresist layer as a shield to form the reduced surface electric field region and the step of implanting a plurality of second conductive type impurities into the substrate using the first photoresist layer as a shield to form the enhanced drift region.
[0008] In one embodiment, the step of etching the first polysilicon gate layer through the first photoresist layer as a shield to form the field plate trench is performed after the step of implanting a plurality of first conductive type impurities into the substrate using the first photoresist layer as a shield to form the reduced surface electric field region and the step of implanting a plurality of second conductive type impurities into the substrate using the first photoresist layer as a shield to form the enhanced drift region.
[0009] In one embodiment, the method for manufacturing a power device with a double polysilicon gate further includes: forming a liner oxide layer by a deposition process after forming the field plate trench, wherein the liner oxide layer completely covers the field plate trench.
[0010] In one embodiment, after forming the liner oxide layer, a deposition process and a chemical mechanical polishing process are performed to form a liner oxide region and the field plate region, wherein the liner oxide region completely covers the field plate trench.
[0011] In one embodiment, after forming the liner oxide layer, an anisotropic etching process is performed to etch the liner oxide layer to form a spacer oxide region, wherein the spacer oxide region covers the sidewalls of the field plate trench but does not cover a bottom of the field plate trench.
[0012] In one embodiment, the field plate region includes a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and / or a high-k dielectric (high-k) layer.
[0013] In one embodiment, a method for manufacturing a power element having a double polysilicon gate further includes: forming a body region in the substrate, wherein a portion of the body region is located directly below a portion of the first polysilicon gate region; and forming a source and a drain in the substrate below both sides of the double polysilicon gate, wherein the source is located in the body region.
[0014] From another perspective, the present invention provides a method for manufacturing a power device with a dual polysilicon gate, comprising: forming a well region in a substrate; forming a gate oxide layer directly connected to and completely covering the substrate; forming a first polysilicon gate layer directly connected to and completely covering the gate oxide layer; forming a first photoresist layer on the first polysilicon gate layer using a first lithography process step to simultaneously define a resurf region, an enhanced drift region, and a field plate trench; using the first photoresist layer as a shield, implanting a plurality of first conductive type impurities into the substrate to form the resurf region; and implanting a plurality of second conductive type impurities into the substrate using the first photoresist layer as a shield to form the enhanced drift region. The plurality of first conductive type impurities and the plurality of second conductive type impurities have opposite electrical properties; oxygen ions are implanted into the first polysilicon gate layer through an oxygen ion implantation process step with the first photoresist layer as a shield to form the field plate region; a second polysilicon gate layer is formed to directly connect to and completely cover the first polysilicon gate layer and the field plate region; and the first polysilicon gate layer and the second polysilicon gate layer are etched to form a first polysilicon gate region and a second polysilicon gate region, thereby forming the double polysilicon gate; a portion of the second polysilicon gate region is directly connected to and completely covers the first polysilicon gate region, and another portion of the second polysilicon gate region is directly connected to and covers a portion of the field plate region.
[0015] The advantages of the present invention are that the profile and thickness of the field plate region can be precisely controlled, and since the field plate region does not need to be etched, there will be no oxide damage and purity issues.
[0016] The following is a detailed description through specific embodiments to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor integrated structure 10 having high and low voltage components according to the prior art.
[0018] Figure 2A-2J FIG. 1 is a cross-sectional view showing a method for manufacturing a power device 30 having a double polysilicon gate according to an embodiment of the present invention.
[0019] Figure 3A-3H FIG. 1 is a cross-sectional view showing a method for manufacturing a power device 50 having a double polysilicon gate according to an embodiment of the present invention.
[0020] Figures 4A-4I FIG. 1 is a cross-sectional view showing a method for manufacturing a power device 70 having a double polysilicon gate according to an embodiment of the present invention.
[0021] Figure 5A-5G FIG. 1 is a cross-sectional view showing a method for manufacturing a power device 90 having a double polysilicon gate according to an embodiment of the present invention.
[0022] Explanation of symbols in the figure
[0023] 10: Semiconductor integrated structure with high and low voltage components
[0024] 11: Substrate
[0025] 12, 32a, 52a, 72a, 92a: Gate oxide region
[0026] 13: Gate
[0027] 17: Field oxidation region
[0028] 19: Interval
[0029] 20, 40, 60, 80, 100: body area
[0030] 21, 41, 61, 81, 101: Source
[0031] 22, 42, 62, 82, 102: drain
[0032] 23: Shallow Trench Isolation Area
[0033] 30, 50, 70, 90: Power components with double polysilicon gates
[0034] 31, 51, 71, 91: substrate
[0035] 31a, 51a, 71a, 91a: Well region
[0036] 32, 52, 72, 92: Gate oxide
[0037] 33, 53, 73, 93: first polysilicon gate layer
[0038] 33a, 53a, 73a, 93a: first polysilicon gate region
[0039] 34, 54, 74, 94: Reduced surface electric field area
[0040] 35, 55, 75, 95: Enhanced drift zone
[0041] 36, 56, 76: lining oxide layer
[0042] 36a, 56a, 76a: lining oxidation area
[0043] 37', 57', 77', 97': first photoresist layer
[0044] 37a, 57a, 77a: Field plate grooves
[0045] 37b, 57b, 77b, 97b: Field plate area
[0046] 38, 58, 78, 98: Second polysilicon gate layer
[0047] 38a, 58a, 78a, 98a: second polysilicon gate region
[0048] 39, 59, 79, 99: Gate spacer
[0049] 41a, 61a, 81a, 101a: Extension area DETAILED DESCRIPTION
[0050] The foregoing and other technical aspects, features, and effects of the present invention will be more clearly understood in the following detailed description of preferred embodiments with reference to the accompanying drawings. The drawings in this application are schematic, primarily intended to illustrate the process steps and the hierarchical relationship between layers. Shapes, thicknesses, and widths are not drawn to scale.
[0051] Please refer to Figure 2A-2J , which is a cross-sectional schematic diagram showing a method for manufacturing a power device 30 with a double polysilicon gate according to an embodiment of the present invention. The power device 30 with a double polysilicon gate comprises: a substrate 31, a well region 31a, a gate oxide region 32a, a first polysilicon gate region 33a, a resurf region 34, an enhanced drift region 35, a liner oxide region 36a, a field plate region 37b, a second polysilicon gate region 38a, a gate spacer region 39, a body region 40, a source 41, and a drain 42. Figure 2A As shown, a substrate 31 is first provided, and a well region 31a is formed in the substrate 31. In one embodiment, a photoresist layer is formed on the substrate 31 by a lithography process step to define the well region 31a. Figure 2A As shown, the photoresist layer is used as a shield, for example, an ion implantation process step is used to inject multiple impurities in the form of accelerated ions, such as Figure 2A As indicated by the arrows in FIG. 3 , the ions are implanted into the substrate 31 to form a well region 31 a .
[0052] Then, if Figure 2B As shown, a gate oxide layer 32 is formed to directly connect to and completely cover the substrate 31. In one embodiment, the gate oxide layer 32 is formed by a thermal oxidation process. Figure 2B As shown, a first polysilicon gate layer 33 is formed to directly connect to and completely cover the gate oxide layer 32. In one embodiment, the polysilicon gate layer 33 is formed by a deposition process step. Figure 2C As shown, a first photoresist layer 37' is formed on the first polysilicon gate layer 33 by a first lithography process step, so as to simultaneously define the resurf region 34, the enhanced drift region 35 and the field plate trench 37a. Figure 2C As shown, with the first photoresist layer 37' as a shield, for example, an ion implantation process is performed to inject a plurality of first conductive type impurities in the form of accelerated ions, such as Figure 2C As indicated by the arrows in FIG. 3 , the substrate 31 is implanted to form a resurf region 34 .
[0053] Afterwards, if Figure 2C As shown, with the first photoresist layer 37' as a shield, multiple second conductive type impurities are implanted into the substrate 31 by, for example, an ion implantation process step to form an enhanced drift region 35. It should be noted that the multiple first conductive type impurities and the multiple second conductive type impurities have opposite electrical properties. Figure 2C and Figure 2D As shown, the first polysilicon gate layer 33 is etched through the first photoresist layer 37' as a shield to form a field plate trench 37a. Figure 2E and Figure 2F As shown, a field plate region 37b is formed in the field plate trench 37a by, for example, a self-aligned process step. Figure 2D and Figure 2E As shown, after forming the field plate trench 37a, a liner oxide layer 36 is formed by, for example, a deposition process step, wherein the liner oxide layer 36 completely covers the field plate trench 37a. Figure 2E and Figure 2F As shown, after forming the liner oxide layer 36, a liner oxide region 36a and a field plate region 37b are formed by, for example, a deposition process and a chemical mechanical polishing process, wherein the liner oxide region 36a completely covers the field plate trench 37a. In one embodiment, the field plate region 37b includes a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a high-k dielectric (high-k) layer.
[0054] Afterwards, if Figure 2G As shown in FIG. 3 , a second polysilicon gate layer 38 is formed to directly connect to and completely cover the first polysilicon gate layer 33 and the field plate region 37 b. Figure 2H As shown, for example, a lithography process step and an anisotropic etching process step are used to etch the first polysilicon gate layer 33 and the second polysilicon gate layer 38 to form a first polysilicon gate region 33a and a second polysilicon gate region 38a, thereby forming a double polysilicon gate. Figure 2H As shown, a portion of the second polysilicon gate region 38a is directly connected to and completely covers the first polysilicon gate region 33a, and another portion of the second polysilicon gate region 38a is directly connected to and covers a portion of the field plate region 37b. Figure 2I As shown, for example, a plurality of first conductive type impurities are implanted into the substrate 31 by an ion implantation process step to form a body region 40, wherein a portion of the body region 40 is located directly below a portion of the first polysilicon gate region 33a. Figure 2I As shown, a plurality of second conductivity type impurities are implanted into substrate 31, for example, by an ion implantation process step, to form an extension region 41a of source 41. Extension region 41a is a portion of source 41 and is located directly below a gate spacer 39 formed subsequently, which is close to source 41.
[0055] Then, if Figure 2J As shown, gate spacers 39 are formed on both sides of the double polysilicon gate formed by the first polysilicon gate region 33a and the second polysilicon gate region 38a. Figure 2J As shown, a source 41 and a drain 42 are formed in the substrate 31 below both sides of the double polysilicon gate, wherein the source 41 is located in the body region 40 .
[0056] The substrate 31 is, for example but not limited to, a P-type or N-type semiconductor substrate, which is well known to those skilled in the art and will not be described in detail here.
[0057] Well region 31a is of the first conductivity type, for example, formed by implanting N-type or P-type impurities in the form of accelerated ions into the respective defined regions through an ion implantation process. This process is well known to those skilled in the art and will not be described in detail here. The first conductivity type can be either P-type or N-type. When the first conductivity type is P-type, the second conductivity type is N-type; when the first conductivity type is N-type, the second conductivity type is P-type.
[0058] In one embodiment, if Figure 2C and Figure 2DAs shown, the step of etching the first polysilicon gate layer 33 using the first photoresist layer 37' as a shield to form the field plate trench 37a is performed after the step of injecting a plurality of first conductive type impurities into the substrate 31 using the first photoresist layer 37' as a shield to form the resurf region 34 and the step of injecting a plurality of second conductive type impurities into the substrate 31 using the first photoresist layer 37' as a shield to form the enhanced drift region 35.
[0059] Figure 3A-3H FIG1 is a cross-sectional view showing a method for manufacturing a power device 50 having a double polysilicon gate according to an embodiment of the present invention. The power device 50 having a double polysilicon gate comprises: a substrate 51, a well region 51a, a gate oxide region 52a, a first polysilicon gate region 53a, a resurf region 54, an enhanced drift region 55, a liner oxide region 56a, a field plate region 57b, a second polysilicon gate region 58a, a gate spacer region 59, a body region 60, a source 61, and a drain 62. This embodiment is similar to the Figure 2A-2J The embodiment is similar to that of Figure 3D and Figure 3E As shown, after forming the liner oxide layer 56, the liner oxide layer 56 is etched by, for example, an anisotropic etching process step to form a spacer oxide region 56a, wherein the spacer oxide region 56a covers the sidewalls of the field plate trench 57a but does not cover the bottom of the field plate trench 57a. Figure 3F As shown, after forming the spacer oxide region 56a, the field plate region 57b is formed by, for example, a deposition process step and, for example, a chemical mechanical polishing step. In this embodiment, the gate oxide layer 52, the first polysilicon gate layer 53, the liner oxide layer 56, the first photoresist layer 57', the field plate trench 57a, the second polysilicon gate layer 58, and the extension region 61a are described in detail in FIG. Figure 2A-2J In the embodiment of the present invention, the gate oxide layer 32, the first polysilicon gate layer 33, the liner oxide layer 36, the first photoresist layer 37', the field plate trench 37a, the second polysilicon gate layer 38, and the extension region 41a are described.
[0060] Figures 4A-4I FIG1 is a cross-sectional view showing a method for manufacturing a power device 70 having a double polysilicon gate according to an embodiment of the present invention. The power device 70 having a double polysilicon gate comprises a substrate 71, a well region 71a, a gate oxide region 72a, a first polysilicon gate region 73a, a resurf region 74, an enhanced drift region 75, a liner oxide region 76a, a field plate region 77b, a second polysilicon gate region 78a, a gate spacer region 79, a body region 80, a source 81, and a drain 82. This embodiment is similar to FIG1. Figures 3A-3H The embodiment is different in that Figure 4C and Figure 4DAs shown, the step of etching the first polysilicon gate layer 73 using the first photoresist layer 77' as a shield to form the field plate trench 77a is performed before the step of implanting a plurality of first conductivity type impurities into the substrate 71 using the first photoresist layer 77' as a shield to form the RESURF region 74 and the step of implanting a plurality of second conductivity type impurities into the substrate 71 using the first photoresist layer 77' as a shield to form the enhanced drift region 75. In this embodiment, for a description of the gate oxide layer 72, the first polysilicon gate layer 73, the liner oxide layer 76, the first photoresist layer 77', the field plate trench 77a, the second polysilicon gate layer 78, and the extension region 81a, please refer to FIG. Figure 2A-2J In the embodiment of the present invention, the gate oxide layer 32, the first polysilicon gate layer 33, the liner oxide layer 36, the first photoresist layer 37', the field plate trench 37a, the second polysilicon gate layer 38, and the extension region 41a are described.
[0061] Figure 5A-5G FIG1 is a cross-sectional view showing a method for manufacturing a power device 90 having a double polysilicon gate according to an embodiment of the present invention. The power device 90 having a double polysilicon gate comprises a substrate 91, a well region 91a, a gate oxide region 92a, a first polysilicon gate region 93a, a resurf region 94, an enhanced drift region 95, a field plate region 97b, a second polysilicon gate region 98a, a gate spacer region 99, a body region 100, a source 101, and a drain 102. This embodiment is similar to the Figure 2A-Figure 2I The embodiment is similar to the embodiment of Figure 5D As shown, oxygen ions are implanted into the first polysilicon gate layer 93 by using the first photoresist layer 97' as a shield, for example, by an oxygen ion implantation process step, to form a field plate region 97b. In this embodiment, no liner oxide region is required. In this embodiment, for descriptions of the gate oxide layer 92, the first polysilicon gate layer 93, the first photoresist layer 97', the field plate trench 97a, the second polysilicon gate layer 98, and the extension region 101a, please refer to FIG. Figure 2A-2J In the embodiment of the present invention, the gate oxide layer 32, the first polysilicon gate layer 33, the liner oxide layer 36, the first photoresist layer 37', the field plate trench 37a, the second polysilicon gate layer 38, and the extension region 41a are described.
[0062] In summary, the present invention can precisely control the profile and thickness of the field plate region, and since the field plate region does not need to be etched, there will be no oxide damage and purity issues.
[0063] The present invention has been described above with respect to the preferred embodiments, but the above is only to make it easier for those skilled in the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. For example, other process steps or structures, such as lightly doped drain regions, etc., can be added without affecting the main characteristics of the component; for example, lithography technology is not limited to mask technology, but may also include electron beam lithography technology. All of these can be derived by analogy based on the teachings of the present invention. In addition, the various embodiments described are not limited to individual applications, but may also be applied in combination, such as but not limited to the use of two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any embodiment of the present invention does not necessarily achieve all purposes or advantages, and therefore, any claim should not be limited to this.
Claims
1. A method for manufacturing a power device having a double polysilicon gate, comprising: forming a well region in a substrate; forming a gate oxide layer directly connected to and completely covering the substrate; forming a first polysilicon gate layer directly connected to and completely covering the gate oxide layer; forming a first photoresist layer on the first polysilicon gate layer by a first lithography process step to simultaneously define a resurf region, an enhanced drift region, and a field plate trench; Using the first photoresist layer as a shield, etching the first polysilicon gate layer to form the field plate trench; Using the first photoresist layer as a shield, a plurality of first conductive type impurities are implanted into the substrate to form the resurf region; Using the first photoresist layer as a shield, a plurality of second conductive type impurities are implanted into the substrate to form the enhanced drift region, wherein the plurality of first conductive type impurities have opposite electrical properties to the plurality of second conductive type impurities; forming a field plate region in the field plate trench by a self-aligned process step; forming a second polysilicon gate layer directly connected to and completely covering the first polysilicon gate layer and the field plate region; and Etching the first polysilicon gate layer and the second polysilicon gate layer to form a first polysilicon gate region and a second polysilicon gate region, thereby forming the double polysilicon gate; A portion of the second polysilicon gate region is directly connected to and completely covers the first polysilicon gate region, and another portion of the second polysilicon gate region is directly connected to and covers a portion of the field plate region.
2. The method for manufacturing a power device having a double polysilicon gate according to claim 1, wherein: The step of etching the first polysilicon gate layer through the first photoresist layer as a shield to form the field plate groove is before the step of injecting multiple first conductive type impurities into the substrate using the first photoresist layer as a shield to form the reduced surface electric field region and the step of injecting multiple second conductive type impurities into the substrate using the first photoresist layer as a shield to form the enhanced drift region.
3. The method for manufacturing a power device having a double polysilicon gate according to claim 1, wherein: The step of etching the first polysilicon gate layer through the first photoresist layer as a shield to form the field plate groove is followed by the step of injecting multiple first conductive type impurities into the substrate using the first photoresist layer as a shield to form the reduced surface electric field region and the step of injecting multiple second conductive type impurities into the substrate using the first photoresist layer as a shield to form the enhanced drift region.
4. The method for manufacturing a power device having a double polysilicon gate according to claim 1, wherein: The method further comprises: forming a liner oxide layer by a deposition process step after forming the field plate trench, wherein the liner oxide layer completely covers the field plate trench.
5. The method for manufacturing a power device having a double polysilicon gate according to claim 4, wherein: After forming the liner oxide layer, a deposition process step and a chemical mechanical polishing step are performed to form a liner oxide region and the field plate region, wherein the liner oxide region completely covers the field plate trench.
6. The method for manufacturing a power device having a double polysilicon gate according to claim 4, wherein: After forming the liner oxide layer, an anisotropic etching process is used to etch the liner oxide layer to form a spacer oxide region, wherein the spacer oxide region covers a plurality of sidewalls of the field plate trench but does not cover a bottom of the field plate trench.
7. The method for manufacturing a power device having a double polysilicon gate according to claim 1, wherein: The field plate region includes a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and / or a high dielectric layer.
8. The method for manufacturing a power device having a double polysilicon gate according to claim 1, wherein: Also includes: forming a body region in the substrate, wherein a portion of the body region is directly below a portion of the first polysilicon gate region; and A source and a drain are formed in the substrate below both sides of the double polysilicon gate, wherein the source is located in the body region.
9. A method for manufacturing a power device having a double polysilicon gate, comprising: forming a well region in a substrate; forming a gate oxide layer directly connected to and completely covering the substrate; forming a first polysilicon gate layer directly connected to and completely covering the gate oxide layer; forming a first photoresist layer on the first polysilicon gate layer by a first lithography process step to simultaneously define a resurf region, an enhanced drift region and a field plate trench; Using the first photoresist layer as a shield, a plurality of first conductive type impurities are implanted into the substrate to form the resurf region; Using the first photoresist layer as a shield, a plurality of second conductive type impurities are implanted into the substrate to form the enhanced drift region, wherein the plurality of first conductive type impurities have opposite electrical properties to the plurality of second conductive type impurities; Using the first photoresist layer as a shield, oxygen ions are implanted into the first polysilicon gate layer in an oxygen ion implantation process to form the field plate region; forming a second polysilicon gate layer directly connected to and completely covering the first polysilicon gate layer and the field plate region; and Etching the first polysilicon gate layer and the second polysilicon gate layer to form a first polysilicon gate region and a second polysilicon gate region, thereby forming the double polysilicon gate; A portion of the second polysilicon gate region is directly connected to and completely covers the first polysilicon gate region, and another portion of the second polysilicon gate region is directly connected to and covers a portion of the field plate region.
10. The method for manufacturing a power device having a double polysilicon gate according to claim 9, wherein: Also includes: forming a body region in the substrate, wherein a portion of the body region is directly below a portion of the first polysilicon gate region; and A source and a drain are formed in the substrate below both sides of the double polysilicon gate, wherein the source is located in the body region.