Integrated circuit structure with cut metal gate with dielectric plug

Abstract

An integrated circuit structure having a cut metal gate with a dielectric plug. An integrated circuit structure includes a fin or a plurality of horizontally stacked nanowires over a shallow trench isolation (STI) structure. A layer of gate dielectric material is over the fin or the plurality of horizontally stacked nanowires and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced from the fin or the plurality of horizontally stacked nanowires, the dielectric gate plug comprising a dielectric liner comprising silicon and oxygen and a dielectric fill comprising silicon and oxygen with a seam therebetween. The gate dielectric material layer and the conductive gate layer are not along a side of the dielectric gate plug, and the conductive gate fill material is in contact with the side of the dielectric gate plug.

Description

Background Art

[0001] Over the past few decades, feature scaling in integrated circuits has been the driving force behind the continued growth of the semiconductor industry. Scaling to smaller and smaller features has enabled the density of functional units to be increased within the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increasing number of memory or logic devices on a chip, leading to the manufacture of products with increased capacity. However, the drive for ever-increasing capacity is not without its challenges. The need to optimize the performance of each device has become increasingly important.

[0002] In the manufacture of integrated circuit devices, as device sizes continue to shrink, multi-gate transistors (such as tri-gate transistors) have become more common. In conventional processes, tri-gate transistors are generally manufactured on bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complex tri-gate manufacturing process. On the other hand, when microelectronic device sizes are scaled to below the 10 nanometer (nm) node, maintaining improved mobility and short channel control presents a challenge in device manufacturing. Nanowires used to manufacture devices provide improved short channel control.

[0003] However, scaling multi-gate and nanowire transistors is not without consequences. As the dimensions of these fundamental building blocks of microelectronic circuits decrease, and as the sheer number of these building blocks that can be fabricated in a given area increases, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there can be a trade-off between the minimum size (critical dimension) of a feature patterned in a semiconductor stack and the spacing between such features. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A A cross-sectional view of an integrated circuit structure with fins and a metal-first gate dielectric plug is illustrated.

[0005] Figure 1B A cross-sectional view of an integrated circuit structure with fins and cut metal gate dielectric plugs according to an embodiment of the present disclosure is illustrated.

[0006] Figure 2A A cross-sectional view of an integrated circuit structure with fins and a metal-first gate dielectric plug is illustrated.

[0007] Figure 2B A cross-sectional view of an integrated circuit structure with fins and cut metal gate dielectric plugs according to an embodiment of the present disclosure is illustrated.

[0008] Figure 3AA cross-sectional view of an integrated circuit structure with nanowires and metal-front gate dielectric plugs is illustrated.

[0009] Figure 3B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs according to an embodiment of the present disclosure is illustrated.

[0010] Figure 4A A cross-sectional view of an integrated circuit structure with nanowires and metal-front gate dielectric plugs is illustrated.

[0011] Figure 4B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs according to an embodiment of the present disclosure is illustrated.

[0012] Figures 5A-5C Illustrated is a plan view of a comparative integrated circuit structure according to an embodiment of the present disclosure.

[0013] Figures 6A-6C Illustrated are cross-sectional views of comparative integrated circuit structures according to embodiments of the present disclosure.

[0014] Figures 7A-7J Illustrated are cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0015] Figure 8 A cross-sectional view of a non-planar integrated circuit structure as taken along a gate line according to an embodiment of the present disclosure is illustrated.

[0016] Figure 9 Illustrated are cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) and a self-aligned gate endcap (SAGE) architecture (right-hand side (b)) according to embodiments of the present disclosure.

[0017] Figure 10 Illustrated are cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure having a gate-all-around device, in accordance with an embodiment of the present disclosure.

[0018] Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is illustrated.

[0019] Figure 11B FIGURE 1 shows a diagram of a plane according to an embodiment of the present disclosure as taken along the a-a' axis. Figure 11A A cross-sectional view of a source or drain electrode of a nanowire-based integrated circuit structure.

[0020] Figure 11CFIG2 shows a diagram of a vehicle according to an embodiment of the present disclosure as taken along the bb' axis. Figure 11A Cross-sectional view of the channel of a nanowire-based integrated circuit structure.

[0021] Figure 12 A computing device according to one implementation of an embodiment of the present disclosure is illustrated.

[0022] Figure 13 An interposer including one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0023] An integrated circuit structure having a cut metal gate with a dielectric plug, and a method of manufacturing an integrated circuit structure having a cut metal gate with a dielectric plug are described. In the following description, numerous specific details are set forth, such as particular integration and material regimes, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be appreciated that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0024] Certain terms may also be used in the following description for reference purposes only and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the accompanying drawings to which they are referenced. Terms such as "front," "back," "rear," and "side" describe the orientation and / or position of parts of a component within a consistent but arbitrary reference frame, as made clear by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0025] The embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0026] The embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., (one or more) metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. During the BEOL portion of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in the BEOL.

[0027] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although exemplary processing schemes may be described using FEOL processing scenarios, such methods may also be applicable to BEOL processing. Similarly, although exemplary processing schemes may be described using BEOL processing scenarios, such methods may also be applicable to FEOL processing.

[0028] One or more embodiments described herein are directed to integrated circuit structures having cut work function metal for gate end-to-end isolation. One or more embodiments described herein are directed to FinFET structures having cut work function metal for gate end-to-end isolation. One or more embodiments described herein are directed to all-around gate devices having cut work function metal for gate end-to-end isolation. It should be understood that references to nanowires herein may refer to nanowires or nanoribbons unless otherwise indicated. One or more embodiments described herein are directed to improving yield by shielding transistor sources and drains.

[0029] To provide context, to reduce cell height in future or scaled technology nodes, both the gate endcap and gate cut sizes need to be scaled down. Performing gate cuts before gate metal fill can limit the effective endcap available for the work function and can make metal fill in tighter spaces challenging. This defect can be exacerbated by any gate end-to-end misalignment that creates even smaller endcap spaces.

[0030] According to one or more embodiments of the present disclosure that solve the above-mentioned problems, a metal gate cutting process is implemented after the gate dielectric and work function metal deposition and patterning are completed.

[0031] Advantages for implementing the methods described herein may include a so-called "plug last" approach, with the result that a gate dielectric layer (such as a high-k gate dielectric layer) is not deposited on the gate plug sidewalls, effectively saving additional space for work function metal deposition. In contrast, during the so-called conventional "plug first" approach, the metal gate fill material may be sandwiched between the plug and the fin. Due to plug misalignment in the latter approach, the space for metal fill may be narrower and may result in voids during metal fill. In the embodiments described herein, using the "plug last" approach, the work function metal deposition can be seamless (e.g., void-free).

[0032] According to one or more embodiments of the present disclosure, an integrated circuit structure has an interface between a gate plug dielectric and a gate metal. It should be appreciated that many embodiments can benefit from the methods described herein, such as the plug-last method. For example, the following relates Figure 1B and Figure 2B Describes metal gate cutting on FinFET devices. The metal gate cutting scheme can be implemented for gate-all-around (GAA) devices, such as the following related Figure 3B and Figure 4B Furthermore, the metal gate cut and plug formation may look different based on the structure introduced. For example, the plug may fall on a shallow trench isolation (STI) structure, such as the associated Figure 1A 、 Figure 2B and Figure 3B described, or may fall on a prefabricated gate wall made of dielectric, such as associated Figure 4B The metal gate cutting method described can be selective to the gate spacer dielectric, such as the associated Figure 5B and Figure 6B described, or may have no selectivity for gate spacer materials, such as associated Figure 5C and Figure 6C Non-selective metal gate cut embodiments may require alternative contact metal schemes to accommodate the dielectric plug between the epitaxial source / drain. Plug etch selectivity to the epitaxial source / drain material is optional. However, in one embodiment, if the epitaxial source / drain is exposed to the plug etch (e.g., due to device dimensions), the etch can anisotropically trim the source / drain, such as in the following example. Figure 5C Such an approach can be implemented to achieve close end cap spacing.

[0033] To provide further background, source and drain (S / D) are key elements of any transistor device, and their health and function basically determine device performance. After forming source and drain on the PMOS and NMOS sides of transistor, device undergoes many operations (particularly physical and chemical treatments), which may erode and damage source and drain, for example, remove and etch them away, which in turn will cause open circuit or at least resistance increase. This may be a very common defect mode in chip manufacturing process. Many efforts have been made to protect S / D from being etched away, such as improving S / D materials and formation technology, adopting various ashing and cleaning hardware and platforms as key factors, process optimization, etc. that damage S / D. However, these methods hardly all solve the S / D etching away problem, and more importantly, they add extra operations to the chip manufacturing integrated process, therefore adding extra cost.

[0034] According to one or more embodiments of the present disclosure, a method for protecting S / Ds is implemented that reduces manufacturing costs by potentially reducing the amount of cleaning required to remove dry-etch polymer, shortening the dry-etch process time, and not requiring any specialized hardware. In one embodiment, a low-cost and straightforward method is implemented to protect S / Ds by stabilizing desired etch byproducts and removing undesirable etch byproducts in situ during the metal gate cutting MGC main etch. In one embodiment, the MGC etch process involves several in-situ ashing operations to stabilize the desired byproducts and remove undesirable byproducts. In one embodiment, the remaining byproducts are primarily silicon oxide, which may include negligible amounts of carbon, boron, and halogen elements. These byproducts may be oxide-based and may promote oxide gap fill within the plug and improve device performance. Therefore, in one embodiment, a dielectric plug for cutting a metal gate includes a dielectric liner comprising silicon and oxygen (and possibly carbon, boron, and halogen elements) and a dielectric fill comprising silicon and oxygen and / or nitrogen. In one such embodiment, a seam is detectable between the dielectric liner and the dielectric fill.

[0035] In a first aspect, a dielectric gate plug is fabricated for a FinFET device. As a comparative example, Figure 1A A cross-sectional view of an integrated circuit structure with fins and a metal-first gate dielectric plug is illustrated. Figure 1B A cross-sectional view of an integrated circuit structure with fins and cut metal gate dielectric plugs according to an embodiment of the present disclosure is illustrated.

[0036] refer to Figure 1A, the integrated circuit structure 100 includes a fin 102 having a portion protruding above a shallow trench isolation (STI) structure 104. A gate dielectric material layer 106 (such as a high-k gate dielectric layer) is above the protruding portion of the fin 102 and above the STI structure 104. It should be appreciated that, although not depicted, an oxidized portion of the fin 102 may be between the protruding portion of the fin 102 and the gate dielectric material layer 106 and may be included with the gate dielectric material layer 106 to form a gate dielectric structure. A conductive gate layer 108 (such as a work function metal layer) is above the gate dielectric material layer 106 and may be directly on the gate dielectric material layer 106, as depicted. A conductive gate fill material 110 is above the conductive gate layer 108 and may be directly on the conductive gate layer 108, as depicted. A dielectric gate cap 112 is on the conductive gate fill material 110. The dielectric gate plug 114 is laterally spaced apart from the fin 102 and is on the STI structure 104. The gate dielectric material layer 106 and the conductive gate layer 108 are along the sides of the dielectric gate plug 114. As a result, the region 116 between the dielectric gate plug 114 and the fin 102 effectively includes two layers of gate dielectric material 106 and two layers of conductive gate layer 108 in the already compact area of ​​the structure 100.

[0037] Furthermore, in addition to the gate dielectric and metal fill, patterning for different VT devices (e.g., different metal thicknesses, dipoles, etc.) can become challenging when the space in region 116 is relatively small. For example, if etching is used to expose and remove material from one VT while protecting another VT, etching may be hindered if the space in region 116 is relatively small. As such, there may also be patterning implications beyond the metal fill itself.

[0038] and Figure 1A Compared with reference Figure 1B , the integrated circuit structure 150 includes a fin 152 having a portion protruding above a shallow trench isolation (STI) structure 154. A gate dielectric material layer 156 (such as a high-k gate dielectric layer) is above the protruding portion of the fin 152 and above the STI structure 154. It should be appreciated that, although not depicted, the oxidized portion of the fin 152 may be between the protruding portion of the fin 152 and the gate dielectric material layer 156 and may be included with the gate dielectric material layer 156 to form a gate dielectric structure. A conductive gate layer 158 (such as a work function metal layer) is above the gate dielectric material layer 156 and may be directly on the gate dielectric material layer 156, as depicted. A conductive gate fill material 160 is above the conductive gate layer 158 and may be directly on the conductive gate layer 158, as depicted. A dielectric gate cap 162 is on the conductive gate fill material 160.

[0039] In one embodiment, the dielectric gate plug 164 is laterally spaced from the fin 152 and is on the STI structure 154 but not through the STI structure 154. As used throughout this disclosure, a dielectric plug referred to as "on the STI structure but not through the STI structure" can refer to a dielectric plug that lands on the top or uppermost surface of the STI, or can refer to a plug that extends into the STI but does not penetrate the STI, for example, as depicted by region 164C. In other embodiments, the plugs described herein can extend completely through or penetrate the STI. According to an embodiment of the present disclosure, the dielectric gate plug 164 includes a dielectric liner 164B comprising silicon and oxygen (and possibly Cl, F, and / or B) and a dielectric fill 164A comprising silicon and oxygen. In one such embodiment, as depicted, a seam is detectable between the dielectric liner 164B and the dielectric fill 164A. In one embodiment, the dielectric liner 164B portion of the dielectric gate plug 164 is formed during a metal gate cut etch process, such as described above.

[0040] In one embodiment, the gate dielectric material layer 156 and the conductive gate layer 158 do not extend along the sides of the dielectric gate plug 164. Instead, the conductive gate fill material 160 contacts the sides of the dielectric gate plug 164. As a result, the area between the dielectric gate plug 164 and the fin 152 includes only one layer of the gate dielectric material layer 156 and only one layer of the conductive gate layer 158, thereby easing spatial constraints in such a compact area of ​​the structure 150. Easing spatial constraints can improve metal fill and / or can facilitate patterning of multiple VTs.

[0041] Reference again Figure 1B In one embodiment, dielectric gate plug 164 is formed after forming gate dielectric material layer 156, conductive gate layer 158, and conductive gate fill material 160. As a result, gate dielectric material layer 156 and conductive gate layer 158 are not formed along the sides of dielectric gate plug 164. In one embodiment, as depicted, dielectric gate plug 164 has an uppermost surface that is coplanar with an uppermost surface of dielectric gate cap 162. In another embodiment, not depicted, dielectric gate cap 162 is not included, and dielectric gate plug 164 has an uppermost surface that is coplanar (e.g., along plane 180) with an uppermost surface of conductive gate fill material 160.

[0042] In a second aspect, a misaligned dielectric gate plug is fabricated for a FinFET device. As a comparative example, Figure 2A A cross-sectional view of an integrated circuit structure with fins and a metal-first gate dielectric plug is illustrated. Figure 2BA cross-sectional view of an integrated circuit structure with fins and cut metal gate dielectric plugs according to an embodiment of the present disclosure is illustrated.

[0043] refer to Figure 2A , the integrated circuit structure 200 includes a fin 202 having a portion protruding above a shallow trench isolation (STI) structure 204. A gate dielectric material layer 206 (such as a high-k gate dielectric layer) is above the protruding portion of the fin 202 and above the STI structure 204. It should be appreciated that, although not depicted, an oxidized portion of the fin 202 may be between the protruding portion of the fin 202 and the gate dielectric material layer 206 and may be included with the gate dielectric material layer 206 to form a gate dielectric structure. A conductive gate layer 208 (such as a work function metal layer) is above the gate dielectric material layer 206 and may be directly on the gate dielectric material layer 206, as depicted. A conductive gate fill material 210 is above the conductive gate layer 208 and may be directly on the conductive gate layer 208, as depicted. A dielectric gate cap 212 is on the conductive gate fill material 210. The dielectric gate plug 214 is laterally spaced apart from the fin 202 and is on the STI structure 204. The gate dielectric material layer 206 and the conductive gate layer 208 are along the sides of the dielectric gate plug 214. However, when the dielectric gate plug 214 is misaligned (e.g., Figure 1A In the case where the dielectric gate plug 214 is spaced closer to the fin 202 than in the comparative example of FIG. 5 , a void 216 may be disadvantageously formed in the region between the dielectric gate plug 214 and the fin 202 .

[0044] and Figure 2A Compared with reference Figure 2B, the integrated circuit structure 250 includes a fin 252 having a portion protruding above a shallow trench isolation (STI) structure 254. A gate dielectric material layer 256 (such as a high-k gate dielectric layer) is above the protruding portion of the fin 252 and above the STI structure 254. It should be appreciated that, although not depicted, the oxidized portion of the fin 252 may be between the protruding portion of the fin 252 and the gate dielectric material layer 256 and may be included with the gate dielectric material layer 256 to form a gate dielectric structure. A conductive gate layer 258 (such as a work function metal layer) is above the gate dielectric material layer 256 and may be directly on the gate dielectric material layer 256, as depicted. A conductive gate fill material 260 is above the conductive gate layer 258 and may be directly on the conductive gate layer 258, as depicted. A dielectric gate cap 262 is on the conductive gate fill material 260. The dielectric gate plug 264 is laterally spaced from the fin 252 and is on the STI structure 254 but not through the STI structure 254. As used throughout this disclosure, a dielectric plug referred to as "on the STI structure but not through the STI structure" can refer to a dielectric plug that lands on the top or uppermost surface of the STI, or can refer to a plug that extends into the STI but does not penetrate the STI, for example, as depicted by region 264C. In other embodiments, the plugs described herein can extend completely through or through the STI. However, the gate dielectric material layer 256 and the conductive gate layer 258 do not follow the sides of the dielectric gate plug 264. Instead, the conductive gate fill material 260 contacts the sides of the dielectric gate plug 264. As a result, even if the dielectric gate plug 264 is misaligned (e.g., with Figure 1B In the case where the dielectric gate plug 264 is spaced closer to the fin 252 than in the comparative example of FIG. 2 , a void is not formed in the region between the dielectric gate plug 264 and the fin 252. According to an embodiment of the present disclosure, the dielectric gate plug 164 includes a dielectric liner 264B including silicon and oxygen (and possibly carbon, boron, and halogen elements) and a dielectric fill 264A including silicon and oxygen and / or nitrogen. In one such embodiment, as depicted, a seam is detectable between the dielectric liner 264B and the dielectric fill 264A. In one embodiment, the dielectric liner 264B portion of the dielectric gate plug 264 is formed during a metal gate cut etch process, such as described above.

[0045] Reference again Figure 2BIn one embodiment, dielectric gate plug 264 is formed after forming gate dielectric material layer 256, conductive gate layer 258, and conductive gate fill material 260. As a result, gate dielectric material layer 256 and conductive gate layer 258 are not formed along the sides of dielectric gate plug 264. In one embodiment, as depicted, dielectric gate plug 264 has an uppermost surface that is coplanar with an uppermost surface of dielectric gate cap 262. In another embodiment, not depicted, dielectric gate cap 262 is not included, and dielectric gate plug 264 has an uppermost surface that is coplanar (e.g., along plane 280) with an uppermost surface of conductive gate fill material 260.

[0046] In a third aspect, a dielectric gate plug is fabricated for a nanowire device. As a comparative example, Figure 3A A cross-sectional view of an integrated circuit structure with nanowires and metal-front gate dielectric plugs is illustrated. Figure 3B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs according to an embodiment of the present disclosure is illustrated.

[0047] refer to Figure 3A , the integrated circuit structure 300 includes a sub-fin 302 having a portion protruding above a shallow trench isolation (STI) structure 304. A plurality of horizontally stacked nanowires 305 are above the sub-fin 302. A gate dielectric material layer 306, such as a high-k gate dielectric layer, is above the protruding portion of the sub-fin 302, above the STI structure 304, and surrounding the horizontally stacked nanowires 305. It should be appreciated that, although not depicted, the oxidized portion of the sub-fin 302 and the horizontally stacked nanowires 305 can be between the protruding portion of the sub-fin 302 and the gate dielectric material layer 306, as well as between the horizontally stacked nanowires 305 and the gate dielectric material layer 306, and can be included with the gate dielectric material layer 306 to form a gate dielectric structure. A conductive gate layer 308, such as a work function metal layer, is above the gate dielectric material layer 306 and can be directly on the gate dielectric material layer 306, as depicted. Conductive gate fill material 310 is above, and may be directly on, the conductive gate layer 308, as depicted. A dielectric gate cap 312 is on the conductive gate fill material 310. A dielectric gate plug 314 is laterally spaced apart from the sub-fin 302 and the plurality of horizontally stacked nanowires 305 and is on the STI structure 304. A gate dielectric material layer 306 and a conductive gate layer 308 flank the dielectric gate plug 314. As a result, a region 316 between the dielectric gate plug 314 and the combination of the sub-fin 302 and the plurality of horizontally stacked nanowires 305 effectively includes two layers of gate dielectric material 306 and two layers of conductive gate layer 308 within the already compact area of ​​the structure 300.

[0048] contrast Figure 3A ,refer to Figure 3B , the integrated circuit structure 350 includes a sub-fin 352 having a portion protruding above a shallow trench isolation (STI) structure 354. A plurality of horizontally stacked nanowires 355 are above the sub-fin 352. A gate dielectric material layer 356, such as a high-k gate dielectric layer, is above the protruding portion of the sub-fin 352, above the STI structure 354, and around the horizontally stacked nanowires 355. It should be appreciated that, although not depicted, the oxidized portion of the sub-fin 352 can be between the protruding portion of the sub-fin 352 and the gate dielectric material layer 356, as well as between the horizontally stacked nanowires 355 and the gate dielectric material layer 356, and can be included with the gate dielectric material layer 356 to form a gate dielectric structure. A conductive gate layer 358, such as a work function metal layer, is above the gate dielectric material layer 356 and can be directly on the gate dielectric material layer 356, as depicted. A conductive gate fill material 360 is above the conductive gate layer 358 and may be directly on the conductive gate layer 358, as depicted. A dielectric gate cap 362 is on the conductive gate fill material 360. A dielectric gate plug 364 is laterally spaced apart from the sub-fins 352 and the plurality of horizontally stacked nanowires 355 and is on, but not through, the STI structure 354. As used throughout this disclosure, a dielectric plug referred to as "on, but not through, the STI structure" may refer to a dielectric plug that lands on the top or uppermost surface of the STI, or may refer to a plug that extends into, but does not penetrate, the STI, for example, as depicted by region 364C. In other embodiments, the plugs described herein may extend completely through or penetrate the STI. However, the gate dielectric material layer 356 and the conductive gate layer 358 do not extend along the sides of the dielectric gate plug 364. Instead, the conductive gate fill material 360 contacts the sides of the dielectric gate plug 364. As a result, the area between the dielectric gate plug 364 and the combination of the sub-fin 352 and the plurality of horizontally stacked nanowires 355 includes only one layer of gate dielectric material 356 and only one layer of conductive gate layer 358, thereby easing spatial constraints in such a compact area of ​​the structure 350. According to an embodiment of the present disclosure, the dielectric gate plug 364 includes a dielectric liner 364B comprising silicon and oxygen (and possibly carbon, boron, and halogen elements) and a dielectric fill 364A comprising silicon and oxygen and / or nitrogen. In one such embodiment, as depicted, a seam is detectable between the dielectric liner 364B and the dielectric fill 364A. In one embodiment, the dielectric liner 364B portion of the dielectric gate plug 364 is formed during a metal gate cut etch process, such as described above.

[0049] Reference again Figure 3B In one embodiment, dielectric gate plug 364 is formed after forming gate dielectric material layer 356, conductive gate layer 358, and conductive gate fill material 360. As a result, gate dielectric material layer 356 and conductive gate layer 358 are not formed along the sides of dielectric gate plug 364. In one embodiment, as depicted, dielectric gate plug 364 has an uppermost surface that is coplanar with an uppermost surface of dielectric gate cap 362. In another embodiment, not depicted, dielectric gate cap 362 is not included, and dielectric gate plug 364 has an uppermost surface that is coplanar (e.g., along plane 380) with an uppermost surface of conductive gate fill material 360.

[0050] In a fourth aspect, a dielectric gate plug is fabricated on a gate end cap wall for a nanowire device. As a comparative example, Figure 4A A cross-sectional view of an integrated circuit structure with nanowires and metal-front gate dielectric plugs is illustrated. Figure 4B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs according to an embodiment of the present disclosure is illustrated.

[0051] refer to Figure 4A, the integrated circuit structure 400 includes a sub-fin 402 having a portion protruding above a shallow trench isolation (STI) structure 404. A plurality of horizontally stacked nanowires 405 are above the sub-fin 402. A gate endcap structure 403, such as a self-aligned gate endcap structure, is on the STI structure 404 and is laterally spaced apart from the sub-fin 402 and the plurality of horizontally stacked nanowires 405. A gate dielectric material layer 406, such as a high-k gate dielectric layer, is above the protruding portion of the sub-fin 402, above the STI structure 404, along the sides of the gate endcap structure 403, and around the horizontally stacked nanowires 405. It should be understood that, although not depicted, the oxidized portion of the sub-fin 402 and the horizontally stacked nanowires 405 can be between the protruding portion of the sub-fin 402 and the gate dielectric material layer 406, as well as between the horizontally stacked nanowires 405 and the gate dielectric material layer 406, and can be included together with the gate dielectric material layer 406 to form a gate dielectric structure. A conductive gate layer 408 (such as a work function metal layer) is above the gate dielectric material layer 406 and can be directly on the gate dielectric material layer 406, as depicted. A conductive gate fill material 410 is above the conductive gate layer 408 and can be directly on the conductive gate layer 408, as depicted. A dielectric gate cap 412 is on the conductive gate fill material 410. A dielectric gate plug 414 is on the gate end cap structure 403. The gate dielectric material layer 406 and the conductive gate layer 408 are along the sides of the dielectric gate plug 414.

[0052] and Figure 4A Compared with reference Figure 4B, the integrated circuit structure 450 includes a sub-fin 452 having a portion protruding above a shallow trench isolation (STI) structure 454. A plurality of horizontally stacked nanowires 455 are above the sub-fin 452. A gate endcap structure 453, such as a self-aligned gate endcap structure, is on the STI structure 454 but does not pass through the STI structure 454 and is laterally spaced apart from the sub-fin 452 and the plurality of horizontally stacked nanowires 455. As used throughout this disclosure, a gate endcap structure referred to as "on the STI structure but not through the STI structure" may refer to a gate endcap structure that falls on the top or uppermost surface of the STI, or may refer to a gate endcap structure that extends into the STI but does not penetrate the STI. In other embodiments, the gate endcap structures described herein may extend completely through or penetrate the STI. A gate dielectric material layer 456, such as a high-k gate dielectric layer, is positioned over the protruding portions of the sub-fins 452, over the STI structures 454, along the sides of the gate end cap structures 453, and around the horizontally stacked nanowires 455. It should be appreciated that, although not depicted, the oxidized portions of the sub-fins 452 may be between the protruding portions of the sub-fins 452 and the gate dielectric material layer 456, as well as between the horizontally stacked nanowires 455 and the gate dielectric material layer 456, and may be included with the gate dielectric material layer 456 to form a gate dielectric structure. A conductive gate layer 458, such as a work function metal layer, is positioned over the gate dielectric material layer 456 and may be directly on the gate dielectric material layer 456, as depicted. A conductive gate fill material 460 is positioned over the conductive gate layer 458 and may be directly on the conductive gate layer 458, as depicted. A dielectric gate cap 462 is positioned over the conductive gate fill material 460. The dielectric gate plug 464 is on the gate endcap structure 453 but does not pass through the gate endcap structure 453. As used throughout this disclosure, a dielectric plug referred to as "on the gate endcap structure but not through the gate endcap structure" can refer to a dielectric plug that rests on the top or uppermost surface of the gate endcap structure, or can refer to a plug that extends into the gate endcap structure but does not penetrate the gate endcap structure, for example, as depicted by region 464C. In other embodiments, the plugs described herein can extend completely through or penetrate the gate endcap structure. The gate dielectric material layer 456 and the conductive gate layer 458 do not follow the sides of the dielectric gate plug 464. Instead, the conductive gate fill material 460 contacts the sides of the dielectric gate plug 464. According to an embodiment of the present disclosure, dielectric gate plug 464 includes a dielectric liner 464B comprising silicon and oxygen (and possibly carbon, boron, and halogen elements) and a dielectric fill 464A comprising silicon and oxygen and / or nitrogen. In one such embodiment, as depicted, a seam is detectable between dielectric liner 464B and dielectric fill 464A.In one embodiment, the dielectric liner 464B portion of the dielectric gate plug 464 is formed during a metal gate cut etch process, such as described above.

[0053] Reference again Figure 4B In one embodiment, dielectric gate plug 464 is formed after forming gate dielectric material layer 456, conductive gate layer 458, and conductive gate fill material 460. As a result, gate dielectric material layer 456 and conductive gate layer 458 are not formed along the sides of dielectric gate plug 464. In one embodiment, as depicted, dielectric gate plug 464 has an uppermost surface that is coplanar with an uppermost surface of dielectric gate cap 462. In another embodiment, not depicted, dielectric gate cap 462 is not included, and dielectric gate plug 464 has an uppermost surface that is coplanar (e.g., along plane 480) with an uppermost surface of conductive gate fill material 460.

[0054] In the fifth aspect, selective or non-selective variations of metal gate cutting can be implemented. As an example, Figures 5A-5C Illustrated is a plan view of a comparative integrated circuit structure according to an embodiment of the present disclosure. Figure 5A represents the conventional "plug first" approach, illustrating two gate plugs in adjacent gates. Figure 5B Figure 2 represents a selective metal gate cutting method, which illustrates two gate plugs in adjacent gates. Figure 5C Represents a non-selective metal gate cutting method, which illustrates a long gate plug spanning multiple gates.

[0055] refer to Figure 5A , the integrated circuit structure 500 includes gate lines between dielectric spacers 517 and conductive source or drain contacts 518. Each gate line includes a gate dielectric material layer 506, a conductive gate layer 508 (such as a work function metal layer), and a conductive gate fill material 510. Dielectric gate plugs 514 may be formed to decompose portions of the corresponding gate lines. The dielectric gate plugs 514 are in contact with the conductive gate layer 508, but not with the gate dielectric material layer 506 or the conductive gate fill material 510. Figure 5A The plan view can correspond to Figure 1A 、 Figure 2A 、 Figure 3A or Figure 4A It should be appreciated that although referred to above as a conductive source or drain contact 518 , a placeholder dielectric or dielectric plug replaces the conductive source or drain contact 518 at an earlier stage of the process or elsewhere in the integrated circuit structure.

[0056] refer to Figure 5B, the integrated circuit structure 550 includes gate lines between dielectric spacers 567 and conductive source or drain contacts 568. Each gate line includes a gate dielectric material layer 556, a conductive gate layer 558 (such as a work function metal layer), and a conductive gate fill material 560. Dielectric gate plugs 564 may decompose portions of the corresponding gate lines. Dielectric gate plugs 564 are in contact with the conductive gate fill material 560, the gate dielectric material layer 556, and the conductive gate layer 558. Figure 5B The plan view can correspond to Figure 1B 、 Figure 2B 、 Figure 3B or Figure 4B structure. It should be appreciated that, although referred to above as conductive source or drain contacts 568, placeholder dielectrics or dielectric plugs replace the conductive source or drain contacts 568 at earlier stages of the process or elsewhere in the integrated circuit structure. According to an embodiment of the present disclosure, the dielectric gate plugs 564 each include a dielectric liner 564B comprising silicon and oxygen (and possibly carbon, boron, and halogen elements) and a dielectric fill 564A comprising silicon and oxygen and / or nitrogen. In one such embodiment, as depicted, a seam is detectable between the dielectric liner 564B and the dielectric fill 564A. In one embodiment, the dielectric liner 564B portion of the dielectric gate plug 564 is formed during a metal gate cut etch process, such as described above.

[0057] refer to Figure 5C , the integrated circuit structure 570 includes gate lines between dielectric spacers 587 and conductive source or drain contacts 588. Each gate line includes a gate dielectric material layer 576, a conductive gate layer 578 (such as a work function metal layer), and a conductive gate fill material 580. A single dielectric gate plug 584 can break up portions of the gate line and can extend through the dielectric spacers 587 and even partially or completely into one or more of the conductive source or drain contacts 588. The dielectric gate plug 584 contacts the conductive gate fill material 580, the gate dielectric material layer 576, and the conductive gate layer 578. Figure 5C The plan view can correspond to Figure 1B 、 Figure 2B 、 Figure 3B or Figure 4BAccording to an embodiment of the present disclosure, dielectric gate plug 584 includes a dielectric liner 584B comprising silicon and oxygen (and possibly carbon, boron, and halogen elements) and a dielectric fill 564A comprising silicon and oxygen and / or nitrogen. In one such embodiment, as depicted, a seam is detectable between dielectric liner 584B and dielectric fill 584A. In one embodiment, dielectric liner 584B portion of dielectric gate plug 584 is formed during a metal gate cut etch process, such as described above.

[0058] Reference again Figure 5C It should be understood that, although referred to above as conductive source or drain contacts 588, placeholder dielectrics or dielectric plugs may replace conductive source or drain contacts 588 at earlier stages of the process or elsewhere in the integrated circuit structure. In one embodiment, the etch used to form the opening in which the single dielectric gate plug 584 is ultimately formed is referred to as a non-selective etch. Where conductive source or drain contacts 588 have already been formed, the non-selective etch may etch into the conductive material of the conductive source or drain contacts 588. In other embodiments, where placeholder dielectrics or dielectric plugs replace conductive source or drain contacts 588, the non-selective etch may etch into the placeholder dielectrics or dielectric plugs. In either case, the non-selective etch may etch through and potentially separate the epitaxial semiconductor material of the source or drain regions formed beneath the location of the conductive source or drain contacts 588. Where conductive source or drain contacts 588 have already been formed, the epitaxial semiconductor material of the source or drain regions may include silicided portions.

[0059] Figures 6A-6C Illustrated are cross-sectional views of comparative integrated circuit structures according to embodiments of the present disclosure. Figure 6A Represents the traditional "plug first" approach. Figure 6B Represents the selective metal gate cutting method. Figure 6C Represents the non-selective metal gate cutting method.

[0060] refer to Figure 6A , the integrated circuit structure 600 includes a dielectric gate plug 614 between a dielectric spacer 617 and a conductive source or drain contact 618 . Figure 6A A cross-sectional view may correspond to Figure 1A 、 Figure 2A 、 Figure 3A 、 Figure 4A or Figure 5A Orthogonal view of the structure.

[0061] refer to Figure 6B, the integrated circuit structure 650 includes a dielectric gate plug 664 between a dielectric spacer 667 and a conductive source or drain contact 668 . Figure 6B A cross-sectional view may correspond to Figure 1B 、 Figure 2B 、 Figure 3B 、 Figure 4B or Figure 5B Orthogonal view of the structure.

[0062] refer to Figure 6C , the integrated circuit structure 670 includes a single dielectric gate plug 684 between conductive source or drain contacts 688. The dashed box 690 shows the Figure 6B The dotted box 692 shows the position where the corresponding discrete gate plug (such as gate plug 664) will be aligned. Figure 6B The area between the dotted box 690 and the dotted box 692 shows where the non-recessed source or drain contact 668 will be aligned. Figure 6B In this case the dielectric spacer 667 will be present in position. Figure 6C A cross-sectional view may correspond to Figure 1B 、 Figure 2B 、 Figure 3B 、 Figure 4B or Figure 5C Orthogonal view of the structure.

[0063] In embodiments, the metal work function can be: (a) the same metal system in NMOS and PMOS, (b) different metal systems between NMOS and PMOS, and / or (c) a single material or multiple metal layers (e.g., W, TiN, TiXAlYCz, TaN, Mo, MoN). In one embodiment, the metal cutting etch chemistry includes a chlorine-containing or fluorine-containing etchant, with possible additional carbon-containing or silicon-containing components to provide passivation.

[0064] It should be appreciated that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials including, but not limited to, Si and SiGe. For example, Group III-V materials may be used.

[0065] It will be appreciated that in certain embodiments, the nanowires or nanoribbons or sacrificial intermediate layer may be composed of silicon. As used throughout, a silicon layer may be used to describe a silicon material composed of a very large amount (if not entirely) of silicon. However, it will be appreciated that, in practice, 100% pure silicon may be difficult to form and may therefore include a very small percentage of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during silicon deposition, or may "contaminate" the silicon when diffused during post-deposition processing. As such, embodiments described herein for a silicon layer may include a silicon layer that contains relatively small amounts (e.g., "impurity" levels) of non-silicon atoms or substances (such as Ge, C, or Sn). It will be appreciated that the silicon layer as described herein may be undoped or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0066] It will be appreciated that in certain embodiments, the nanowires or nanoribbons or the sacrificial intermediate layer may be composed of silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material composed of a substantial portion of both silicon and germanium, such as at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, the silicon germanium layer comprises approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer comprises approximately 30% germanium and approximately 70% silicon (Si 70 Ge 30 ). It will be appreciated that, in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form, and therefore may include very small percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may "contaminate" the SiGe when diffused during post-deposition processing. As such, embodiments described herein for silicon germanium layers may include silicon germanium layers that include relatively small amounts (e.g., "impurity" levels) of non-Ge and non-Si atoms or species (such as carbon or tin). It will be appreciated that silicon germanium layers as described herein may be undoped, or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0067] Various devices and processing schemes that can be used to manufacture devices that can be integrated with cut metal gates are described below. It should be appreciated that exemplary embodiments do not necessarily require all of the features described, or may include more features than described. For example, a nanowire release process can be performed by replacing the gate trench. An example of such a release process is described below. Additionally, in yet another aspect, back-end (BE) interconnect scaling can result in lower performance and higher manufacturing costs due to the complexity of patterning. The embodiments described herein can be implemented to achieve front and back-end interconnect integration for nanowire transistors. The embodiments described herein can provide a method for achieving a relatively wide interconnect pitch. The result can improve product performance and reduce patterning costs. The embodiments can be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0068] One or more embodiments described herein are directed bi-epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In one embodiment, an integrated circuit structure is fabricated by forming source-drain openings for a nanowire / nanoribbon transistor, partially filling the openings with SD epitaxy. The remainder of the openings is filled with a conductive material. Deep trenches are formed on one of the source or drain sides to enable direct access to a backside interconnect level.

[0069] As an exemplary process flow for fabricating a gate-all-around device of a gate-all-around integrated circuit structure, Figures 7A-7J Illustrated are cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0070] refer to Figure 7A , a method of fabricating an integrated circuit structure includes forming a starting stack comprising alternating sacrificial layers 704 and nanowires 706 above fins 702 (such as silicon fins). The nanowires 706 may be referred to as a vertical arrangement of nanowires. As depicted, a protective cap 708 may be formed above the alternating sacrificial layers 704 and nanowires 706. Also as depicted, a relaxed buffer layer 752 and a defect modification layer 750 may be formed below the alternating sacrificial layers 704 and nanowires 706.

[0071] refer to Figure 7B , a gate stack 710 is formed above the vertical arrangement of horizontal nanowires 706. Figure 7C As depicted in , the vertically arranged portions of the horizontal nanowires 706 are then released by removing portions of the sacrificial layer 704 to provide a recessed sacrificial layer 704 ′ and cavity 712 .

[0072] It will be appreciated that fabrication can be accomplished without first performing the deep etch and asymmetric contact processing described below. Figure 7C In either case (e.g., with or without asymmetric contact processing), in one embodiment, the fabrication process involves using a process scheme that provides a gate-all-around integrated circuit structure with epitaxial dice that can be vertically discrete source or drain structures.

[0073] refer to Figure 7D , an upper gate spacer 714 is formed at the sidewalls of the gate structure 710. A cavity spacer 716 is formed in the cavity 712 below the upper gate spacer 714. A deep trench contact etch is then optionally performed to form a trench 718 and form the recessed nanowire 706'. As depicted, there may also be a patterned relaxed buffer layer 752' and a patterned defect modification layer 750'.

[0074] A sacrificial material 720 is then formed in the trench 718, such as Figure 7E In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0075] refer to Figure 7F , a first epitaxial source or drain structure (e.g., left-hand feature 722) is formed at a first end of the vertical arrangement of horizontal nanowire 706'. A second epitaxial source or drain structure (e.g., right-hand feature 722) is formed at a second end of the vertical arrangement of horizontal nanowire 706'. In one embodiment, as depicted, epitaxial source or drain structures 722 are vertically discrete source or drain structures and can be referred to as epitaxial nuggets.

[0076] like Figure 7G As depicted in FIG, an inter-layer dielectric (ILD) material 724 is then formed on the side of the gate electrode 710 and adjacent to the source or drain structure 722. Figure 7H , a replacement gate process is used to form a permanent gate dielectric 728 and a permanent gate electrode 726. Figure 7I , the ILD material 724 is then removed. The sacrificial material 720 is then removed from one of the source drain locations (eg, the right hand side) to form the trench 732, but the sacrificial material 720 is not removed from the other of the source drain locations to form the trench 730.

[0077] refer to Figure 7J, forming a first conductive contact structure 734 coupled to the first epitaxial source or drain structure (e.g., left-hand feature 722). Forming a second conductive contact structure 736 coupled to the second epitaxial source or drain structure (e.g., right-hand feature 722). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In one embodiment, although Figure 7J Not depicted, but the method further includes forming an exposed surface of a second conductive contact structure 736 at the bottom of the fin 702. The conductive contact may include a contact resistance reducing layer and a main contact electrode layer, examples of which may include Ti, Ni, Co (for the former) and W, Ru, Co (for the latter).

[0078] In one embodiment, as depicted, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734. In one such embodiment, as depicted, the first conductive contact structure 734 is not along the fin 702. In another such embodiment, not depicted, the first conductive contact structure 734 is partially along the fin 702.

[0079] In one embodiment, the second conductive contact structure 736 is along the entire fin 702. In one embodiment, although not depicted, the second conductive contact structure 736 has an exposed surface at the bottom of the fin 702 if the bottom of the fin 702 is exposed by a backside substrate removal process.

[0080] In one embodiment, Figure 7J structure or Figures 7A-7J The related structures can be formed using the cutting metal gate method, such as the related Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 5C 、 Figure 6B or Figure 6C Descriptive.

[0081] In another aspect, in order to enable access to two conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structures described herein can be manufactured using backside exposure of a frontside structure manufacturing method. In some exemplary embodiments, exposing the backside of the transistor or other device structure requires wafer-level backside processing. Compared to conventional TSV-type technologies, the exposure of the backside of the transistor described herein can be performed at the density of the device cell, and even within a sub-region of the device. In addition, such exposure of the backside of the transistor can be performed to remove substantially all of the donor substrate on which the device layers are disposed during frontside device processing. As such, micron-deep TSVs become unnecessary, where the semiconductor thickness in the device cell after the backside of the transistor is exposed may be only tens or hundreds of nanometers.

[0082] The exposure technology described herein can enable a paradigm shift from "bottom-up" device manufacturing to "center-out" manufacturing, where the "center" is any layer employed in front-side manufacturing, exposed from the backside, and employed again in back-side manufacturing. Processing both the front-side and exposed backside of the device structure can address many of the challenges associated with manufacturing 3DICs when relying primarily on front-side processing.

[0083] Methods for exposing the back side of the transistor can be employed, for example, to remove at least a portion of the carrier layer and intermediate layers of the donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for carrier layer components can be employed. For example, where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be employed. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can be employed.

[0084] In some embodiments, prior to the above, the carrier layer is cleaved along a fracture plane substantially parallel to the intermediate layer. The cleaving or fracture process can be used to remove a substantial portion of the carrier layer as a large block, thereby reducing the polishing or etching time required to remove the carrier layer. For example, where the carrier layer thickness is 400-900 μm, 100-700 μm can be cleaved by practicing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted to a uniform target depth within the carrier layer where the fracture plane is desired. Following such a cleaving process, the remaining thickness of the carrier layer in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be employed to remove a greater thickness of the carrier layer.

[0085] Next, the exposure of the intermediate layer is detected. Detection is used to identify the point when the back surface of the donor substrate has advanced close to the device layer. Any endpoint detection technique known to be suitable for detecting transitions between the materials used in the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting changes in absorbance or emission of the back surface of the donor substrate during polishing or etching. In some other embodiments, the endpoint criteria are associated with changes in absorbance or emission of byproducts during polishing or etching of the back surface of the donor substrate. For example, the absorbance or emission wavelength associated with the carrier layer etching byproducts can change as a function of the different components of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of the byproducts of polishing or etching the back surface of the donor substrate. For example, the byproducts of the process can be sampled by a quadrupole mass analyzer, and the changes in the mass of the material can be related to the different components of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in friction between the back surface of the donor substrate and the polishing surface in contact with the back surface of the donor substrate.

[0086] Detection of the intermediate layer can be enhanced where the removal process is selective for the carrier layer relative to the intermediate layer because non-uniformities in the carrier removal process can be mitigated by the etch rate delta between the carrier layer and the intermediate layer. Detection can even be skipped if the grinding, polishing, and / or etching operation removes the intermediate layer at a rate sufficiently lower than the rate at which the carrier layer is removed. If an endpoint criterion is not employed, a grinding, polishing, and / or etching operation of a predetermined fixed duration can be stopped at the intermediate layer material (if the thickness of the intermediate layer is sufficient for etching selectivity). In some examples, the carrier etch rate:intermediate layer etch rate is 3:1-10:1 or higher.

[0087] When exposing the interlayer, at least a portion of the interlayer can be removed. For example, one or more component layers of the interlayer can be removed. For example, the thickness of the interlayer can be uniformly removed by polishing. Alternatively, the thickness of the interlayer can be removed using a mask or blanket etching process. This process can employ the same polishing or etching process used to thin the carrier, or it can be a different process with different process parameters. For example, where the interlayer provides an etch stop for the carrier removal process, the latter operation can employ a different polishing or etching process that favors removal of the interlayer over removal of the device layers. Where an interlayer less than a few hundred nanometers thick is to be removed, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than the process used to remove the carrier layer. The CMP process employed can, for example, employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or higher) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layers and embedded within the interlayer, for example, to serve as electrical isolation between adjacent device regions.

[0088] For embodiments in which the device layer is exposed by completely removing the intermediate layer, backside processing can be initiated on the exposed backside of the device layer or specific device regions therein. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through the device layer thickness between the intermediate layer and the device regions previously fabricated in the device layer (such as source or drain regions).

[0089] In some embodiments where wet and / or plasma etching is used to recess the back surface of the carrier layer, the intermediate layer, or the device layer, such etching can be patterned etching or material selective etching that imparts significant non-planarity or topography to the back surface of the device layer. As further described below, patterning can be within a device cell (i.e., "intra-cell" patterning) or can be across device cells (i.e., "inter-cell" patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the back device layer. Thus, the mask etching process can begin with etching the device layer corresponding to the mask.

[0090] The processing scheme described above can produce a donor-host substrate assembly comprising an IC device having an intermediate layer backside, a device layer backside, and / or a backside of one or more semiconductor regions within a device layer and / or exposed front side metallization. Additional backside processing can then be performed on any of these exposed regions during downstream processing.

[0091] It will be appreciated that the structures produced by the exemplary processing schemes described above can be used in the same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and / or NMOS device fabrication. As an example of a complete device, Figure 8A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is illustrated.

[0092] refer to Figure 8 , the semiconductor structure or device 800 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 804 and a sub-fin region 805) within a trench isolation region 806. In one embodiment, instead of a solid fin, the non-planar active region is divided into nanowires (such as nanowires 804A and 804B) above the sub-fin region 805, as represented by the dotted lines. In either case, for ease of describing the non-planar integrated circuit structure 800, the non-planar active region 804 is referred to below as the protruding fin portion. In one embodiment, as depicted, the sub-fin region 805 also includes a relaxed buffer layer 842 and a defect modification layer 840.

[0093] The gate line 808 is disposed over the protruding portion 804 of the non-planar active area (including surrounding nanowires 804A and 804B, if applicable), and over a portion of the trench isolation region 806. As shown, the gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. Also seen from this view are the gate contact 814 and the overlying gate contact via 816, along with the overlying metal interconnect 860, all of which are disposed in an interlayer dielectric stack or layer 870. Figure 8 It can also be seen from the perspective of FIG that, in one embodiment, the gate contact 814 is disposed above the trench isolation region 806 but not above the non-planar active region. In another embodiment, the gate contact 814 is above the non-planar active region.

[0094] In one embodiment, semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is composed of or formed within a three-dimensional body. In one such embodiment, the gate electrode stack of gate line 808 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body.

[0095] Also like Figure 8 As depicted in FIG, in one embodiment, an interface 880 exists between the protruding fin portion 804 and the sub-fin region 805. The interface 880 can be a transition region between the doped sub-fin region 805 and the lightly doped or undoped upper fin portion 804. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is optionally supplied from an adjacent solid-state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0096] although Figure 8Not depicted, but understood, is the source or drain region of the protruding fin portion 804 or adjacent the protruding fin portion 804 on either side of the gate line 808 (i.e., in-page and out-page). In one embodiment, the material of the protruding fin portion 804 in the source or drain location is removed and replaced with another semiconductor material, for example by epitaxial deposition to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 806, i.e., into the sub-fin region 805. According to an embodiment of the present disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below the interface 880) suppresses source to drain leakage through that portion of the bulk semiconductor fin. In one embodiment, the source and drain regions have associated asymmetric source and drain contact structures, as described above in connection with Figure 7J Descriptive.

[0097] Reference again Figure 8 In one embodiment, the fins 804 / 805 (and possibly nanowires 804A and 804B) are composed of a crystalline silicon germanium layer, which may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0098] In one embodiment, the trench isolation region 806 and the trench isolation regions described throughout (trench isolation structures or trench isolation layers) may be composed of a material suitable for ultimately electrically isolating portions of the permanent gate structure from the underlying bulk substrate or facilitating isolation of portions of the permanent gate structure from the underlying bulk substrate, or may be composed of a material that isolates active regions formed within the underlying bulk substrate (such as isolating fin active regions). For example, in one embodiment, the trench isolation region 806 is composed of a dielectric material (such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride).

[0099] The gate line 808 can be composed of a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In one embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 852 is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer 852 can include a native oxide layer formed from the top layers of the substrate fin 804. In one embodiment, the gate dielectric layer 852 is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 852 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a “U”-shaped structure including a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the substrate top surface.

[0100] In one embodiment, the gate electrode layer 850 is composed of a metal layer, such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode layer 850 is composed of a non-work function setting fill material formed on a metal work function setting layer. Depending on whether the transistor will be a PMOS or NMOS transistor, the gate electrode layer 850 can be composed of a P-type work function metal or an N-type work function metal. In some implementations, the gate electrode layer 850 can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and a conductive metal oxide (e.g., ruthenium oxide). The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between approximately 4.9 eV and approximately 5.2 eV. For NMOS transistors, metals that can be used for gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between approximately 3.9 eV and approximately 4.2 eV. In some implementations, the gate electrode can be composed of a "U"-shaped structure comprising a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode can simply be a planar layer substantially parallel to the top surface of the substrate and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In a further implementation of the present disclosure, the gate electrode can be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode can be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0101] The spacers associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts) or facilitating isolation of the permanent gate structure from adjacent conductive contacts (such as self-aligned contacts). For example, in one embodiment, the spacers are composed of a dielectric material (such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride).

[0102] The gate contact 814 and the covering gate contact via 816 can be composed of a conductive material. In one embodiment, one or more of the contacts or vias are composed of a metallic substance. The metallic substance can be a pure metal, such as tungsten, nickel, or cobalt; or it can be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

[0103] In one embodiment (although not shown), a contact pattern is formed that is substantially fully aligned with the existing gate pattern 808 while eliminating the use of photolithography steps with extremely tight registration budgets. In one embodiment, the contact pattern is a vertically symmetric contact pattern, or such as a related Figure 7J The asymmetric contact pattern described. In other embodiments, all contacts are front-connected and are not asymmetric. In one such embodiment, the self-aligned method enables the use of inherently highly selective wet etching (e.g., relative to conventional dry or plasma etching) to generate contact openings. In one embodiment, the contact pattern is formed by combining contact plug lithography operations with existing gate patterns. In one such embodiment, the method enables the elimination of the need for other critical lithography operations for generating contact patterns as used in conventional methods. In one embodiment, the trench contact grid is not patterned separately, but is formed between the polycrystalline (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grating is patterned but before the gate grating is cut.

[0104] In one embodiment, providing structure 800 involves manufacturing gate stack structure 808 by a replacement gate process. In such an approach, dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being implemented from earlier processing. In one embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a dry etch process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed by a wet etch process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed by a wet etch including aqueous phosphoric acid.

[0105] Reference again Figure 8 , the arrangement of the semiconductor structure or device 800 places the gate contact above the isolation region. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts portions of a gate electrode formed above the active region (e.g., above the fin 805) and in the same layer as the trench contact via.

[0106] In one embodiment, a cut metal gate method may be used to form Figure 8 Structures such as associations Figure 1B 、 Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 5C 、 Figure 6B or Figure 6C Descriptive.

[0107] It should be appreciated that not all aspects of the processes described above need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. In addition, the processes described herein can be used to manufacture one or more semiconductor devices. The semiconductor device can be a transistor or similar device. For example, in one embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. In addition, in one embodiment, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessed dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for manufacturing semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0108] In one embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0109] In one embodiment, as also used throughout this specification, the metal line or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper lines and copper structures, which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term "metal" includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, the interconnect may be a single material layer, or may be formed from several layers (including a conductive liner layer and a filler layer). Any suitable deposition process (such as electroplating, chemical vapor deposition, or physical vapor deposition) may be used to form the interconnect. In one embodiment, the interconnect is composed of a conductive material such as, but not limited to, copper, aluminum, titanium, zirconium, hafnium, vanadium, ruthenium, cobalt, nickel, palladium, platinum, tungsten, silver, gold, or an alloy thereof. In the art, interconnects are sometimes also referred to as traces, wires, lines, metals, or simply interconnects.

[0110] In one embodiment, as used throughout this specification, a hard mask material, a capping layer, or a plug is composed of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask materials, capping materials, or plug materials may be used in different regions to provide different growth or etching selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping layer, or plug layer comprises a silicon nitride layer (e.g., silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask layers, capping layers, or plug layers known in the art may be used. The hard mask layer, capping layer, or plug layer may be formed by CVD, PVD, or by other deposition methods.

[0111] In one embodiment, as used throughout this specification, photolithography operations are performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, among others. Positive tone resist or negative tone resist may be used. In one embodiment, the photolithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0112] In another aspect, one or more embodiments are directed to adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may be directed to the integration of multi-width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture, separated by SAGE walls. In one embodiment, the nanowires / nanoribbons are integrated with multiple Wsi in the SAGE architecture portion of the front-end process flow. Such a process flow may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., removing portions of the nanowires and then performing source or drain (S / D) growth).

[0113] To provide further context, advantages of the self-aligned gate endcap (SAGE) architecture can include achieving higher layout density, and in particular, diffusion to diffusion pitch ratio. To provide an illustrative comparison, Figure 9 Illustrated are cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) and a self-aligned gate endcap (SAGE) architecture (right-hand side (b)) according to embodiments of the present disclosure.

[0114] refer to Figure 9On the left-hand side (a) of FIG, an integrated circuit structure 900 includes a substrate 902 having a fin 904 that protrudes a certain amount 906 from an isolation structure 908 that laterally surrounds a lower portion of the fin 904. As depicted, the upper portion of the fin may include a relaxed buffer layer 922 and a defect modification layer 920. A corresponding nanowire 905 is above the fin 904. A gate structure may be formed above the integrated circuit structure 900 to fabricate a device. However, breaks in such a gate structure may be accommodated by increasing the spacing between the fin 904 / nanowire 905 pairs.

[0115] In comparison, reference Figure 9 On the right-hand side (b) of FIG, integrated circuit structure 950 includes substrate 952 having fins 954 that protrude a certain amount 956 above isolation structure 958, which laterally surrounds the lower portion of fin 954. As depicted, the upper portion of the fin may include a relaxed buffer layer 972 and a defect modification layer 970. Corresponding nanowires 955 are above fins 954. Isolation SAGE walls 960 (which, as depicted, may include a hard mask thereon) are included within isolation structure 952 and between adjacent fin 954 / nanowire 955 pairs. The distance between isolation SAGE walls 960 and the nearest fin 954 / nanowire 955 pair defines a gate endcap spacing 962. Gate structures may be formed above integrated circuit structure 900 between isolation SAGE walls to fabricate devices. Breaks in such gate structures are imposed by the isolation SAGE walls. Because the isolation SAGE walls 960 are self-aligned, limitations from conventional methods can be minimized to achieve more aggressive diffusion-to-diffusion spacing. In addition, because the gate structure includes breaks at all locations, the various gate structure portions can be layered together via local interconnects formed above the isolation SAGE walls 960. In one embodiment, as depicted, the SAGE walls 960 each include a lower dielectric portion and a dielectric cap on the lower dielectric portion. According to embodiments of the present disclosure, Figure 9 The fabrication process of the associated structure involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0116] In one embodiment, Figure 9 The structure of part (a) can be formed using a cutting metal gate method, such as the associated Figure 3B 、 Figure 5B 、 Figure 5C 、 Figure 6B or Figure 6C In one embodiment, Figure 9 The structure of part (b) can be formed using a cutting metal gate method, such as the associated Figure 4B 、 Figure 5B 、 Figure 5C 、 Figure 6B or Figure 6C Descriptive.

[0117] A self-aligned gate endcap (SAGE) process involves forming a gate / trench contact endcap that is self-aligned with the fin, without requiring additional length to account for mask misalignment. Thus, embodiments can be implemented to reduce the transistor layout area. Embodiments described herein can relate to the fabrication of a gate endcap isolation structure, which can also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate endcap (SAGE) wall.

[0118] In an exemplary processing scheme having a structure with SAGE walls separating adjacent devices, Figure 10 Illustrated are cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure having a gate-all-around device, in accordance with an embodiment of the present disclosure.

[0119] refer to Figure 10 10. In part (a) of FIG. 10, a starting structure includes a nanowire patterned stack 1004 on a substrate 1002. A lithographically patterned stack 1006 is formed on the nanowire patterned stack 1004. As depicted, the nanowire patterned stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be on top of a relaxed buffer layer 1082 and a defect modification layer 1080. A protective mask 1014 is between the nanowire patterned stack 1004 and the lithographically patterned stack 1006. In one embodiment, the lithographically patterned stack 1006 is a triple-layer mask consisting of a topography masking portion 1020, an anti-reflective coating (ARC) layer 1022, and a photoresist layer 1024. In a particular such embodiment, the topography masking portion 1020 is a carbon hard mask (CHM) layer, and the anti-reflective coating layer 1022 is a silicon ARC layer.

[0120] refer to Figure 10 The stack of portion (b), portion (a) is photolithographically patterned and then etched to provide an etched structure including patterned substrate 1002 and trench 1030.

[0121] refer to Figure 10 1. In portion (c), the structure of portion (b) has isolation layer 1040 and SAGE material 1042 formed in trench 1030. The structure is then planarized to leave patterned topographical masking layer 1020' as an exposed upper layer.

[0122] refer to Figure 10In portion (d), the isolation layer 1040 is recessed below the upper surface of the patterned substrate 1002 , for example, to define a protruding fin portion and provide a trench isolation structure 1041 below the SAGE wall 1042 .

[0123] refer to Figure 10 In the portion (e), the sacrificial layer 1010 is removed at least in the channel region to release the nanowires 1012A and 1012B. Figure 10 After forming the structure of portion (e), a gate stack can be formed around nanowire 1012B or 1012A, above the protruding fin of substrate 1002, and between SAGE walls 1042. In one embodiment, the remaining portion of protective mask 1014 is removed before forming the gate stack. In another embodiment, the remaining portion of protective mask 1014 remains as an insulating fin cap as an artifact of the processing scheme.

[0124] Reference again Figure 10 1012A, 1012B, and 1012A, respectively, are respectively distinguished as nanowires and nanoribbons, both structures are generally referred to herein as nanowires. It will also be appreciated that references or depictions of fin / nanowire pairs throughout the document may refer to a structure comprising a fin and one or more overlying nanowires (e.g., nanowires 1012B and 1012A). Figure 10 According to an embodiment of the present disclosure, with Figure 10 The fabrication process of the associated structure involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0125] In one embodiment, Figure 10 The structure of part (e) can be formed using a cutting metal gate method, such as the associated Figure 4B 、 Figure 5B 、 Figure 5C 、 Figure 6B or Figure 6C Descriptive.

[0126] In one embodiment, as described throughout, a self-aligned gate end cap (SAGE) isolation structure can be composed of (one or more) materials suitable for ultimately electrically isolating portions of a permanent gate structure from one another, or for facilitating isolation of portions of a permanent gate structure from one another. Exemplary materials or material combinations include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include multilayer stacks having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a higher dielectric constant material (such as hafnium oxide).

[0127] To highlight an exemplary integrated circuit structure with three vertically arranged nanowires, Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is illustrated. Figure 11B The diagram shows the image taken along the a-a' axis. Figure 11A A cross-sectional view of a source or drain electrode of a nanowire-based integrated circuit structure. Figure 11C The diagram shows the image taken along the axis bb'. Figure 11A Cross-sectional view of the channel of a nanowire-based integrated circuit structure.

[0128] refer to Figure 11A , the integrated circuit structure 1100 includes one or more vertically stacked nanowires (a set of 1104) above a substrate 1102. In one embodiment, as depicted, a relaxed buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are included in the substrate 1102, as depicted. For illustrative purposes, the optional fins below the bottommost nanowire and formed by the substrate 1102 are not depicted in order to emphasize the nanowire portion. The embodiments herein are directed to both single-wire devices and multi-wire devices. As an example, for illustrative purposes, three nanowire-based devices having nanowires 1104A, 1104B, and 1104C are shown. For ease of description, nanowire 1104A is used as an example, where the description focuses on one of the nanowires. It should be appreciated that where the properties of one nanowire are described, embodiments based on multiple nanowires can have the same or substantially the same properties for each nanowire.

[0129] Each nanowire 1104 includes a channel region 1106 in the nanowire. The channel region 1106 has a length (L). Figure 11C , the channel region also has a perimeter (Pc) perpendicular to the length (L). Figure 11A and Figure 11C, a gate electrode stack 1108 surrounds the entire perimeter (Pc) of each channel region 1106. The gate electrode stack 1108 includes a gate electrode along with a gate dielectric layer between the channel region 1106 and the gate electrode (not shown). In one embodiment, the channel region is discrete in that it is completely surrounded by the gate electrode stack 1108 without any intervening materials, such as underlying substrate material or overlying channel fabrication materials. Therefore, in embodiments having multiple nanowires 1104, the channel regions 1106 of the nanowires are also discrete relative to each other.

[0130] refer to Figure 11A and Figure 11B In both cases, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. The pair of non-discrete source or drain regions 1110 / 1112 are on either side of a channel region 1106 of a plurality of vertically stacked nanowires 1104. Furthermore, the pair of non-discrete source or drain regions 1110 / 1112 are adjacent to the channel regions 1106 of the plurality of vertically stacked nanowires 1104. In one such embodiment (not depicted), the pair of non-discrete source or drain regions 1110 / 1112 are directly adjacent to the channel regions 1106 because epitaxial growth occurs on and between portions of the nanowires that extend beyond the channel regions 1106, with the nanowire ends shown within the source or drain structure. In another embodiment, as Figure 11A As depicted in , the pair of non-discrete source or drain regions 1110 / 1112 are indirectly vertically adjacent to the channel region 1106 because they are formed at the ends of the nanowires and not between the nanowires.

[0131] In one embodiment, as depicted, the source or drain regions 1110 / 1112 are non-discrete in that there is no separate and discrete source or drain region for each channel region 1106 of the nanowire 1104. Thus, in embodiments having multiple nanowires 1104, the source or drain regions 1110 / 1112 of the nanowires are global or unified source or drain regions, as opposed to being discrete for each nanowire. That is, the non-discrete source or drain regions 1110 / 1112 are global in the sense that a single unified feature is used as the source or drain region for multiple (in this case, three) nanowires 1104, and more particularly, for more than one discrete channel region 1106. In one embodiment, each of the pair of non-discrete source or drain regions 1110 / 1112 is approximately rectangular in shape, having a bottom tapered portion and a top apex portion, as seen from a cross-sectional perspective perpendicular to the length of the discrete channel region 1106. Figure 11B However, in other embodiments, the source or drain regions 1110 / 1112 of the nanowire are relatively large, but are separate, non-vertically merged epitaxial structures, such as those associated with Figures 7A-7J Small pieces of description.

[0132] According to the embodiments of the present disclosure, and as Figure 11A and Figure 11B As depicted in , the integrated circuit structure 1100 further includes a pair of contacts 1114, each contact 1114 being on one of the pair of non-discrete source or drain regions 1110 / 1112. In one such embodiment, each contact 1114 completely surrounds the corresponding non-discrete source or drain region 1110 / 1112 in a vertical sense. In another aspect, the entire perimeter of the non-discrete source or drain region 1110 / 1112 may not be accessible for contact with the contacts 1114, and thus the contacts 1114 only partially surround the non-discrete source or drain region 1110 / 1112, as shown in FIG. Figure 11B In a comparative embodiment, not depicted, the entire perimeter of the non-discrete source or drain region 1110 / 1112 , as taken along the aa′ axis, is surrounded by the contact 1114 .

[0133] Reference again Figure 11A In one embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As depicted, outer portions of the pair of spacers 1116 may overlap portions of the non-discrete source or drain regions 1110 / 1112, providing "embedded" portions of the non-discrete source or drain regions 1110 / 1112 beneath the pair of spacers 1116. Also as depicted, the embedded portions of the non-discrete source or drain regions 1110 / 1112 may not extend entirely beneath the pair of spacers 1116.

[0134] Substrate 1102 can be composed of materials suitable for integrated circuit structure fabrication. In one embodiment, substrate 1102 includes a lower bulk substrate composed of a single crystal material, which may include but is not limited to silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or a III-V compound semiconductor material. An upper insulator layer composed of a material that may include but is not limited to silicon dioxide, silicon nitride, or silicon oxynitride is on the lower bulk substrate. Thus, structure 1100 can be manufactured from a starting semiconductor-on-insulator substrate. Alternatively, structure 1100 is formed directly from a bulk substrate, and local oxidation is used to form an electrically insulating portion in place of the upper insulator layer described above. In another alternative embodiment, structure 1100 is formed directly from a bulk substrate, and doping is used to form an electrically isolated active region, such as a nanowire, thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an omega-FET type structure.

[0135] In one embodiment, the nanowires 1104 can be sized as wires or strips, as described below, and can have square or rounded corners. In one embodiment, the nanowires 1104 are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, for silicon nanowires 1104, the single crystalline nanowires can be based on a (100) global orientation, such as having a z-direction of <100> As described below, other orientations are also contemplated. In one embodiment, the dimensions of nanowire 1104 are nanometer-scale when viewed from a cross-sectional perspective. For example, in certain embodiments, the smallest dimension of nanowire 1104 is less than approximately 20 nanometers. In one embodiment, nanowire 1104 is composed of a strained material, particularly in channel region 1106.

[0136] refer to Figure 11C In one embodiment, each channel region 1106 has a width (Wc) and a height (Hc), with the width (Wc) being approximately the same as the height (Hc). That is, in both cases, the cross-sectional profile of the channel region 1106 is square or, if rounded, circular. In another aspect, the width and height of the channel region need not be the same, such as in the case of nanoribbons as described throughout.

[0137] In one embodiment, as described throughout, an integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate device, with corresponding one or more overlying nanowire structures. In such an embodiment, the corresponding semiconductor channel region is comprised of or formed within a three-dimensional body, wherein one or more discrete nanowire channel portions overlie the three-dimensional body. In one such embodiment, a gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions.

[0138] In one embodiment, Figures 11A-11C The structure can be formed using a cutting metal gate method, such as the associated Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 5C 、 Figure 6B or Figure 6C described.

[0139] In one embodiment, as described throughout, the underlying substrate can be composed of a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In one embodiment, the substrate is a bulk substrate composed of crystalline silicon, silicon / germanium, or germanium layers doped with charge carriers (such as, but not limited to, phosphorus, arsenic, boron, gallium, or a combination thereof) to form the active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a different crystalline substrate (e.g., a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate). Alternatively, the bulk substrate can be composed of a III-V material. In one embodiment, the bulk substrate is composed of a III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate is composed of a III-V material, and the charge carrier dopant impurity atoms are atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0140] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, the integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic devices, etc. The integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0141] Figure 12 A computing device 1200 is illustrated according to one implementation of an embodiment of the present disclosure. Computing device 1200 houses a board 1202. Board 1202 may include multiple components, including, but not limited to, a processor 1204 and at least one communication chip 1206. Processor 1204 is physically and electrically coupled to board 1202. In some implementations, at least one communication chip 1206 is also physically and electrically coupled to board 1202. In further implementations, communication chip 1206 is part of processor 1204.

[0142] Depending on its application, the computing device 1200 may include other components that may or may not be physically and electrically coupled to the board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.).

[0143] The communication chip 1206 implements wireless communications for data transfer to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data via a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 1206 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing device 1200 may include multiple communication chips 1206. For example, the first communication chip 1206 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 1206 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0144] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures, such as a gate-all-around integrated circuit structure having a cut metal gate with a dielectric plug, constructed according to an implementation of an embodiment of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0145] The communication chip 1206 also includes an integrated circuit die packaged within the communication chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures such as a gate-all-around integrated circuit structure having a cut metal gate with a dielectric plug constructed according to implementations of the disclosed embodiments.

[0146] In further implementations, another component housed within computing device 1200 may include an integrated circuit die including one or more structures, such as a gate-all-around integrated circuit structure having a cut metal gate with a dielectric plug, constructed according to implementations of the disclosed embodiments.

[0147] In various implementations, computing device 1200 may be a laptop computer, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1200 may be any other electronic device that processes data.

[0148] Figure 13 An interposer 1300 including one or more embodiments of the present disclosure is illustrated. Interposer 1300 is an intermediate substrate used to bridge a first substrate 1302 to a second substrate 1304. First substrate 1302 can be, for example, an integrated circuit die. Second substrate 1304 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally speaking, the purpose of interposer 1300 is to extend connections to a wider pitch or to reroute connections to different connections. For example, interposer 1300 can couple an integrated circuit die to a ball grid array (BGA) 1306, which can then be coupled to a second substrate 1304. In some embodiments, the first and second substrates 1302 / 1304 are attached to opposite sides of interposer 1300. In other embodiments, the first and second substrates 1302 / 1304 are attached to the same side of interposer 1300. And in further embodiments, three or more substrates are interconnected by means of interposer 1300.

[0149] Interposer 1300 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further implementations, interposer 1300 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0150] The interposer 1300 may include metal interconnects 1308 and through-holes 1310, including but not limited to through-silicon vias (TSVs) 1312. The interposer 1300 may further include embedded devices 1314, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1300. According to embodiments of the present disclosure, the apparatus or process disclosed herein may be used to manufacture the interposer 1300 or to manufacture components included in the interposer 1300.

[0151] Thus, embodiments of the present disclosure include an integrated circuit structure having a cut metal gate with a dielectric plug, and a method of fabricating an integrated circuit structure having a cut metal gate with a dielectric plug.

[0152] The above description of the illustrated implementations of the embodiments of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, as those skilled in the relevant art will appreciate, various equivalent modifications are possible within the scope of the present disclosure.

[0153] These modifications may be made to the present disclosure in light of the foregoing detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0154] Example embodiment 1: An integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is above the protruding portion of the fin and above the STI structure. A conductive gate layer is above the gate dielectric material layer. A conductive gate fill material is above the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug including a dielectric liner comprising silicon and oxygen and a dielectric fill comprising silicon and oxygen, with a seam between the dielectric liner and the dielectric fill. The gate dielectric material layer and the conductive gate layer do not extend along a side of the dielectric gate plug, and the conductive gate fill material is in contact with the side of the dielectric gate plug.

[0155] Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the gate dielectric material layer is a high-k gate dielectric layer.

[0156] Example Embodiment 3: The integrated circuit structure according to Example Embodiment 1 or 2, wherein the conductive gate layer is a work function metal layer.

[0157] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, 2, or 3, wherein the dielectric gate overlies the conductive gate fill material.

[0158] Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3, or 4, wherein the dielectric liner further comprises one or more of carbon, boron, or a halogen.

[0159] Example embodiment 6: An integrated circuit structure comprising a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires are above the sub-fin. A gate dielectric material layer is above the protruding portion of the sub-fin, above the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is above the gate dielectric material layer. A conductive gate fill material is above the conductive gate layer. The dielectric gate plug is laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires. The dielectric gate plug comprises a dielectric liner comprising silicon and oxygen and a dielectric fill comprising silicon and oxygen, with a seam between the dielectric liner and the dielectric fill. The gate dielectric material layer and the conductive gate layer are not along the sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

[0160] Example Embodiment 7: The integrated circuit structure of Example Embodiment 6, wherein the gate dielectric material layer is a high-k gate dielectric layer.

[0161] Example Embodiment 8: The integrated circuit structure according to Example Embodiment 6 or 7, wherein the conductive gate layer is a work function metal layer.

[0162] Example Embodiment 9: The integrated circuit structure of Example Embodiment 6, 7, or 8, wherein the dielectric gate overlies the conductive gate fill material.

[0163] Example Embodiment 10: The integrated circuit structure of Example Embodiment 6, 7, 8, or 9, wherein the dielectric liner further comprises one or more of carbon, boron, or a halogen.

[0164] Example embodiment 11: A computing device comprising a board and a component coupled to the board. The component comprises an integrated circuit structure comprising a fin or a plurality of horizontally stacked nanowires above a shallow trench isolation (STI) structure. A gate dielectric material layer is above the fin or the plurality of horizontally stacked nanowires and above the STI structure. A conductive gate layer is above the gate dielectric material layer. A conductive gate fill material is above the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin or the plurality of horizontally stacked nanowires, the dielectric gate plug comprising a dielectric liner comprising silicon and oxygen and a dielectric fill comprising silicon and oxygen, with a seam between the dielectric liner and the dielectric fill. The gate dielectric material layer and the conductive gate layer are not along the sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

[0165] Example Embodiment 12: The computing device of Example Embodiment 11, comprising a fin.

[0166] Example Embodiment 13: The computing device of Example Embodiment 11, comprising a plurality of horizontally stacked nanowires.

[0167] Example Embodiment 14: The computing device of Example Embodiment 11, 12, or 13, further comprising a memory coupled to the board.

[0168] Example Embodiment 15: The computing device of Example Embodiment 11, 12, 13, or 14, further comprising a communication chip coupled to the board.

[0169] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14, or 15, further comprising a battery coupled to the board.

[0170] Example Embodiment 17: The computing device of Example Embodiment 11, 12, 13, 14, 15, or 16, further comprising a camera coupled to the board.

[0171] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, or 17, further comprising a display coupled to the board.

[0172] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0173] Example Embodiment 20: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

Claims

1. An integrated circuit structure comprising: a fin having a portion protruding above a shallow trench isolation (STI) structure; a gate dielectric material layer over the protruding portion of the fin and over the STI structure; a conductive gate layer overlying the gate dielectric material layer; a conductive gate fill material overlying the conductive gate layer; and A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug comprising a dielectric liner comprising silicon and oxygen and a dielectric fill comprising silicon and oxygen, with a seam between the dielectric liner and the dielectric fill, wherein the gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and wherein the conductive gate fill material is in contact with the sides of the dielectric gate plug. 2 . The integrated circuit structure of claim 1 , wherein the gate dielectric material layer is a high-k gate dielectric layer. 3 . The integrated circuit structure according to claim 1 , wherein the conductive gate layer is a work function metal layer.

4. The integrated circuit structure according to claim 1 or 2, wherein the dielectric gate covers the conductive gate filling material.

5. The integrated circuit structure of claim 1 or 2, wherein the dielectric liner further comprises one or more of carbon, boron, or halogen.

6. An integrated circuit structure comprising: a sub-fin having a portion protruding above a shallow trench isolation (STI) structure; a plurality of horizontally stacked nanowires above the sub-fins; a gate dielectric material layer over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires; a conductive gate layer overlying the gate dielectric material layer; a conductive gate fill material overlying the conductive gate layer; and A dielectric gate plug is laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate plug comprising a dielectric liner comprising silicon and oxygen and a dielectric fill comprising silicon and oxygen, with a seam between the dielectric liner and the dielectric fill, wherein the gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and wherein the conductive gate fill material is in contact with the sides of the dielectric gate plug.

7. The integrated circuit structure of claim 6, wherein the gate dielectric material layer is a high-k gate dielectric layer.

8. The integrated circuit structure according to claim 6 or 7, wherein the conductive gate layer is a work function metal layer.

9. The integrated circuit structure of claim 6 or 7, wherein the dielectric gate overlies the conductive gate fill material.

10. The integrated circuit structure of claim 6 or 7, wherein the dielectric liner further comprises one or more of carbon, boron, or a halogen.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: Fins or multiple horizontally stacked nanowires on top of shallow trench isolation (STI) structures; a gate dielectric material layer over the fin or the plurality of horizontally stacked nanowires and over the STI structure; a conductive gate layer overlying the gate dielectric material layer; a conductive gate fill material overlying the conductive gate layer; and A dielectric gate plug laterally spaced apart from a fin or a plurality of horizontally stacked nanowires, the dielectric gate plug comprising a dielectric liner comprising silicon and oxygen and a dielectric fill comprising silicon and oxygen, with a seam between the dielectric liner and the dielectric fill, wherein the gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and wherein the conductive gate fill material is in contact with the sides of the dielectric gate plug.

12. The computing device of claim 11, comprising a fin.

13. The computing device of claim 11, comprising a plurality of horizontally stacked nanowires.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12, or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12, or 13, further comprising: A battery coupled to the board.

17. The computing device of claim 11, 12, or 13, further comprising: A camera is coupled to the board.

18. The computing device of claim 11, 12, or 13, further comprising: A display is coupled to the panel.

19. The computing device of claim 11, 12, or 13, wherein the component is a packaged integrated circuit die.

20. The computing device of claim 11, 12 or 13, wherein the component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

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