Whole wafer metrology

Abstract

A method for operating an integrated evaluation system, the method comprising: (i) introducing, by a motion system, relative motion between a sample and at least one of an IM head or an IIU head, (ii) performing, by the IM head, measurements of a set of measurement sites of the sample; (iii) acquiring, by the IIU head, an image of the region of the sample comprising the measurement site; (iv) receiving, by the processing circuitry, an image of the set of measurements and areas; and (v) estimating measurements located within the region and outside the measurement site using a mapping between the measurements and pixels of the image corresponding to the measurement site.

Description

[0001] Cross-citation

[0002] This application claims priority to U.S. Provisional Patent Serial No. 63 / 483,960, filed February 8, 2023, which is incorporated herein by reference. Background Art

[0003] Semiconductor process control is based on a wide range of high-end characterization solutions. Optical metrology is of particular value, providing fast, non-destructive solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, the invention as to its organization and method of operation, together with objects, features and advantages thereof, may be best understood by reference to the following detailed description when read in connection with the accompanying drawings, in which:

[0005] Figures 1A to 1F An embodiment of an integrated solution is shown;

[0006] Figure 2 Examples of regions and measurement sites are shown;

[0007] Figure 3 Examples of images, measurements, mapping, and estimated measurements are shown;

[0008] Figure 4 An embodiment of a method is shown; and

[0009] Figures 5 to 7 An embodiment of an integrated solution is shown. DETAILED DESCRIPTION

[0010] This invention specifically focuses on integrated metrology (IM), a metrology approach that attaches metrology tools to manufacturing process tools, enabling measurements of processed wafers immediately before and / or after processing. The rapid feedback ("time to measurement") provided by IM is crucial for process control in technologies such as chemical mechanical planarization (CMP), where advanced process control (APC) protocols utilize rapid metrology feedback to maintain the process within required margins. IM typically provides dimensional information characterizing fabricated nanostructures at a few points on the wafer, from which process information can be derived.

[0011] IM provides accurate but sparse metrology on the wafer, i.e., at most a few dozen points. IM tools provide values ​​for a few parameters of interest (POIs) or a small number of POIs that characterize the structure being measured. Typical POIs are layer thickness and structure size.

[0012] Extending this characterization to the entire wafer is typically accomplished through interpolation or extrapolation algorithms. However, these methods can introduce significant errors when the full-wafer variation is not perfectly smooth, such as failing to identify offsets between measurement points and at the wafer edge.

[0013] As process margins become increasingly tight, the feedback required for metrology is becoming increasingly complex. A common requirement is to significantly increase the number of characterized sites to provide higher-resolution coverage of processed wafers. However, simply increasing the number of points on the wafer requires significantly longer measurement times, which is incompatible with the high throughput (TPT) requirements of metrology solutions. Conversely, simplified solutions such as low-resolution full-wafer imaging lack the detailed information and sensitivity required to analyze complex nanostructures being measured.

[0014] The goal of this invention is to extend the high-end metrology provided by IM to large-scale, cross-wafer characterization. Metrology will no longer be limited to fragmented information at a few sites, but will instead cover many sites across the wafer (potentially hundreds or thousands). We will refer to this capability as "POI mapping." However, by combining information from high-end IM with an area coverage imaging channel, integrated into the same metrology platform, this expansion will be achieved with minimal loss in metrology quality.

[0015] Current solutions cover a range of metrology methods that vary in quality and time. These include:

[0016] a. In-situ "endpoint" detectors: Metrology modules integrated into the processing tool provide feedback during the process. These low-end solutions cannot measure at specific locations and offer poor control over measurement conditions and quality, making them suitable only for coarse process control. They cannot provide the high-quality feedback provided by the methods detailed below and described in this invention.

[0017] b. Integrated metrology (IM): These tools are typically based on broadband optical scatterometry and provide optical critical dimensions (OCDs) at selected metrology sites. As mentioned above, IM solutions are very useful in process control where rapid measurements are time-consuming, but they can only provide feedback on a limited number of sites on the wafer (a few dozen at most).

[0018] c. Full-wafer imaging: In these solutions, a complete image of the wafer is acquired. This large-scale data collection comes at the expense of information quality, as each location is measured at only one or a few wavelengths, and spatial resolution is typically poor. While high-end full-wafer metrology solutions exist, these are expensive and available only as standalone metrology stations, making rapid measurement impossible.

[0019] None of these solutions combines the high-end metrology quality offered by optical scatterometry with the extensive aerial coverage.

[0020] The goal of this invention is to extend the high-end metrology provided by IM to large-scale, cross-wafer characterization. Metrology will no longer be limited to fragmented information at a few sites, but will instead cover many sites across the wafer (potentially hundreds or thousands). We will refer to this capability as "POI mapping." However, by combining information from high-end IM with an area coverage imaging channel, integrated into the same metrology platform, this expansion will be achieved with minimal loss in metrology quality.

[0021] The goal of this invention is to provide a broad (up to full wafer-wide) metrology solution with quality comparable to that provided by high-end IMs. This is accomplished through a hardware-based implementation that combines IM measurement capabilities with an integrated imaging unit (IIU), where the IIU provides extensive coverage of a significant portion of the wafer under test within a limited spectral bandwidth. Achieving this goal requires a combination of hardware-based implementation, measurement protocols, and specialized interpretation algorithms. The invention is based on the following key elements:

[0022] An IM metrology platform that provides OCD metrology at a small number of sites on the wafer (as IM typically does). This set of measurements serves two purposes:

[0023] a. Metrology anchor point: The POI value measured at the point where IM is performed is used as a "known" point. The POI map (i.e., the POI value of the entire imaging area ultimately derived) must have a corresponding value at the IM measurement point.

[0024] b. POI training: The same set of points measured using IM are also measured using IIU (or at least most of them). A dedicated algorithm is used to identify potential correlations between the IIU data and the IM POI interpretation.

[0025] An integrated IIU, incorporated into the same platform, provides wide coverage of the critical portion of the wafer under test in a few spectral bandwidths.

[0026] A measurement protocol whereby two measurement modules (OCD and IIU) each provide their portion of the metrology with minimal impact on the overall wafer characterization time (compared to standard IM performance).

[0027] A set of algorithms allows to combine IM and IIU information together. The end result of this analysis engine is to extend the data measured in IM to all areas covered by IIU.

[0028] Below we will describe and elaborate on the unique attributes of each of these elements. It should be emphasized that the present invention relies on the common combined function of all these elements.

[0029] IM metrology platform and integrated imaging unit

[0030] The footprint of integrated metrology platforms is severely restricted due to the limitations imposed by their integration into the host process tool. The present invention must meet these constraints, which poses a significant challenge to integrating the OCD and IIU units without violating size constraints.

[0031] For the sake of clarity, let's first introduce the basic elements involved in the IM unit:

[0032] The IM tool is connected to a process tool (e.g., a CMP platform). A robotic arm transfers wafers between the process tool and the metrology unit (MU). Below, we use the term MU to refer to the entire metrology tool, including both the IM and IIU.

[0033] Inside the IM tool, a measurement head directs light to a specific location on the wafer and collects the scattered light. The same measurement head may also include an imaging channel that provides an image of the area being measured.

[0034] Due to floor space limitations, lateral movement of the wafer is significantly restricted. To enable the measurement head to reach all desired points on the wafer, the measurement head is typically moved above the wafer, or both the measurement head and the wafer are moved simultaneously.

[0035] Here are several possible implementations to achieve the integration of IM and IIU required by the present invention:

[0036] IIU scanning during wafer loading / unloading: In this embodiment, the imaging module is placed above the wafer entrance of the IM unit and images the wafer as it is transferred between the IM tool and the process tool by the tool robot. This implementation is discussed in detail in PCT patent application publication WO 2022 / 043935 Al. This approach has minimal (almost no) impact on the overall metrology throughput (TPT). However, imaging is performed in a highly uncontrolled manner, with the motion and vertical position of the wafer controlled by the robot and moving at very high speeds and accelerations. Therefore, the expected imaging quality is poor, which limits the overall performance and usability in high-end applications.

[0037] Furthermore, in this embodiment, the allowed volume of the IIU module is greatly constrained due to the space limitations required for metrology integration, which further limits its achievable quality. See, for example, Figure 1A and Figure 6 To Figure 8.

[0038] Measurement Unit Partitioning: In some implementations, the space used for IM metrology can be limited to a portion of the MU while still providing full coverage of the wafer. This can be achieved by simultaneously controlling the IM measurement head above the wafer and the wafer itself. For example:

[0039] a. The wafer can be placed on a rotating stage, the moving IM measurement head can scan half of the wafer area, and the rotating stage rotates 180° to cover the other half of the wafer. For example, see Figure 1B .

[0040] b. The IM measurement head can be placed on a translation stage that covers the radial path of the wafer, and the wafer is rotated to achieve full wafer metrology coverage.

[0041] c. The IM measurement head can remain static while the wafer moves in one direction. Lateral movement of the wafer places the IM measurement head at a selected radial position, while rotation of the wafer provides full wafer coverage (R-θ configuration). For example, see Figure 1C .

[0042] Importantly, this implementation allows for a large amount of free space above the wafer to be used for additional metrology equipment. In the present invention, this space will be used to place the IIU module.

[0043] It should be noted that in some implementations, the IM and IIU modules may not easily cover the entire wafer area. For example, if the MU is split so that the IM and IIU each cover half of the wafer, some buffer area will need to be left between these modules to ensure that there is no collision between the moving elements. Measures to address this challenge may include adding a motor to allow lateral movement of the wafer or implementing advanced synchronization between the two measurement heads to ensure that such collisions do not occur.

[0044] On-the-go integration: The most challenging aspect of implementing optical head movement and integrating IM and IIU measurement within the same enclosure is undoubtedly the joint motion of the two modules. The motor and support mechanism must scan across the wafer surface without collision, while also meeting space constraints.

[0045] One measure to cope with this possibility is to combine the IM and IIU modules on the same mobile module. Figure 1D This approach utilizes the same motion components, greatly simplifying the integration and measurement process. However, this integration has a negative impact on the TPT achieved, as the measurement head must sequentially traverse all IM sites and complete a complete IIU scan. Furthermore, due to the significantly heavier measurement head, this approach has the disadvantage of reducing measurement speed even for IM sites alone.

[0046] The negative impact of this approach on TPT can be mitigated to some extent if partial IIU coverage is allowed: the image area on the wafer can be restricted to only the areas that have been covered when the measurement head moves between IM sites.

[0047] Measures to mitigate the throughput impact of this approach include the use of detachable IIU units: the IM measurement head can perform the measurement process while the IIU head is placed at a designated location within the enclosure. When performing an IIU measurement, the measurement head travels to the location of the IIU head, picks it up, and performs the measurement. Conversely, during this exchange process, the IIU head can replace the IM measurement head. For example, see Figure 1E , the figure shows the movement of only the IIU head or the movement of both heads.

[0048] Flexible solution: By placing the IIU unit above the entrance of the measurement cell, it is ensured that the wafer passes under it when loaded by the robot (and is removed when unloaded). The IIU can perform imaging in one (or both) of these steps, similar to the external integration option described above. As mentioned above, this imaging will be affected by poor control of wafer speed and positioning, which will reduce the imaging quality, but it may be sufficient in some cases. When higher quality imaging is required, the same IIU can be moved above the wafer (for example, using "fly-by-wire integration").

[0049] Partial wafer coverage: By limiting the IIU measurement to a partial coverage of the wafer area, this integration challenge is significantly simplified. The IIU module can be significantly smaller and integrated into the free space of the measurement unit.

[0050] Specifically, the IIU module can be placed on a moving motor. When the IIU measurement is to be performed, the motor will position it above the wafer. When the IM measurement is to be performed, the IIU module will retract, allowing the IM measurement head to move freely above the wafer. For example, see Figure 1F .

[0051] exist Figures 1A to 1F , the following reference numerals are used: wafer 110, IIU head 120, IM head 130, linear mechanical stage 141, rotary mechanical stage 142, and selector 50 for selecting which head(s) are attached to the mechanical stage.

[0052] IIU measurements can be acquired using time allocated to other functions. For example, a "notch finder" process is typically performed before any IM measurements are taken. This involves rotating the wafer to find the notch at the edge of the wafer to properly orient the wafer. IIU measurements can be taken during these rotations (for example, covering a portion of the wafer from the edge to its center), allowing for large area coverage without compromising TPT.

[0053] The IIU module can be based on a variety of design concepts. Typically, the implementation will include the following key elements:

[0054] a. Illumination: It is best to provide a variety of different bandwidths with high intensity and high lighting stability to provide a high signal-to-noise ratio even with short acquisition times. Illumination can be based on a stroboscopic light source or a continuous light source.

[0055] b. Optics: These guide light from the light source to the wafer and reflect it back to the detection system. The optics can include an autofocus mechanism, but this can be omitted if the depth of focus is sufficiently large (thus reducing cost and complexity). In the current implementation, a telecentric, low-numerical aperture (low-NA) approach is used to achieve low-aberration, large-field-of-view imaging.

[0056] c. Detection: A variety of detectors can be implemented, including CCD, CMOS, and TDI-based cameras. The choice of the optimal detector will depend on other system attributes, required specifications, and the module's usage model.

[0057] Since the details of the specific implementation are secondary to the present invention, they will not be further described here.

[0058] Dual coverage metering agreement

[0059] The basic measurement flow required includes IM measurement and IIU measurement on the wafer. Several implementation possibilities offer different advantages and limitations:

[0060] a. Independent Flow: In this approach, IM and IIU measurements are performed independently. For example, IM measurements can follow a standard IM sampling scheme. IIU measurements will cover the entire wafer or areas of interest, depending on their speed.

[0061] b. "IM-First": In this flow, IM metrology is used to identify areas on the wafer suspected of requiring more intensive metrology coverage. For example, trends in POI values ​​can be identified, indicating that certain areas at the wafer edge are at risk of reaching process window limits. IIU measurements are performed on the priority areas identified during this first metrology flow.

[0062] c. "IIU First": First, IIU measurements are collected over a large area. Then, algorithmic analysis identifies variations in the fabricated structural features across the wafer. Based on these inputs, the IM sampling scheme is adjusted to perform more intensive measurements in areas where large variations are observed or where POI deviations are suspected.

[0063] d. IM head-to-tail measurement: An initial IM sampling is performed, followed by an IIU measurement. The IIU measurement can be determined by the IM measurement (as in the "IM-first" scenario) or not. Based on these two data sets, the algorithm interpretation layer (described in more detail below) creates a detailed POI map of the entire IIU measurement area. This map identifies anomalous POI values ​​or suspicious areas, prompting IM to perform additional, more intensive measurements. This process can be performed multiple times, providing increasingly accurate and intensive measurements in the most critical areas of the wafer.

[0064] Algorithm data fusion solution

[0065] Integrating information from IM and IIU is a challenging task, as the two datasets have completely different sensitivities. However, modern algorithms, often leveraging machine learning methods, offer significant potential in these tasks. The proposed algorithmic approach is based on the following structure.

[0066] Interpretation of IM measurements can be performed in the current conventional manner, separate from the unique challenges currently faced. While this is the simplest implementation, alternative approaches are discussed below.

[0067] Interpretation and large-scale analysis of IIU data:

[0068] a. A semiconductor wafer consists of a series of identically designed regions called "fields." Within each field, there may be several identically designed sub-regions called "die." These sub-regions are ultimately cut and packaged to produce the desired semiconductor chips. These dies are separated by thin regions called "streaks." Screak streets are ultimately cut to separate the individual dies, but during the manufacturing process, they carry multiple test structures used for metrology and process control.

[0069] b. Metrology is typically performed at dedicated metrology sites within the scribe lanes. In some cases (more common in memory device applications), some metrology can be performed at periodic regions within the die. Regardless of the specific measurement location, IM measurements provide information about the characteristics of the field (or die) being measured. In other words, IM metrology for field i involves a set of measurement spectra. Different spectra S i (λ) can represent different metrology channels (polarization, azimuth, angle of incidence) as well as different metrology sites associated with the same field. Typically, a small number of such spectra are collected per field, each containing roughly a thousand different wavelengths.

[0070] c. The IIU measurement is similarly split into data sets related to different fields on the wafer. For each field i, the IIU measurement can be obtained by Here, M(x) represents the field image at point x, and x represents a number of image pixels covering the field; multiple images can be taken with different spectral bandwidths, polarizations, etc.

[0071] d. The IM interpretation process provides the measured and the relevant POI value P (i) From this result, the IIU measurement is obtained With the same POI value P (i) The relationship between them.

[0072] e. Using this association, we can identify the transformation between IIU readings and POI values. We call this relationship "instant training."

[0073] f. The just-in-time training is then applied to all fields measured by the IIU, providing POI values ​​for most areas of the wafer (or the entire wafer).

[0074] While this basic principle is the core principle behind this invention, it can be further refined in several ways:

[0075] a. Initial training phase: The described method is based on identifying the relationship between the full-field IIU measurements and the corresponding POI values ​​provided by IM. However, identifying this relationship based on the limited dataset provided by IM measurements on a single wafer may not be reliable and robust enough.

[0076] b. The training protocol can be expanded by adding a preliminary phase during which several wafers are measured using both IM and IIU, and the relationship between the two is identified through algorithmic analysis. The results of this phase will then improve and stabilize the subsequent "just-in-time training" step. Various algorithmic approaches are known to solve this task, such as "dimensionality reduction" and "transfer learning."

[0077] c. Relying on an "upsampling" approach: Another approach to scaling IM measurements to full-wafer metrology, referred to as "sampling enhancement" or "upsampling," is proposed in U.S. Patent No. 11,093,840 and U.S. Provisional Patent No. 63 / 328,332. In this approach, extensive preliminary processing of IM measurements across multiple wafers is used to train a machine learning-based solution, which allows for a degree of scaling of IM results to the full wafer. The approach proposed in this invention relies on the "upsampling" results as initial guesses and guidance, significantly improving upon them by leveraging the additional information provided by the IIU. Furthermore, this approach significantly simplifies the initial training process, significantly reducing the number of samples required for training.

[0078] The joint integration of IM and IIU modules offers several potential benefits:

[0079] a. As mentioned above, the key benefit provided involves extending the IM measurement to a large area of ​​the wafer or the entire wafer, ideally providing IM level feedback for all fields on the wafer.

[0080] b. Residue Detection: Another potential benefit involves identifying material residues through IIU imaging. Combining this capability with IM metrology has significant benefits for various process control steps. For example, in CMP applications, this can enhance metrology solutions, enabling them to identify incomplete removal of polishing layers.

[0081] c. Macro scratch and macro defect detection: IIU can identify large scratches and defects generated during wafer processing.

[0082] d. This identification can be based on a variety of algorithmic approaches borrowed from the field of defect detection.

[0083] e. Although the optical quality of the IIU module cannot identify small defects and sub-micron scratches, it can be used to identify large defects.

[0084] f. Specific variations of optical implementations (e.g., dark-field imaging, cross-polarization imaging, etc.) may have significant advantages for this metrology and may be incorporated into IIU implementations.

[0085] g. System Health Monitoring: One concern when using IM metrology is that particles in the measurement system can fall onto the wafer surface and damage the fabricated device. A common solution to this problem is to add a transparent window between the optical layer and the wafer being measured. However, over time, particles can fall and accumulate on the window surface, adversely affecting the metrology quality at that location. This problem is typically addressed by periodically cleaning or replacing the window, a process that incurs cost and loss of tool availability, and which, in turn, may not be frequent enough to ensure measurement quality. The IIU can be used to map the window surface to identify any loss of transparency caused by particle accumulation. Possibly, a focusing mechanism could be added to enable the IIU module to image the window surface.

[0086] h. Notch finding capability of the IIU: During the introduction of the wafer into the IM enclosure, the wafer is typically rotated to align it with the measurement system. This alignment is typically achieved by identifying a notch located at a specific location on the edge of the wafer. This notch identification (a process known as “notch finding”) can be achieved in a variety of ways. The IIU can be used to achieve this goal, replacing other hardware designed for the same purpose. Additionally, while the wafer is rotated for notch finding, the IIU can collect measurements of the wafer surface, providing imaging metrology without TPT penalties.

[0087] In either of the above configurations, there is processing circuitry, Figure 1B 199. The processing circuit may be implemented as a central processing unit (CPU), and / or one or more other integrated circuits, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a full custom integrated circuit, etc., or a combination of such integrated circuits.

[0088] Figure 2 The diagram shows wafer 110, first region 181, second region 182, measurement sites 171'-175' within the first region, measurement sites 171-177 within the second region, and locations outside measurement site 179 (within the first and / or second regions). The IIU head captures images of the first and second regions. The IM head measures these measurement sites.

[0089] Figure 3 Shown are the first and second images (of the first and second regions) (labeled IIU image 181 and IIU image 182), measurements 190 of measurement sites (including measurements 184 (171')-184 (175') and 184 (171)-184 (177)), the measurement sites being contained in the first and / or second images and their pixels within the first and / or second images being labeled 183 (171')-183 (175') and 183 (171)-183 (177), respectively; also shown are the mappings between pixels and measurements 192, and estimated measurements outside of the measurement site 193.

[0090] Measurements and pixels associated with the same measurement site may be used for training and / or retraining and / or adjusting and / or testing the mapping.

[0091] Figure 4 A method 200 for operating an integrated assessment system is shown.

[0092] According to an embodiment, method 200 includes step 210: introducing, by a motion system of the integrated evaluation system, relative motion between the sample and at least one of an integrated metrology (IM) head of the integrated evaluation system or an integrated imaging unit (IIU) head of the integrated evaluation system.

[0093] According to an implementation, the method 200 includes step 220 : performing, by the IM head, measurements of a set of measurement sites of the sample.

[0094] According to an embodiment, the method 200 comprises step 230 : acquiring, by the IIU head, an image of a region of the sample including the measurement site; wherein the total area of ​​the region of the sample exceeds the total area of ​​the measurement site.

[0095] Step 230 may be performed after step 220 , before step 230 , or (at least partially) in parallel with step 230 .

[0096] Step 220 may be performed based on the result of step 230 , or may be performed regardless of the result of step 230 .

[0097] Step 230 may be performed based on the result of step 220 , or may be performed regardless of the result of step 220 .

[0098] According to an embodiment, method 200 includes determining, by the processing circuit, a region to be imaged during step 230 based on the set of measurements acquired during step 220. And step 230 includes acquiring, by the IIU head, an image of the region after determining the region.

[0099] According to an embodiment, method 200 comprises determining, by the processing circuit, measurement sites to be measured during step 220 based on the image of the area acquired during step 230. And step 220 comprises performing, by the IM head, the set of measurements after determining the area.

[0100] There may be any temporal relationship between the execution of step 210 and the execution of step 220 and / or step 230. The relative motion may be introduced before the execution of step 220, before the execution of step 230, between the execution of step 220 and the execution of step 230, between the execution of step 230 and the execution of step 220, at least partially overlapping with the execution of step 220, at least partially overlapping with the execution of step 230, and / or after the execution of at least one of steps 220 and 230.

[0101] According to an embodiment, steps 220 and 230 are followed by step 240 of receiving, by a processing circuit of the integrated evaluation system, the set of measurements and an image of the area.

[0102] According to an embodiment, step 240 is followed by step 250 of estimating measurement values ​​within the region but outside the measurement site using the mapping between the measurement and the image pixels corresponding to the measurement site. For example, the mapping can be applied to pixels outside the measurement site to provide an estimated measurement value. The relationship between the measurement result at the measurement site and the pixels at the measurement site can be used to validate the estimated measurement value and / or test the estimated measurement value and / or fine-tune the estimated measurement value.

[0103] Figure 5 and 6 An embodiment of a metrology system 40 (an embodiment of an MI module) and its environment, for example, an IM tool 31 integrated with an EFEM 30 of a processing tool (CMP polisher), is shown. Figure 6It is referenced in the figure at 70. Other environments may be provided, for example, another environment may not include the IM tool 31.

[0104] The environment also includes a robot 60 (shown holding a wafer 99) and an IM module 31 (or any other high resolution optical metrology process, where "high" refers to a higher resolution than the process performed by the optical metrology system 40) having a chamber 35 configured to receive the wafer 99 from the robot, perform a high resolution spectroscopic reflectance measurement process, and then return the wafer to the robot.

[0105] The robot may place the wafer into one or more wafer pods (FOUPs) 62 , 63 , and 64 of the EFEM 30 and / or provide the wafer to another tool, such as a polisher 74 .

[0106] The robot 60 can be part of the EFEM and can travel within it. The wafer cassette and the IM tool can be connected to the EFEM through ports / openings. The IM tool is typically fixedly connected using six bolts, while the wafer cassette is placed on a so-called load port that supports them. The metrology system 40 is assembled between the IM module 31 and the EFEM. The metrology system 40 can be aligned along the Z axis according to the Z axis position of the robot arm (part or all of it can be configured to be adjustable during installation, for example, according to the Z axis position of the wafer on the robot arm).

[0107] The optical metrology system 40 is positioned to perform metrology when wafers are loaded into the IM module 31 by the robot 60 and / or when wafers are unloaded from the IM module 31 .

[0108] The optical metrology system 40 may be an additional system, and its shape and size should be determined based on the size constraints of other structural elements in the environment (eg, configured to be installed between the EFEM and the IM module 31).

[0109] The metrology system 40 can be configured as a "frame-like" structure surrounding an opening / port, with optics / lighting located on top, and the connection between the IM tool and the EFEM at least partially sealed. The metrology system 40 can be connected to the control unit / computer of the IM module 31, or an additional independent control unit / computing device for the metrology system 40 can be housed inside or outside the IM tool.

[0110] Figure 7An embodiment of a metrology system 40, a spectroscopic reflectance measurement tool 31 ' (an embodiment of an IIU module) and its chamber 35 are shown in front and side views. The metrology system 40 is compact and its dimensions (width and / or height and / or depth and / or portion extending outside the spectroscopic reflectance measurement tool) may be much less than one meter. For example, the portion of the metrology system 40 extending outside the spectroscopic reflectance measurement tool may be 5-15 cm (or more) and its width and height may be approximately 25-45 cm, and so on. Figure 4 In some embodiments, at least a portion of the measurement system 40 is located within the spectroscopic reflectance measurement tool 31 ′.

[0111] The spectral reflectance measurement tool 31 ' may further process the results of the metrology system 40 for various purposes, such as calibration, validation, selecting sites to be evaluated (where the results of the metrology system 40 may indicate the presence of problems, deviations from specifications, etc.).

[0112] In the above detailed description, numerous specific details have been set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other cases, well-known methods, processes, and components have not been described in detail in order to avoid obscuring the present invention.

[0113] The subject matter relating to the present invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, the invention as to its organization, method of operation, together with objects, features and advantages thereof, will be best understood from the following detailed description when read in connection with the accompanying drawings.

[0114] It should be understood that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, where deemed appropriate, reference numerals may be reused in the figures to indicate corresponding or similar elements.

[0115] Since the illustrated embodiments of the present invention can be implemented for the most part using electronic components and circuits known to those skilled in the art, no more details will be explained than necessary as described above in order to understand and appreciate the basic concepts of the present invention and to avoid obscuring or distracting from the teachings of the present invention.

[0116] Any reference in the specification to a method shall apply mutatis mutandis to a system capable of performing the method and shall apply mutatis mutandis to a non-transitory computer-readable medium storing instructions that, when executed by a computer, result in the performance of the method.

[0117] Any reference in the specification to a system shall apply mutatis mutandis to a method executable by the system and shall apply mutatis mutandis to a non-transitory computer-readable medium storing instructions executable by the system.

[0118] Any reference in the specification to a non-transitory computer-readable medium shall apply, mutatis mutandis, to a system capable of executing instructions stored in the non-transitory computer-readable medium, and shall apply, mutatis mutandis, to a method executable by a computer that reads the instructions stored in the non-transitory computer-readable medium.

[0119] The present invention may also be implemented as a computer program running on a computer system, the program comprising at least the following code portions: when run on a programmable device (such as a computer system), the program performs the steps of the method according to the present invention; or enables the programmable device to perform the functions of the apparatus or system according to the present invention. The computer program may cause a storage system to assign a disk drive to a disk drive group.

[0120] A computer program is a listing of instructions, such as a specific application program and / or an operating system. A computer program may comprise, for example, one or more of the following: a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, source code, object code, a shared / dynamically loadable library, and / or other instruction sequences designed for execution on a computer system.

[0121] The computer program may be stored internally on a non-transitory computer-readable medium. All or part of the computer program may be provided permanently, removably, or remotely on a computer-readable medium coupled to an information processing system. Computer-readable media may include, for example, but not limited to, any number of the following: magnetic storage media, including magnetic disk and tape storage media; optical storage media, such as optical disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; non-volatile storage media, including semiconductor-based storage units, such as flash memory, EEPROM, EPROM, ROM; ferromagnetic digital memory; magnetoresistive random access memory; MRAM; volatile storage media, including registers, buffers or caches, main memory, RAM, etc.

[0122] A computer process typically consists of the program or portion of a program being executed (running), current program values ​​and state information, and the resources used by the operating system to manage process execution. An operating system (OS) is software that manages the sharing of a computer's resources and provides programmers with an interface for accessing those resources. The OS processes system data and user input and responds by allocating and managing tasks and internal system resources as services to system users and programs.

[0123] A computer system may, for example, include at least one processing unit, associated memory, and a plurality of input / output (I / O) devices.When executing a computer program, the computer system processes information according to the computer program and produces resultant output information via the I / O devices.

[0124] In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims.

[0125] Furthermore, the terms "front," "rear," "top," "bottom," "above," "below," and the like, if any, in the description and claims are used for descriptive purposes and are not necessarily intended to describe permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that, for example, the embodiments of the invention described herein are capable of operation in other orientations than shown or described herein.

[0126] Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative, and that alternative implementations may merge logic blocks or circuit elements, or employ another functional decomposition of the various logic blocks or circuit elements. Therefore, it should be understood that the architectures described herein are merely exemplary, and that many other architectures that achieve the same functionality may be implemented.

[0127] Any arrangement of components capable of achieving the same functionality is effectively "associated" to achieve the intended functionality. Thus, any two components described herein that are combined to achieve a particular functionality may be considered "associated" with each other to achieve the intended functionality, regardless of their architecture or intervening components. Similarly, any two components so associated may also be considered "operably connected" or "operably coupled" to each other to achieve the intended functionality.

[0128] Furthermore, those skilled in the art will recognize that the boundaries between the above-described operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be divided into multiple operations, and operations may be performed at least partially overlapping in time. Furthermore, alternative embodiments may include multiple instances of a particular operation, and in various other implementations, the order of the operations may be changed.

[0129] Furthermore, for example, in one embodiment, the illustrated embodiments may be implemented as circuits located on a single integrated circuit or within the same device. Alternatively, the embodiments may be implemented as any number of separate integrated circuits or separate devices interconnected in a suitable manner.

[0130] Furthermore, for example, embodiments or portions thereof may be implemented as soft or code representations of physical circuitry, or may be converted into logical representations of physical circuitry, for example using any suitable type of hardware description language. Furthermore, the present invention is not limited to physical devices or units implemented in non-programmable hardware, but may also be applied to programmable devices or units capable of performing desired device functions by operating according to suitable program code, such as mainframes, minicomputers, servers, workstations, personal computers, notebooks, personal digital assistants, electronic games, automobiles and other embedded systems, cell phones and various other wireless devices, which are generally referred to in this application as "computer systems."

[0131] However, other modifications, changes, and substitutions are possible. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0132] In the claims, any reference signs placed between brackets should not be interpreted as limiting the claims. The word "comprising" does not exclude the presence of other elements or steps other than those listed in the claim. In addition, the terms "a" or "an" as used herein are defined as one or more. Similarly, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as meaning that any particular claim containing such introduced claim elements by introducing another claim element with the indefinite article "a" or "an" should be limited to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an". The same applies to the use of definite articles. Unless otherwise specified, terms such as "first" and "second" are only used to arbitrarily distinguish the elements they describe. Therefore, these terms are not necessarily intended to indicate the time or other priority of such elements. The fact that certain measures are listed in different claims does not mean that the combination of these measures cannot be used advantageously.

[0133] While certain features of the present invention have been shown and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is therefore intended that the appended claims cover all such modifications and changes that fall within the true spirit of the invention.

Claims

1. An integrated evaluation system comprising: Integrated metering (IM) head; Integrated Imaging Unit (IIU) head; a motion system configured to introduce relative motion between a sample and at least one of the IM head or the IIU head; as well as processing circuit; wherein the IM head is configured to perform measurements on a set of measurement sites of the sample; wherein the IIU head is configured to acquire an image of a region of the sample including the measurement sites; wherein a total area of ​​the regions of the sample exceeds a total area of ​​the measurement sites; Wherein, the processing circuit is configured to: (i) receiving the set of measurements and an image of the area; and (ii) using a mapping between the measurements and pixels of the image corresponding to the measurement site to estimate the value of the measurements that are within the region and outside the measurement site.

2. The integrated evaluation system of claim 1, configured to perform a first measurement phase and a second measurement phase; in, During the first measurement phase, the IM head is configured to perform measurements of a first measurement site of the set located within a first portion of the sample, and the IIU head is configured to acquire an image of a second area located within a second portion of the sample; wherein, during the second measurement phase: the IM head is configured to perform a measurement of a second measurement site in the group located within a second portion of the sample, and the IIU head is configured to acquire an image of a first area located within a first portion of the sample; Therein, the motion system is configured to introduce the relative motion between the end of the first measurement phase and the beginning of the second measurement phase.

3. The integrated evaluation system according to claim 2, wherein: The movement is a rotational movement.

4. The integrated evaluation system according to claim 2, wherein: The movement is a combination of a rotational movement and another movement.

5. The integrated evaluation system according to claim 1, wherein: The motion system is configured to induce relative motion between the sample and the IM head and the IIU head while maintaining a spatial relationship between the IM head and the IIU head.

6. The integrated assessment system according to claim 1, wherein: The motion system is configured to move different ones of the IM head and the IIU head relative to the sample at different points in time.

7. The integrated assessment system according to claim 1, wherein: The motion system is configured to: At a first point in time, moving only one of the IM head and the IIU head relative to the sample; and At a second point in time, both the IM head and the IIU head are moved.

8. The integrated assessment system according to claim 1, wherein: The area of ​​the sample covers the entirety of the sample.

9. The integrated assessment system according to claim 1, wherein: The IM head is configured to acquire images of the region and perform the set of measurements independently of the IIU head.

10. The integrated assessment system according to claim 1, wherein: The processing circuitry is configured to determine the region based on the set of measurements, and the IIU head is configured to acquire an image of the region after determining the region.

11. The integrated assessment system according to claim 1, wherein: The processing circuit is configured to determine the measurement site based on an image of the area, and the IM head is configured to perform the set of measurements after determining the area.

12. The integrated assessment system according to claim 1, wherein: The processing circuit is configured to determine additional measurement sites based on the image of the region and the measurement sites, and wherein the IM head is configured to perform measurements of the additional measurement sites after determining the additional measurement sites.

13. The integrated assessment system according to claim 1, wherein: The processing circuit is configured to apply a machine learning process to estimate measurement values ​​within the region and outside the measurement site.

14. The integrated assessment system according to claim 1, wherein: The measurements of the set of measurement sites on the sample are optical critical dimension measurements.

15. A non-transitory computer-readable medium storing instructions that, when executed by an integrated assessment system, cause the integrated assessment system to: relative motion between a sample and at least one of an integrated metrology (IM) head of the integrated evaluation system or an integrated imaging unit (IIU) head of the integrated evaluation system, introduced by a motion system of the integrated evaluation system; performing, by the IM head, measurements on a set of measurement sites of the sample; Acquiring an image of a region of the sample including the measurement site by the IIU head; wherein a total area of ​​the region of the sample exceeds a total area of ​​the measurement site; receiving, by processing circuitry of the integrated assessment system, the set of measurements and the image of the area; and The mapping between the measurements and pixels of the image corresponding to the measurement sites is used to estimate measurement values ​​within the region and outside the measurement sites.

16. The non-transitory computer-readable medium according to claim 15, storing instructions for: determining, by the processing circuit, an additional measurement site based on the image of the region and the measurement site, and performing, by the IM head, measurement of the additional measurement site after determining the additional measurement site.

17. A method for operating an integrated assessment system, the method comprising: relative motion between a sample and at least one of an integrated metrology (IM) head of the integrated evaluation system or an integrated imaging unit (IIU) head of the integrated evaluation system, introduced by a motion system of the integrated evaluation system; performing, by the IM head, measurements on a set of measurement sites of the pair of samples; Acquiring an image of a region of the sample including the measurement site by the IIU head; wherein a total area of ​​the region of the sample exceeds a total area of ​​the measurement site; receiving, by processing circuitry of the integrated assessment system, the set of measurements and the image of the area; and The mapping between the measurements and pixels of the image corresponding to the measurement sites is used to estimate measurement values ​​within the region and outside the measurement sites.

18. The method according to claim 17, comprising: The region is determined by the processing circuit based on the set of measurements, and after determining the region, an image of the region is acquired by the IIU head.

19. The method according to claim 17, comprising: The measurement sites are determined by the processing circuit based on an image of the area, and after determining the area, the set of measurements is performed by the IM head.

20. The method of claim 17, comprising: determining, by the processing circuit, additional measurement locations based on the image of the region and the measurement locations; And after determining the additional measurement site, the IM head performs measurement on the additional measurement site.

Images