Storage device, electronic apparatus, and method of controlling storage device

Abstract

A memory device according to an embodiment of the present disclosure includes: a magnetoresistive element whose resistance value is variable; a selection element connected to the magnetoresistive element; and a write circuit including a load resistance circuit having a variable resistance value, in which the write circuit applies a voltage to the magnetoresistive element via the load resistance circuit.

Description

Technical Field

[0001] The present disclosure relates to a storage device, an electronic device, and a method of controlling the storage device. Background Art

[0002] The state of a magnetoresistive random access memory (MRAM) using a magnetoresistive element is maintained by the magnetization state of a ferromagnetic substance, making the MRAM non-volatile, wherein data is retained even when the power is disconnected. Examples of MRAM include VC-MRAM using voltage-controlled magnetic anisotropy (VCMA). For example, Patent Document 1 discloses a technology for reversing magnetization by applying a pulse voltage to a magnetoresistive element having a VCMA effect. In Patent Document 1, an initial read is performed as the first process after starting writing.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: JP 2018-92696A

[0006] Non-patent literature

[0007] Non-patent literature 1: YCWu et al., "Deterministic and field-free voltage-controlled MRAM for high performance and low power applications", 2020IEEESymposium on V L SI Technology, July 16, 2020 Summary of the Invention

[0008] Technical issues

[0009] Unfortunately, in the technique described in Patent Document 1, the initial read operation prolongs the overall write process. Therefore, it is desirable to omit the initial read operation. However, omitting the initial read operation can lead to erroneous writes and degrade data writing accuracy. Furthermore, the technique described in Patent Document 1 makes it difficult to properly control the pulse width required for magnetization reversal in the pulse voltage, making it difficult to accurately apply the pulse voltage to the magnetoresistive element. Consequently, data writing accuracy degrades.

[0010] Therefore, the present disclosure provides a storage device, an electronic device, and a method of controlling the storage device capable of improving data writing accuracy.

[0011] Solution to the problem

[0012] A memory device according to one aspect of the present disclosure includes: a magnetoresistive element having a variable resistance value; a selection element connected to the magnetoresistive element; and a write circuit including a load resistance circuit having a variable resistance value through which a voltage is applied to the magnetoresistive element.

[0013] An electronic device according to one aspect of the present disclosure includes a storage device for storing data, wherein the storage device includes: a magnetoresistive element having a variable resistance value; a selection element connected to the magnetoresistive element; and a write circuit including a load resistance circuit having a variable resistance value, applying a voltage to the magnetoresistive element via the load resistance circuit.

[0014] A method of controlling a memory device according to aspects of the present disclosure includes controlling a memory device including: a magnetoresistive element having a variable resistance value; and a selection element connected to the magnetoresistive element, wherein a write circuit applies a voltage to the magnetoresistive element via a load resistance circuit having a variable resistance value. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A configuration example of the storage device according to the first embodiment is shown.

[0016] Figure 2 A configuration example of the memory cell according to the first embodiment is shown.

[0017] Figure 3 Configuration examples of various circuits including the load resistance circuit according to the first embodiment are shown.

[0018] Figure 4 is a flowchart showing the write process according to the first embodiment.

[0019] Figure 5 is a timing chart showing a write process to a high resistance according to the first embodiment.

[0020] Figure 6 is a timing chart showing a write process to a low resistance according to the first embodiment.

[0021] Figure 7 is a graph showing the voltage dependency of the perpendicular magnetic anisotropy (constant) of the magnetoresistive element according to the first embodiment.

[0022] Figure 8 The voltage division in the case where a voltage is applied to the magnetoresistive element via the fixed resistor R1 or R2 according to the first embodiment is shown.

[0023] Figure 9 The behavior of the magnetization vector caused by voltage application via the fixed resistor R1 according to the first embodiment is shown.

[0024] Figure 10 The behavior of the magnetization vector caused by voltage application via the fixed resistor R2 according to the first embodiment is shown.

[0025] Figure 11 A configuration example of a storage device according to Modification 1 of the first embodiment is shown.

[0026] Figure 12 A configuration example of a memory cell array of a memory device according to Modification 2 of the first embodiment is shown.

[0027] Figure 13 is a flowchart illustrating a write process according to the second embodiment.

[0028] Figure 14 is a timing chart showing a write process to a high resistance according to the second embodiment.

[0029] Figure 15 is a timing chart showing a write process to a low resistance according to the second embodiment.

[0030] Figure 16 : is a flowchart showing a write process according to Modification 1 of the second embodiment.

[0031] Figure 17 : is a flowchart showing a write process according to Modification 2 of the second embodiment.

[0032] Figure 18 A configuration example of a load resistance circuit according to the third embodiment is shown.

[0033] Figure 19 is a timing chart showing a write process to a high resistance according to the third embodiment.

[0034] Figure 20 is a timing chart showing a write process to a low resistance according to the third embodiment.

[0035] Figure 21 is a flowchart showing a write process according to the fourth embodiment.

[0036] Figure 22 : is a timing chart showing a write process to a high resistance according to the fourth embodiment.

[0037] Figure 23 is a timing chart showing a write process to a low resistance according to the fourth embodiment.

[0038] Figure 24 A configuration example of a load resistance circuit of a storage device according to a fifth embodiment is shown.

[0039] Figure 25 is a flowchart showing a write process according to the fifth embodiment.

[0040] Figure 26 is a timing chart showing the write process according to the fifth embodiment.

[0041] Figure 27 is a graph showing characteristics of the magnetoresistive element according to the fifth embodiment.

[0042] Figure 28 is a graph showing the voltage dependency of the perpendicular magnetic anisotropy (constant) of the magnetoresistive element according to the fifth embodiment.

[0043] Figure 29 The voltage division in the case where a voltage is applied to the magnetoresistive element via the fixed resistor R4 according to the fifth embodiment is shown.

[0044] Figure 30 The voltage change of the magnetoresistive element according to the fifth embodiment is shown.

[0045] Figure 31 Shown are simulation results in the case where a pulse voltage is applied to the magnetoresistive element in the high-resistance state or the low-resistance state according to the fifth embodiment via the fixed resistor R4.

[0046] Figure 32 : is a flowchart showing a write process according to Modification 1 of the fifth embodiment.

[0047] Figure 33 is a flowchart showing a write process according to the sixth embodiment.

[0048] Figure 34 is a timing chart showing a write process according to the sixth embodiment.

[0049] Figure 35 The voltage change of the magnetoresistive element according to the sixth embodiment is shown.

[0050] Figure 36 is a flowchart showing a write process according to the seventh embodiment.

[0051] Figure 37 is a timing chart showing a write process according to the seventh embodiment.

[0052] Figure 38 The voltage change of the magnetoresistive element according to the seventh embodiment is shown.

[0053] Figure 39 is a timing chart showing a write process according to the eighth embodiment.

[0054] Figure 40An example of a schematic configuration of an imaging device is shown.

[0055] Figure 41 An example of a schematic configuration of a distance measuring device is shown. DETAILED DESCRIPTION

[0056] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments also include examples and variations. It should be noted that the devices, apparatuses, methods, etc. according to the embodiments of the present disclosure are not limited to the embodiments of the present disclosure. In addition, in the following embodiments, substantially the same components are marked with the same reference numerals, and repeated descriptions are omitted.

[0057] The following or multiple embodiments can be implemented independently of each other. Conversely, at least a portion of the following multiple embodiments can be appropriately combined with at least a portion of other embodiments to be implemented. These multiple embodiments may include different novel features. Therefore, they can help achieve different objectives or solve different problems and can produce different effects. It should be noted that the effects in the embodiments are merely examples and not limitations. Other effects may be exhibited.

[0058] The present disclosure will be described in the following order.

[0059] 1. First Implementation

[0060] 1-1. Storage Device Configuration Example

[0061] 1-2. Storage Unit Configuration Example

[0062] 1-3. Configuration Examples of Various Circuits Including Load Resistance Circuits

[0063] 1-4. Example of writing process

[0064] 1-5. Example of a timing diagram for write processing

[0065] 1-6. Example of Voltage Dependence of Perpendicular Magnetic Anisotropy of Magnetoresistive Element

[0066] 1-7. Example of load voltage-dividing resistor

[0067] 1-8. Example of Behavior of Magnetization Vector Caused by Voltage Application via Load Resistor 1-9. Modification 1 of Memory Device

[0068] 1-10. Modification 2 of Storage Device

[0069] 2. Second Implementation

[0070] 2-1. Example of writing process

[0071] 2-2. Example of a timing diagram for write processing

[0072] 2-3. Modification 1 of Write Process

[0073] 2-4. Modification 2 of Write Process

[0074] 3. Third Implementation

[0075] 3-1. Load resistance circuit configuration example

[0076] 3-2. Example of a timing diagram for write processing

[0077] 4. Fourth Implementation

[0078] 4-1. Example of writing process

[0079] 4-2. Example of a timing diagram for write processing

[0080] 5. Fifth embodiment

[0081] 5-1. Storage device configuration example

[0082] 5-2. Example of writing process

[0083] 5-3. Example of a timing diagram for write processing

[0084] 5-4. Example of Characteristics of Magnetoresistive Elements

[0085] 5-5. Example of Voltage Dependence of Perpendicular Magnetic Anisotropy of Magnetoresistive Element

[0086] 5-6. Example of load voltage-dividing resistor

[0087] 5-7. Example of Voltage Change in Magnetoresistive Element

[0088] 5-8. Example of written simulation results

[0089] 5-9. Modification 1 of Write Process

[0090] 6. Sixth Implementation

[0091] 6-1. Example of writing process

[0092] 6-2. Example of a timing diagram for write processing

[0093] 6-3. Example of Voltage Change in Magnetoresistive Element

[0094] 7. Seventh Implementation

[0095] 7-1. Example of writing process

[0096] 7-2. Example of a timing diagram for write processing

[0097] 7-3. Example of Voltage Change of Magnetoresistive Element

[0098] 8. Eighth Implementation

[0099] 8-1. Example of a timing diagram for write processing

[0100] 9. Functions and effects according to various embodiments

[0101] 10. Other Implementation Methods

[0102] 11. Configuration Examples of Electronic Devices

[0103] 11-1. Imaging Device

[0104] 11-2. Distance measuring device

[0105] 12. Appendix

[0106] <1. First embodiment>

[0107] <1-1. Configuration Example of Storage Device>

[0108] Will refer to Figure 1 A configuration example of the storage device 100 according to the first embodiment is described. Figure 1 A configuration example of the storage device 100 according to the first embodiment is shown.

[0109] like Figure 1 As shown, the memory device 100 includes a memory cell array 1. The memory device 100 is an example of a memory device that stores data by the magnetization direction of a magnetic substance.

[0110] The memory cell array 1 includes a plurality of memory cells 10 arranged two-dimensionally. These memory cells 10 are connected to bit lines BL, source lines SL, and word lines WL. For example, the word lines WL are arranged to extend in the row direction. The bit lines BL and the source lines SL are arranged to extend in the column direction. The bit lines BL, source lines SL, and word lines WL serve as control lines.

[0111] Each memory cell 10 includes a magnetoresistive element (MR element) 11 and a selection element 12. A MR element, such as a magnetic tunnel junction (MTJ), can be used as the MR element 11. The selection element 12 is connected to one end of the MR element 11 and controls the application of voltage or current to the MR element 11. For example, various transistors can be used as the selection element 12.

[0112] Note that each memory cell 10 shares one source line SL with every two other memory cells 10 in the column direction. That is, each of the memory cells 10 arranged in two lines in the column direction is connected to two bit lines BL and one source line SL (2BL / 1SL).

[0113] The memory device 100 includes a peripheral circuit 20 in addition to the memory cell array 1. Figure 1 In the example of FIG, the peripheral circuit 20 includes an I / O 21, a control circuit 22, a voltage generating circuit 23, a write circuit 24, a read circuit 25, a bit line address decoder 26, a bit line control circuit 27, a word line address decoder 28, a word line control circuit 29, and a sense amplifier 30. The bit line control circuit 27 is connected to the bit line BL. The word line control circuit 29 is connected to the word line WL. The sense amplifier 30 is connected to the source line SL. Since this basic configuration of a memory is well known, it will be briefly described.

[0114] The I / O 21 enables exchanges of commands related to reading and writing of data, addresses of memory cells 10 to be accessed, data, etc. between an external circuit (eg, CPU) of the memory device 100 and the control circuit 22 of the memory device 100 .

[0115] The control circuit 22 performs control related to writing and reading data into and from the memory cell 10 according to commands.

[0116] The voltage generating circuit 23 generates a voltage (for example, a pulse voltage) for reading and writing data from and to the memory cell 10. Note that voltages required for circuit operation are given separately.

[0117] The write circuit 24 controls the voltage and current (eg, pulse voltage and pulse current) for writing data to the memory cell 10. The write circuit 24 functions as a write unit. The write circuit 24 includes a load resistance circuit 241. Details of the load resistance circuit 241 will be described later.

[0118] The read circuit 25 controls a voltage (for example, a pulse voltage) for reading data from the memory cell 10, specifically, detection of the resistance value of the magnetoresistive element 11. The read circuit 25 functions as a read unit.

[0119] The bit line address decoder 26 obtains the address of the bit line BL corresponding to the address received by the above-mentioned I / O 21.

[0120] The bit line control circuit 27 selectively controls the bit line BL corresponding to the address of the bit line address decoder 26. For example, data writing to the memory cell 10 by the write circuit 24 and data reading from the memory cell 10 by the read circuit 25 are performed via the bit line control circuit 27.

[0121] The word line address decoder 28 obtains the address of the word line WL corresponding to the address received by the above-mentioned I / O 21.

[0122] The word line control circuit 29 selectively controls the word line WL corresponding to the address of the word line address decoder 28 .

[0123] The read amplifier 30 detects data read from the memory cell 10 by the read circuit 25 , specifically, the resistance value of the magnetoresistive element 11 .

[0124] <1-2. Storage Unit Configuration Example>

[0125] Will refer to Figure 2 A configuration example of the storage unit 10 according to the first embodiment is described. Figure 2 A configuration example of the storage unit 10 according to the first embodiment is shown.

[0126] like Figure 2 As shown, the memory cell 10 includes a magnetoresistive element 11 and a selection element 12. The magnetoresistive element 11 and the selection element 12 are connected in series between the bit line BL and the source line SL. Figure 2 In the example of FIG, the voltage that can be applied to the memory cell 10 and the load resistance circuit 241 is referred to as voltage V. Voltage V is generated by the write circuit 24, the read circuit 25 (see FIG. Figure 1 ) and is applied to the memory cell 10 via the load resistance circuit 241. That is, the voltage V is applied to the memory cell 10 including the load resistance circuit 241. In addition, the resistance value of the selection element 12 is much smaller than the resistance values ​​of the magnetoresistive element 11 and the load resistance circuit 241.

[0127] The magnetoresistive element 11 is, for example, an MTJ element having a VCMA effect and has a stacked structure. Figure 2 In the example, for ease of description, an XYZ coordinate system for the magnetoresistive element 11 is shown. The X-axis direction and the Y-axis direction correspond to the layer plane direction. The X-axis direction, the Y-axis direction, and the XY plane direction can be referred to as horizontal directions. The Z-axis direction corresponds to a direction perpendicular to the layer plane direction (stack direction). The Z-axis direction can be referred to as a vertical direction.

[0128] The magnetoresistive element 11 includes a fixed layer 111, a tunnel barrier layer 112, a recording layer 113, and a plurality of magnetic field generating layers 114 and 115. In this example, the magnetic field generating layer 115, the fixed layer 111, the tunnel barrier layer 112, the recording layer 113, and the magnetic field generating layer 114 are stacked in this order in the positive direction of the Z axis. Various known materials can be used as the materials of the layers. Only one of the magnetic field generating layers 114 and 115 may be provided.

[0129] The pinned layer 111 is a magnetic layer whose magnetization direction is fixed, and is also called a reference layer, etc. For example, the magnetization of the pinned layer 111 is fixed in the positive Z-axis direction.

[0130] The tunnel barrier layer 112 is a non-magnetic layer provided between the pinned layer 111 and the recording layer 113 .

[0131] The recording layer 113 is a magnetic layer whose magnetization direction changes, and is also called a free layer, etc. For example, the magnetization of the recording layer 113 changes between the Z-axis positive direction and the Z-axis negative direction.

[0132] It should be noted that the fixed layer 111 and the recording layer 113 may be Figure 2 In this case, the recording layer 113, the tunnel barrier layer 112, and the pinned layer 111 are stacked in this order in the positive Z-axis direction.

[0133] The magnetic field generating layer 114 generates a horizontal magnetic field. That is, the memory cell 10 is configured so that the recording layer 113 is placed in a magnetic field (horizontal magnetic field) in the layer plane direction (XY plane direction). Figure 2 In the example of FIG. 1 , the magnetic field generating layer 114 is provided on the opposite sides of the tunnel barrier layer 112 with the recording layer 113 sandwiched therebetween.

[0134] Note that the magnetic field generating layer 114 can be provided on opposite sides of the tunnel barrier layer 112, with the fixed layer 111 sandwiched therebetween. Furthermore, a method other than the magnetic field generating layer 114 can be used to generate a horizontal magnetic field. For example, a magnetic field can be generated by forming a magnetic layer above (on the positive Z-axis side) or below (on the negative Z-axis side) the magnetoresistive element 11. A magnetic field can also be generated by circumferentially arranging permanent magnets.

[0135] The magnetic field generating layer 115 generates a perpendicular magnetic field. That is, the memory cell 10 is configured so that the recording layer 113 is also placed in a magnetic field (perpendicular magnetic field) in a direction perpendicular to the layer plane direction (Z-axis direction). Figure 2 In the example of FIG. 1 , the magnetic field generating layer 115 is provided on opposite sides of the tunnel barrier layer 112 with the pinned layer 111 sandwiched therebetween.

[0136] Note that the magnetic field generating layer 115 is provided on opposite sides of the tunnel barrier layer 112, with the recording layer 113 sandwiched therebetween. Furthermore, a method other than the magnetic field generating layer 115 can be used to generate a perpendicular magnetic field. For example, a magnetic field can be generated by forming a magnetic layer above (on the positive Z-axis side) or below (on the negative Z-axis side) the magnetoresistive element 11. A magnetic field can also be generated by arranging permanent magnets on the periphery.

[0137] The selection element 12 is, for example, a field effect transistor (FET). One of the drain and source terminals of the selection element 12 is connected to the magnetoresistive element 11. The other of the drain and source terminals of the selection element 12 is connected to the source line SL. The gate terminal of the selection element 12 is connected to the word line WL. When a voltage signal from the word line WL is applied to the gate of the selection element 12 and the selection element 12 is turned on (the drain and source enter a conductive state), the magnetoresistive element 11 is connected to the bit line BL and the source line SL, and a voltage V is applied to the magnetoresistive element 11.

[0138] By L ) and high resistance state (high resistance value R H ) to write data (e.g., 0 or 1) to the memory cell 10. In the low resistance state, the magnetization of the fixed layer 111 is parallel to the magnetization of the recording layer 113. In the high resistance state, the magnetization of the fixed layer 111 is antiparallel to the magnetization of the recording layer 113. For example, by reversing the magnetization direction of the recording layer 113 between the positive Z-axis direction and the negative Z-axis direction, the resistance state of the magnetoresistive element 11 is switched between the low resistance state and the high resistance state. For example, the data corresponding to the low resistance state is 0, and the data corresponding to the high resistance state is 1. The magnetoresistive element 11 is, for example, an MTJ element capable of reversing the magnetization of the recording layer 113 by using the VCMA effect.

[0139] Furthermore, in the magnetoresistive element 11, not only a horizontal magnetic field but also a vertical magnetic field is used. The vertical magnetic field causes the magnetization component m of the recording layer 113 to Z The change of magnetic field energy from (-1 to 1) is asymmetric. By design, the magnetic field energy is Z Negative (-1≤magnetization component m Z <0), that is, when the magnetization of the recording layer 113 is minimized at a position close to the negative direction of the Z axis, oscillation in the magnetization direction can be suppressed, and the magnetization direction can be reversed in the negative direction of the Z axis. The resistance value R of the magnetoresistive element 11 can be set to a high resistance value R without having to control the pulse width of the voltage V with high precision. H .

[0140] As described above, the magnetoresistive element 11 has a basic sandwich structure in which a non-magnetic thin film of an insulator is sandwiched between two magnetic layers including a thin film of a magnetic substance. This structure is called a magnetic tunnel junction (MTJ). Since the non-magnetic thin film has an extremely small thickness of about a few nanometers, a tunnel current flows when a voltage is applied to both ends of the element. The characteristic is that the magnitude of the tunnel current depends on the relative angle between the magnetizations of the two magnetic layers. This is called the tunnel magnetoresistance (TMR) effect. In MRAM, the magnetization of one of the two magnetic layers (the fixed layer 111) is fixed, and the magnetization of the other (the recording layer 113) is controlled by an external field. Examples of external fields for magnetization direction control include methods using voltage-controlled magnetic anisotropy (VCMA). The TMR effect is used for reading the state.

[0141] <1-3. Configuration Examples of Various Circuits Including Load Resistance Circuit>

[0142] Will refer to Figure 3 Configuration examples of various circuits including the load resistance circuit 241 according to the first embodiment are described. Figure 3 There is shown a configuration example of various circuits including the load resistance circuit 241 according to the first embodiment.

[0143] like Figure 3 As shown, the load resistance circuit 241 includes a plurality of fixed resistors R1 and R2 and a switch SW1 . The load resistance circuit 241 is provided in a wiring path between the voltage generation circuit 23 and the bit line control circuit 27 .

[0144] Each of the fixed resistors R1 and R2 functions as a load resistor. The resistance value of the fixed resistor R1 is smaller than the resistance value of the fixed resistor R2 (R1 < R2). The switch SW1 receives a switching signal from the control circuit 22 to switch the wiring path. For example, the switch SW1 switches between a wiring path passing through the fixed resistor R1 and a wiring path passing through the fixed resistor R2. That is, the load resistance circuit 241 can switch between the wiring paths passing through the fixed resistors R1 and R2 using the switch SW1, and can be connected to the voltage generation circuit 23 and the bit line control circuit 27.

[0145] The load resistance circuit 241 switches and uses fixed resistors R1 and R2 as described above, and makes the resistance value variable. That is, the load resistance circuit 241 has a function of setting a plurality of different resistance values. When the resistance value of the magnetoresistive element 11 is set to a low resistance value R L When writing with low resistance, the load resistance circuit 241 applies a voltage V to the magnetoresistive element 11 via the fixed resistor R1. When the resistance value of the magnetoresistive element 11 is set to a high resistance value R HWhen writing to high resistance, that is, when writing to high resistance, the load resistance circuit 241 applies voltage V to the magnetoresistive element 11 via the fixed resistor R2. The magnitude of voltage V when writing to low resistance is the same as when writing to high resistance is performed.

[0146] The bit line address decoder 26 has a function of connecting (conducting) only the bit line BL of the memory cell 10 to be accessed to the voltage generation circuit 23 via the load resistance circuit 241 for the address instructed by the control circuit 22 and disconnecting (turning off) the other bit lines BL.

[0147] The bit line control circuit 27 transmits a write signal (program signal) only to the bit line BL to be accessed according to the control signal of the bit line address decoder 26. Note that the potential applied to the bit line BL not to be accessed may be switched to the ground potential (GND potential) or floating potential.

[0148] The word line address decoder 28 has a function of connecting (turning on) only the word line WL of the memory cell 10 to be accessed to the voltage generation circuit 23 for an address instructed from the control circuit 22 and disconnecting (turning off) the other word lines WL.

[0149] The word line control circuit 29 turns on only the selection element 12 of the word line WL to be accessed according to the control signal of the word line address decoder 28. The GND potential is applied to the word line WL not to be accessed, and the selection element 12 is turned off. A negative voltage may be used instead of the GND potential as long as the selection element 12 can be turned off.

[0150] The source line SL is connected to GND during writing (programming) and is connected to the read amplifier 30 during reading. For example, reading is performed by detecting a current flowing through the memory cell 10 using the sense amplifier 30.

[0151] <1-4. Example of Write Processing>

[0152] Will refer to Figure 4 An example of the writing process according to the first embodiment is described. Figure 4 is a flowchart showing the write process according to the first embodiment.

[0153] The control circuit 22 (e.g., a state machine of the control circuit 22) controls the write process. This flowchart starts with the input of a write command and write data from the I / O 21 to the control circuit 22. Note that for convenience, data corresponding to low resistance is 0, and data corresponding to high resistance is 1.

[0154] like Figure 4As shown, in step S11, it is determined whether writing high resistance is performed, that is, whether the write data is 1. When it is determined that the write data is 1 (yes in step S11), the load resistor is set to the fixed resistor R1 in step S12, that is, the resistance value of the load resistor is set to the resistance value R1 of the fixed resistor R1.

[0155] In contrast, when it is determined in step S11 that the write data is 1 (No in step S11), in step S13, the load resistor is set to the fixed resistor R2, that is, the resistance value of the load resistor is set to the resistance value R2 of the fixed resistor R2.

[0156] In step S14, the set resistance value R1 or R2 is used and a program is executed. This program refers to writing for reversing the resistance state of the magnetoresistive element 11. Data is written to the target magnetoresistive element 11. The writing process then ends. The writing process refers to the entire process associated with data recording and includes, for example, the setting of the load resistor and the program.

[0157] Note that in the above procedure, the write circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 via the fixed resistor R1 or R2 of the load resistance circuit 241. Thus, the resistance value R of the magnetoresistive element 11 is set to a high resistance value R H or low resistance R L .

[0158] <1-5. Example of Timing Chart of Write Processing>

[0159] Will refer to Figure 5 and Figure 6 An example of a timing chart of the write process according to the first embodiment is described. Figure 5 is a timing chart showing a write process to a high resistance according to the first embodiment. Figure 6 is a timing chart showing a write process to a low resistance according to the first embodiment.

[0160] exist Figure 4 In step S12 or S13 in FIG. 2 , the control circuit 22 transmits the setting of the fixed resistor R1 or R2 to the load resistance circuit 241 , and transmits the address of the programming target to the word line address decoder 28 and the bit line address decoder 26 .

[0161] Specifically, if Figure 5 As shown, when the signal of the resistance setting (resistance setting) is turned off, the control circuit 22 transmits the setting of the fixed resistor R1 to the load resistance circuit 241 (Set R1). The load resistance circuit 241 switches the switch SW1 according to the setting sent from the control circuit 22 to set the load resistor to the fixed resistor R1.

[0162] Furthermore, the control circuit 22 sends the address of the programming target (WL address: ADRS) to the word line address decoder 28 , and sends the address of the programming target (BL address: ADRS) to the bit line address decoder 26 .

[0163] The word line address decoder 28 decodes the address input from the control circuit 22 and turns on the corresponding word line WL (WL control). This “turning on” connects the corresponding word line WL to the voltage generating circuit 23 .

[0164] The bit line address decoder 26 decodes the address input from the control circuit 22 and turns on the corresponding bit line BL (BL control). This “turning on” connects the corresponding bit line BL to the load resistance circuit 241 .

[0165] When both the word line WL and the bit line BL are turned on, the voltage V is applied only to the memory cell 10 at the corresponding address and the fixed resistor R1. The voltage V is a pulse voltage.

[0166] like Figure 6 As shown, when the resistance setting signal (resistance setting) is turned on, the control circuit 22 transmits the setting of the resistance value R2 to the load resistance circuit 241. The load resistance circuit 241 switches the switch SW1 according to the setting sent from the control circuit 22 and sets the load resistor to the fixed resistor R2.

[0167] Although subsequent processing and Figure 5 The process in is similar, but the load resistor is set to the fixed resistor R2. Therefore, when both the word line WL and the bit line BL are turned on, the voltage V is applied only to the memory cell 10 at the corresponding address and the fixed resistor R2.

[0168] Here, voltage V preferably has a pulse width of, for example, 0.1 ns to 20 ns. A pulse width of 0.1 ns or more reliably induces precession. A pulse width of 20 ns or less stabilizes the precession. A pulse width exceeding 20 ns causes the magnetization to completely face the direction of the external magnetic field, thereby ending the precession.

[0169] Note that although the voltage written to the high resistor is the same as the voltage written to the low resistor, the voltage written to the high resistor may be different from the voltage written to the low resistor. In addition, although the voltage is a pulse voltage, the voltage is not limited to the pulse voltage.

[0170] <1-6. Example of Voltage Dependence of Perpendicular Magnetic Anisotropy of Magnetoresistive Element>

[0171] Will refer to Figure 7 An example of the voltage dependency of the perpendicular magnetic anisotropy of the magnetoresistive element 11 according to the first embodiment is described. Figure 7Graph showing the voltage dependency of the perpendicular magnetic anisotropy (constant) of the magnetoresistive element 11 according to the first embodiment. The horizontal axis of the graph represents the voltage V. The vertical axis of the graph represents the perpendicular magnetic anisotropy of the recording layer 113 .

[0172] like Figure 7 As shown in Figure 2, the perpendicular magnetic anisotropy is almost zero near the voltage Vc. The perpendicular magnetic anisotropy is maintained at a voltage V less than the voltage Vc. L At a voltage V greater than Vc H In-plane magnetic anisotropy exists at the recording layer 113. Regions with negative perpendicular magnetic anisotropy have in-plane magnetic anisotropy. Larger perpendicular magnetic anisotropy makes it more likely that the recording layer 113 will be magnetized in the perpendicular direction. More specifically, positive perpendicular magnetic anisotropy makes it more likely that the recording layer 113 will be magnetized in the perpendicular direction (Z-axis direction). Negative perpendicular magnetic anisotropy makes it more likely that the recording layer 113 will be magnetized in the horizontal direction (XY plane direction).

[0173] Here, "perpendicular" refers to the z-axis direction, which is perpendicular to the inside of the xy plane where the external magnetic field is applied. "Inside the plane" refers to the inside of the xy plane. When in-plane magnetic anisotropy is present, the magnetization vector rotates within the xy plane and does not rotate in the z-axis direction, resulting in no reversal.

[0174] <1-7. Example of Voltage Division Using Load Resistors>

[0175] Will refer to Figure 8 An example of voltage division by the load resistor (ie, the fixed resistor R1 or R2 ) according to the first embodiment is described. Figure 8 The divided voltage in the case where the voltage V according to the first embodiment is applied to the magnetoresistive element 11 via the fixed resistor R1 or R2 is shown.

[0176] here, Figure 8 (a) shows the time of writing high resistance, and shows the writing of making the low resistance state enter the high resistance state and the writing of maintaining the high resistance state. Then, Figure 8 (b) shows the timing of writing low resistance, and shows writing in which the high resistance state enters the low resistance state and writing in which the low resistance state is maintained.

[0177] like Figure 8 As shown in (a), in a system where a fixed resistor R1 is connected in series with a magnetoresistive element 11, assuming a voltage V, a voltage Vc is distributed to the magnetoresistive element 11 in a low resistance state. In the same system, when the magnetoresistive element 11 is in a high resistance state, a smaller voltage is distributed to the fixed resistor R1, and a voltage V greater than Vc is applied to the magnetoresistive element 11. H .

[0178] That is, when voltage V is applied to the magnetoresistive element 11 and the fixed resistor R1 in the low resistance state, the voltage of the magnetoresistive element 11 becomes voltage Vc, and the perpendicular magnetic anisotropy becomes almost 0, and the inversion occurs. On the other hand, when voltage V is applied to the magnetoresistive element 11 and the fixed resistor R1 in the high resistance state, the voltage of the magnetoresistive element 11 becomes voltage Vc. H , the perpendicular magnetic anisotropy is less than 0, and no reversal occurs (maintained).

[0179] like Figure 8 As shown in (b), in a system where a fixed resistor R2 is connected in series with a magnetoresistive element 11, a voltage V is set, and a voltage Vc is distributed to the magnetoresistive element 11 in a high resistance state. In the same system, when the magnetoresistive element 11 is in a low resistance state, a large voltage is distributed to the fixed resistor R2, and a voltage V smaller than Vc is applied to the magnetoresistive element 11. L .

[0180] That is, when a voltage V is applied to the magnetoresistive element 11 and the fixed resistor R2 in a high resistance state, the voltage of the magnetoresistive element 11 becomes the voltage Vc, and the perpendicular magnetic anisotropy becomes almost 0, and the inversion occurs. On the other hand, when a voltage V is applied to the magnetoresistive element 11 and the fixed resistor R2 in a low resistance state, the voltage of the magnetoresistive element 11 becomes the voltage Vc. L , so the perpendicular magnetic anisotropy is greater than 0 and no reversal occurs (maintained).

[0181] As described above, the load resistance circuit 241 is configured differently depending on whether a program for changing the state of the magnetoresistive element 11 from a high resistance state to a low resistance state is executed or a program for changing the state of the magnetoresistive element 11 from a low resistance state to a high resistance state is executed. For example, the load resistance circuit 241 uses a fixed resistor R1 when a program for changing the resistance state of the magnetoresistive element 11 from a low resistance state to a high resistance state is executed, and uses a fixed resistor R2 when a program for changing the resistance state of the magnetoresistive element 11 from a high resistance state is executed.

[0182] <1-8. Example of Behavior of Magnetization Vector Caused by Voltage Application via Load Resistor>

[0183] Will refer to Figure 9 and Figure 10 An example of the behavior of the magnetization vector caused by applying a voltage via the load resistor (ie, the fixed resistor R1 or R2 according to the first embodiment) is described. Figure 9 The behavior of the magnetization vector caused by voltage application via the fixed resistor R1 according to the first embodiment is shown. Figure 10 The behavior of the magnetization vector caused by voltage application via the fixed resistor R2 according to the first embodiment is shown.

[0184] exist Figure 9 and Figure 10 In the example, the magnetization vector is set to (m x ,m y ,m z The magnetization vector (m) is positive in the z-axis direction. z >0) indicates a low resistance state. The negative magnetization vector (m z <0) indicates a high resistance state.

[0185] Figure 9 The graph (a1) (graph at the middle stage) and the graph (a2) (graph at the lower stage) in FIG. 1 show the magnetization vector (m) when a voltage V is applied to the magnetoresistive element 11 via the fixed resistor R1. x ,m y ,m z ) behavior. Figure 10 The graph (b1) (graph at the middle stage) and the graph (b2) (graph at the lower stage) in FIG. 1 show the magnetization vector (m) when a voltage V is applied to the magnetoresistive element 11 via the fixed resistor R2. x ,m y ,m z ) behavior.

[0186] exist Figure 9 In the graph of (a1), when the resistance is low (m z >0) and the fixed resistor R1, the magnetoresistive element 11 changes from the low resistance state (m z >0) changes to high resistance state (m z <0).

[0187] exist Figure 9 In the (a2) graph, when the direction is in the high resistance state (m z <0) and the fixed resistor R1, the magnetoresistive element 11 does not change from the high resistance state (m z <0) changes and maintains high resistance state (m z <0).

[0188] exist Figure 10 In the (b1) graph, when the direction is in high resistance state (m z <0) and the fixed resistor R2, the magnetoresistive element 11 changes from the high resistance state (m z <0) changes to low resistance state (m z >0).

[0189] exist Figure 10 In the (b2) graph, when the direction is in the low resistance state (mz >0) and the fixed resistor R2. When a voltage V is applied to the magnetoresistive element 11 and the fixed resistor R2, the magnetoresistive element 11 will not change from the low resistance state (m z >0) changes and maintains a low resistance state (m z >0).

[0190] As described above, in order to put the magnetoresistive element 11 into a low resistance state, it is sufficient to set the fixed resistor R1 and apply a voltage V to the magnetoresistive element 11 via the fixed resistor R1. In addition, in order to put the magnetoresistive element 11 into a high resistance state, it is sufficient to set the fixed resistor R2 and apply a voltage V to the magnetoresistive element 11 via the fixed resistor R2. This eliminates the need to determine whether to perform an initial read and execute a program. This eliminates the need for an initial read, thereby shortening the write time. In addition, power consumption can be reduced by shortening the write time. In addition, the fact that the initial read is not required does not cause erroneous writes, which can improve write accuracy.

[0191] Note that in a write method that does not require initial reading, the gate voltage of the selection transistor used as the selection element 12 can be switched between writing from the low resistance state of the magnetoresistive element 11 to the high resistance state and writing from the high resistance state to the low resistance state. Changing the gate voltage has the effect of changing the on-resistance of the selection transistor. Depending on whether the magnetoresistive element 11 is high resistance or low resistance, the voltage applied to the magnetoresistive element 11 can be controlled. However, in this case, because the gate voltage of the selection transistor is controlled, it may be difficult to control the on-resistance of the selection transistor, or the desired resistance value may not be obtained. The expected operation may not be achieved. This reduces the data writing accuracy. By using the load resistance circuit 241 as described above, the load resistance on the magnetoresistive element 11 can be easily and accurately controlled, and the desired action can be achieved. Therefore, compared with the case of controlling the gate voltage of the selection transistor, the data writing accuracy can be improved.

[0192] <1-9. Modification 1 of Storage Device>

[0193] Will refer to Figure 11 Modification 1 of the storage device 100 according to the first embodiment will be described. Figure 11 The following shows a configuration example of a memory device 100 according to a first modification of the first embodiment. The memory device 100 of the first modification is basically the same as that of the first embodiment. Here, the difference therebetween (load resistance circuit 241) will be described.

[0194] like Figure 11As shown, the load resistance circuit 241 of Modification 1 includes a variable resistor R3. Variable resistor R3 is a resistor with a variable resistance value. Variable resistor R3 serves as a load resistor. Load resistance circuit 241 changes the resistance value of variable resistor R3 under the control of control circuit 22. For example, load resistance circuit 241 changes the resistance value of variable resistor R3 to resistance value R1 or R2 under the control of control circuit 22. Other structures and various processes are the same as those of the first embodiment described above. Modification 1 also achieves the same effects as the first embodiment.

[0195] <1-10. Modification 2 of Storage Device>

[0196] Will refer to Figure 12 Modification 2 of the storage device 100 according to the first embodiment will be described. Figure 12 The following shows an example of the configuration of a memory cell array 1 of a memory device 100 according to a second modification of the first embodiment. The memory device 100 of the second modification is basically the same as that of the first embodiment. Here, the difference therebetween (memory cell array 1) will be described.

[0197] like Figure 12 As shown, in the memory cell array 1 according to Modification 2, each memory cell 10 has one source line SL per column line. That is, each of the memory cells 10 arranged in a column line is connected to one bit line BL and one source line SL (1BL / 1SL). Other structures and various processes are the same as those of the first embodiment described above. Modification 2 also achieves the same effects as the first embodiment.

[0198] <2. Second embodiment>

[0199] <2-1. Example of Write Processing>

[0200] Will refer to Figure 13 An example of the writing process according to the second embodiment is described. Figure 13 1 is a flowchart showing a write process according to the second embodiment. The second embodiment is basically the same as the first embodiment. The difference therebetween (write process) will be described here.

[0201] While the program (writing) is executed once in the first embodiment, the program is executed multiple times in the second embodiment. As a result, even if one program fails, the write error rate, which is the probability of failure of writing, can be reduced by trying the program multiple times.

[0202] like Figure 13As shown, in step S21, it is determined whether writing high resistance is performed, that is, whether the write data is 1. When it is determined that the write data is 1 ("Yes" in step S21), in step S22, the load resistor is set to the fixed resistor R1, that is, the resistance value of the load resistor is set to the resistance value R1 of the fixed resistor R1.

[0203] In contrast, when it is not determined in step S21 that the write data is 1 (No in step S21 ), the load resistor is set to the fixed resistor R2 , ie, in step S23 , the resistance value of the load resistor is set to the resistance value R2 of the fixed resistor R2 .

[0204] In step S24, the program is executed by using the set resistance value R1 or R2. In step S25, the program is similarly executed. In step S26, the program is similarly executed. As described above, the program is repeated three times, and data is written to the target magnetoresistive element 11. Then, the writing process ends.

[0205] Note that in the above procedure executed three times, the write circuit 24 applies the predetermined voltage V to the magnetoresistive element 11 three times via the fixed resistor R1 or R2 of the load resistance circuit 241. Thus, the resistance value R of the magnetoresistive element 11 is set to the high resistance value R H or low resistance R L .

[0206] In this write process, the program is executed multiple times after setting the resistance value R1 or R2. The program can be executed any number of times. For example, when the primary write error rate is set to 0.01 and the write error rate is required to be 1.E-6, the program is executed three times. Although preset, the number of times the program is executed can be changed according to input operations to an external device such as an input device connected to the storage device 100.

[0207] <2-2. Example of Timing Chart of Write Processing>

[0208] Will refer to Figure 14 and Figure 15 An example of a timing chart of the write process according to the second embodiment is described. Figure 14 is a timing chart showing a write process to a high resistance according to the second embodiment. Figure 15 is a timing chart showing a write process to a low resistance according to the second embodiment.

[0209] Although Figure 14 The timing diagram in Figure 5 The timing diagram in is basically the same, but Figure 14The middle bit line BL is turned on three times while the word line WL remains turned on. This allows the voltage V to be applied only three times to the memory cell 10 and the fixed resistor R1 at the corresponding address. That is, the program is executed three times. This can reduce the write error rate.

[0210] although Figure 15 The timing diagram in Figure 6 The timing diagram in is basically the same, but Figure 15 In the example, bit line BL is turned on three times, while word line WL remains on. This causes voltage V to be applied only three times to memory cell 10 and fixed resistor R2 at the corresponding address. That is, the program is executed three times. This can reduce the write error rate.

[0211] Note that the voltage V has a constant pulse width, which is not restrictive. The voltage V may have a pulse width that is different for each application of the voltage V. The optimal write pulse width may vary between the magnetoresistive elements 11 in the memory cell array 1. By performing multiple writes with different pulse widths, the write error rate can be reduced.

[0212] <2-3. Modification 1 of Write Processing>

[0213] Will refer to Figure 16 Modification 1 of the write process according to the second embodiment will be described. Figure 16 1 is a flowchart showing a write process according to Modification 1 of the second embodiment. Modification 1 is basically the same as the first embodiment. The difference therebetween (write process) will be described here.

[0214] In Modification 1, verification reading can be performed every time programming is performed. For example, when the power consumption required for reading is lower than the power consumption required for programming, excessive execution of the program can be reduced, thereby reducing power consumption.

[0215] like Figure 16 As shown, in step S31, it is determined whether writing high resistance is performed, that is, whether the write data is 1. When it is determined that the write data is 1 (yes in step S31), the load resistor is set to the fixed resistor R1, that is, in step S32, the resistance value of the load resistor is set to the resistance value R1 of the fixed resistor R1.

[0216] In contrast, when it is not determined in step S31 that the write data is 1 (No in step S31), the load resistor is set to the fixed resistor R2, that is, in step S33, the resistance value of the load resistor is set to the resistance value R2 of the fixed resistor R2.

[0217] In step S34 , the set resistance value R1 or R2 is used and the program is executed, thereby writing data to the target magnetoresistive element 11 .

[0218] Note that in the above procedure, the write circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 via the fixed resistor R1 or R2 of the load resistance circuit 241. Thus, the resistance value R of the magnetoresistive element 11 is set to the high resistance value R H or low resistance R L .

[0219] In step S35, verification reading is performed. In step S36, it is determined whether the read data matches the expected value. The data read from the target magnetoresistive element 11 by verification reading. The expected value is the value of the written data.

[0220] When it is not determined in step S36 that the read write data matches the expected value (No in step S36), the process returns to step S34. Conversely, when it is determined that the read write data matches the expected value (Yes in step S36), the write process ends.

[0221] In this writing process, a program is executed after setting the resistance value R1 or R2, and the program is repeatedly executed until writing is successful. This makes it possible to reduce excessive execution of the program while suppressing the write error rate, thereby reducing power consumption.

[0222] <2-4. Modification 2 of Write Processing>

[0223] Will refer to Figure 17 Modification 2 of the write processing according to the second embodiment will be described. Figure 17 1 is a flowchart showing a write process according to Modification 2 of the second embodiment. Modification 2 is basically the same as the first embodiment. The difference therebetween (write process) will be described here.

[0224] In Modification 2, verification is performed each time a program (write) is executed on the fixed resistor R1 (resistance value R1) side, and the program is repeatedly executed on the fixed resistor R2 (resistance value R2) side. For example, in a situation where there is a high possibility that the high resistance state cannot be maintained due to the application of voltage to the magnetoresistive element 11 and the fixed resistor R1, by performing verification, excessive execution of the program can be reduced, and the probability of unintended reversal can be reduced.

[0225] like Figure 17 As shown, in step S41, it is determined whether writing is performed to a high resistance, that is, whether the write data is 1. When it is determined that the write data is 1 (yes in step S41), the load resistor is set to the fixed resistor R1, that is, in step S42, the resistance value of the load resistor is set to the resistance value R1 of the fixed resistor R1.

[0226] In step S43 , the set resistance value R1 is used and the program is executed, thereby writing data to the target magnetoresistive element 11 .

[0227] In the above-mentioned procedure, the write circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 via the fixed resistor R1 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 becomes a high resistance value R. H .

[0228] In step S44, verification reading is performed. In step S45, it is determined whether the read data matches the expected value. The data read from the target magnetoresistive element 11 by verification reading. The expected value is the value of the written data.

[0229] When it is not determined in step S45 that the read / write data matches the expected value (No in step S45), the process returns to step S43. Conversely, when it is determined that the read / write data matches the expected value (Yes in step S45), the write process ends.

[0230] In contrast, when it is not determined in step S41 that the write data is 1 (No in step S41 ), the load resistor is set to the fixed resistor R2 , that is, the resistance value is set to the resistance value R2 in step S46 .

[0231] In step S47, the program is executed by using the set resistance value R2. In step S48, the program is similarly executed. In step S49, the program is similarly executed. As described above, the program is repeated three times, and data is written to the target magnetoresistive element 11. Then, the writing process ends.

[0232] In addition, when the above procedure is executed three times, the write circuit 24 applies the predetermined voltage V three times to the magnetoresistive element 11 via the fixed resistor R2 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 is set to the low resistance value R L .

[0233] In this write process, a verify read is performed after programming from a low-resistance state to a high-resistance state. If the read data matches the expected value, the program ends. If the read data does not match the expected value, the program is repeated. Furthermore, programming from a high-resistance state to a low-resistance state is performed multiple times without performing a verify read. By performing a verify read while suppressing the write error rate, over-execution of the program can be reduced, and the probability of unexpected reversals can be lowered.

[0234] <3. Third embodiment>

[0235] <3-1. Configuration Example of Load Resistor Circuit>

[0236] Will refer to Figure 18 A configuration example of the load resistance circuit 241 according to the third embodiment is described. Figure 18A configuration example of a load resistance circuit 241 according to a third embodiment is shown. The third embodiment is basically the same as the first embodiment. The differences therebetween (the load resistance circuit 241 and the writing process) will be described here.

[0237] In the first embodiment (or the second embodiment), the setting of the load resistors (fixed resistors R1 and R2) is set for each of the case where the program is executed from the high resistance state to the low resistance state and the case where the program is executed from the low resistance state to the high resistance state. In contrast, in the third embodiment, a plurality of settings of the load resistors (fixed resistors R1, R2a, and R2b) for executing the program from the high resistance state to the low resistance state are provided, and switching between the load resistors is performed in the middle of the pulse of the voltage V.

[0238] like Figure 18 As shown, the load resistance circuit 241 includes a plurality of fixed resistors R1, R2a, and R2b and a switch SW2. As in the first embodiment, the load resistance circuit 241 is provided in a wiring path between the voltage generating circuit 23 and the bit line control circuit 27.

[0239] Each of the fixed resistors R1, R2a, and R2b serves as a load resistor. The resistance value of the fixed resistor R1 is smaller than the resistance value of the fixed resistor R2b, and the resistance value of the fixed resistor R2a is greater than the resistance value of the fixed resistor R2b (R1 < R2b < R2a). The switch SW2 receives a switching signal from the control circuit 22 and switches the wiring path. For example, the switch SW2 switches between a wiring path passing through the fixed resistor R1, a wiring path passing through the fixed resistor R2a, and a wiring path passing through the fixed resistor R2b. That is, the load resistance circuit 241 can use the switch SW2 to switch between the wiring paths passing through the fixed resistors R1, R2a, and R2b, and can be connected to the voltage generation circuit 23 and the bit line control circuit 27.

[0240] The load resistance circuit 241 as described above switches and uses fixed resistors R1, R2a and R2b, and makes the resistance value variable. That is, the load resistance circuit 241 has the function of setting a plurality of different resistance values. In addition, the load resistance circuit 241 has a plurality of settings for executing a program from a high resistance state to a low resistance state. For example, the load resistance circuit 241 divides the pulse voltage into the first half and the second half, and makes the value of the load resistor in the second half less than the value of the load resistor in the first half. Specifically, when executing a program for setting the state of the magnetoresistive element 11 from a high resistance state to a low resistance state, the load resistance circuit 241 sets the load resistance to a fixed resistor R2a in the first half pulse of the pulse voltage and sets the load resistance to a fixed resistor R2b in the second half pulse of the pulse voltage.

[0241] Note that the load resistance circuit 241 may use a variable resistor R3 instead of the fixed resistors R1, R2a, and R2b. For example, the load resistance circuit 241 may be configured with fixed resistors R1, R2a, and R2b by using the variable resistor R3. Furthermore, the size relationship between the fixed resistors R1, R2a, and R2b is not limited to the size relationship described above.

[0242] <3-2. Example of Timing Chart of Write Processing>

[0243] Reference Figure 19 and Figure 20 , describing an example of a timing chart of a write process according to the third embodiment. Figure 19 is a timing chart showing a write process to a high resistance according to the third embodiment. Figure 20 is a timing chart showing a write process to a low resistance according to the third embodiment.

[0244] exist Figure 19 and Figure 20 In this example, two bits are used as setting signals for the three types of fixed resistors R1, R2a, and R2b to switch between them. The fixed resistor R1 is set to 0x0 for high resistance, and the two load resistors are set to 0x2 and 0x1 for low resistance.

[0245] although Figure 19 The timing diagram in Figure 5 The timing diagram in is basically the same, but Figure 19 In the example of , the setting signal of the fixed resistor R1 is 0×0. Figure 19 In the example, as in Figure 5 In the embodiment of FIG. 1 , the word line WL remains on while the bit line BL is on. This causes the voltage V to be applied only to the memory cell 10 of the corresponding address and the fixed resistor R1.

[0246] although Figure 20 The timing diagram in Figure 6 The timing diagrams in are basically the same, but Figure 20 In the example of , the setting signal of the fixed resistor R2a is 0×2 and the setting signal of the fixed resistor R2b is 0×1. Figure 20 In the example of FIG, the load resistor is switched from the fixed resistor R2a to the fixed resistor R2b while the word line WL remains on. This causes the voltage V to be applied only to the memory cell 10 and the fixed resistor R2a at the corresponding address, and causes the voltage V to be applied only to the memory cell 10 and the fixed resistor R2b at the middle of the pulse.

[0247] As described above, by changing the load resistor in the middle of the pulse of the voltage V, the write error rate from the high resistance state to the low resistance state can be reduced.

[0248] <4. Fourth embodiment>

[0249] <4-1. Example of Write Processing>

[0250] Will refer to Figure 21 A processing example of a write process according to the fourth embodiment will be described. Figure 21 : is a flowchart showing a write process according to the fourth embodiment. The fourth embodiment is basically the same as the first embodiment. The difference therebetween (write process) will be described here.

[0251] In the fourth embodiment, the second embodiment is applied when performing a program (write) for high resistance. When performing a program for low resistance, the third embodiment is applied. As a result, effects similar to those of the second and third embodiments can be obtained.

[0252] like Figure 21 As shown, in step S51, it is determined whether writing is performed to a high resistance, that is, whether the write data is 1. When it is determined that the write data is 1 (yes in step S51), the load resistor is set to the fixed resistor R1, that is, in step S52, the resistance value of the load resistor is set to the resistance value R1 of the fixed resistor R1.

[0253] In step S53, the program is executed by using the set resistance value R1. In step S54, the program is similarly executed. In step S55, the program is similarly executed. As described above, the program is repeated three times, and data is written to the target magnetoresistive element 11. Then, the writing process ends.

[0254] Furthermore, when the above procedure is executed three times, the write circuit 24 applies the predetermined voltage V three times to the magnetoresistive element 11 via the fixed resistor R1 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 becomes the high resistance value R H .

[0255] In contrast, when it is not determined in step S51 that the write data is 1 (No in step S51 ), the load resistor is set to the fixed resistor R2 , ie, the resistance value of the load resistor is set to the resistance value R2 of the fixed resistor R2 , in step S56 .

[0256] In step S57, the set resistance value R2 is used and the program is executed to write data to the target magnetoresistive element 11. Then, the writing process ends.

[0257] In the above procedure, the write circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 via the fixed resistor R2 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 is set to a low resistance value R. L .

[0258] In this write process, when performing a high resistance program, the program is performed multiple times. When performing a low resistance program, the program is performed once. However, it should be noted that when performing a low resistance program, one programming (pulse width of the pulse voltage) may be longer, as shown in the next timing diagram (see FIG. Figure 23 ) shown in .

[0259] <4-2. Example of Timing Chart of Write Processing>

[0260] Will refer to Figure 22 and Figure 23 An example of a timing chart of the write process according to the fourth embodiment is described. Figure 22 : is a timing chart showing a write process to a high resistance according to the fourth embodiment. Figure 23 is a timing chart showing a write process to a low resistance according to the fourth embodiment.

[0261] Figure 22 The timing diagram in Figure 14 The timing diagram in is basically the same. Figure 22 In the example of , the setting signal of the fixed resistor R1 is 0×0. Figure 22 In the example, Figure 14 In the example, bit line BL is turned on three times, while word line WL remains on. This allows voltage V to be applied only three times to memory cell 10 and fixed resistor R1 at the corresponding address. That is, the program is executed three times. This can reduce the write error rate.

[0262] although Figure 23 The timing diagram in Figure 20 The timing diagrams in are basically the same, but Figure 23 In the example of , one pulse width is longer than the pulse width in the third embodiment. When the program for setting the state of the magnetoresistive element 11 from the high resistance state to the low resistance state is executed, as shown in FIG. Figure 23 As shown, while the bit line BL remains on, the load resistor switches from fixed resistor R2a to fixed resistor R2b. Note that although one pulse width is longer than that in the third embodiment, this is not restrictive. One pulse width may be shorter than that in the third embodiment.

[0263] <5. Fifth embodiment>

[0264] <5-1. Configuration Example of Storage Device>

[0265] Will refer to Figure 24 A configuration example of the storage device 100 according to the fifth embodiment will be described. Figure 24 The following describes a configuration example of the load resistance circuit 241 of the memory device 100 according to the fifth embodiment. The memory device 100 according to the fifth embodiment is substantially the same as the memory device 100 according to the first embodiment. Here, the difference therebetween (the load resistance circuit 241) is described.

[0266] like Figure 24 As shown, the load resistance circuit 241 according to the fifth embodiment includes a fixed resistor R4, a wiring L1, and a plurality of switches SW3a and SW3b. The switches SW3a and SW3b each receive a switching signal from the control circuit 22 and switch between paths. For example, the switches SW3a and SW3b respectively switch between a wiring path passing through the fixed resistor R4 and a wiring path not passing through the fixed resistor R4. The wiring path not passing through the fixed resistor R4 passes through the wiring L1. It should be noted that although Figure 24 In the example of , two switches SW3a and SW3b are provided, but the number of switches SW3a and SW3b is not limited. Figure 3 As shown, only one switch may be provided.

[0267] The load resistance circuit 241 as described above switches between the switches SW3a and SW3b under the control of the control circuit 22, and switches between on / off of the fixed resistor R4. For example, the load resistance circuit 241 switches between the switches SW3a and SW3b. The load resistance circuit 241 turns on the fixed resistor R4 when writing from high resistance to low resistance, and turns off the fixed resistor R4 when writing from low resistance to high resistance. "On" is a state in which the fixed resistor R4 is connected to the voltage generating circuit 23 and the bit line control circuit 27. "Off" is a state in which the fixed resistor R4 is not connected to the voltage generating circuit 23 and the bit line control circuit 27. In addition, the other structures are the same as those of the first embodiment described above.

[0268] <5-2. Example of Write Processing>

[0269] Will refer to Figure 25 A processing example of a write process according to the fifth embodiment will be described. Figure 25 is a flowchart showing a write process according to the fifth embodiment.

[0270] The control circuit 22 (e.g., a state machine of the control circuit 22) controls the write process. This flowchart starts with the input of a write command and write data from the I / O 21 to the control circuit 22. Note that for convenience, data corresponding to the low resistance state is 0, and data corresponding to the high resistance state is 1.

[0271] like Figure 25 As shown, in step S61, an initial read is performed. That is, it is determined whether the read data is 1 or 0. In step S62, it is determined whether the read data matches the write data. When it is determined that the read data matches the write data (yes in step S62), the process ends.

[0272] In contrast, when it is not determined in step S62 that the read data matches the write data (No in step S62 ), it is determined in step S63 whether writing to high resistance is performed, that is, whether the write data is 1.

[0273] When it is determined in step S63 that the write data is 1 (Yes in step S63), the fixed resistor R4 is set to be disconnected (load resistor disconnection) in step S64. The load resistor circuit 241 switches between the switches SW3a and SW3b under the switching control of the control circuit 22, and selects a wiring path that does not pass through the fixed resistor R4, that is, a wiring path that passes through the wiring L1.

[0274] On the other hand, when it is not determined in step S63 that the write data is 1 (No in step S63), the fixed resistor R4 is set to be on (load resistor on) in step S65. The load resistor circuit 241 switches between the switches SW3a and SW3b under the switching control of the control circuit 22, and selects the wiring path passing through the fixed resistor R4.

[0275] In step S66, writing (programming) is performed based on the fixed resistor R4 set to on or off. In step S67, verification reading is performed. The process returns to step S62.

[0276] Note that in the above-described writing, the writing circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 without the fixed resistor R4 of the load resistance circuit 241. As a result, the resistance value R of the magnetoresistive element 11 becomes a high resistance value R H Alternatively, the write circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 via the fixed resistor R4 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 is set to a low resistance value R. L .

[0277] The voltage is pulsed so that a constant voltage Vc with a perpendicular magnetic anisotropy of zero is applied only during the magnetization reversal period (the time required for half a rotation) of the recording layer 113. However, since the magnetization reversal period of the recording layer 113 depends on the horizontal magnetic field strength and is a short period of, for example, 0.7 ns, pulse control with high precision of approximately ±0.1 ns is required. This pulse control is not easy, and control becomes even more difficult if component variations are taken into account.

[0278] In contrast, the fifth embodiment facilitates writing from high resistance to low resistance. The fixed resistor R4, which functions as a load resistor, changes its resistance, causing the voltage distributed to the magnetoresistive element 11 to decrease, increasing the perpendicular magnetic anisotropy. Propulsion centered on the horizontal magnetic field stops at a low resistance state. That is, in VC-MRAMs requiring short pulse control, a writing method can be implemented with a reversal probability that does not degrade despite long pulse widths. This eliminates the need for high-precision pulse width control, simplifies circuit design, and suppresses degradation of the reversal probability caused by variations in pulse width and components.

[0279] <5-3. Example of Timing Chart of Write Processing>

[0280] Will refer to Figure 26 An example of a timing chart of the write process according to the fifth embodiment is described. Figure 26 is a timing chart showing the write process according to the fifth embodiment.

[0281] exist Figure 26 In (a), the data of the memory cell 10 is rewritten from "high" to "low". Figure 26 In (b), the data of the memory cell 10 is rewritten from "low" to "high". It should be noted that the data corresponding to the low resistance value R L The data is also called "low" and corresponds to a high resistance value R H Data that is “low” is also referred to as “high”. For example, data “low” corresponds to “0” and data “high” corresponds to “1”.

[0282] like Figure 26 As shown in (a) and (b) of FIG. 1 , an initial read is performed. The control circuit 22 sends a read start signal (Read Start) to the read circuit 25. The read circuit 25 issues a read pulse (Read Pulse). The read pulse is supplied to the bit line BL connected to the memory cell 10 to which the data is to be written via the bit line control circuit 27.

[0283] The read voltage (read voltage) from the magnetoresistive element 11 to be accessed is input to the sense amplifier 30. The control circuit 22 enables the sense amplifier 30 (SA enable). The potential changes depending on the state of the resistance value R of the magnetoresistive element 11 (the recording state of the memory cell 10). Therefore, the sense amplifier 30 detects the read voltage (high or low) when determining the potential. This detection is equivalent to the resistance value R of the magnetoresistive element 11 (high resistance value R H or low resistance R L ) is detected. Therefore, the data of the memory cell 10 is read.

[0284] The control circuit 22 compares the data of the memory cell 10 read by the sense amplifier 30 with the write data (data to be written). Here, the comparison result indicates a mismatch (Result, mismatch). The control circuit 22 sends a write start signal (Write Start) to the write circuit 24.

[0285] The write circuit 24 generates a write pulse (Write Pulse). The write pulse is supplied via the bit line control circuit 27 to the bit line BL connected to the memory cell 10 to which the data is to be written.

[0286] exist Figure 26 In (a), the write circuit 24 enables the load resistance function of the load resistance circuit 241 (load resistance enabled). The write circuit 24 applies a predetermined voltage (pulse width W1) to the magnetoresistive element 11 via the fixed resistor R4 of the load resistance circuit 241. As a result, the resistance value R of the magnetoresistive element 11 changes from the high resistance value R H Switch to a low resistance value R L , write data "high".

[0287] exist Figure 26 In (b), the write circuit 24 does not enable the load resistance function of the load resistance circuit 241. The write circuit 24 applies a predetermined voltage V (pulse width W2) to the magnetoresistive element 11. As a result, the resistance value R of the magnetoresistive element 11 changes from the low resistance value R to the high resistance value R. L Switch to a high resistance value R H , write data “low”.

[0288] exist Figure 26 In the examples of (a) and (b), the voltage V having a different pulse width (the voltage V having the pulse width W1 or W2 ) is applied to the magnetoresistive element 11 according to the on / off switching of the fixed resistor R4 .

[0289] After that, a verification read is performed. The control circuit 22 compares the data of the memory cell 10 read by the verification read with the write data. Here, the comparison result indicates a match. Therefore, the data writing is completed.

[0290] <5-4. Example of Characteristics of Magnetoresistive Element>

[0291] use Figure 27 An example of characteristics of the magnetoresistive element 11 according to the fifth embodiment will be described. Figure 27 is a graph showing characteristics of the magnetoresistive element 11 according to the fifth embodiment.

[0292] Figure 27 shows the magnetization component m of the recording layer 113Z The resistance ratio R(m Z ) / R H The horizontal axis of the graph represents the magnetization component m of the recording layer 113. Z . Magnetization component m Z is the magnetization intensity of the recording layer 113 in the Z-axis direction. Z When the magnetization component m is 1, the magnetization direction of the recording layer 113 is in the positive direction (upward direction) of the Z axis. Z When the value is -1, the magnetization direction of the recording layer 113 is in the negative direction (downward direction) of the Z axis. High The normalized resistance ratio R(m Z ) / R H . R(m Z ) is based on the magnetization component m Z The resistance value of the magnetoresistive element 11 changes.

[0293] When the magnetization of the recording layer 113 rotates, the magnetization component m Z changes between -1 and 1. When the magnetization component m Z When 1 is 1, the magnetization direction of the recording layer 113 is in the positive Z-axis direction in the same manner as the magnetization direction of the fixed layer 111, and the resistance value R of the magnetoresistive element 11 is a low resistance value R L On the contrary, when the magnetization component m Z When it is -1, the magnetization direction of the recording layer 113 is in the negative Z-axis direction in a manner opposite to the magnetization direction of the fixed layer 111, and the resistance value R of the magnetoresistive element 11 is a high resistance value R H The resistance value R of the magnetoresistive element 11 is between the low resistance value R and the low resistance value R during the magnetization rotation of the recording layer 113. L and high resistance R H Gradually changes between.

[0294] <5-5. Example of Voltage Dependence of Perpendicular Magnetic Anisotropy of Magnetoresistive Element>

[0295] Will refer to Figure 28 An example of the voltage dependency of the perpendicular magnetic anisotropy of the magnetoresistive element 11 according to the fifth embodiment is described. Figure 28 Graph showing the voltage dependency of the perpendicular magnetic anisotropy (constant) of the magnetoresistive element 11 according to the fifth embodiment. The horizontal axis of the graph represents the voltage V. The vertical axis of the graph represents the perpendicular magnetic anisotropy of the recording layer 113 .

[0296] like Figure 28As shown, a larger perpendicular magnetic anisotropy makes the recording layer 113 more likely to be magnetized in the perpendicular direction. More specifically, a positive perpendicular magnetic anisotropy makes the recording layer 113 more likely to be magnetized in the perpendicular direction (Z-axis direction). A negative perpendicular magnetic anisotropy makes the recording layer 113 more likely to be magnetized in the horizontal direction (XY plane direction).

[0297] As can be seen from this graph, when voltage V is 0, that is, when no voltage V is applied to the magnetoresistive element 11, the perpendicular magnetic anisotropy is positive. In this case, the recording layer 113 is more likely to be magnetized in the perpendicular direction. When voltage V is applied to the magnetoresistive element 11, the value of the perpendicular magnetic anisotropy changes. Specifically, as voltage V increases, the perpendicular magnetic anisotropy decreases. When voltage V exceeds a certain voltage Vc, the perpendicular magnetic anisotropy becomes negative. In this case, the recording layer 113 is more likely to be magnetized in the horizontal direction.

[0298] As described above, when a voltage V that makes the recording layer 113 more likely to be magnetized in the horizontal direction is applied to the magnetoresistive element 11, the magnetization of the recording layer 113 of the magnetoresistive element 11 rotates by precession centered on the horizontal magnetic field. By utilizing the rotation, the resistance value R of the magnetoresistive element 11 is reduced to a low resistance value R. L and high resistance R H The magnetization of the recording layer 113 is reversed by switching between the two. Thus, data can be written to the memory cell 10.

[0299] <5-6. Example of Voltage Division Using Load Resistors>

[0300] Will refer to Figure 29 An example of voltage division by the fixed resistor R4 according to the fifth embodiment is described. Figure 29 1 shows the voltage division when the voltage V is applied to the magnetoresistive element 11 via the fixed resistor R4 according to the fifth embodiment. Figure 29 In this example, the load resistor R X Corresponding to the fixed resistor R4.

[0301] like Figure 29 As shown, when the magnetoresistive element 11 is in a high resistance state and the load resistance R X When the voltage V is applied to the magnetoresistive element 11, the voltage Vc is applied to the magnetoresistive element 11 by voltage division. X When the same voltage V is applied to the magnetoresistive element 11, the load resistor R XThe allocated voltage is large, and the voltage across magnetoresistive element 11 is smaller than voltage Vc. At voltage Vc, a reversal occurs, bringing the perpendicular magnetic anisotropy to zero. When voltage Vc is applied to magnetoresistive element 11 in a high-resistance state, a reversal occurs, while in magnetoresistive element 11 in a low-resistance state, no reversal occurs. Furthermore, when magnetoresistive element 11 transitions from a high-resistance state to a low-resistance state, the allocated voltage decreases. This increases the perpendicular magnetic anisotropy, and the reversal stops.

[0302] <5-7. Example of Voltage Change of Magnetoresistive Element>

[0303] use Figure 30 , an example of voltage change of the magnetoresistive element 11 according to the fifth embodiment will be described. Figure 30 The voltage change of the magnetoresistive element 11 according to the fifth embodiment is shown.

[0304] exist Figure 30 In the example, the voltage of the magnetoresistive element 11 is set to V MTJ , representing the voltage V in the case of (a) writing from high resistance to low resistance and (b) writing from low resistance to high resistance MTJ changes. Figure 30 In (a), the initial read data is "high", and the write data is "low". Figure 30 In (b), the initial read data is "low" and the write data is "high".

[0305] From time t11 to time t12, the initial reading of data is performed. The reading circuit 25 detects the resistance value R of the magnetoresistive element 11 by applying a low voltage that does not reverse the magnetization of the recording layer 113 to the magnetoresistive element 11. Figure 30 In (a), a high resistance value R is detected H .exist Figure 30 In (b), a low resistance value R is detected L .

[0306] At time t13, data is written. The write circuit 24 reverses the magnetization of the recording layer 113 so that the resistance value R of the magnetoresistive element 11 is at a low resistance value R. L and high resistance R H Switch between.

[0307] exist Figure 30 In (a), the write circuit 24 applies a predetermined voltage V (pulse width W1) to the magnetoresistive element 11 via the fixed resistor R4 of the load resistance circuit 241. In the magnetoresistive element 11, the resistance value R has been detected as a high resistance value R by the read circuit 25. H As a result, the resistance value R of the magnetoresistive element 11 changes from the high resistance value R H Switch to a low resistance value R L, write data “low”.

[0308] exist Figure 30 In (b), the write circuit 24 applies a predetermined voltage V (pulse width W2) to the magnetoresistive element 11 without the fixed resistor R4 of the load resistance circuit 241, wherein the resistance value R is detected as a low resistance value R by the read circuit 25. L As a result, the resistance value R of the magnetoresistive element 11 changes from the low resistance value R L Switch to a high resistance value R H , data “High” is written. Note that, for example, the pulse width W2 of the voltage V may be the same as the pulse width within the reversal period of the magnetization of the recording layer 113 .

[0309] To determine whether the write circuit 24 has switched the resistance value R of the magnetoresistive element 11 , the read circuit 25 detects the resistance value R of the magnetoresistive element 11 by applying a voltage that does not reverse the magnetization of the recording layer 113 to the magnetoresistive element 11 .

[0310] Check the recording state of the memory cell 10, that is, whether the resistance value R of the magnetoresistive element 11 is correctly switched. Here, it is assumed that data writing fails at the above time t13 and the same resistance value R as the resistance value R at the time of initial reading is detected. Therefore, data is written again.

[0311] At time t16, data is written in. The details are similar to those of the data writing at time t13 described above, and therefore, description thereof will not be repeated.

[0312] From time t17 to time t18, verification reading is performed. Here, it is assumed that data writing has been successful at the above-mentioned time t16. Therefore, data writing is completed.

[0313] like Figure 30 As shown in (a), when writing from high resistance to low resistance, the voltage applied to magnetoresistive element 11 changes according to the resistance change via fixed resistor R4. The voltage decreases as the resistance changes, increasing the perpendicular magnetic anisotropy, which stops the precession centered on the horizontal magnetic field. Therefore, the low resistance state stops the magnetization vector from changing, and the reversal probability does not oscillate.

[0314] On the contrary, Figure 30 As shown in (b), when writing from low resistance to high resistance, since fixed resistor R4 is not used, there is no voltage change or change in the perpendicular magnetic anisotropy, and precession centered on the horizontal magnetic field continues. Continuing precession causes the reversal probability to oscillate, requiring appropriate voltage cutoff.

[0315] <5-8. Example of written simulation results>

[0316] Will refer to Figure 31 An example of simulation results of writing according to the fifth embodiment is described. Figure 31 Shown are simulation results in the case where a pulse voltage is applied to the magnetoresistive element 11 in the high-resistance state or the low-resistance state according to the fifth embodiment via the fixed resistor R4 .

[0317] like Figure 31 As shown in the left figure of FIG, when a pulse voltage is applied to the magnetoresistive element 11 in a high resistance state via the fixed resistor R4, the write error rate does not oscillate to the pulse width. That is, by applying a pulse voltage via the fixed resistor R4, writing can be achieved without oscillating to the pulse width of the pulse voltage. In addition, as Figure 31 As shown in the right figure, Figure 31 Under the same conditions as shown in the left figure of FIG, when a pulse voltage is applied to the magnetoresistive element 11 in the low resistance state via the fixed resistor R4, no writing is performed. In other words, no reverse writing occurs.

[0318] As described above, writing from high resistance to low resistance is facilitated. The load resistor causes a change in resistance and a decrease in the voltage distributed to the magnetoresistive element 11, which increases magnetic anisotropy. Propulsion centered on a horizontal magnetic field stops at the low resistance state. Note that writing from low resistance to high resistance is similar to conventional writing.

[0319] <5-9. Modification 1 of Write Processing>

[0320] Will refer to Figure 32 Modification 1 of the write process according to the fifth embodiment will be described. Figure 32 1 is a flowchart showing a write process according to Modification 1 of the fifth embodiment. Modification 1 is basically the same as the fifth embodiment. The difference therebetween (write process) will be described here.

[0321] like Figure 32 As shown, in step S71, it is determined whether writing to the high resistance is performed, that is, whether the write data is 1. When it is determined that the write data is 1 ("Yes" in step S71), the fixed resistor R4 is set to be off (load resistor off) in step S72. The load resistor circuit 241 switches between the switches SW3a and SW3b under the switching control of the control circuit 22, and selects a wiring path that does not pass through the fixed resistor R4.

[0322] In step S73, initial reading is performed. That is, it is determined whether the read data is 1 or 0. In step S74, it is determined whether the read data matches the write data. When it is determined that the read data matches the write data (yes in step S74), the process ends.

[0323] On the other hand, when it is not determined in step S74 that the read data matches the write data (No in step S74), writing (programming) is performed based on the fixed resistor R4 set to be off in step S75. In step S76, verification reading is performed. Thereafter, the process returns to step S74.

[0324] Note that in the above-described writing, the writing circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 without the fixed resistor R4 of the load resistance circuit 241. As a result, the resistance value R of the magnetoresistive element 11 becomes a high resistance value R H .

[0325] When it is not determined in step S71 that the write data is 1 ("No" in step S63), the fixed resistor R4 is set to be on (load resistor on) in step S77. The load resistor circuit 241 switches between the switches SW3a and SW3b under the switching control of the control circuit 22, and selects the wiring path passing through the fixed resistor R4.

[0326] In step S78, writing (program) is performed by using the fixed resistor R4 set to be turned on. In step S79, writing is performed similarly. In step S80, writing is performed similarly. As described above, writing is repeated three times to write data to the target magnetoresistive element 11. Then, the writing process ends.

[0327] Note that in the above writing performed three times, the writing circuit 24 applies the predetermined voltage V three times to the magnetoresistive element 11 via the fixed resistor R4 of the load resistor circuit 241. Thus, the resistance value R of the magnetoresistive element 11 is set to the low resistance value R L .

[0328] Furthermore, writing from high resistance to low resistance via fixed resistor R4 does not depend on the pulse width, and reverse writing does not occur, so that initial reading can be omitted. In addition, to improve the write error rate, voltages with the same pulse width or different pulse widths can be applied.

[0329] <6. Sixth embodiment>

[0330] <6-1. Example of Write Processing>

[0331] Will refer to Figure 33 A processing example of a write process according to the sixth embodiment is described. Figure 33 : is a flowchart showing a write process according to the sixth embodiment. The sixth embodiment is basically the same as the fifth embodiment. The difference therebetween (write process) will be described here.

[0332] In the sixth embodiment, data writing to the memory cell 10 includes initialization rather than initial reading. Initialization eliminates the need for initial reading. For example, the write circuit 24 uses fixed resistor R4 to write from high resistance to low resistance for initialization.

[0333] In the low-resistance state of the magnetoresistive element 11, the voltage allocated to the fixed resistor R4 is increased, and the voltage VMTJ is decreased. In this case, the perpendicular magnetic anisotropy does not decrease, and precession centered on the horizontal magnetic field does not occur, preventing reversal. Therefore, since reversal occurs only in the high-resistance state of the magnetoresistive element 11, the magnetoresistive element 11 can be adjusted to a low-resistance state regardless of its initial state. This enables initialization, eliminating the need for initial reading.

[0334] like Figure 33 As shown, in step S81, the fixed resistor R4 is set to be on (load resistor on). In step S82, writing (initialization) from high resistance to low resistance is performed.

[0335] In the above-mentioned writing, the writing circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 via the fixed resistor R4 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 is initialized to a low resistance value R L .

[0336] In step S83 , it is determined whether high resistance is written, that is, whether the written data is 1. When it is not determined that the written data is 1 (“No” in step S83 ), the process ends.

[0337] On the contrary, when it is determined that the write data is 1 (yes in step S83), in step S84, the fixed resistor R4 is set to off (load resistor off). In step S85, based on the fixed resistor R4 set to off, writing from low resistance to high resistance is performed.

[0338] In addition, during the above-mentioned writing, the writing circuit 24 applies a constant voltage V to the magnetoresistive element 11. The resistance value R of the magnetoresistive element 11 changes from a low resistance value R to a high resistance value R. L Switch to a high resistance value R H .

[0339] In step S86, verification (verification read) is performed. In step S87, it is determined whether the read data matches the written data. When it is determined that the read data matches the written data ("Yes" in step S87), the process ends. Conversely, when it is determined that the read data matches the written data ("No" in step S87), the process returns to step S85.

[0340] In this process, fixed resistor R4 is turned on for initialization. Then, voltage is applied to all magnetoresistive elements 11 (all bits) at the specified address. In the low resistance state, since no voltage is applied to the magnetoresistive elements 11, the perpendicular magnetic anisotropy increases and no reversal occurs. Since voltage is applied to the magnetoresistive elements 11 in the high resistance state, the perpendicular magnetic anisotropy decreases and reversal occurs. Only the magnetoresistive elements 11 in the high resistance state change to the low resistance state, and all magnetoresistive elements 11 at the target address can be set to the low resistance state.

[0341] Fixed resistor R4 is disconnected, and writing is performed only on the magnetoresistive element 11 where the write data is 1, requiring writing in a high-resistance state. Verification is performed to check the result. The recorded state is read to determine whether the magnetoresistive element 11 is in a high-resistance state. If the magnetoresistive element 11 is in a high-resistance state, the process ends. If the magnetoresistive element 11 is not in a high-resistance state, the write process is performed again. Note that, for example, a maximum number of verification and rewrite times may be provided.

[0342] <6-2. Example of Timing Chart of Write Processing>

[0343] Will refer to Figure 34 An example of a timing chart of a write process according to the sixth embodiment is described. Figure 34 is a timing chart showing a write process according to the sixth embodiment.

[0344] In the sixth embodiment, the resistance state of the magnetoresistive element 11 is adjusted to a low resistance state through initialization. During initialization, voltage is applied to the magnetoresistive element 11 in both the low resistance state and the high resistance state via a fixed resistor R4. The magnetoresistive element 11 in the low resistance state remains unchanged, while writing to the low resistance state is performed in the magnetoresistive element 11 in the high resistance state. Writing is performed by applying a constant voltage pulse to the magnetoresistive element 11 (bit) in which the write data is 1 (high resistance state).

[0345] exist Figure 34 In (a), data "low" is written when writing low resistance. Figure 34 In (b), data "high" is written when writing high resistance. Figure 34 In the example of , the magnetoresistive element 11 is initialized to the low resistance state. Writing is performed only on the magnetoresistive element 11 in which the write data is 1 (high resistance state).

[0346] like Figure 34As shown in (a), the initialization is performed. The write circuit 24 issues a write pulse. The write pulse is provided to the bit line BL connected to the memory cell 10 to which the data is written via the bit line control circuit 27. The write circuit 24 applies a predetermined voltage V (pulse width W1) to the magnetoresistive element 11 via the fixed resistor R4 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 is initialized to a low resistance value R L .

[0347] exist Figure 34 In (a), data "Low" is written by the above initialization, and data writing is completed. Note that verification reading can be performed.

[0348] exist Figure 34 In (b), the data is written as "High". The write circuit 24 issues a write pulse (Write Pulse). The write circuit 24 applies a predetermined voltage V (pulse width W2) to the magnetoresistive element 11 without the fixed resistor R4 of the load resistance circuit 241. As a result, the resistance value R of the magnetoresistive element 11 becomes a high resistance value R H .

[0349] After that, a verification read is performed. Here, the comparison result indicates a mismatch. Therefore, the data is written again. In the subsequent verification read, the comparison result indicates a match, and the data writing is completed.

[0350] <6-3. Example of Voltage Change of Magnetoresistive Element>

[0351] Will refer to Figure 35 An example of voltage change of the magnetoresistive element 11 according to the sixth embodiment will be described. Figure 35 The voltage change of the magnetoresistive element 11 according to the sixth embodiment is shown.

[0352] In the sixth embodiment, when the magnetoresistive element 11 is in the high resistance state, the magnetoresistive element 11 is initialized to the low resistance state, and writing is performed only when the write data is 1 (high resistance state). When the magnetoresistive element 11 is in the low resistance state, this state does not change, and writing is performed only when the write data is 1 (high resistance state).

[0353] exist Figure 35 In (a), the data before initialization is "High", and the written data is also "High". Figure 35 In (b), the data before initialization is "high" and the written data is "low". Figure 35 In (c), the data before initialization is "low", and the written data is "high". Figure 35 In (d), data before initialization is “Low”, and write data is also “Low.” Write data is data to be written.

[0354] like Figure 35 As shown, initialization is performed from time t31 to time t32. The write circuit 24 applies a predetermined voltage (pulse width W1) to the magnetoresistive element 11 via the fixed resistor R4 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 is initialized to a low resistance value R L .exist Figure 35 In (a) and (b), the resistance value R of the magnetoresistive element 11 changes from a high resistance value R H Switch to a low resistance value R L .exist Figure 35 In (c) and (d), the resistance value R of the magnetoresistive element 11 is kept at a high resistance value R H (No change).

[0355] From time t33 to time t34, data is written as needed. Figure 35 In (a) and (c), the data is written as "High". The write circuit 24 applies a predetermined voltage (pulse width W2) to the magnetoresistive element 11. As a result, the resistance value R of the magnetoresistive element 11 changes from the low resistance value R to the high resistance value R. L Switch to a high resistance value R H .exist Figure 35 In (b) and (d), no data is written.

[0356] From time t35 to time t36, verification reading is performed as needed. Figure 35 In (a) and (c), verification reading is performed based on the data writing from time t33 to time t34. Here, it is assumed that the data writing is successful. Therefore, the data writing is completed. Figure 35 In (b) and (d), the verification read is omitted and the data writing ends. However, it should be noted that Figure 35 Verification reading can also be performed in (b) and (d).

[0357] <7. Seventh embodiment>

[0358] <7-1. Example of Write Processing>

[0359] Will refer to Figure 36 A processing example of a write process according to the seventh embodiment is described. Figure 36 : is a flowchart showing a write process according to the seventh embodiment. The seventh embodiment is basically the same as the fifth embodiment. The difference therebetween (write process) will be described here.

[0360] In the seventh embodiment, the first embodiment is combined with the non-patent document. In the first embodiment, pulse control of writing from high resistance to low resistance is facilitated by using load resistors (e.g., fixed resistors R1 and R2). In the non-patent document, pulse control of writing from low resistance to high resistance is facilitated by using a magnetic field in a perpendicular direction. In the seventh embodiment, the method in the non-patent document is used for initialization by combining with the first embodiment to facilitate pulse control in both directions.

[0361] As mentioned above, it is helpful to write from high resistance to low resistance. In addition, fixed resistor R4 causes the change of resistance and the reduction of the voltage distributed to magnetoresistive element 11, which increases the perpendicular magnetic anisotropy. The propulsion centered on the horizontal magnetic field stops in the low resistance state. In addition, it is also convenient to initialize (write from low resistance to high resistance). In both the write from low resistance to high resistance and the write from high resistance to low resistance, in combination with the method of non-patent literature, short pulse control is unnecessary.

[0362] like Figure 36 As shown, in step S91, initialization is performed (all initialized to high resistance). A predetermined voltage V is applied to all magnetoresistive elements 11 (all bits) at a specified address. As a result, the resistance value R of the magnetoresistive element 11 is initialized to a high resistance value R. H .

[0363] In step S92 , it is determined whether writing to the low resistance is performed, that is, whether the write data is 0. When it is not determined that the write data is 0 (No in step S92 ), the process ends.

[0364] On the other hand, when it is determined that the write data is 0 (Yes in step S92), the fixed resistor R4 is set to be on (load resistor on) in step S93. This enables the load resistance function of the load resistance circuit 241. In step S94, writing from high resistance to low resistance is performed based on the fixed resistor R4 set to be off.

[0365] In addition, during the above writing, the writing circuit 24 applies a predetermined voltage V to the magnetoresistive element 11 via the fixed resistor R4 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 changes from the high resistance value R H Switch to a low resistance value R L .

[0366] In step S95, verification (verification reading) is performed. Thereafter, in step S96, it is determined whether the read data matches the write data. When it is determined that the read data matches the write data (yes in step S96), the process ends. Conversely, when it is determined that the read data does not match the write data (no in step S96), the process returns to step S94.

[0367] <7-2. Example of Timing Chart of Write Processing>

[0368] Will refer to Figure 37 An example of a timing chart of the write process according to the seventh embodiment is described. Figure 37 is a timing chart showing a write process according to the seventh embodiment.

[0369] In the seventh embodiment, the initialization method for adjusting the magnetoresistive element 11 to a high resistance state uses a method described in a non-patent literature. As in the second embodiment, the write data is written to the magnetoresistive element 11 (bit) with a value of 0 (low resistance state) via fixed resistor R4. In writing according to the seventh embodiment, the use of fixed resistor R4 to perform writing stops precession, eliminating the need for conventional short pulses and facilitating pulse control.

[0370] exist Figure 37 In (a), data "low" is written when writing low resistance. Figure 37 In (b), data "high" is written when writing high resistance. Figure 37 In the example of FIG, the magnetoresistive element 11 is initialized to a high resistance state. Writing is performed only on the magnetoresistive element 11 in which the write data is 0 (low resistance state). In addition, the write pulse is shown as Figure 34 The write pulse length in .

[0371] like Figure 37 As shown in (a), the initialization is performed. The write circuit 24 issues a write pulse. The write pulse is provided to the bit line BL connected to the memory cell 10 to which the data is written via the bit line control circuit 27. The write circuit 24 applies a predetermined voltage V (pulse width W3) to the magnetoresistive element 11. As a result, the resistance value R of the magnetoresistive element 11 is initialized to a high resistance value R. H .

[0372] exist Figure 37 In (a), the data is written as "low". The write circuit 24 issues a write pulse (Write Pulse). The write circuit 24 applies a predetermined voltage V (pulse width W1) to the magnetoresistive element 11 via the fixed resistor R4 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 changes from the high resistance value R to the low resistance value R. H Switch to a low resistance value R L .

[0373] After that, a verification read is performed. Here, the comparison result indicates a mismatch. Therefore, the data is written again. In the subsequent verification read, the comparison result indicates a match, and the data writing is completed.

[0374] exist Figure 37 In (b), data "High" is written by the above initialization, and data writing is completed. Note that verification reading can be performed.

[0375] <7-3. Example of Voltage Change of Magnetoresistive Element>

[0376] Reference Figure 38 , an example of voltage change of the magnetoresistive element 11 according to the seventh embodiment will be described. Figure 38 The voltage change of the magnetoresistive element 11 in the seventh embodiment is shown.

[0377] exist Figure 38 In (a), the data before initialization is "high", and the written data is also "high". Figure 38 In (b), the data before initialization is "high" and the written data is "low". Figure 38 In (c), the data before initialization is "low", and the written data is "high". Figure 38 In (d), the data before initialization is "Low", and the write data is also "Low". The write data is the data to be written.

[0378] Initialization is performed from time t41 to time t42. The write circuit 24 applies a predetermined voltage V (pulse width W3) to the magnetoresistive element 11. As a result, the resistance value R of the magnetoresistive element 11 is initialized to a high resistance value R. H The pulse width W3 of the voltage V can be longer than the pulse width W2 (see Figure 30 and Figure 35 ).exist Figure 38 In (a) and (b), the resistance value R of the magnetoresistive element 11 is kept at a high resistance value R H (No change). Figure 38 In (c) and (d), the resistance value R of the magnetoresistive element 11 is increased from a low resistance value R L Switch to a high resistance value R H .

[0379] From time t43 to time t44, data is written as needed. Figure 38 In (a) and (c), no data is written. Figure 38 In (b) and (d), data is written. The write circuit 24 applies a predetermined voltage V (pulse width W1) to the magnetoresistive element 11 via the fixed resistor R4 of the load resistor circuit 241. As a result, the resistance value R of the magnetoresistive element 11 changes from the high resistance value R H Switch to a low resistance value R L , write data “low”.

[0380] From time t45 to time t46, a verification read is performed as needed. Figure 38 In (a) and (c) of , the verification read is omitted and the data writing ends. However, note that the verification read can be performed. Figure 38 In (b) and (d), based on the above data writing from time t43 to time t44, a verification read is performed. Here, it is assumed that the data writing is successful. Therefore, the data writing is completed.

[0381] In this process, first, initialization to a high resistance state is performed using a method in a non-patent literature. A prescribed constant voltage is applied to all magnetoresistive elements 11 (all bits) at a specified address. Next, a low resistance state is written to the magnetoresistive element 11 (bit) whose write data is 0. In this case, the fixed resistor R4 is set to be on, and writing is performed. Verification is performed to check the result. The recorded state is read to determine whether the magnetoresistive element 11 is in a high resistance state. When the magnetoresistive element 11 is in a high resistance state, the process ends. In the case where the magnetoresistive element 11 is not in a high resistance state, the write process is performed again. Note that, for example, a maximum number of verifications and rewrites can be provided.

[0382] In the seventh embodiment, when the magnetoresistive element 11 is in the high resistance state, the state is not changed, and writing is performed only when the write data is 0 (low resistance state). When the magnetoresistive element 11 is in the low resistance state, the magnetoresistive element 11 is initialized to the high resistance state, and writing is performed only when the write data is 0 (low resistance state).

[0383] <8. Eighth embodiment>

[0384] <8-1. Example of Timing Chart of Write Processing>

[0385] Will refer to Figure 39 An example of a timing chart of a write process according to the eighth embodiment is described. Figure 39 1 is a timing chart showing a write process according to the eighth embodiment. The eighth embodiment is basically the same as the fifth embodiment. The difference therebetween (write process) will be described here.

[0386] In the eighth embodiment, the first embodiment and the non-patent document are combined, but initialization is not performed. In the first embodiment, pulse control of writing from high resistance to low resistance is facilitated by using load resistors (e.g., fixed resistors R1 and R2). In the non-patent document, pulse control of writing from low resistance to high resistance is facilitated by using a magnetic field in a perpendicular direction. Pulse control in two directions is facilitated by their combination.

[0387] exist Figure 39 In (a), write data "low". Figure 39 In (b), data "high" is written. Here, Figure 39 (a) and the above Figure 26 Same as (a). In addition, Figure 39 (b) and the above Figure 26 The difference of (b) is that the resistance value R is lower than the resistance value R L Switch to a high resistance value R H In the case of , a voltage V having a pulse width W3 is applied. Figure 26 (b) The voltage V of the short pulse width W2.

[0388] In the eighth embodiment, initial reading is performed, and the low resistance value R L With high resistance R H For example, when the data "high" is written, a constant voltage V (pulse width W3) is applied to the magnetoresistive element 11 to switch the resistance value R of the magnetoresistive element 11 from a low resistance value R to a high resistance value R. L Switch to a high resistance value R H .

[0389] <9. Functions / Effects According to Each Implementation>

[0390] As described above, according to various embodiments, the storage device 100 includes a magnetoresistive element 11, a selection element 12, and a write circuit 24. The magnetoresistive element 11 has a variable resistance value. The selection element 12 is connected to the magnetoresistive element 11. The write circuit 24 includes a load resistance circuit 241 having a variable resistance value, and applies a voltage V to the magnetoresistive element 11 via the load resistance circuit 241. Thus, by changing the resistance value of the load resistance circuit 241 and applying a voltage V to the magnetoresistive element 11 via the load resistance circuit 241, data can be correctly written to the magnetoresistive element 11. Therefore, the initial read is unnecessary. The write time can be shortened and the power consumption can be reduced. Even when the initial read is unnecessary, erroneous writing does not occur, which can improve the writing accuracy.

[0391] In addition, the load resistance circuit 241 may include a plurality of fixed resistors (e.g., fixed resistors R1, R2, R2a, and R2b) having fixed and different resistance values, and a switch (e.g., switch SW1 or SW2) that switches a plurality of wiring paths passing through the fixed resistors. This enables the load resistance circuit 241 to have a simple configuration.

[0392] In addition, the plurality of fixed resistors may include fixed resistors R1 and R2. When the resistance value R of the magnetoresistive element 11 is set to a high resistance value R HWhen the resistance value R of the magnetoresistive element 11 is set to the low resistance value R L When , the write circuit 24 can apply the voltage V to the magnetoresistive element 11 via the fixed resistor R2. This can reliably improve the writing accuracy.

[0393] Furthermore, the fixed resistor R1 may have a resistance value smaller than the resistance value of the fixed resistor R2 , thereby reliably improving the writing accuracy.

[0394] In addition, the plurality of fixed resistors may include fixed resistors R1, R2a, and R2b. When the resistance value R of the magnetoresistive element 11 is set to a high resistance value R H When the resistance value R of the magnetoresistive element 11 is set to the low resistance value R L When the voltage V is supplied via the fixed resistor R2a, the write circuit 24 can apply the voltage V to the magnetoresistive element 11 via the fixed resistor R2b. In the process of supplying the voltage V via the fixed resistor R2a, when the fixed resistor R2a is not present, the voltage V is applied to the magnetoresistive element 11 via the fixed resistor R2b. This reliably improves the writing accuracy.

[0395] Furthermore, the fixed resistor R1 may have a resistance value smaller than that of the fixed resistor R2b, and the fixed resistor R2a may have a resistance value larger than that of the fixed resistor R2b.

[0396] Furthermore, the load resistance circuit 241 may include a variable resistor R3 having a variable resistance value. This enables the load resistance circuit 241 to have a simple configuration.

[0397] In addition, when the resistance value R of the magnetoresistive element 11 is set to a high resistance value R H When the resistance value R of the magnetoresistive element 11 is set to the low resistance value R, the write circuit 24 may apply the voltage V to the magnetoresistive element 11 via the variable resistor R3 having the first resistance value. L When , the write circuit 24 can apply a voltage to the magnetoresistive element 11 via the variable resistor R3 having the second resistance value. This can reliably improve the writing accuracy.

[0398] Furthermore, the first resistance value may be smaller than the second resistance value, thereby reliably improving writing accuracy.

[0399] In addition, when the resistance value R of the magnetoresistive element 11 is set to a high resistance value R HWhen the resistance value R of the magnetoresistive element 11 is set to the low resistance value R, the write circuit 24 may apply the voltage V to the magnetoresistive element 11 via the variable resistor R3 having the first resistance value. L When the voltage V is applied to the magnetoresistive element 11 via the variable resistor R3 having the second resistance value, the write circuit 24 can apply the voltage V to the magnetoresistive element 11 via the variable resistor R3 having the second resistance value. Furthermore, while the voltage V is being applied via the variable resistor R3 having the second resistance value, the voltage V can be applied to the magnetoresistive element 11 via the variable resistor R3 having the third resistance value, rather than via the variable resistor R3 having the second resistance value. This reliably improves the writing accuracy.

[0400] Furthermore, the first resistance value may be smaller than the third resistance value, and the second resistance value may be larger than the third resistance value. Thus, the writing accuracy can be reliably improved.

[0401] Furthermore, the load resistance circuit 241 may include a fixed resistor R4 having a fixed resistance value and one or both of two switches SW3a and SW3b that switch between a wiring path passing through the fixed resistor R4 and a wiring path not passing through the fixed resistor R4. This enables the load resistance circuit 241 to have a simple configuration.

[0402] Furthermore, when the resistance value R of the magnetoresistive element 11 is set to a high resistance value R H or low resistance R L When , the write circuit 24 can apply the voltage V to the magnetoresistive element 11 via the fixed resistor R4. This can reliably improve the writing accuracy.

[0403] Furthermore, the write circuit 24 can divide the voltage V by using the load resistance circuit 241 and apply the voltage V to the magnetoresistive element 11 . Thus, the writing accuracy can be reliably improved.

[0404] Furthermore, the load resistance circuit 241 may be connected to the side of the magnetoresistive element 11 opposite to the side facing the selection element 12. This ensures that writing accuracy can be improved.

[0405] Furthermore, the voltage V may be a pulse voltage. The pulse voltage may have a pulse width of 0.1 ns to 20 ns. This can reduce the write error rate and reliably improve the write accuracy.

[0406] Furthermore, the voltage V may be a pulse voltage. The write circuit 24 may perform writing by repeatedly applying the pulse voltage once or multiple times. This can reduce the write error rate and reliably improve the write accuracy.

[0407] Furthermore, the pulse voltage may have a pulse width that is different each time the pulse voltage is applied. This can reduce the writing error rate and reliably improve the writing accuracy.

[0408] <10. Other Implementation Methods>

[0409] In addition to the above-described embodiments, the configuration and processing segments according to the above-described embodiments (examples and variations) can be implemented in various different forms. For example, the configuration and processing segments are not limited to the above-described examples and can be implemented in various ways. In addition, the configuration, processing procedures, specific names, and information including various data and parameters in the above-described documents and drawings can be optionally changed unless otherwise specified. For example, the information in each figure is not limited to the information shown.

[0410] Furthermore, the configuration and processing according to the above-described embodiments (examples and modifications) do not necessarily require the physical configuration shown. That is, the specific form of distribution / integration of each device is not limited to the form shown, and all or part of them can be configured in any unit in a functionally or physically distributed / integrated manner according to various loads and usage situations.

[0411] In addition, the configuration and processing according to the above-mentioned embodiments (examples and variations) can be appropriately combined. For example, at least a part of the embodiment can be appropriately combined with at least a part of another embodiment. In addition, the effects in the embodiments are only examples and not limitations. Other effects can be exhibited.

[0412] <11. Configuration Examples of Electronic Devices>

[0413] As an electronic device to which the storage device 100 according to the above-described embodiment (including modified examples) is applied, reference will be made to Figures 40 to 41 The imaging device 300 and the distance measuring device 400 are described. For example, each of the imaging device 300 and the distance measuring device 400 uses the storage device 100 according to each of the above-described embodiments as a memory. Examples of the memory include a flash memory and the like.

[0414] <11-1. Imaging Device>

[0415] Will refer to Figure 40 An imaging device 300 to which the storage device 100 according to the above-described embodiment is applied is described. Figure 40 1 is a diagram showing an example of a schematic configuration of an imaging device 300. The imaging device 300 is an example of an electronic device to which the storage device 100 according to this embodiment is applied. Examples of the imaging device 300 include electronic devices such as digital cameras, video cameras, smartphones with imaging functions, and mobile phones.

[0416] like Figure 40As shown, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element (solid-state imaging device) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 can capture still images and moving images.

[0417] The optical system 301 includes one or more lenses and guides light (incident light) from a subject to the imaging element 303 , forming an image on the light-receiving surface of the imaging element 303 .

[0418] The shutter device 302 is provided between the optical system 301 and the imaging element 303. The shutter device 302 controls a light irradiation period and a light shielding period for the imaging element 303 according to control of the control circuit 304.

[0419] The imaging element 303 accumulates signal charges for a certain period of time based on light formed on the light receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the imaging element 303 are transferred based on a drive signal (timing signal) supplied from the control circuit 304.

[0420] The control circuit 304 outputs a drive signal for controlling the transfer operation of the imaging element 303 and the shutter operation of the shutter device 302 to drive the imaging element 303 and the shutter device 302 .

[0421] The signal processing circuit 305 performs various types of signal processing on the signal charge output from the imaging element 303. An image (image data) obtained by the signal processing by the signal processing circuit 305 is supplied to a monitor 306 and also supplied to a memory 307.

[0422] The monitor 306 displays a moving image or a still image captured by the imaging element 303 based on the image data supplied from the signal processing circuit 305. The monitor 306 uses a panel-type display device such as a liquid crystal panel or an organic electroluminescence (EL) panel, for example.

[0423] The memory 307 stores image data supplied from the signal processing circuit 305, that is, image data of a moving image or a still image captured by the imaging element 303. The memory 307 corresponds to the storage device 100 according to the above-described embodiment.

[0424] Also in the imaging device 300 configured in this manner, data writing accuracy can be improved by using the above-described storage device 100 as the memory 307 .

[0425] <11-2. Distance Measuring Device>

[0426] Will refer to Figure 41A distance measuring device 400 to which the storage device 100 according to the above-described embodiment is applied will be described. Figure 41 2 is a diagram illustrating an example of a schematic configuration of a distance measurement device 400. The distance measurement device 400 is an example of an electronic device to which the storage device 100 according to the present embodiment is applied.

[0427] like Figure 41 As shown, the distance measuring device (distance image sensor) 400 includes a light source unit 401, an optical system 402, an imaging element (solid-state imaging device) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. The distance measuring device 400 can acquire a distance image according to the distance to the object by projecting light from the light source unit 401 toward the object and receiving light (modulated light or pulsed light) reflected from the surface of the object.

[0428] The light source unit 401 projects light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line, is used as the light source unit 401. Note that the laser diode array is supported by a predetermined drive unit (not shown) and scans in a direction perpendicular to the array direction of the laser diodes.

[0429] The optical system 402 includes one or more lenses. The optical system 402 guides light (incident light) from a subject to the imaging element 403 to form an image on a light receiving surface (sensor unit) of the imaging element 403.

[0430] The imaging element 403 stores signal charge corresponding to light of an image formed on the light receiving surface via the optical system 402. A distance signal indicating a distance obtained from a light reception signal (APDOUT) output from the imaging element 403 is supplied to the signal processing circuit 405. As the imaging element 403, for example, a solid-state imaging element such as an image sensor is used.

[0431] The control circuit 404 outputs a drive signal (control signal) for controlling the operation of the light source unit 401 , the imaging element 403 , and the like, and drives the light source unit 401 , the imaging element 403 , and the like.

[0432] The signal processing circuit 405 performs various types of signal processing on the distance signal supplied from the imaging element 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to the monitor 406 and also to the memory 407.

[0433] The monitor 406 displays the distance image captured by the imaging element 403 based on the image data supplied from the signal processing circuit 405. As the monitor 406, for example, a panel-type display device such as a liquid crystal panel or an organic EL panel is used.

[0434] The memory 407 stores the image data supplied from the signal processing circuit 405, that is, the image data of the range image captured by the imaging element 403. The memory 407 corresponds to the storage device 100 according to the above-described embodiment.

[0435] Also in the distance measuring device 400 configured in this manner, by using the above-described storage device 100 as the memory 407 , data writing accuracy can be improved.

[0436] It should be noted that the memory device 100 according to the above-described embodiment may be mounted on the same semiconductor chip together with a semiconductor circuit forming an arithmetic device or the like to form a semiconductor device (system on chip: SoC).

[0437] Furthermore, the storage device 100 according to the above embodiment can be installed in various electronic devices. As described above, the memory (storage unit) can be installed in various electronic devices. For example, in addition to the imaging device 300 and the distance measuring device 400, the storage device 100 can be installed in various electronic devices such as gaming devices, notebook personal computers (PCs), mobile devices (e.g., smartphones, tablet PCs, etc.), personal digital assistants (PDAs), wearable devices, and music devices. For example, the storage device 100 is used as various memories such as memory.

[0438] <12. Appendix>

[0439] It should be noted that the present technology can also have the following configurations. (1)

[0441] A storage device, comprising:

[0442] a magnetoresistive element having a variable resistance value;

[0443] a selection element connected to the magnetoresistive element; and

[0444] The write circuit includes a load resistance circuit having a variable resistance value, and applies a voltage to the magnetoresistive element via the load resistance circuit. (2)

[0446] According to the storage device of (1),

[0447] The load resistance circuit includes:

[0448] a plurality of fixed resistors having fixed and respectively different resistance values; and

[0449] The switch switches a plurality of wiring paths passing through the plurality of fixed resistors. (3)

[0451] According to the storage device of (2),

[0452] wherein the plurality of fixed resistors include a first fixed resistor and a second fixed resistor, and

[0453] When the resistance value of the magnetoresistive element is set to a high resistance value, the write circuit applies a voltage to the magnetoresistive element via the first fixed resistor, and

[0454] When the resistance value of the magnetoresistive element is set to a low resistance value, the write circuit applies a voltage to the magnetoresistive element via the second fixed resistor. (4)

[0456] According to the storage device of (3),

[0457] The resistance value of the first fixed resistor is smaller than the resistance value of the second fixed resistor. (5)

[0459] According to the storage device of (2),

[0460] wherein the plurality of fixed resistors include a first fixed resistor, a second fixed resistor, and a third fixed resistor, and

[0461] When the resistance value of the magnetoresistive element is set to a high resistance value, the write circuit applies a voltage to the magnetoresistive element via the first fixed resistor, and

[0462] When the resistance value of the magnetoresistive element is set to a low resistance value, the write circuit applies voltage to the magnetoresistive element via the second fixed resistor, and applies voltage to the magnetoresistive element via the third fixed resistor instead of the second fixed resistor while supplying voltage via the second fixed resistor. (6)

[0464] According to the storage device of (5),

[0465] wherein the resistance value of the first fixed resistor is smaller than the resistance value of the third fixed resistor, and

[0466] The resistance value of the second fixed resistor is greater than the resistance value of the third fixed resistor. (7)

[0468] According to the storage device of (1),

[0469] The load resistance circuit includes a variable resistor with a variable resistance value. (8)

[0471] According to the storage device of (7),

[0472] wherein, when the resistance value of the magnetoresistive element is set to a high resistance value, the write circuit applies a voltage to the magnetoresistive element via a variable resistor having a first resistance value, and

[0473] When the resistance value of the magnetoresistive element is set to a low resistance value, the write circuit applies a voltage to the magnetoresistive element via the variable resistor having a second resistance value. (9)

[0475] According to the storage device of (8),

[0476] The first resistance value is smaller than the second resistance value. (10)

[0478] According to the storage device of (7),

[0479] wherein, when the resistance value of the magnetoresistive element is set to a high resistance value, the write circuit applies a voltage to the magnetoresistive element via a variable resistor having a first resistance value, and

[0480] When the resistance value of the magnetoresistive element is set to a low resistance value, the write circuit applies a voltage to the magnetoresistive element via a variable resistor having a second resistance value, and applies a voltage to the magnetoresistive element via a variable resistor having a third resistance value instead of the variable resistor having the second resistance value in the middle of supplying the voltage via the variable resistor having the second resistance value. (11)

[0482] According to the storage device of (10),

[0483] wherein the first resistance value is smaller than the third resistance value, and

[0484] The second resistance value is greater than the third resistance value. (12)

[0486] According to the storage device of (1),

[0487] The load resistance circuit includes:

[0488] a fixed resistor having a fixed resistance value; and

[0489] The switch switches between a wiring path passing through the fixed resistor and a wiring path not passing through the fixed resistor. (13)

[0491] According to the storage device of (12),

[0492] When the resistance value of the magnetoresistive element is set to a high resistance value or a low resistance value, the write circuit applies a voltage to the magnetoresistive element via the fixed resistor. (14)

[0494] The storage device according to any one of (1) to (13),

[0495] Among them, the write circuit divides the voltage by using a load resistance circuit and applies the voltage to the magnetoresistive element. (15)

[0497] The storage device according to any one of (1) to (14),

[0498] Here, the load resistance circuit is connected to the side of the magnetoresistive element opposite to the side of the selection element. (16)

[0500] The storage device according to any one of (1) to (15),

[0501] where voltage is the pulse voltage, and

[0502] The pulse voltage has a pulse width of 0.1 ns to 20 ns. (17)

[0504] The storage device according to any one of (1) to (16),

[0505] where voltage is the pulse voltage, and

[0506] The writing circuit performs writing by repeatedly applying a pulse voltage one or more times. (18)

[0508] According to the storage device of (17),

[0509] The pulse voltage has a pulse width that is different every time the pulse voltage is applied. (19)

[0511] An electronic device comprising a storage device for storing data,

[0512] The storage device includes:

[0513] a magnetoresistive element having a variable resistance value;

[0514] a selection element connected to the magnetoresistive element; and

[0515] The write circuit includes a load resistance circuit having a variable resistance value, and applies a voltage to the magnetoresistive element via the load resistance circuit. (20)

[0517] A method for controlling a storage device includes controlling the storage device, the storage device including: a magnetoresistive element having a variable resistance value; and a selection element connected to the magnetoresistive element,

[0518] Here, the write circuit applies a voltage to the magnetoresistive element via a load resistor circuit having a variable resistance value. (twenty one)

[0520] An electronic device includes the storage device according to any one of (1) to (18). (twenty two)

[0522] A method of controlling a storage device, comprising controlling the storage device according to any one of (1) to (18).

[0523] Explanation of symbols

[0524] 1 Memory cell array 10 Memory cell 11 Magnetoresistive element 12 Selecting element

[0525] 21 I / O 22 Control circuit 23 Voltage generation circuit 24 Write circuit

[0526] 25 Read circuit 26 Bit line address decoder 27 Bit line control circuit

[0527] 28 word line address decoder 29 word line control circuit 30 sense amplifier

[0528] 100 Storage device 111 Pinned layer 112 Tunnel barrier layer 113 Recording layer

[0529] 114 magnetic field generating layer 115 magnetic field generating layer 241 load resistance circuit

[0530] 300 Imaging device 307 Memory 400 Distance measuring device 407 Memory

[0531] L1 wiring R1 fixed resistor R2 fixed resistor R2a fixed resistor

[0532] R2b fixed resistor R3 variable resistor R4 fixed resistor SW1 switch

[0533] SW2 switch SW3a switch SW3b switch BL bit line

[0534] SL source line WL word line.

Claims

1. A storage device comprising: a magnetoresistive element having a variable resistance value; a selection element connected to the magnetoresistive element; as well as The write circuit includes a load resistance circuit having a variable resistance value, and applies a voltage to the magnetoresistive element via the load resistance circuit.

2. The storage device according to claim 1, in, The load resistance circuit comprises: a plurality of fixed resistors having fixed and different resistance values; and A switch switches the plurality of wiring paths passing through the plurality of fixed resistors.

3. The storage device according to claim 2, in, The plurality of fixed resistors include a first fixed resistor and a second fixed resistor, and When the resistance value of the magnetoresistive element is set to a high resistance value, the write circuit applies a voltage to the magnetoresistive element via the first fixed resistor, and When the resistance value of the magnetoresistive element is set to a low resistance value, the write circuit applies a voltage to the magnetoresistive element via the second fixed resistor.

4. The storage device according to claim 3, in, A resistance value of the first fixed resistor is smaller than a resistance value of the second fixed resistor.

5. The storage device according to claim 2, in, The plurality of fixed resistors include a first fixed resistor, a second fixed resistor, and a third fixed resistor, and When the resistance value of the magnetoresistive element is set to a high resistance value, the write circuit applies a voltage to the magnetoresistive element via the first fixed resistor, and When the resistance value of the magnetoresistive element is set to a low resistance value, the write circuit applies a voltage to the magnetoresistive element via the second fixed resistor, and applies a voltage to the magnetoresistive element via the third fixed resistor instead of the second fixed resistor in the middle of supplying the voltage via the second fixed resistor.

6. The storage device according to claim 5, in, The resistance value of the first fixed resistor is smaller than the resistance value of the third fixed resistor, and The resistance value of the second fixed resistor is greater than the resistance value of the third fixed resistor.

7. The storage device according to claim 1, in, The load resistance circuit includes a variable resistor having a variable resistance value.

8. The storage device according to claim 7, in, When the resistance value of the magnetoresistive element is set to a high resistance value, the write circuit applies a voltage to the magnetoresistive element via the variable resistor having a first resistance value, and When the resistance value of the magnetoresistive element is set to a low resistance value, the write circuit applies a voltage to the magnetoresistive element via the variable resistor having a second resistance value.

9. The storage device according to claim 8, in, The first resistance value is smaller than the second resistance value.

10. The storage device according to claim 7, in, When the resistance value of the magnetoresistive element is set to a high resistance value, the write circuit applies a voltage to the magnetoresistive element via the variable resistor having a first resistance value, and When the resistance value of the magnetoresistive element is set to a low resistance value, the write circuit applies a voltage to the magnetoresistive element via the variable resistor having the second resistance value, and applies a voltage to the magnetoresistive element via the variable resistor having the third resistance value instead of the variable resistor having the second resistance value in the middle of supplying the voltage via the variable resistor having the second resistance value.

11. The storage device according to claim 10, in, The first resistance value is smaller than the third resistance value, and The second resistance value is greater than the third resistance value.

12. The storage device according to claim 1, in, The load resistance circuit comprises: a fixed resistor having a fixed resistance value; and A switch switches between a wiring path passing through the fixed resistor and a wiring path not passing through the fixed resistor.

13. The storage device according to claim 12, in, When the resistance value of the magnetoresistive element is set to a high resistance value or a low resistance value, the write circuit applies a voltage to the magnetoresistive element via the fixed resistor.

14. The storage device according to claim 1, in, The write circuit divides the voltage by using the load resistance circuit and applies the voltage to the magnetoresistive element.

15. The storage device according to claim 1, in, The load resistance circuit is connected to a side of the magnetoresistive element opposite to a side of the selection element.

16. The storage device according to claim 1, in, The voltage is a pulse voltage, and The pulse voltage has a pulse width of 0.1 ns or more and 20 ns or less.

17. The storage device according to claim 1, in, The voltage is a pulse voltage, and The writing circuit performs writing by repeatedly applying the pulse voltage one or more times.

18. The storage device according to claim 17, in, The pulse voltage has a pulse width that is different for each application of the pulse voltage.

19. An electronic device comprising a storage device for storing data, in, The storage device includes: a magnetoresistive element having a variable resistance value; a selection element connected to the magnetoresistive element; and The write circuit includes a load resistance circuit having a variable resistance value, and applies a voltage to the magnetoresistive element via the load resistance circuit.

20. A method for controlling a storage device, comprising controlling a storage device, wherein the storage device comprises: a magnetoresistive element having a variable resistance value; and a selection element connected to the magnetoresistive element, wherein the write circuit applies a voltage to the magnetoresistive element via a load resistance circuit having a variable resistance value.

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