Utilizing multiple analog-to-digital converters in conversion circuit

Abstract

Examples related to analog-to-digital conversion are disclosed. One example provides a conversion circuit including a first analog-to-digital converter (ADC) configured to convert an analog voltage to generate a first subset of digital output bits from a most significant bit (MSB) to a bit k and a second subset of digital output bits from bit k-1 to a least significant bit (LSB) of the first ADC. The bit k is located between the MSB and the LSB. The first ADC includes a residual output configured to output a residual voltage of the analog voltage after the conversion bit k. The conversion circuit also includes an amplifier stage connected to the residual output and configured to generate an amplified residual voltage. The conversion circuit also includes a second ADC connected to the amplifier stage and configured to convert the amplified residual voltage to generate additional digital output bits.

Description

Background Art

[0001] Many sensors use analog-to-digital converters (ADCs) to convert analog voltages into digital bits for subsequent processing. In some sensor applications, high-resolution ADCs can be beneficial. However, designing a high-resolution ADC can be challenging. Furthermore, high-resolution ADCs can incur higher development costs than lower-resolution ADCs. Furthermore, many high-resolution ADCs can consume more power and / or area than lower-resolution ADCs. Summary of the Invention

[0002] This summary is provided to introduce a series of concepts in a simplified form that are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that solve any or all disadvantages noted in any part of this disclosure.

[0003] Examples are disclosed relating to a conversion circuit for converting an analog voltage into digital output bits. One example provides a conversion circuit comprising a first analog-to-digital converter (ADC) configured to convert an analog voltage to generate a first subset of digital output bits of the first ADC from a most significant bit (MSB) to bit k, and then generate a second subset of digital output bits of the first ADC from bit k-1 to a least significant bit (LSB). Bit k of the first ADC is between the MSB and the LSB. The first ADC includes a residual output configured to output a residual voltage of the analog voltage after converting bit k. The conversion circuit also includes an amplifier stage connected to the residual output of the first ADC. The amplifier stage is configured to generate an amplified residual voltage at the output of the amplifier stage. The conversion circuit also includes a second ADC connected to the output of the amplifier stage. The second ADC is configured to convert the amplified residual voltage at the output of the amplifier stage to generate additional digital output bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An example device in the form of a digital pen utilizing conversion circuitry is schematically depicted.

[0005] Figure 2 A block diagram of an example device including conversion circuitry is shown.

[0006] Figure 3 An example conversion circuit using the same circuit template for a first ADC and a second ADC is schematically depicted.

[0007] Figure 4 An example conversion circuit using different circuit templates for a first ADC and a second ADC is schematically depicted.

[0008] Figure 5 An example successive approximation register (SAR) ADC circuit template is schematically depicted.

[0009] Figure 6 A flow chart illustrating an example method for using a conversion circuit is illustrated.

[0010] Figure 7 A block diagram of an example computing system is depicted. DETAILED DESCRIPTION

[0011] As mentioned earlier, many sensors use an ADC to convert analog voltages into digital bits for later processing. Some ADCs convert analog voltages from the ADC's most significant bit (MSB) to the least significant bit (LSB). The MSB is associated with a larger analog voltage difference in the ADC, and the LSB is associated with a smaller analog voltage difference in the ADC. Smaller analog voltage differences can be closer to the noise floor of the ADC's comparator. Therefore, when evaluating smaller analog voltage differences, the comparator may have a higher probability of error. One possible solution is to use a sub-ranging technique in the ADC. For example, this sub-ranging technique first converts Nk bits serially, then multiplies the residue, and then converts the remaining k bits. This enables a larger analog voltage difference to be generated when evaluating the less significant bits. However, this sub-ranging technique relies on the precise gain stage of the amplifier to evaluate the next stage.

[0012] Therefore, an example is disclosed involving a conversion circuit including a first ADC, an amplifier stage, and a second ADC. The first ADC is configured to convert an analog voltage to generate a first subset of digital output bits from the MSB to bit k of the first ADC, and then generate a second subset of digital output bits from bit k-1 to the LSB of the first ADC. Bit k of the first ADC is located between the MSB and the LSB. The first ADC includes a residue output configured to output a residual voltage of the analog voltage after converting bit k. An amplifier stage is connected to the residue output of the first ADC. The amplifier stage is configured to generate an amplified residual voltage at the output of the amplifier stage. A second ADC is connected to the output of the amplifier stage. The second ADC is configured to convert the amplified residual voltage at the output of the amplifier stage to generate additional digital output bits. The additional digital output bits and the second subset of digital output bits include overlapping information related to the residual voltage. Post-processing the bits generated by the first ADC and the bits generated by the second ADC can help extend the bit resolution of the conversion circuit compared to using only the first ADC. Using a conversion circuit including two ADCs can help improve the accuracy of the conversion circuit compared to using a single high-resolution ADC. Furthermore, the conversion circuit can help reduce area, power, and / or development costs compared to a single ADC at high resolution.The disclosed dialog circuit can be particularly well-suited for circuit designs where the design limiting factor is the noise constraint of the comparator rather than the self-noise of previous circuits.

[0013] Before discussing the disclosed examples in detail, Figure 1 An example device 100 including a conversion circuit 102 is depicted. Device 100 is in the form of a digital pen. Here, device 100 communicates with a tablet computer 104. Device 100 includes a pressure sensor 106 for sensing pressure at the tip of device 100. This pressure can indicate the writing pressure of device 100 against tablet computer 104 or another suitable pressure measurement. Conversion circuit 102 is connected to the output of pressure sensor 106. Conversion circuit 102 is configured to convert an analog voltage from the pressure sensor and generate digital output bits for later processing, as will be discussed in more detail below. The later processing can cause device 100 and / or tablet computer 104 to perform a specified task based on the writing pressure of device 100. Although depicted as a digital pen, device 100 can take other suitable forms, such as a tablet computer, a mobile phone, a laptop computer, a microphone, and a digital sensor. Figure 1 In other examples, conversion circuit 102 may sample another suitable analog voltage from any other suitable type of sensor, such as a light sensor, an acoustic sensor, a thermal sensor, a touch sensor, and a chemical sensor.

[0014] As mentioned earlier, for some applications, a high-resolution conversion circuit may be required. Figure 1 In the example of FIG, the high resolution of the conversion circuit 102 can help detect more different write pressure levels of the device 100. However, developing a single high resolution ADC may incur additional development time and / or cost.

[0015] Therefore, compared with a single high-resolution ADC, a conversion circuit using two ADCs can extend the bit resolution. In addition, a conversion circuit using two ADCs can help improve the accuracy of the conversion circuit. Figure 2 A block diagram of an example device 200 including conversion circuitry 202 is depicted. Conversion circuitry 102 is an example of conversion circuitry 202. Device 200 can be any suitable device that utilizes a method of converting an analog voltage into digital bits for later processing. Example devices include, but are not limited to, a digital pen, a tablet computer, a mobile phone, a microphone, and a digital sensor. Conversion circuitry 202 is configured to sample an analog voltage 204 from an analog source 206 and generate digital output bits 208 and additional digital output bits 210 based on the analog voltage 204. Analog source 206 can include the output of a sensor, a detection input of device 200, a received electromagnetic signal, or another suitable analog voltage source. Device 200 also includes a digital signal processing (DSP) module 212 for post-processing digital output bits 208 and additional digital output bits 210 to generate digital resolution bits 214. Here, the number of digital output bits 208 and additional digital output bits 210 is greater than the number of digital resolution bits 214. Therefore, the DSP module 212 is configured to extract desired bits from the digital output bits 208 and the additional digital output bits 210 to generate the digital resolution bits 214. As a specific example, the DSP module 212 may use interpolation or another suitable signal processing algorithm to generate the digital resolution bits 214. Furthermore, the DSP module 212 may use some form of error correction when receiving both the digital output bits 208 and the additional digital output bits 210, where the digital output bits 208 and the additional digital output bits 210 have overlap.

[0016] The conversion circuit 202 includes a first ADC 216 connected to an analog source 206, an amplifier stage 218 connected to a residual output 220 of the first ADC 216, and a second ADC 222 connected to the output of the amplifier stage 218. The first ADC 216 is configured to convert the analog voltage 204 to generate a first subset of digital output bits 208 from the MSB to bit k of the first ADC 216, and then generate a second subset of digital output bits 208 from bit k-1 to the LSB of the first ADC 216. Bit k of the first ADC 216 is located between the MSB and the LSB. In some examples, bit k can be configured to a different value, such as using firmware. The residual output 220 is configured to output a residual voltage 224 of the analog voltage 204 after converting bit k. The first ADC 216 can include any suitable ADC configured to gradually convert an analog voltage, such as a successive approximation register (SAR) ADC and a pipeline ADC. Figure 5 An example ADC circuit for use as the first ADC 216 is discussed.

[0017] Amplifier stage 218 is configured to amplify residue voltage 224 to generate an amplified residue voltage 226 at the output of amplifier stage 218. As a specific example, residue voltage 224 can be multiplied by a gain factor of amplifier stage 218 to generate amplified residue voltage 226. In some examples, the gain factor can be configurable, for example, using firmware of device 200. The higher the gain factor of amplifier stage 218, the more overlap is generated between additional digital output bits 210 and digital output bits 208. This overlap can help DSP module 212 generate digital resolution bits 214. It should be understood that noise on residue voltage 224 is also amplified by amplifier stage 218. Therefore, amplifier stage 218 includes a linear low-noise amplifier. Furthermore, amplifier stage 218 can include an operational amplifier or another suitable amplifier. In some examples, amplified residue voltage 226 is configured to be less than the full dynamic range of second ADC 222. In some such examples, one or more more significant bits of second ADC 222 can be preloaded with logic zeros. In other examples, the amplified residue voltage 226 may be configured to use the full dynamic range of the second ADC 222 .

[0018] The second ADC 222 is configured to convert the amplified residual voltage 226 at the output of the amplifier stage 218 to generate the additional digital output bits 210. In some examples, the second ADC 222 is configured to generate the additional digital output bits 210 in parallel with the first ADC 216 generating the second subset of digital output bits 208. This configuration can help reduce the time to generate both the second subset of digital output bits 208 and the additional digital output bits 210 and thereby generate the digital resolution bits 214. In some examples, the second ADC 222 can include the same circuit template as the first ADC 216 to help reduce development costs, as shown in FIG. Figure 3 More specifically, using the same circuit template for both the first ADC 216 and the second ADC 222 reduces the number of unique circuits that need to be designed and verified. In other examples, the first ADC 216 and the second ADC 222 may include different circuit templates, such as those described in reference to FIG. Figure 4 As discussed, using different circuit templates, the second ADC 222 can have different circuitry than the first ADC 216, which can consume less area and / or power.

[0019] The digital resolution bits 214 may optionally include N bits 228 indicating the value of the analog voltage 204. As used herein, "N" indicates the number of bits from the MSB to the LSB of the first ADC 216. Using the conversion circuit 202 to help generate the N bits 228 of the digital resolution bits 214 can help improve the accuracy of the analog-to-digital conversion compared to using only the first ADC 216. Alternatively, the digital resolution bits 214 can include N+j bits 230. As used herein, "j" is used to represent the number of bits used to extend the resolution of the first ADC 216. Typically, j is less than the number of additional digital output bits 210. In some examples, j can include one, two, or three bits. In this way, the conversion circuit 202 can help extend the bit resolution of the analog-to-digital conversion compared to using only the first ADC 216, while also helping to reduce development costs.

[0020] As mentioned above, the same circuit template can be used to implement the first ADC and the second ADC. Figure 3An example conversion circuit 300 is schematically depicted, which utilizes the same circuit template to implement a first ADC 302 and a second ADC 304. Conversion circuit 300 is an example implementation of conversion circuit 202. As shown, first ADC 302 and second ADC 304 utilize the same N-bit SAR ADC circuit template. In other examples, first ADC 302 and second ADC 304 may utilize the same circuit template, including another suitable gradually converging ADC circuit template, such as a pipelined ADC circuit template. Using a gradually converging ADC facilitates providing the first ADC's residual voltage to the second ADC at a known bit position.

[0021] The first ADC 302 is configured to convert an analog voltage 306 (shown here as Vin) into digital output bits 308 using a reference voltage Vref 310. More specifically, the first ADC 302 is configured to convert the analog voltage 306 to generate a first subset of digital output bits 308 from the MSB to bit k of the first ADC 302, and to generate a second subset of digital output bits 308 from bit k-1 to the LSB of the first ADC. Bit k is located between the MSB and the LSB of the first ADC 302. Here, the MSB is represented as "N-1" and the LSB is represented as "0". The first ADC 302 includes a residual output that is configured to output a residual voltage 312 of the analog voltage 306 after converting bit k. As shown, the residual voltage 312 includes "Vdacp" and "Vdacn". In other examples, the residual voltage 312 may include another suitable voltage.

[0022] The conversion circuit 300 further includes an amplifier stage 314 connected to the residue output of the first ADC 302. Similar to the amplifier stage 218, the amplifier stage 314 is configured to generate an amplified residue voltage 316 at the output of the amplifier stage 314.

[0023] Second ADC 304 is connected to the output of amplifier stage 314. Second ADC 304 is configured to convert amplified residual voltage 316 at the output of amplifier stage 314 to generate additional digital output bits 317. In some examples, amplified residual voltage 316 may be less than the full resolution of second ADC 304. In some such examples, one or more high-resolution bits of second ADC 304 may be preloaded with logic zeros. A high-resolution bit corresponds to a voltage resolution of second ADC 304 greater than amplified residual voltage 316. This configuration facilitates implementing first ADC 302 and second ADC 304 using the same circuit template. As shown, additional digital output bits 317 include the MSB, which is "N-1," to the LSB, which is "0." Second ADC 304 is configured to generate additional digital output bits 317 in parallel with the generation of the second subset of digital output bits 308 by first ADC 302. This configuration can help reduce the time required to generate both the second subset of digital output bits 308 and the additional digital output bits 317. Because both first ADC 302 and second ADC 304 include the same circuit template, second ADC 304 has an additional residual output 318. Here, additional residual output 318 includes no connection and is therefore not connected to other circuits. In other examples, additional residual output 318 can be connected to other circuits. The depicted example conversion circuit 300 is illustrative, and in other examples, any other suitable circuit can be used as conversion circuit 300.

[0024] exist Figure 3 In the example of FIG. 5 , the first ADC and the second ADC are implemented using the same circuit template. Alternatively, the first ADC and the second ADC may be implemented using different circuit templates. Figure 4An example conversion circuit 400 is schematically depicted, which uses different circuit templates to implement a first ADC 402 and a second ADC 404. Conversion circuit 400 is an example of conversion circuit 202. Similar to conversion circuit 300, conversion circuit 400 includes a first ADC 402 having an N-bit SAR ADC circuit template and an amplifier stage 406. In contrast, second ADC 404 of conversion circuit 400 includes a different ADC circuit template. In some examples, second ADC 404 uses a SAR ADC template with a smaller bit resolution than first ADC 402. In these examples, it should be understood that the reference voltage 408 of second ADC 404 is selected to be compatible with the gain factor of amplifier stage 406. This configuration can help reduce the area and / or power consumption of conversion circuit 400. In other examples, second ADC 404 can include any other suitable ADC, such as a flash ADC, an integrated ADC, or a sigma-delta ADC. The different ADC circuit templates of second ADC 404 can be selected to help reduce the area, power consumption, and / or development cost of conversion circuit 400. The depicted example conversion circuit 400 is illustrative, and in other examples, any other suitable circuit may be used as the conversion circuit 400 .

[0025] Figure 5 An example SAR ADC 500 is schematically depicted. For example, the SAR ADC 500 can be used as the first ADC 216, the second ADC 222, the first ADC 302, the second ADC 304, and the first ADC 402. The SAR ADC 500 is configured to convert an analog voltage 502 (shown here as "Vin") to generate digital bits 504 from the MSB to bit k and from bit k-1 to the LSB of the SAR ADC 500. Here, the MSB is shown as "N-1" and the LSB is shown as "0". Bit k of the SAR ADC 500 is located between the MSB and the LSB. The SAR ADC 500 is also configured to output a residual voltage of the analog voltage 502 after converting bit k (shown here as Vdacp 506 and Vdacn 508). More specifically, both Vdacp 506 and Vdacn 508 are used internally within the SAR ADC 500 and are connected to a residue output (not shown) of the SAR ADC 500 .

[0026] SAR ADC 500 includes a first digital-to-analog converter (DAC) 510, a second DAC 512, a comparator 514, and SAR logic 516 for converting analog voltage 502. More specifically, based on analog voltage 502 and a reference voltage, first DAC 510 outputs Vdacn 508, and second DAC outputs Vdacp 506. First DAC 510 and second DAC 512 may include any suitable DAC circuitry. Comparator 514 then compares Vdacn 508 with Vdacp 506. Comparator 514 is configured to output a logic 1 or 0 based on the comparison. SAR logic 516 is configured to sequentially determine digital bits 504 from the MSB to the LSB based on the output of comparator 514. SAR ADC 500 can be reset using switch 518 between converting different analog voltages. In other examples, SAR ADC 500 can be reset in another suitable manner. The depicted example SAR ADC 500 is illustrative, and in other examples, any other suitable circuit may be used as the SAR ADC 500 .

[0027] Figure 6 A flow chart illustrating an example method 600 for using a conversion circuit (e.g., conversion circuit 102, conversion circuit 202, conversion circuit 300, or conversion circuit 400) is shown. The conversion circuit includes a first ADC, an amplifier stage connected to a residual output of the first ADC, and a second ADC connected to an output of the amplifier stage. Method 600 includes, at 602, converting an analog voltage using the first ADC to generate a first subset of digital output bits from the MSB to bit k of the first ADC, and then generating a second subset of digital output bits from bit k-1 to the LSB of the first ADC. Bit k of the first ADC is between the MSB and the LSB. In some examples, the analog voltage is related to a sensed pressure on a digital pen, as shown at 604. In other examples, the analog voltage can be related to another sensed quantity or another suitable analog voltage.

[0028] Method 600 also includes, at 606, outputting a residual voltage of the analog voltage from the first ADC after conversion of bit k. Next, method 600 includes, at 608, amplifying the residual voltage using an amplifier stage to generate an amplified residual voltage at the output of the amplifier stage. Then, method 600 includes, at 610, converting the amplified residual voltage at the output of the amplifier stage using a second ADC to generate additional digital output bits. Furthermore, generating the second subset of digital output bits and generating the additional digital output bits are performed in parallel, as shown at 612. In examples where the first ADC and the second ADC are implemented using the same circuit template, method 600 may include, at 614, preloading one or more high-resolution bits of the second ADC with logic zeros. This configuration facilitates reuse of the same circuit template between the first ADC and the second ADC. Optionally, method 600 also includes, at 616, determining N digital resolution bits for output based on at least the plurality of bits generated by the first ADC and the one or more bits generated by the second ADC. As a specific example, at least some of the bit values ​​of the digital resolution bits are determined using digital signal processing. In some examples, N digital resolution bits can be used for later processing. Alternatively, method 600 includes, at 618, determining N+j digital resolution bits for output based on at least a plurality of bits generated by the first ADC and one or more bits generated by the second ADC. This configuration extends the bit resolution of the conversion circuit.

[0029] As disclosed herein, a conversion circuit including a first ADC, an amplifier stage, and a second ADC can help extend bit resolution while also helping to reduce area, power, and / or development cost of the conversion circuit compared to using only the first ADC. Alternatively, a conversion circuit including the first ADC and the second ADC can help improve accuracy of the conversion circuit compared to using only the first ADC.

[0030] In some embodiments, the methods and processes described herein may be associated with a computing system of one or more computing devices. In particular, such methods and processes may be implemented as computer applications or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0031] Figure 7 A non-limiting embodiment of a computing system 700 is schematically illustrated that can implement one or more of the methods and processes described above. Computing system 700 is shown in simplified form. Computing system 700 can take the form of one or more personal computers, server computers, tablet computers, home entertainment computers, network computing devices, gaming devices, mobile computing devices, mobile communication devices (e.g., smartphones), and / or other computing devices. Tablet computer 104 and device 200 are examples of computing system 700.

[0032] The computing system 700 includes a logic subsystem 702 and a storage subsystem 704. The computing system 700 may optionally include a display subsystem 706, an input subsystem 708, a communication subsystem 710, and / or Figure 7 Other components not shown.

[0033] The logic subsystem 702 includes one or more physical devices configured to execute instructions. For example, the logic machine can be configured to execute instructions that are part of one or more applications, services, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions can be implemented to perform a task, implement a data type, transform the state of one or more components, achieve a technical effect, or otherwise achieve a desired result.

[0034] The logic machine may include one or more processors configured to execute software instructions. Additionally or alternatively, the logic machine may include one or more hardware or firmware logic machines configured to execute hardware or firmware instructions. The processors of the logic machine may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel, and / or distributed processing. Individual components of the logic machine may optionally be distributed between two or more separate devices, which may be remotely located and / or configured for coordinated processing. Aspects of the logic machine may be virtualized and executed by a remotely accessible, networked computing device configured in a cloud computing configuration.

[0035] The storage subsystem 704 includes one or more physical devices configured to store instructions that are executable by a logic machine to implement the methods and processes described herein. When such methods and processes are implemented, the state of the storage subsystem 704 may be transformed, for example, to store different data.

[0036] The storage subsystem 704 may include removable and / or built-in devices. The storage subsystem 704 may include optical storage (e.g., CD, DVD, HD-DVD, Blu-ray Disc, etc.), semiconductor memory (e.g., RAM, EPROM, EEPROM, etc.), and / or magnetic storage (e.g., hard disk drive, floppy disk drive, tape drive, MRAM, etc.), etc. The storage subsystem 704 may include volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location addressable, file addressable, and / or content addressable devices.

[0037] It should be understood that storage subsystem 704 includes one or more physical devices. However, aspects of the instructions described herein may also be transmitted via communication media (eg, electromagnetic signals, optical signals, etc.) that are not retained by physical devices for a finite duration.

[0038] Aspects of the logic subsystem 702 and the storage subsystem 704 may be integrated together into one or more hardware logic components. For example, such hardware logic components may include field programmable gate arrays (FPGAs), program and application specific integrated circuits (PASIC / ASICs), program and application specific standard products (PSSP / ASSPs), systems on chips (SOCs), and complex programmable logic devices (CPLDs).

[0039] When included, the display subsystem 706 can be used to present a visual representation of the data stored by the storage subsystem 704. This visual representation can take the form of a graphical user interface (GUI). Since the methods and processes described herein change the data stored by the storage machine and thereby transform the state of the storage machine, the state of the display subsystem 706 can also be transformed to visually represent the changes in the underlying data. The display subsystem 706 may include one or more display devices utilizing almost any type of technology. Such a display device can be combined with the logic subsystem 702 and / or the storage subsystem 704 in a shared housing, or such a display device can be a peripheral display device.

[0040] When included, the input subsystem 708 may include or interface with one or more user input devices (such as a keyboard, mouse, touch screen, or game controller). In some examples, the device 100 in the form of a digital pen may be configured as a user input device. In some embodiments, the input subsystem may include or interact with selected natural user input (NUI) components. Such components may be integrated or peripheral, and the transduction and / or processing of input actions may be handled on-board or off-board. Example NUI components may include microphones for voice and / or sound recognition; infrared, color, stereo, and / or depth cameras for machine vision and / or gesture recognition; head trackers, eye trackers, accelerometers, and / or gyroscopes for motion detection and / or intent recognition; and electric field sensing components for assessing brain activity.

[0041] When included, the communication subsystem 710 can be configured to communicatively couple the computing system 700 with one or more other computing devices. The communication subsystem 710 can include wired and / or wireless communication devices compatible with one or more different communication protocols. As non-limiting examples, the communication subsystem can be configured to communicate via a wireless telephone network or a wired or wireless local area network or wide area network. In some embodiments, the communication subsystem can allow the computing system 700 to send messages to and / or receive messages from other devices via a network such as the Internet.

[0042] Another example provides a conversion circuit comprising: a first analog-to-digital converter (ADC) configured to convert an analog voltage to generate a first subset of digital output bits of the first ADC from a most significant bit (MSB) to bit k, and to generate a second subset of digital output bits of the first ADC from bit k-1 to a least significant bit (LSB), bit k of the first ADC being between the MSB and the LSB, the first ADC including a residue output configured to output a residual voltage of the analog voltage after converting bit k; an amplifier stage connected to the residue output of the first ADC and configured to generate an amplified residual voltage at an output of an amplifier stage; and a second ADC connected to the output of the amplifier stage, the second ADC configured to convert the amplified residual voltage at the output of the amplifier stage to generate additional digital output bits. In some such examples, alternatively or additionally, the second ADC is configured to generate the additional digital output bits in parallel with the first ADC generating the second subset of digital output bits. In some such examples, alternatively or additionally, the first ADC is a successive approximation ADC. In some such examples, alternatively or additionally, the first ADC and the second ADC are implemented using the same circuit template. In some such examples, alternatively or additionally, the first ADC and the second ADC are implemented using different circuit templates. In some such examples, alternatively or additionally, the amplifier stage comprises a linear amplifier.

[0043] Another example provides a method comprising: converting an analog voltage using a first analog-to-digital converter (ADC) to generate a first subset of digital output bits of the first ADC from a most significant bit (MSB) to bit k, and generating a second subset of digital output bits of the first ADC from bit k-1 to a least significant bit (LSB), bit k of the first ADC being between the MSB and the LSB; outputting a residual voltage of the analog voltage from the first ADC after conversion of bit k; amplifying the residual voltage using an amplifier stage to generate an amplified residual voltage at an output of the amplifier stage; and converting the amplified residual voltage at the output of the amplifier stage using a second ADC to generate additional digital output bits. In some such examples, alternatively or additionally, generating the second subset of digital output bits and generating the additional digital output bits are performed in parallel. In some such examples, alternatively or additionally, the method comprises determining N digital resolution bits for output based on at least a plurality of bits generated by the first ADC and one or more bits generated by the second ADC. In some such examples, alternatively or additionally, the method comprises determining N+j digital resolution bits for output based on at least a plurality of bits generated by the first ADC and one or more bits generated by the second ADC. In some such examples, alternatively or additionally, the first ADC and the second ADC are implemented using the same circuit template, and alternatively or additionally, the method includes preloading one or more high-resolution bits of the second ADC with logic zeros. In some such examples, alternatively or additionally, the analog voltage is related to a sensed pressure on the digital stylus.

[0044] Another example provides a device including a conversion circuit, the conversion circuit including: a first analog-to-digital converter (ADC) configured to convert an analog voltage to generate a first subset of digital output bits of the first ADC from a most significant bit (MSB) to bit k, and to generate a second subset of digital output bits of the first ADC from bit k-1 to a least significant bit (LSB), bit k of the first ADC being between the MSB and the LSB, the first ADC including a residue output configured to output a residue voltage of the analog voltage after converting bit k; an amplifier stage connected to the residue output of the first ADC and configured to generate an amplified residue voltage at an output of an amplifier stage; and a second ADC connected to the output of the amplifier stage, the second ADC configured to convert the amplified residue voltage at the output of the amplifier stage to generate additional digital output bits. In some such examples, alternatively or additionally, the second ADC is configured to generate the additional digital output bits in parallel with the first ADC generating the second subset of digital output bits. In some such examples, alternatively or additionally, the device includes a digital signal processing module configured to determine N digital resolution bits for output based on at least a plurality of bits generated by the first ADC and one or more bits generated by the second ADC. In some such examples, alternatively or additionally, the device includes a digital signal processing module configured to determine N+j digital resolution bits for output based on at least a plurality of bits generated by the first ADC and one or more bits generated by the second ADC. In some such examples, alternatively or additionally, the first ADC is a successive approximation ADC. In some such examples, alternatively or additionally, the first ADC and the second ADC are implemented using the same circuit template. In some such examples, alternatively or additionally, the first ADC and the second ADC are implemented using different circuit templates. In some such examples, alternatively or additionally, the amplifier stage includes a linear amplifier.

[0045] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these specific embodiments or examples should not be considered restrictive, as many variations are possible. The specific routines or methods described herein may represent one or more processing strategies in any number of processing strategies. Therefore, the various actions shown and / or described may be performed in the order shown and / or described, performed in other orders, performed in parallel, or omitted. Likewise, the order of the above-mentioned processing may be changed.

[0046] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.

Claims

1. A conversion circuit comprising: a first analog-to-digital converter (ADC) configured to convert an analog voltage to generate a first subset of digital output bits of the first ADC from a most significant bit (MSB) to a bit k, and to generate a second subset of digital output bits of the first ADC from a bit k-1 to a least significant bit (LSB), the bit k being between the MSB and the LSB of the first ADC, the first ADC including a residue output configured to output a residue voltage of the analog voltage after converting the bit k; an amplifier stage connected to the residue output of the first ADC and configured to generate an amplified residue voltage at an output of the amplifier stage; as well as A second ADC is connected to the output of the amplifier stage, the second ADC being configured to convert the amplified residue voltage at the output of the amplifier stage to generate an additional digital output bit. 2 . The circuit of claim 1 , wherein the second ADC is configured to generate the additional digital output bits in parallel with the first ADC generating the second subset of the digital output bits.

3. The circuit according to any one of claims 1 to 2, wherein the first ADC is a successive approximation ADC. 4 . The circuit according to claim 1 , wherein the first ADC and the second ADC are implemented using the same circuit template. 5 . The circuit according to claim 1 , wherein the first ADC and the second ADC are implemented using different circuit templates.

6. A circuit according to any one of claims 1 to 5, wherein the amplifier stage comprises a linear amplifier.

7. A method comprising: converting an analog voltage using a first analog-to-digital converter (ADC) to generate a first subset of digital output bits of the first ADC from a most significant bit (MSB) to bit k, and generating a second subset of digital output bits of the first ADC from bit k-1 to a least significant bit (LSB), the bit k being between the MSB and the LSB of the first ADC; outputting a residual voltage of the analog voltage from the first ADC after conversion of the bit k; amplifying the residue voltage using an amplifier stage to generate an amplified residue voltage at an output of the amplifier stage; as well as The amplified residue voltage at the output of the amplifier stage is converted using a second ADC to generate additional digital output bits.

8. The method of claim 7, wherein generating the second subset of digital output bits and generating the additional digital output bits are performed in parallel.

9. The method of any one of claims 7 to 8, further comprising determining N digital resolution bits for output based at least on a plurality of bits generated by the first ADC and one or more bits generated by the second ADC.

10. The method of any one of claims 7 to 8, further comprising determining N+j digital resolution bits for output based at least on a plurality of bits generated by the first ADC and one or more bits generated by the second ADC.

11. The method of any one of claims 7 to 10, wherein the first ADC and the second ADC are implemented using the same circuit template, and the method further comprises preloading one or more high resolution bits of the second ADC with logic zeros.

12. The method of any one of claims 7 to 11, wherein the analog voltage is related to sensed pressure on the digital pen.

13. A device comprising: Conversion circuit, comprising: a first analog-to-digital converter (ADC) configured to convert an analog voltage to generate a first subset of digital output bits of the first ADC from a most significant bit (MSB) to a bit k, and to generate a second subset of digital output bits of the first ADC from a bit k-1 to a least significant bit (LSB), the bit k being between the MSB and the LSB of the first ADC, the first ADC including a residue output configured to output a residue voltage of the analog voltage after converting the bit k; an amplifier stage connected to the residue output of the first ADC and configured to generate an amplified residue voltage at an output of the amplifier stage; and A second ADC is connected to the output of the amplifier stage, the second ADC being configured to convert the amplified residue voltage at the output of the amplifier stage to generate an additional digital output bit. 14 . The apparatus of claim 13 , wherein the second ADC is configured to generate the additional digital output bits in parallel with the first ADC generating the second subset of the digital output bits.

15. The apparatus of any one of claims 13 to 14, further comprising a digital signal processing module configured to determine N digital resolution bits for output based at least on a plurality of bits generated by the first ADC and one or more bits generated by the second ADC.

16. The apparatus of any one of claims 13 to 14, further comprising a digital signal processing module configured to determine N+j digital resolution bits for output based at least on a plurality of bits generated by the first ADC and one or more bits generated by the second ADC.

17. The apparatus of any one of claims 13 to 16, wherein the first ADC is a successive approximation ADC.

18. The apparatus according to any one of claims 13 to 17, wherein the first ADC and the second ADC are implemented using the same circuit template.

19. The circuit of any one of claims 13 to 17, wherein the first ADC and the second ADC are implemented using different circuit templates.

20. A circuit as claimed in any one of claims 13 to 19, wherein the amplifier stage comprises a linear amplifier.

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