Negative temperature coefficient thermosensitive film array embedded substrate for chip temperature monitoring

Abstract

The invention provides a negative temperature coefficient thermosensitive film array embedded substrate for chip temperature monitoring, which is composed of a substrate, a negative temperature coefficient thermosensitive film array and a packaging layer, and is characterized in that an embedded structure of the negative temperature coefficient film array at the substrate is optimized; and the substrate which only has a single supporting function originally becomes a functional layer for monitoring the in-situ temperature of the chip. Array structure design and arrangement are performed according to a test scene, on-chip in-situ temperature monitoring is realized, delay and errors of temperature measurement are reduced, performance and stability of a chip are ensured, key problems of low integration level of a sensor and the chip, incomplete temperature field monitoring and the like in the prior art are solved, and an innovative solution is provided for chip thermal management. The scheme can be applied to the field of temperature monitoring of various chips and wafers.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip temperature monitoring technology, specifically to a substrate embedded with a negative temperature coefficient (NTC) thermistor thin film array for chip temperature monitoring. By embedding a negative temperature coefficient (NTC) thermistor thin film array within the substrate, real-time, multi-point, high-precision monitoring of the chip's operating temperature is achieved. This technology is suitable for heat dissipation and temperature control scenarios in integrated circuits, micro-nano devices, and high-power chips. Background Art

[0002] In the field of chip temperature monitoring, traditional methods rely on external temperature sensors or indirect control based on heat dissipation systems. These methods suffer from problems such as delayed response, low spatial resolution, and difficulty in compatibility with the trend of chip miniaturization. For example, existing patents (such as CN 109904129A) regulate chip heat generation through stepped heat sink design and substrate bias technology, but their temperature control relies on heat dissipation balance and lacks real-time direct monitoring of the chip's internal temperature. While methods that add temperature measurement devices to the outside of the packaging structure (such as patent CN 119005106 A) achieve in-situ temperature measurement to a certain extent, the delay and error in temperature measurement are still large. Existing embedded temperature sensors (such as patent CN 111816652 B) are mostly based on RTDs and silicon-based materials, but their temperature range, sensitivity, and stability are limited by material properties.

[0003] Thin-film negative temperature coefficient (NTC) thermistors have been widely studied due to their high sensitivity (resistance temperature coefficient of -3% to -6%) and miniaturization (thickness less than 0.3 mm). Our research team previously successfully fabricated manganese-cobalt-nickel-based NTC thin films using magnetron sputtering, but their applications were limited to standalone sensors rather than direct integration with chip substrates. Challenges remain in complex array structures and compatibility with semiconductor processes.

[0004] Therefore, there is an urgent need for a chip-embedded temperature monitoring solution that combines high-precision temperature measurement, rapid response, process compatibility, and miniaturization. This invention addresses key issues in traditional technologies, such as low sensor-to-chip integration and incomplete temperature field monitoring, by optimizing the embedded substrate structure and fabrication process of negative temperature coefficient (NTC) thin film arrays. This provides an innovative solution for chip thermal management. Summary of the Invention

[0005] The purpose of the present invention is to provide a negative temperature coefficient thermistor thin film array embedded substrate for chip temperature monitoring in order to overcome the shortcomings of the existing technology. The substrate is composed of a base plate, a negative temperature coefficient thermistor thin film array and a packaging layer. By optimizing the embedded structure of the negative temperature coefficient thin film array at the substrate, the substrate, which originally only had a single supporting function, becomes a functional layer for in-situ temperature monitoring of the chip. The array structure is designed and arranged according to the test scenario to achieve in-situ temperature monitoring on the chip, reducing the delay and error of temperature measurement, ensuring the performance and stability of the chip, and solving the key problems of low sensor and chip integration and incomplete temperature field monitoring in traditional technologies, providing an innovative solution for chip thermal management. This solution can be used in a variety of chip and wafer temperature monitoring fields.

[0006] The present invention discloses a negative temperature coefficient thermistor thin film array embedded substrate for chip temperature monitoring. The substrate comprises a substrate (1), a negative temperature coefficient thermistor thin film array (2) and an encapsulation layer (3). The negative temperature coefficient thermistor thin film array (2) comprises two parts: a thermosensitive thin film layer (4) and an interdigital electrode layer (5). The negative temperature coefficient thermistor thin film array (2) consisting of the thermosensitive thin film layer (4) and the interdigital electrode layer (5) is sequentially grown on a substrate (1) such as a silicon wafer, aluminum oxide or silicon nitride. The encapsulation layer (3) is provided on the negative temperature coefficient thermistor thin film array (2). The specific operation is performed according to the following steps:

[0007] a. Magnetron sputtering, electron beam evaporation or pulsed laser deposition is used to grow a MnCoOO, MnCoNiO or MnCoFeO thin film as a negative temperature coefficient thermistor film layer (4) on a 4-inch surface-oxidized silicon substrate (1) with a thickness of 0.05-1 μm, followed by high-temperature annealing at a temperature of 500-850° C.;

[0008] b. Using a MEMS process to form a pattern mask of the interdigital electrode layer (5) on the negative temperature coefficient thermosensitive film layer (4) in the order of coating, photolithography, and development, and then growing aluminum, platinum, or gold as the interdigital electrode layer (5) by magnetron sputtering, electron beam evaporation, or pulsed laser deposition to a thickness of 0.05-0.5 μm, and then stripping the photoresist to obtain the interdigital electrode layer (5);

[0009] c. Using MEMS technology on the interdigitated electrode layer (5) in the order of coating, photolithography, and development to complete the pattern mask of the packaging layer (3), and then selecting magnetron sputtering, electron beam evaporation, or pulsed laser deposition to grow silicon oxide, aluminum oxide, or silicon nitride insulating packaging material as the packaging layer (3), with a thickness of 0.2-1 μm, and then performing photoresist stripping to complete the silicon oxide packaging layer (3), and setting the packaging layer (3) on the negative temperature coefficient thermistor thin film array (2), covering the entire chip surface except the electrode endpoints.

[0010] The interdigital electrode layer (5) is an array structure composed of a plurality of evenly arranged interdigital electrodes.

[0011] The beneficial technical effects achieved by the present invention include:

[0012] The present invention describes a negative temperature coefficient (NTC) thermistor thin film array embedded substrate for chip temperature monitoring. By optimizing the embedded structure of the NTC thin film array in the substrate and designing and deploying the array structure based on test scenarios, this approach enables on-chip, in-situ temperature monitoring. This reduces temperature measurement delays and errors, ensuring chip performance and stability. This approach addresses key issues in traditional technologies, such as low sensor-to-chip integration and incomplete temperature field monitoring, providing an innovative solution for chip thermal management. This solution can be used in a variety of chip and wafer temperature monitoring applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic structural diagram of the present invention having a surface temperature measurement array;

[0014] Figure 2 Schematic diagram of the chip structure after packaging of the present invention;

[0015] Figure 3 1 is a graph showing the test results of the temperature measurement array prepared according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The present invention will be further understood from the following description in conjunction with the accompanying drawings.

[0017] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with its embodiments; it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. For those skilled in the art, after reviewing the following detailed description, other systems, methods and / or features of the present embodiment will become apparent. It should be noted that, unless there is a conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0018] Example 1

[0019] The present invention discloses a negative temperature coefficient thermistor thin film array embedded substrate for chip temperature monitoring. The substrate comprises a substrate 1, a negative temperature coefficient thermistor thin film array 2, and an encapsulation layer 3. The negative temperature coefficient thermistor thin film array 2 comprises a thermosensitive thin film layer 4 and an interdigital electrode layer 5. The negative temperature coefficient thermistor thin film array 2, comprising the thermosensitive thin film layer 4 and the interdigital electrode layer 5, is sequentially grown on a substrate 1, which may be a silicon wafer, aluminum oxide, or silicon nitride. The encapsulation layer 3 is disposed on the negative temperature coefficient thermistor thin film array 2. The specific operation is performed according to the following steps:

[0020] a. Magnetron sputtering is used to grow a MnCoO thin film as a negative temperature coefficient thermistor thin film layer 4 on a 4-inch surface-oxidized silicon substrate 1, with a thickness of 0.05 μm, and then high-temperature annealing is performed at a temperature of 500°C;

[0021] b. Using a MEMS process, a pattern mask for the interdigital electrode layer 5 is formed on the negative temperature coefficient thermistor film layer 4 in the order of coating, photolithography, and development. Aluminum is then grown by magnetron sputtering to a thickness of 0.05 μm as the interdigital electrode layer 5. The photoresist is then stripped to obtain an interdigital electrode layer 5 having a total of nine interdigital electrode pairs forming a 3×3 array structure.

[0022] c. Use the MEMS process on the interdigital electrode layer 5 to complete the pattern mask of the packaging layer 3 in the order of coating, photolithography, and development. Then, select magnetron sputtering to grow silicon nitride insulating packaging material as the packaging layer 3 with a thickness of 0.2μm. Then, perform photoresist stripping to complete the silicon oxide packaging layer 3. The packaging layer 3 is set on the negative temperature coefficient thermistor film array 2, covering the entire chip surface except the electrode endpoints.

[0023] Example 2

[0024] The present invention discloses a negative temperature coefficient thermistor thin film array embedded substrate for chip temperature monitoring. The substrate comprises a substrate 1, a negative temperature coefficient thermistor thin film array 2, and an encapsulation layer 3. The negative temperature coefficient thermistor thin film array 2 comprises a thermosensitive thin film layer 4 and an interdigital electrode layer 5. The negative temperature coefficient thermistor thin film array 2, comprising the thermosensitive thin film layer 4 and the interdigital electrode layer 5, is sequentially grown on a substrate 1, which may be a silicon wafer, aluminum oxide, or silicon nitride. The encapsulation layer 3 is disposed on the negative temperature coefficient thermistor thin film array 2. The specific operation is performed according to the following steps:

[0025] a. Magnetron sputtering is used to grow a 0.5 μm thick MnCoNiO thin film as the negative temperature coefficient thermistor layer 4 on a 2-inch surface nitrided silicon substrate 1 using pulsed laser deposition, followed by high-temperature annealing at 700°C.

[0026] b. Using a MEMS process, a pattern mask for the interdigital electrode layer 5 is formed on the negative temperature coefficient thermistor film layer 4 in the order of coating, photolithography, and development. Then, gold is grown by pulsed laser deposition to a thickness of 0.15 μm as the interdigital electrode layer 5. The photoresist is then stripped to obtain an interdigital electrode layer 5 having a total of 9 interdigital electrode pairs forming a 3×3 array structure.

[0027] c. Use the MEMS process on the interdigital electrode layer 5 to complete the pattern mask of the packaging layer 3 in the order of coating, photolithography, and development. Then, select magnetron sputtering to grow silicon oxide insulating packaging material as the packaging layer 3 with a thickness of 0.15 μm. Then, perform photoresist stripping to complete the silicon oxide packaging layer 3. The packaging layer 3 is set on the negative temperature coefficient thermistor thin film array 2, covering the entire chip surface except the electrode endpoints.

[0028] Example 3

[0029] The present invention discloses a negative temperature coefficient thermistor thin film array embedded substrate for chip temperature monitoring. The substrate comprises a substrate 1, a negative temperature coefficient thermistor thin film array 2, and an encapsulation layer 3. The negative temperature coefficient thermistor thin film array 2 comprises a thermosensitive thin film layer 4 and an interdigital electrode layer 5. The negative temperature coefficient thermistor thin film array 2, comprising the thermosensitive thin film layer 4 and the interdigital electrode layer 5, is sequentially grown on a substrate 1, which may be a silicon wafer, aluminum oxide, or silicon nitride. The encapsulation layer 3 is disposed on the negative temperature coefficient thermistor thin film array 2. The specific operation is performed according to the following steps:

[0030] a. A MnCoFeO thin film was grown on an alumina substrate of 10×10 mm in size by electron beam evaporation to form the negative temperature coefficient thermistor layer 4 with a thickness of 1 μm, and then subjected to high temperature annealing at 850°C.

[0031] b. Using a MEMS process, a pattern mask for the interdigital electrode layer 5 is formed on the negative temperature coefficient thermistor film layer 4 in the order of coating, photolithography, and development. Platinum is then grown by electron beam evaporation to a thickness of 0.5 μm as the interdigital electrode layer 5. The photoresist is then stripped to obtain an interdigital electrode layer 5 having a total of nine interdigital electrode pairs forming a 3×3 array structure.

[0032] c. Use the MEMS process on the interdigital electrode layer 5 to complete the pattern mask of the packaging layer 3 in the order of coating, photolithography, and development. Then, select magnetron sputtering to grow aluminum oxide insulating packaging material as the packaging layer 3 with a thickness of 1 μm. Then, perform photoresist stripping to complete the silicon oxide packaging layer 3. The packaging layer 3 is set on the negative temperature coefficient thermistor film array 2, covering the entire chip surface except the electrode endpoints.

[0033] The above description of the present invention and its embodiments is non-limiting. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. In short, if a person skilled in the art is inspired by it, without departing from the principles of the present invention, he or she may make several improvements, modifications, or variations, and may also combine the above technical features in appropriate ways. Such improvements, modifications, variations, or combinations, or the direct application of the inventive concept and technical solution to other occasions without modification, shall all fall within the scope of protection of the present invention.

Claims

1. A negative temperature coefficient thermistor thin film array embedded substrate for chip temperature monitoring, characterized in that: The substrate is composed of a substrate (1), a negative temperature coefficient thermistor thin film array (2) and a packaging layer (3), wherein the negative temperature coefficient thermistor thin film array (2) is composed of two parts, namely a thermosensitive thin film layer (4) and an interdigital electrode layer (5). The negative temperature coefficient thermistor thin film array (2) consisting of the thermosensitive thin film layer (4) and the interdigital electrode layer (5) is sequentially grown on a substrate (1) which is a silicon wafer, aluminum oxide or silicon nitride, and the packaging layer (3) is provided on the negative temperature coefficient thermistor thin film array (2). The specific operation is carried out according to the following steps: a. Magnetron sputtering, electron beam evaporation or pulsed laser deposition is used to grow a MnCoO, MnCoNiO or MnCoFeO thin film as a negative temperature coefficient thermistor film layer (4) on a 4-inch surface-oxidized silicon substrate (1) with a thickness of 0.05-1µm, followed by high-temperature annealing at a temperature of 500-850°C; b. Using MEMS technology to form a pattern mask of the interdigital electrode layer (5) on the negative temperature coefficient thermosensitive film layer (4) in the order of coating, photolithography, and development, and then selecting magnetron sputtering, electron beam evaporation, or pulsed laser deposition to grow aluminum, platinum, or gold as the interdigital electrode layer (5) to a thickness of 0.05-0.5µm, and then performing photoresist stripping to obtain the interdigital electrode layer (5); c. Use MEMS technology to complete the pattern mask of the packaging layer (3) on the interdigitated electrode layer (5) in the order of coating, photolithography, and development, and then select magnetron sputtering, electron beam evaporation or pulsed laser deposition to grow silicon oxide, aluminum oxide or silicon nitride insulating packaging material as the packaging layer (3), with a thickness of 0.2-1µm, and then perform photoresist stripping to complete the silicon oxide packaging layer (3). The packaging layer (3) is set on the negative temperature coefficient thermistor film array (2), covering the entire chip surface except the electrode endpoints.

2. The negative temperature coefficient thermistor thin film array embedded substrate for chip temperature monitoring according to claim 1, characterized in that: The interdigital electrode layer (5) is an array structure composed of a plurality of evenly arranged interdigital electrodes.

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