Chip assembly detection method

Abstract

The invention relates to a chip assembly detection method. The method comprises the following steps: providing a chip assembly; wherein the chip assembly comprises a growth substrate and a plurality of light-emitting chips formed on the growth substrate; filling a flat layer among the light-emitting chips, and patterning the flat layer to expose the electrodes of the light-emitting chips; forming a test common electrode on the electrode of each light-emitting chip; the test common electrode comprises a plurality of first polarity test electrodes and a plurality of second polarity test electrodes; the first polarity test electrode is configured to be connected with a first electrode of all the light-emitting chips in any to-be-tested area, and the second polarity test electrode is configured to be connected with a second electrode of all the light-emitting chips in the same to-be-tested area; performing a photoelectric test on each light-emitting chip through a test common electrode; and after the test is completed, removing the test common electrode and the flat layer. By applying the scheme of the invention, the photoelectric performance test of all light-emitting chips can be realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor detection technology, and in particular to a chip component detection method. Background Art

[0002] Micro-LEDs, comprised of arrays of micron-scale semiconductor light-emitting units, represent a hybrid technology that integrates new display and light-emitting diode (LED) technologies. They offer the advantages of self-luminescence, high efficiency, low power consumption, high integration, high stability, and all-weather operation, making them considered one of the most promising next-generation display and light-emitting devices. However, due to their small size and the large number of micro-LEDs that can be placed on a 4-inch wafer, testing the optoelectronic performance of each micro-LED is an urgent challenge.

[0003] A traditional inspection method is to test each Micro-LED individually with a probe, which is inefficient. Another inspection method is to randomly inspect an area and then estimate the photoelectric performance of other Micro-LEDs in that area. This method is prone to misjudgment and inaccuracy, resulting in misclassification in subsequent binning and even mura problems when the display module is manufactured. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the purpose of this application is to provide a chip component detection method to solve the above-mentioned technical problems.

[0005] In a first aspect, the present application provides a chip component detection method, comprising:

[0006] A chip assembly is provided; wherein the chip assembly includes a growth substrate and a plurality of light-emitting chips formed on the growth substrate;

[0007] Filling a flat layer between the light-emitting chips, and patterning the flat layer to expose the electrodes of the light-emitting chips;

[0008] A test common electrode is formed on the electrodes of each of the light-emitting chips; wherein the test common electrode includes a plurality of first polarity test electrodes and a plurality of second polarity test electrodes; the first polarity test electrodes are configured to connect to the first electrodes of all light-emitting chips in any area to be tested, and the second polarity test electrodes are configured to connect to the second electrodes of all light-emitting chips in the same area to be tested;

[0009] performing a photoelectric test on each of the light-emitting chips through the test common electrode; and

[0010] After the test is completed, the test common electrode and the planar layer are removed.

[0011] The above-mentioned chip component inspection method can test multiple Micro-LED core particles at a time, which can increase the test efficiency by 100 to 1000 times. In addition, due to the improved test efficiency, the optoelectronic performance of each Micro-LED chip on each COW can be collected, so that each Micro-LED can be binned later, solving the Micro-LED mura problem and high yield requirements.

[0012] In one embodiment, the plurality of light-emitting chips are divided into a plurality of test areas, and each test area includes 1,000 to 10,000 light-emitting chips.

[0013] In one embodiment, the area to be tested includes an area consisting of at least one row and / or one column of light-emitting chips.

[0014] In one embodiment, the step of performing a photoelectric test on each of the light-emitting chips through the test common electrode includes:

[0015] Performing puncture testing on the first polarity test electrode and the second polarity test electrode of each area to be tested;

[0016] The optical performance data and electrical performance data of each chip in the area to be tested are collected respectively.

[0017] In one embodiment, the test common electrode and the light-emitting chip have different materials and compositions.

[0018] In one embodiment, the test common electrode comprises a stack of titanium, aluminum and titanium, and the electrode of the light-emitting chip comprises a stack of chromium, platinum and gold.

[0019] In one embodiment, the step of removing the test common electrode and the planar layer includes:

[0020] placing the chip assembly in a container containing hydrochloric acid to remove the test common electrode;

[0021] The flat layer is removed using a debonding solution.

[0022] In one embodiment, the method for preparing the chip assembly includes:

[0023] Providing an epitaxial wafer; wherein the epitaxial wafer includes the growth substrate and an epitaxial layer formed on the growth substrate;

[0024] performing patterning on the epitaxial layer to form a plurality of independent island-shaped epitaxial structures;

[0025] forming an insulating protective layer on the island epitaxial structure;

[0026] performing patterning on the insulating protection layer so as to expose a portion of the surface of the island-shaped epitaxial structure;

[0027] An electrode layer is evaporated on the exposed surface of the island epitaxial structure.

[0028] In one embodiment, the epitaxial layer includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; and the method for manufacturing the island epitaxial structure includes:

[0029] depositing a current spreading layer on the second conductive type semiconductor layer;

[0030] Step etching and channel etching are performed on the epitaxial layer including the current spreading layer to form the island-shaped epitaxial structure.

[0031] In one embodiment, the thickness of the current spreading layer ranges from 500A to 10000A.

[0032] In one embodiment, the growth substrate is a sapphire substrate, and the epitaxial layer is a gallium nitride-based semiconductor epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of a chip component detection method in one embodiment of the present application;

[0034] Figure 2 For Figure 1 Schematic diagram of partial structural changes of chip components corresponding to the steps of the method;

[0035] Figure 3 This is a schematic structural diagram of a chip assembly in one embodiment of the present application;

[0036] Figure 4(a)-Figure 4(c) for Figure 3 Enlarged views of different embodiments of area A.

[0037] Description of reference numerals:

[0038] 10-light-emitting chip; ST-growth substrate; 210-flat layer; WF-chip component; A-area to be tested; H-through hole; TS1-first polarity test electrode; TS2-second polarity test electrode; PAD1-first electrode; PAD2-second electrode. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] It should be understood that spatial relational terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0042] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0044] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0045] As described in the background of this application, Micro-LEDs, comprised of arrays of micron-scale semiconductor light-emitting units, represent a comprehensive technology that integrates new display and light-emitting diode (LED) technologies. They offer the advantages of self-luminescence, high efficiency, low power consumption, high integration, high stability, and all-weather operation, making them considered one of the most promising next-generation display and light-emitting devices. However, due to the small size of Micro-LEDs and the large number of Micro-LEDs that can be placed on a 4-inch wafer, testing the optoelectronic performance of each Micro-LED is an urgent challenge.

[0046] A traditional inspection method is to test each Micro-LED individually with a probe, which is inefficient. Another inspection method is to randomly inspect an area and then estimate the photoelectric performance of other Micro-LEDs in that area. This method is prone to misjudgment and inaccuracy, resulting in misclassification in subsequent binning and even mura problems when the display module is manufactured.

[0047] Based on this, the present application hopes to provide a solution that can solve the above technical problems, the details of which will be explained in the subsequent embodiments.

[0048] Please refer to Figure 1 , and auxiliary reference Figure 2 , the present application provides a chip component detection method, which may include steps S100-S500.

[0049] Step S100, providing a chip assembly; wherein the chip assembly includes a growth substrate and a plurality of light-emitting chips formed on the growth substrate;

[0050] Step S200 , filling a flat layer between the light-emitting chips, and patterning the flat layer to expose the electrodes of the light-emitting chips;

[0051] Step S300: forming a test common electrode on the electrodes of each of the light-emitting chips; wherein the test common electrode includes a plurality of first polarity test electrodes and a plurality of second polarity test electrodes; the first polarity test electrodes are configured to connect to the first electrodes of all light-emitting chips in any area to be tested, and the second polarity test electrodes are configured to connect to the second electrodes of all light-emitting chips in the same area to be tested;

[0052] Step S400 , performing a photoelectric test on each of the light-emitting chips through the test common electrode; and

[0053] Step S500: After the test is completed, the test common electrode and the planar layer are removed.

[0054] The above-mentioned chip component inspection method can test multiple Micro-LED core particles at a time, which can increase the test efficiency by 100 to 1000 times. In addition, due to the improved test efficiency, the optoelectronic performance of each Micro-LED chip on each COW can be collected, so that each Micro-LED can be binned later, solving the Micro-LED mura problem and high yield requirements.

[0055] Specifically, the growth substrate ST of the present application can be a transparent substrate, and the material of the transparent substrate includes inorganic materials or III-V semiconductor materials. Inorganic materials include silicon carbide (SiC), germanium (Ge), sapphire (Sapphire), lithium aluminate (LiAlO2), zinc oxide (ZnO), glass or quartz. The III-V semiconductor materials include indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), and aluminum nitride (AlN). The growth substrate ST should have sufficient strength to mechanically support the epitaxial layer and be able to transmit light emitted from the epitaxial layer. The thickness of the growth substrate ST can be selected to be more than 50μm. In addition, in order to facilitate the subsequent possible bonding process, the growth substrate ST needs to be mechanically processed (thinned), and the thickness of the selected growth substrate ST is generally not more than 300μm.

[0056] The light-emitting chip 10 can be a blue light-emitting diode, a green light-emitting diode, or a red light-emitting diode; the size of these light-emitting diodes can be less than 50 microns (micro light-emitting diodes) or 50-200 microns (mini light-emitting diodes), and this application does not impose further restrictions on this.

[0057] Among them, in step S200, the height of the flat layer 210 filled between each light-emitting chip 10 in the direction perpendicular to the growth substrate ST is greater than the height of the light-emitting chip 10 in the same direction. The steps of patterning the flat layer 210 mainly include photoresist coating, exposure, development and etching. These steps can be understood with reference to the existing process, and this application will not be further elaborated on this. It should be understood that the flat layer 210 after patterning needs to expose the electrodes of each light-emitting chip 10 through the through hole H to facilitate the formation of the test common electrode (not shown) in the subsequent step. In this specific embodiment, the electrode of the light-emitting chip 10 may include a stack of chromium platinum gold, so as to avoid affecting the electrode of the light-emitting chip 10 when the test common electrode is subsequently removed.

[0058] In step S300, a test common electrode can be formed on the electrodes of each light-emitting chip 10 by evaporation. Specifically, a photoresist can be formed on the flat layer 210, and the photoresist is patterned to expose the electrodes of each light-emitting chip 10. Then, the photoresist is placed in an evaporation machine to evaporate the test common electrode. The test common electrode can be a titanium-aluminum-titanium stack. After reaching a preset thickness, it is taken out and the pattern of the test common electrode can be obtained by stripping the gold and glue. In this specific embodiment, you can refer to Figure 4(a)-Figure 4(c) The test common electrode may include a plurality of first polarity test electrodes TS1 and a plurality of second polarity test electrodes TS2. The first polarity test electrode TS1 may be an electrode with a P polarity, and the second polarity test electrode TS2 may be an electrode with an N polarity. Similarly, the first polarity test electrode TS1 may be an electrode with an N polarity, and the second polarity test electrode TS2 may be an electrode with a P polarity. This is not further limited in this application. It can be determined that adjacent first polarity test electrodes TS1 and second polarity test electrodes TS2 constitute a pair of test common electrodes.

[0059] Further, see Figure 4(a)-Figure 4(c)In order to facilitate the detection of all the light-emitting chips 10 on the growth substrate ST, the present application divides a plurality of light-emitting chips 10 into a plurality of test areas, each of which can be provided with 1,000 to 10,000 light-emitting chips. In this way, a chip assembly having 1,000,000 to 10,000,000 light-emitting chips can be divided into 1,000 test areas, each of which includes an area consisting of at least one row and / or column of light-emitting chips. In other words, a test area in the present application can be composed only of the area where a certain row of light-emitting chips 10 is located, or of a partial area of ​​the row of light-emitting chips 10, or of a certain column of light-emitting chips 10 (as shown in FIG. 4( a )), or of a partial area of ​​the column of light-emitting chips 10. In other embodiments, a test area may also be composed of the area where two rows of light-emitting chips 10 are located (as shown in Figures 4(b) and 4(c)), or may be composed of partial areas of two rows of light-emitting chips 10, or may be composed of the area where two columns of light-emitting chips 10 are located (see Figures 4(b) and 4(c)). This application will not further elaborate on this. By dividing the test area, the detection efficiency can be effectively improved and the wiring cost can be saved (for example, in the case of multiple rows or columns).

[0060] In one embodiment, the step of performing a photoelectric test on each of the light-emitting chips through the test common electrode may include:

[0061] Performing puncture testing on the first polarity test electrode and the second polarity test electrode of each area to be tested;

[0062] The optical performance data and electrical performance data of each chip in the area to be tested are collected respectively.

[0063] In this embodiment, by testing the first polarity test electrode TS1 and the second polarity test electrode TS2 of each area to be tested respectively, the photoelectric performance data of each area to be tested can be collected.

[0064] In one embodiment, the step of removing the test common electrode and the planar layer includes:

[0065] placing the chip assembly in a container containing hydrochloric acid to remove the test common electrode;

[0066] The flat layer is removed using a debonding solution.

[0067] In this embodiment, the structure used for testing can be entirely removed by using hydrochloric acid and a debonding solution.

[0068] In one embodiment, the method for preparing the chip assembly includes:

[0069] Providing an epitaxial wafer; wherein the epitaxial wafer includes the growth substrate and an epitaxial layer formed on the growth substrate;

[0070] performing patterning on the epitaxial layer to form a plurality of independent island-shaped epitaxial structures;

[0071] forming an insulating protective layer on the island epitaxial structure;

[0072] performing patterning on the insulating protection layer so as to expose a portion of the surface of the island-shaped epitaxial structure;

[0073] An electrode layer is evaporated on the exposed surface of the island epitaxial structure.

[0074] Furthermore, the epitaxial layer includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; and the method for manufacturing the island-shaped epitaxial structure includes:

[0075] depositing a current spreading layer on the second conductive type semiconductor layer;

[0076] Step etching and channel etching are performed on the epitaxial layer including the current spreading layer to form the island-shaped epitaxial structure.

[0077] To facilitate understanding of the present application, this specific embodiment uses actual processes to illustrate the manufacturing method of the chip component of the present application. Taking a blue light epitaxial wafer as an example, the epitaxial wafer may include three layers: N-GaN (first conductivity type semiconductor layer), MQW (active layer), and P-GaN (second conductivity type semiconductor layer). The manufacturing of a blue light chip component mainly includes the following steps:

[0078] Step 1: First, a MESA pattern is photolithographically formed on the epitaxial wafer, and then MESA etching is performed using a dry etching machine, wherein the etching gases are BCl3 and Cl2, and the etching depth is between 1um and 2um. After desmearing, the MESA pattern can be obtained;

[0079] Step 2: sputtering a current spreading layer on the epitaxial layer, the current spreading layer having a thickness of 500A-10000A, photolithographically patterning the current spreading layer, wet etching the current spreading layer, and removing the resist to obtain a patterned current spreading layer; the current spreading layer includes but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), zinc oxide (ZnO), indium zinc oxide (IZO), diamond-like carbon film (DLC) or gallium zinc oxide (GZO);

[0080] Step 3: Photolithography of an ISO pattern on the current spreading layer, etching through the N-GaN to the growth substrate layer using a dry etching machine, wherein the etching gas is BCl3 and Cl2, the etching depth is 4um-8um, and the ISO pattern is obtained after desmearing;

[0081] Step 4: Use negative resist photolithography to form a metal pattern on the current spreading layer, and use an evaporation machine to evaporate a metal electrode on the N-GaN with a thickness of 1um-4um. After evaporation, the metal pattern can be obtained by stripping the gold and resist.

[0082] Step 5: Deposit an insulating protective layer on the source in step 4 by PECVD method. The gases of PECVD equipment can be SiH4 and N20. The thickness of the insulating protective layer is 2000A-10000A. The insulating protective layer is dry-etched to expose the current spreading layer and the metal electrode. The etching gas is CF4, O2 and Ar. In this specific embodiment, the insulating protective layer includes but is not limited to polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), magnesium oxide (MgO), Su8, epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon polymer (Fluorocarbon Polymer), glass (Glass), aluminum oxide (Al2O3), silicon oxide (SiO x ), titanium oxide (TiO x ), tantalum oxide (Ta2O5), silicon nitride (SiN x ) or spin-on glass (SOG).

[0083] Step 6: Use negative resist photolithography to form a PAD pattern on the insulating protective layer, and use an evaporation machine to evaporate the PAD electrode. The electrode thickness can be 1um-4um, and the electrode material is a stack of Cr / Pt / Au. After evaporation, the gold and glue are stripped to obtain the aforementioned blue light chip component.

[0084] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A chip component detection method, characterized in that: include: A chip assembly is provided; wherein the chip assembly includes a growth substrate and a plurality of light-emitting chips formed on the growth substrate; Filling a flat layer between the light-emitting chips, and patterning the flat layer to expose the electrodes of the light-emitting chips; A test common electrode is formed on the electrodes of each of the light-emitting chips; wherein the test common electrode includes a plurality of first polarity test electrodes and a plurality of second polarity test electrodes; the first polarity test electrodes are configured to connect to the first electrodes of all light-emitting chips in any area to be tested, and the second polarity test electrodes are configured to connect to the second electrodes of all light-emitting chips in the same area to be tested; performing a photoelectric test on each of the light-emitting chips through the test common electrode; and After the test is completed, the test common electrode and the planar layer are removed.

2. The chip component detection method according to claim 1, wherein: The plurality of light-emitting chips are divided into a plurality of test areas, and each test area includes 1,000 to 10,000 light-emitting chips.

3. The chip component detection method according to claim 2, wherein: The area to be tested includes an area consisting of at least one row and / or one column of light-emitting chips.

4. The chip component detection method according to claim 3, wherein: The step of performing a photoelectric test on each of the light-emitting chips through the test common electrode includes: Performing puncture testing on the first polarity test electrode and the second polarity test electrode of each area to be tested; The optical performance data and electrical performance data of each chip in the area to be tested are collected respectively.

5. The chip component detection method according to claim 1, wherein: The test common electrode and the light-emitting chip have different electrode materials and compositions.

6. The chip component detection method according to claim 5, characterized in that: The test common electrode includes a stack of titanium, aluminum and titanium, and the electrode of the light-emitting chip includes a stack of chromium, platinum and gold.

7. The chip component detection method according to claim 6, wherein: The step of removing the test common electrode and the planar layer comprises: placing the chip assembly in a container containing hydrochloric acid to remove the test common electrode; The flat layer is removed using a debonding solution.

8. The chip component detection method according to any one of claims 1 to 7, characterized in that: The method for preparing the chip assembly comprises: Providing an epitaxial wafer; wherein the epitaxial wafer includes the growth substrate and an epitaxial layer formed on the growth substrate; performing patterning on the epitaxial layer to form a plurality of independent island-shaped epitaxial structures; forming an insulating protective layer on the island epitaxial structure; performing patterning on the insulating protection layer so as to expose a portion of the surface of the island-shaped epitaxial structure; An electrode layer is evaporated on the exposed surface of the island epitaxial structure.

9. The chip component detection method according to claim 8, wherein: The epitaxial layer includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; the method for manufacturing the island-shaped epitaxial structure includes: depositing a current spreading layer on the second conductive type semiconductor layer; Step etching and channel etching are performed on the epitaxial layer including the current spreading layer to form the island-shaped epitaxial structure.

10. The chip component detection method according to claim 9, wherein: The thickness of the current spreading layer ranges from 500A to 10000A.

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