Machine type detection circuit, machine type detection method, machine type detection device and household appliance

Abstract

The invention provides a machine type detection circuit, a machine type detection method, a machine type detection device and a household appliance. The circuit comprises a main control chip, a displacement register and a machine type selection circuit, in the model selection circuit, a common output end of a scanning signal input end group is electrically connected with a control electrode of a switching tube; the scanning signal input end group comprises more than two scanning signal input ends, each scanning signal input end is electrically connected with the corresponding output end of the displacement register, and the scanning signal input ends are connected or disconnected with the common output end; the main control chip sends a serial scanning signal to the displacement register; the displacement register converts the serial scanning signals into parallel scanning signals with preset digits and sends the parallel scanning signals to the model selection circuit, and the preset digits are equal to the number of the scanning signal input ends; and the main control chip acquires a model signal of the model signal output end. According to the invention, IO resources of the chip can be saved, and the accuracy of model detection is improved.

Description

Technical Field

[0001] The present invention relates to the field of machine type detection technology, and more specifically, to a machine type detection circuit, a machine type detection method using the machine type detection circuit, a machine type detection device using the machine type detection circuit, and a household appliance using the machine type detection device. Background Art

[0002] In the increasingly competitive home appliance industry, in order to supplement product lines, improve development efficiency and reduce development costs, companies usually choose to adjust the functions of a certain product based on a certain product and develop new models that meet customer needs.

[0003] To avoid the need to significantly adjust the software logic each time a new model is developed, the hardware layer needs to include a model detection circuit. The main control chip reads the different signals output by this model detection circuit, detects the corresponding model, and executes the corresponding functional logic.

[0004] For the model detection circuit, the current conventional practice is to connect the main control chip port to a pull-up resistor or a pull-down resistor, and read the high and low levels according to the installation method of the resistor; or connect the main control chip port to a resistor group and identify the model through AD sampling.

[0005] For the identification of models by reading high and low levels, such as Figure 1 As shown, first, we freely define the different models corresponding to the high and low levels read by the main control chip port. Depending on how the resistors are installed at the main control chip port, the main control chip can read different data. For example, if a pull-up resistor is installed at the main control chip port, the main control chip port will read a high level, in which case it is determined to be model 1; if a pull-down resistor is installed, it will read a low level, in which case it is determined to be model 2. This shows that a main control chip port can only determine two models. When there are many derived models, more main control chip ports may be occupied.

[0006] For identifying models through AD sampling, such as Figure 2 As shown, a resistor group is installed at the dedicated AD sampling port of the main control chip. By installing the resistors within the resistor group and controlling the closing or opening of switches S1, S2, and S3, different voltage values ​​can be output through resistor voltage division. The chip then samples the output voltage through the AD sampling port to obtain the AD value and then identifies the model based on the model information corresponding to the different AD values. However, this AD sampling method is limited by the resolution of the AD sampling port and is also affected by power supply ripple, resistor accuracy, and resistance value variations. The detection effect is unstable and may lead to misjudgment of the model.

[0007] Therefore, a more optimized model detection method needs to be considered. Summary of the Invention

[0008] A first object of the present invention is to provide a model detection circuit that can save chip IO resources and improve the accuracy of model detection.

[0009] A second object of the present invention is to provide a model detection method that can save chip IO resources and improve the accuracy of model detection.

[0010] A third object of the present invention is to provide a device for detecting a model of an aircraft that can save chip IO resources and improve the accuracy of the detection of the model of an aircraft.

[0011] A fourth object of the present invention is to provide a household appliance that can save chip IO resources and improve the accuracy of model detection.

[0012] In order to achieve the above-mentioned first purpose, the model detection circuit provided by the present invention includes a main control chip, a shift register and a model selection circuit; the model selection circuit includes a model signal output end, a switch tube and a scan signal input end group, the common output end of the scan signal input end group is electrically connected to the control electrode of the switch tube, and the model signal output end is electrically connected to the output end of the switch tube; the scan signal input end group includes more than two scan signal input ends, each scan signal input end is electrically connected to the output end corresponding to the shift register, and the scan signal input end and the common output end are connected or disconnected; the input end of the shift register is electrically connected to the main control chip; the main control chip sends a serial scan signal to the shift register; the shift register converts the serial scan signal into a parallel scan signal of a preset number of bits, and sends the parallel scan signal to the model selection circuit, wherein the preset number of bits is equal to the numerical value of the number of scan signal input ends; the main control chip obtains the model signal from the model signal output end.

[0013] As can be seen from the above scheme, the model detection circuit of the present invention, by providing a main control chip, a shift register, and a model selection circuit, utilizes the shift register to convert serial signals into parallel signals. Only one serial communication port and one clock port of the main control chip are required to control multiple scan signal input terminals, significantly saving the main control chip's IO resources. Simultaneously, the model selection circuit implements model identification through a combination of a switch tube and a scan signal input terminal group. The control electrode of the switch tube is connected to the common output terminal of the scan signal input terminal group. The switch tube is turned on and off by logic level control to generate a model signal. Therefore, it is insensitive to sampling power supply ripple, resistor accuracy, and resistance value, ensuring the accuracy of model detection. Furthermore, the scan signal input terminal is connected to an IO port of the main control chip via the output terminal of the switch tube, further saving the main control chip's IO resources.

[0014] In a further solution, a diode is provided between the conductive scan signal input terminal and the common output terminal.

[0015] It can be seen that by providing a diode and utilizing the unidirectional conductivity of the diode, the phenomenon of misconduction can be avoided and signal interference can be avoided at the same time.

[0016] In a further solution, the control electrode of the switch tube is electrically connected to the common output terminal through a current-limiting resistor.

[0017] It can be seen from this that by setting a current-limiting resistor between the control electrode of the switching tube and the common output terminal, when the scanning signal output by the shift register drives the switching tube through the common output terminal, if the instantaneous current is too large, it may cause the control electrode of the switching tube to break down, thereby protecting the switching tube.

[0018] In a further solution, the switching tube is a PNP transistor; the base of the PNP transistor is electrically connected to the common output terminal, the emitter of the PNP transistor is electrically connected to the power supply terminal, the collector of the PNP transistor is electrically connected to the model signal output terminal, and the collector of the PNP transistor is grounded.

[0019] In a further solution, the switching tube is an NPN transistor; the base of the NPN transistor is electrically connected to the common output terminal, the collector of the NPN transistor is electrically connected to the power supply terminal, the collector of the NPN transistor is also electrically connected to the model signal output terminal, and the emitter of the NPN transistor is grounded.

[0020] It can be seen that by reasonably selecting the type of switching tube, reliable driving of signal outputs of models with different level requirements can be achieved, while meeting the design requirements of low power consumption and high reliability.

[0021] In order to achieve the second purpose of the present invention, the model detection method provided by the present invention includes: the main control chip sends a serial scanning signal to the shift register; the shift register converts the serial scanning signal into a parallel scanning signal with a preset number of bits, and sends the parallel scanning signal to the scanning signal input end in the scanning signal input end group in sequence, wherein the preset number of bits is equal to the numerical value of the number of scanning signal input ends; the main control chip obtains the high and low levels of the model signal output end within a scanning cycle to obtain the model signal, and confirms the model of the device to be detected according to the model signal.

[0022] As can be seen from the above scheme, the model detection method of the present invention utilizes a shift register to convert serial signals into parallel signals. Only one serial communication port and one clock port of the main control chip are required to control multiple scan signal input terminals, significantly saving the main control chip's IO resources. Simultaneously, the model selection circuit implements model identification through a combination of a switch tube and a scan signal input terminal group. The control electrode of the switch tube is connected to the common output terminal of the scan signal input terminal group. The switch tube is turned on and off by controlling the logic level to generate the model signal. Therefore, the method is insensitive to sampling power supply ripple, resistor accuracy, and resistance value, ensuring the accuracy of model detection. Furthermore, the scan signal input terminal is connected to an IO port of the main control chip via the output terminal of the switch tube, further saving the main control chip's IO resources.

[0023] In a further solution, when the main control chip sends a serial scanning signal to the shift register, it also sends a clock signal of a preset frequency; the shift register sends a parallel scanning signal to one of the scanning signal input terminals in the scanning signal input terminal group at every preset time interval of the clock signal.

[0024] This shows that using the synchronous sampling data of the clock signal can effectively filter out glitches and noise during signal transmission, ensuring data accuracy. At intervals of a preset duration, a parallel scan signal is sent to one of the scan signal input terminals in the scan signal input terminal group, ensuring that the main control chip has sufficient time to detect each signal and ensure the accuracy of level detection.

[0025] In a further solution, the main control chip obtains the high and low levels of the model signal output terminal within a scanning cycle to obtain the model signal. The step of confirming the model of the device to be detected based on the model signal includes: obtaining the model signal obtained a preset number of times; when the model signals obtained the preset number of times are consistent, looking up the table according to the model signal to confirm the model of the device to be detected.

[0026] It can be seen that by performing consistency verification on the model signals obtained a preset number of times, the accuracy of the model detection of the device to be detected can be ensured.

[0027] In a further solution, when a table lookup is performed based on the model signal to confirm the model of the device to be detected, the method further includes: if the model of the device to be detected cannot be obtained by the table lookup, the device to be detected is shut down.

[0028] It can be seen that when an unknown model is detected, in order to ensure the safety of the equipment, the equipment to be tested is shut down.

[0029] In order to achieve the third objective of the present invention, the present invention provides a model detection device, which includes a model detection circuit. The model detection circuit applies the above-mentioned model detection circuit.

[0030] In order to achieve the fourth objective of the present invention, the present invention provides a household appliance, including a model detection device, which applies the above-mentioned model detection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a circuit diagram for identifying the model by reading high and low levels in the prior art.

[0032] Figure 2 This is a circuit diagram for identifying machine models through AD sampling in the prior art.

[0033] Figure 3 This is a circuit principle block diagram of the first embodiment of the machine model detection circuit of the present invention.

[0034] Figure 4 This is a circuit principle diagram of a model selection circuit for a model in the first embodiment of the model detection circuit of the present invention.

[0035] Figure 5 It is a circuit principle diagram of a model selection circuit for another model in the first embodiment of the model detection circuit of the present invention.

[0036] Figure 6 It is a flow chart of an embodiment of the machine model detection method of the present invention.

[0037] Figure 7 This is a flowchart of the steps in which the main control chip obtains the high and low levels of the model signal output terminal in a scanning cycle to obtain the model signal, and confirms the model of the device to be detected according to the model signal in an embodiment of the model detection method of the present invention.

[0038] Figure 8 Schematic diagram of the model information table in the embodiment of the model detection method of the present invention.

[0039] Figure 9 This is a circuit principle block diagram of the second embodiment of the machine model detection circuit of the present invention.

[0040] The present invention will be further described below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0041] The first embodiment of the model detection circuit: like Figure 3 As shown, in this embodiment, the model detection circuit includes a main control chip 1, a shift register 2, and a model selection circuit 3. The main control chip 1 is electrically connected to the input end of the shift register 2, the output end of the shift register 2 is electrically connected to the input end of the model selection circuit 3, and the output end of the model selection circuit 3 is electrically connected to the main control chip 1. In this embodiment, the shift register 2 is an 8-bit shift register.

[0042] In this embodiment, see Figure 4 The model selection circuit 3 includes a model signal output terminal SELECT1, a switch tube Q1 and a scan signal input terminal group 31. The common output terminal of the scan signal input terminal group 31 is electrically connected to the control electrode of the switch tube Q1, the model signal output terminal SELECT1 is electrically connected to the output terminal of the switch tube Q1, the model signal output terminal SELECT1 is also electrically connected to the main control chip 1, and the input terminal of the shift register 2 is electrically connected to the main control chip 1.

[0043] The scanning signal input terminal group 31 includes more than two scanning signal input terminals, each of which is electrically connected to the output terminal corresponding to the shift register 2, and the scanning signal input terminal and the common output terminal are connected or disconnected. The number of scanning signal input terminals can be set as needed. In this embodiment, the number of scanning signal input terminals is 8, such as Figure 4 By selecting whether the scan signal input terminal and the common output terminal are connected or disconnected, it can be used to set the model of the device to be detected. For example, Figure 4 In the figure, PIN1 to PIN8 are all connected to the common output terminal, which represents model A; Figure 5 In the figure, PIN2 and PIN3 are disconnected from the common output terminal, and the rest of the scan signal input terminals are connected to the common output terminal, which represents model B.

[0044] In this embodiment, a diode is provided between the conductive scan signal input terminal and the common output terminal. Figure 4 In the example, PIN1 to PIN8 are all connected to the common output terminal. Therefore, diodes D1 to D8 are placed between PIN1 to PIN8 and the common output terminal. By placing diodes, the unidirectional conductivity of the diodes is utilized to avoid misdirection and signal interference.

[0045] In this embodiment, the control electrode of the switch Q1 is electrically connected to the common output terminal via a current-limiting resistor R3. By providing current-limiting resistor R3 between the control electrode of the switch Q1 and the common output terminal, when the scan signal output by the shift register 2 drives the switch Q1 via the common output terminal, if the instantaneous current is too large, the control electrode of the switch Q1 may break down, thereby protecting the switch Q1.

[0046] The type of switch Q1 can be set as needed. In this embodiment, switch Q1 is a PNP transistor. The base of the PNP transistor is electrically connected to the common output terminal, the collector of the PNP transistor is electrically connected to the power supply terminal, and the collector of the PNP transistor is also electrically connected to the model signal output terminal SELECT1 via resistor R1. The emitter of the PNP transistor is grounded. The base of the PNP transistor and the emitter of the PNP transistor are also electrically connected via resistor R2. By combining the parameters of the PNP transistor and the chip port's requirements for sinking and sourcing current, the resistance values ​​of resistors R1, R2, and current-limiting resistor R3 are adjusted to match the saturation conduction of the PNP transistor, thereby reducing power consumption, accelerating switching speed, and thereby improving recognition accuracy.

[0047] In order to more clearly illustrate the present invention, the model detection method of the model detection circuit is described below.

[0048] See also Figure 6 In this embodiment, when the device model detection method is in operation, first, step S1 is executed, where the main control chip 1 sends a serial scan signal to the shift register 2. After power-on, in order to detect the model of the current device, the main control chip 1 needs to output a serial scan signal, for example, an 8-bit serial scan signal "0xFE" to the shift register 2.

[0049] When the main control chip 1 sends a serial scan signal to the shift register 2, it also sends a clock signal of a preset frequency. In order to facilitate the control of the shift register 2 for data sampling, a clock signal is required to the shift register 2. At the same time, in order to ensure that the main control chip 1 has sufficient time to detect each signal, a clock signal of a preset frequency is used. The preset frequency can be pre-set based on experimental data. In this embodiment, the preset frequency clock signal is a 2KHz square wave signal.

[0050] After the main control chip 1 sends the serial scan signal to the shift register 2, step S2 is executed. The shift register 2 converts the serial scan signal into a parallel scan signal with a preset number of bits. The parallel scan signals are then sequentially sent to the scan signal input terminals in the scan signal input terminal group 31. The preset number of bits is equal to the number of scan signal input terminals. In order to read the model information from the model selection circuit 3, the parallel scan signals need to be sequentially sent to the scan signal input terminals in the scan signal input terminal group 31, causing the model selection circuit 3 to output the model signal.

[0051] The shift register 2 sends a parallel scanning signal to one of the scanning signal input terminals in the scanning signal input terminal group 31 according to the preset duration of each clock signal interval. The preset duration is determined by the preset frequency. For example, if the clock signal with the preset frequency is a square wave signal of 2KHz, the preset duration is 0.5ms. At the rising edge of each clock signal, the serial data is sampled and shifted into the internal shift register 2, and then the content of the shift register 2 is output in parallel to the scanning signal input terminal. By using the synchronous sampling data of the clock signal, the burrs and noise in the signal transmission process can be effectively filtered to ensure the accuracy of the data. The parallel scanning signal is sent to one of the scanning signal input terminals in the scanning signal input terminal group 31 at each preset duration interval to ensure that the main control chip 1 has enough time to detect each signal and ensure the correctness of the level detection.

[0052] Specifically, in this embodiment, at a certain clock rising edge, scan signal input PIN1 is at a low level, while the others are at a high level. At the next clock rising edge, the serial scan signal continues to shift, i.e., scan signal input PIN2 is at a low level, while the others are at a high level. This continues in this manner until the 8-bit signal shift is complete, at which point a full scan cycle has passed, and a corresponding level change occurs at model signal output SELECT1. This level change is related to whether the scan signal input terminal is connected to the common output terminal. Taking scan signal input PIN1 as an example, when the scan signal input terminal PIN1 is connected to the common output terminal and PIN1 is at a low level, i.e., when the low-level bit in serial scan signal 0xFE is detected, the PNP transistor turns on, and model signal output SELECT1 is at a high level. When the scan signal input terminal PIN1 is disconnected from the common output terminal, model signal output SELECT1 remains at a low level, regardless of whether the scan signal input terminal PIN1 is detected by a low-level bit. The same applies to the remaining PIN ports. Therefore, the signal output terminal SELECT1 of the model will only be pulled low at the scan signal input terminal disconnected from the common output terminal during the entire scan cycle, and the scan signal input terminal connected to the common output terminal always maintains a high level.

[0053] After the parallel scan signals are sequentially transmitted to the scan signal input terminals in scan signal input terminal group 31, step S3 is executed. The main control chip 1 obtains the high and low levels of the model signal output terminal SELECT1 within a scan cycle to obtain a model signal. The model signal is used to confirm the model of the device to be detected. After the row scan signals are input to scan signal input terminal group 31, the model signal output terminal SELECT1 outputs the model signal, which can be used to further confirm the model of the device to be detected. In this embodiment, see Figure 7The main control chip 1 obtains the high and low levels of the model signal output terminal SELECT1 within a scanning cycle to obtain the model signal. When confirming the model of the device to be detected based on the model signal, step S11 is first executed to obtain the model signal obtained a preset number of times. The preset number of times is pre-set based on experimental data, and preferably, the preset number of times is two.

[0054] After obtaining the model signals obtained for the preset number of times, step S12 is executed to determine whether the model signals obtained for the preset number of times are consistent. In order to ensure the accuracy of the model detection of the device to be detected, the model signals obtained for the preset number of times are subjected to consistency verification.

[0055] When the model signals obtained for the preset number of times are consistent, step S13 is executed to look up the table according to the model signal to confirm the model of the device to be detected. If the model signals obtained for the preset number of times are consistent, it means that the model signal is correct. At this time, the model signal can be looked up in the table to obtain the model of the device to be detected. For example, Figure 8 As shown, the model signal output terminal SELECT1 outputs the model signal "11110000", and the model of the device to be detected is "Model X".

[0056] In this embodiment, when the model signal is used to look up the table to confirm the model of the device to be detected, the following steps are also included: if the model of the device to be detected cannot be obtained by the table lookup, the device to be detected is shut down. When an unknown model is detected, the device to be detected is shut down to ensure the safety of the device and an alarm is issued.

[0057] If the model signals obtained the preset number of times are inconsistent, step S14 is executed to re-detect the model. If the model signals obtained the preset number of times are inconsistent, it means that the model signal is correct or incorrect, and the model detection needs to be re-detected until the model signals obtained the preset number of times are consistent.

[0058] As can be seen from the above, the model detection circuit of the present invention is provided with a main control chip 1, a shift register 2, and a model selection circuit 3. The shift register 2 converts serial signals into parallel signals. Only one serial communication port and one clock port of the main control chip 1 are required to control multiple scan signal input terminals, significantly saving the IO resources of the main control chip 1. At the same time, the model selection circuit 3 realizes model identification through the combination of the switch tube Q1 and the scan signal input terminal group 31. The control electrode of the switch tube Q1 is connected to the common output terminal of the scan signal input terminal group 31. The switch tube Q1 is controlled to be on and off by the logic level to generate the model signal. Therefore, it is insensitive to the ripple of the sampling power supply, the accuracy and resistance value of the resistor, and the accuracy of the model detection is guaranteed. The scan signal input terminal is connected to an IO port of the main control chip through the output terminal of the switch tube, further saving the IO resources of the main control chip.

[0059] Second embodiment of the model detection circuit: The difference between the model detection circuit of this embodiment and the model detection circuit of the first embodiment lies in the different types of switch tubes. The difference is described below.

[0060] See also Figure 9 In this embodiment, the switch tube Q2 is an NPN transistor. The base of the NPN transistor is electrically connected to the common output terminal through the current-limiting resistor R6, the collector of the NPN transistor is electrically connected to the power supply terminal through the resistor R4, the collector of the NPN transistor is also electrically connected to the model signal output terminal SELECT2, the emitter of the NPN transistor is grounded, and the base of the NPN transistor is also electrically connected to the emitter of the NPN transistor through the resistor R5. Correspondingly, the polarity direction of the diode between the conductive scan signal input terminal and the common output terminal also changes accordingly. Of course, the 8-bit serial scan signal sent by the main control chip 1 to the shift register 2 also needs to be changed accordingly. For example, the 8-bit serial scan signal "0x01" is sent to the shift register 2.

[0061] The model detection method of the model detection circuit in this embodiment is similar to the model detection method in the first embodiment, and will not be described in detail here.

[0062] Model detection device embodiment: In this embodiment, the model detection device includes a circuit board, on which a model detection circuit is formed. The model detection circuit applies the model detection circuit in the first embodiment or the second embodiment.

[0063] Household appliances example: In this embodiment, the household appliance includes a model detection device, and the model detection device applies the model detection device of the above embodiment.

[0064] Household appliances include air conditioners, refrigerators, washing machines, fans, dehumidifiers, humidifiers and other equipment.

[0065] It should be noted that the above are only preferred embodiments of the present invention, but the design concept of the invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept also fall within the scope of protection of the present invention.

Claims

1. A model detection circuit, characterized in that: Including main control chip, shift register and model selection circuit; The model selection circuit includes a model signal output terminal, a switch tube and a scan signal input terminal group, the common output terminal of the scan signal input terminal group is electrically connected to the control electrode of the switch tube, and the model signal output terminal is electrically connected to the output terminal of the switch tube; The scanning signal input terminal group includes more than two scanning signal input terminals, each of which is electrically connected to the output terminal corresponding to the shift register, and the scanning signal input terminal is connected or disconnected from the common output terminal; The input end of the shift register is electrically connected to the main control chip; The main control chip sends a serial scanning signal to the shift register; The shift register converts the serial scan signal into a parallel scan signal of a preset number of bits, and sends the parallel scan signal to the model selection circuit, wherein the preset number of bits is equal to the number of the scan signal input terminals; The main control chip obtains the model signal from the model signal output terminal.

2. The model detection circuit according to claim 1, wherein: A diode is provided between the conductive scanning signal input terminal and the common output terminal.

3. The model detection circuit according to claim 1, wherein: The control electrode of the switch tube is electrically connected to the common output end through a current limiting resistor.

4. The model detection circuit according to any one of claims 1 to 3, characterized in that: The switch tube is a PNP transistor; The base of the PNP transistor is electrically connected to the common output end, the emitter of the PNP transistor is electrically connected to the power supply end, the collector of the PNP transistor is electrically connected to the model signal output end, and the collector of the PNP transistor is grounded.

5. The model detection circuit according to any one of claims 1 to 3, characterized in that: The switch tube is an NPN transistor; The base of the NPN transistor is electrically connected to the common output end, the collector of the NPN transistor is electrically connected to the power supply end, the collector of the NPN transistor is also electrically connected to the model signal output end, and the emitter of the NPN transistor is grounded.

6. A model detection method, applied to a model detection circuit, characterized in that: The model detection circuit includes a main control chip, a shift register and a model selection circuit; The model selection circuit includes a model signal output terminal, a switch tube and a scan signal input terminal group, the common output terminal of the scan signal input terminal group is electrically connected to the control electrode of the switch tube, and the model signal output terminal is electrically connected to the output terminal of the switch tube; The scanning signal input terminal group includes more than two scanning signal input terminals, each of which is electrically connected to the output terminal corresponding to the shift register, and the scanning signal input terminal is connected or disconnected from the common output terminal; The input end of the shift register is electrically connected to the main control chip; The method comprises: The main control chip sends a serial scanning signal to the shift register; The shift register converts the serial scan signal into a parallel scan signal with a preset number of bits, and sequentially sends the parallel scan signal to the scan signal input terminals in the scan signal input terminal group, wherein the preset number of bits is equal to the number of the scan signal input terminals; The main control chip obtains the high and low levels of the model signal output terminal in a scanning cycle to obtain a model signal, and confirms the model of the device to be detected according to the model signal.

7. The machine type detection method according to claim 6, wherein: When the main control chip sends a serial scanning signal to the shift register, it also sends a clock signal of a preset frequency; The shift register sends the parallel scanning signal to one of the scanning signal input terminals in the scanning signal input terminal group at intervals of a preset duration according to the clock signal.

8. The machine type detection method according to claim 6 or 7, characterized in that: The main control chip obtains the high and low levels of the model signal output terminal in a scanning cycle to obtain a model signal, and the step of confirming the model of the device to be detected according to the model signal includes: Obtaining the model signal obtained a preset number of times; When the model signals obtained the preset number of times are consistent, a table lookup is performed according to the model signal to confirm the model of the device to be detected.

9. The machine type detection method according to claim 8, characterized in that: When the table is looked up according to the model signal to confirm the model of the device to be detected, the method further includes: If the model of the device to be detected cannot be obtained by looking up the table, the device to be detected will be shut down for processing.

10. A device for detecting a model of an aircraft, comprising a device for detecting a model of an aircraft, characterized in that: The model detection circuit applies the model detection circuit according to any one of claims 1 to 5.

11. A household appliance, comprising a model detection device, characterized in that: The machine type detection device applies the machine type detection device according to claim 10.

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