Double-watchdog monitoring method and device and electronic equipment

Abstract

The invention discloses a double-watchdog monitoring method and device and electronic equipment. The method comprises the steps that when a central processing unit is triggered to reset, the central processing unit is reset through a first watchdog, and the first watchdog is arranged in the central processing unit; if the central processing unit fails to be reset through the first watchdog, the central processing unit is reset through a second watchdog, the second watchdog is arranged in a power supply controller, and the power supply controller is used for controlling power supply to the central processing unit. When the system needs to reset the central processing unit, the central processing unit is reset by the first watchdog, only the central processing unit needs to be restarted, the whole system does not need to be powered off, and the situation that system crash information cannot be kept in the instant power-off process due to the fact that the second watchdog is triggered when a common system is stuck is avoided. And under the condition that the first watchdog fails to reset the central processing unit, the central processing unit is reset through the second watchdog in a power-off mode, so that a guarantee is provided for self-resetting of the central processing unit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a dual watchdog monitoring method and device, and electronic equipment. Background Art

[0002] A CPU (Central Processing Unit) reset is a process in which the CPU automatically restores itself to its initial state under specific conditions. It plays a key role in ensuring the stability and reliability of computer systems. Existing CPU reset methods generally include the following.

[0003] The CPU has a built-in watchdog IP that enables self-reset of the central processing unit. The disadvantage of this method is that it relies on resources provided by the CPU to the watchdog IP, such as clock signals and power. While it can function normally in the event of a software crash, it can fail if there is CPU hardware interference, such as static electricity or a power supply anomaly.

[0004] The external MCU (Microcontroller Unit) resets the central processing unit. The disadvantage of this method is that there are situations where the CPU cannot be reset normally, such as when a status register does not reset with the reset signal or the peripheral power supply is abnormal.

[0005] The power controller watchdog resets the power supply. This method completely resets the system, including the CPU, but completely removes power, making it difficult to preserve debug resources at the scene of the error. Real-time log information is usually stored in DDR (Double Data Rate SDRAM). Resetting the power supply directly will result in DDR data loss, making it impossible to save crash information and hindering product problem location analysis.

[0006] In summary, the existing CPU self-reset method may cause the watchdog to fail, or cause the CPU to be unable to reset normally, or be unable to retain the crash information within the DDR, which is not conducive to locating and analyzing product problems. Summary of the Invention

[0007] The present invention provides a dual watchdog monitoring method and device, and electronic equipment, which can reduce information loss when a DDR internal freezes while ensuring normal CPU reset.

[0008] In one aspect of the present invention, a dual watchdog monitoring method is provided. The method includes: upon triggering a reset of a central processing unit (CPU), resetting the CPU via a first watchdog, the first watchdog being configured in the CPU; and if resetting the CPU via the first watchdog fails, resetting the CPU via a second watchdog, the second watchdog being configured in a power controller for controlling power supply to the CPU. In another aspect of the present invention, a dual watchdog monitoring device is provided. The device includes: a first watchdog, disposed in a central processing unit (CPU), configured to reset the CPU when a reset of the CPU is triggered; and a second watchdog, disposed in a power supply controller, configured to reset the CPU if the CPU fails to be reset by the first watchdog. The power supply controller is electrically coupled to the CPU to control power supply to the CPU.

[0009] In another aspect of the present invention, an electronic device is provided, comprising: a memory configured to store an executable program; and at least one processor configured to execute the program to perform the dual watchdog monitoring method described above.

[0010] According to the technical solution of the present invention, the first watchdog and the second watchdog are enabled simultaneously in the system. When the system triggers the reset of the central processing unit, the first watchdog is used to reset the central processing unit first, that is, only the central processing unit needs to be restarted, and there is no need to power off the entire system, thereby avoiding the situation where the ordinary system is stuck and the second watchdog is triggered, resulting in a momentary power off process and the DDR cannot maintain the system freeze information; when the first watchdog fails to reset the central processing unit, the second watchdog is used to reset the central processing unit by powering off, providing protection for the self-reset of the central processing unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a flow chart illustrating a dual watchdog monitoring method according to an embodiment of the present disclosure; Figure 2 is a flow chart illustrating a dual watchdog monitoring method according to an embodiment of the present invention; Figure 3 is a block diagram illustrating a dual watchdog monitoring device according to an embodiment of the present invention; Figure 4 is a schematic diagram illustrating an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] To illustrate the technical content, achieved objectives and effects of the present invention in detail, the following description is given in conjunction with the embodiments and accompanying drawings.

[0013] A computer system consists of two major components: hardware and software. Hardware, including physical components such as the central processing unit (CPU), memory, storage devices, and input / output devices, is the physical part of the computer, responsible for data processing, storage, and transmission. Existing CPU self-reset solutions primarily include internal watchdog reset, external MCU reset, and a secondary watchdog reset power supply. However, internal watchdog reset can lead to watchdog failure, external MCU reset can prevent the CPU from resetting properly, and a secondary watchdog reset power supply can cause DDR data loss and prevent the storage of crash information, hindering the location and analysis of product issues.

[0014] To address at least the aforementioned technical issues, the present disclosure provides a dual watchdog monitoring method. According to the present disclosure, when a CPU reset is triggered by the system, the first watchdog resets the CPU first. Only after the first watchdog fails to reset the CPU does the second watchdog reset the CPU. In this way, embodiments of the present disclosure utilize both the first and second watchdogs to provide dual reset protection. By prioritizing the use of the two watchdogs, the present disclosure reduces information loss during DDR internal freezes.

[0015] According to the embodiment of the present disclosure, the first watchdog in the central processing unit and the second watchdog in the power controller are enabled, and the feeding time of the two watchdogs is coordinated. When an abnormality occurs, the first watchdog in the central processing unit is triggered first. If the first watchdog cannot reset the system normally, wait for the second watchdog in the power controller to be triggered to reset the power supply. In this way, under general system abnormalities, the central processing unit is not powered off, and the power supply of the DDR is maintained. Therefore, the crash information maintained inside the DDR can be effectively maintained, which is convenient for locating product problems and retaining effective positioning analysis. In addition, it also ensures that in the event that the first watchdog fails due to individual more serious central processing unit abnormalities, the system can also be reset by the second watchdog in the power controller.

[0016] Abnormal situations of the first watchdog in the central processing unit include situations where the external power supply causes the central processing unit to fail to work properly. Because the first watchdog is an IP of the central processing unit and is a part of the central processing unit, for example, an abnormal working power collapse may cause the central processing unit to fail, and the first watchdog may also fail. Or a software error may cause the first watchdog in the central processing unit to fail, or an abnormal clock of the central processing unit may cause an abnormal reference clock of the first watchdog, etc. The second watchdog in the power controller is independent of the central processing unit and is not affected by the central processing unit and the complex operating system. The stability of the second watchdog is much higher than that of the first watchdog and can serve as the last guarantee.

[0017] The technical solution disclosed herein combines a first watchdog in the CPU with a second watchdog in the power controller. By incorporating the first watchdog in the CPU, the second watchdog in the power controller is prevented from being triggered by a typical system freeze, thereby preventing a sudden power outage in the CPU that could cause the DDR to lose system freeze information. Furthermore, by incorporating the second watchdog in the power controller, the system can be reset normally if the first watchdog in the CPU fails, preventing a system freeze.

[0018] Hereinafter, the technical solutions according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0019] Figure 1 FIG. 1 is a flow chart illustrating a dual watchdog monitoring method 100 according to an embodiment of the present disclosure. Figure 1 , the method 100 includes the following steps 102 to 104.

[0020] In step 102, when the CPU reset is triggered, the CPU is reset via a first watchdog, which is set in the CPU.

[0021] In this way, using the first watchdog to reset the CPU can solve system freeze problems caused by software failure, hardware anomalies, etc., such as program dead loop, program runaway, etc., by only restarting the CPU without powering off the entire system.

[0022] In some embodiments, if the first watchdog does not receive a feeding signal within a first time period, a CPU reset is triggered. Furthermore, while the CPU remains powered, the CPU system is reset via the first watchdog. In this manner, the CPU system reset via the first watchdog is automatically triggered by setting a first time period for controlling the first watchdog feeding. Furthermore, if an abnormality occurs in the CPU that prevents it from feeding within the first time period since the last feeding, the first watchdog resets the CPU.

[0023] In some embodiments, log file information corresponding to a reset triggered by the first watchdog is stored in the CPU's memory unit for troubleshooting. This allows for timely storage of critical CPU operational data, such as system status, register values, and program execution locations, immediately preceding the CPU reset. This detailed information allows technicians to quickly determine the exact moment of the CPU reset and its operating status, significantly reducing troubleshooting time and improving diagnostic efficiency.

[0024] In some embodiments, system operating data is obtained and determined to determine whether it meets preset reset conditions. If so, a CPU reset is triggered. Preset reset conditions include, but are not limited to, system abnormality and receipt of an external reset command. In this way, the application of dual reset protection by the first and second watchdogs is not limited to situations where the system is abnormal. By changing the preset reset conditions, the need for external command-controlled reset in other application scenarios can be met, thereby increasing the flexibility of the reset solution.

[0025] In step 104, if the CPU is reset by the first watchdog and fails, the CPU is reset by the second watchdog. The second watchdog is set in the power controller, and the power controller is used to control the power supply to the CPU.

[0026] In this way, by limiting the duration of the watchdog timing, the order of triggering the timeout reset of the first watchdog and the second watchdog is determined, ensuring that after the system stops feeding the watchdog, the first watchdog will perform the timeout reset first, avoiding the ordinary system jamming and triggering the second watchdog, resulting in a momentary power outage, and the DDR will be unable to maintain the system freeze information.

[0027] In some embodiments, if the second watchdog fails to receive a feeding signal within a second time period, the system reset via the first watchdog is determined to have failed. Furthermore, a reset signal is sent from the power controller to the central processing unit via the second watchdog, causing the central processing unit to power off and reset in order to reset the system. In this way, based on the limitations on the watchdog timing, the second watchdog can independently determine whether the first watchdog has successfully reset the system. As long as the second watchdog fails to receive a feeding signal within the second time period, the first watchdog has failed to successfully reset the central processing unit after executing a timeout reset, meaning that the central processing unit is still unable to feed the watchdog properly.

[0028] In some embodiments, it is determined whether the central processing unit has failed abnormally. If so, the central processing unit is reset by powering off the second watchdog. Otherwise, the central processing unit is reset by controlling the first watchdog through the second watchdog. In this way, it is possible to accurately distinguish between different states of the central processing unit, namely abnormal failure and non-abnormal but reset-prone conditions. For more serious faults such as abnormal failure, the use of power-off reset helps to completely eliminate possible error states and unstable factors inside the central processing unit, ensuring that the system can operate in a more reliable state after restarting. In addition, for non-abnormal but reset-prone conditions (such as software running stuck, program deadlock, etc.), unnecessary power-off operations are avoided by controlling the first watchdog to reset the central processing unit.

[0029] In some embodiments, the watchdog timing of the first watchdog is set to a first duration, and the watchdog timing of the second watchdog is set to a second duration, and the second duration is greater than the first duration. Specifically, the first duration is 9 to 11 seconds, for example, 10 seconds, and the second duration is 19 to 21 seconds, for example, 20 seconds. At the same time, the dog feeding timing is set to a third duration, and the third duration is less than the difference between the second duration and the first duration, and the third duration is 6 to 8 seconds, for example, 8 seconds. In this way, a time difference greater than the third duration is left between the first duration and the second duration. After the first watchdog successfully resets the system, it is ensured that the second watchdog can receive a dog feeding signal and restart the watchdog timing to avoid the system triggering the second watchdog reset again.

[0030] Hereinafter, application scenarios of the dual watchdog monitoring method and device according to embodiments of the present invention will be described by way of examples.

[0031] CPU self-reset is crucial to ensuring computer system stability and reliability. Existing methods include: The CPU has a built-in watchdog IP, but this relies on the CPU's own resources and may fail in situations such as hardware interference; an external MCU resets the CPU, but there are situations where the CPU cannot be reset normally; and the power controller watchdog resets the power supply, which can completely reset the system but will cause the freeze information in the DDR to be lost, hindering problem location analysis.

[0032] Figure 2 FIG. 3 is a flow chart illustrating a dual watchdog monitoring method 300 according to an embodiment of the present invention. Figure 2 As shown, the method includes the following steps 302 to 312.

[0033] In step 302, the first watchdog is set to reset after a 10s timeout, the second watchdog is set to reset after a 20s timeout, and an 8s timer dog feeding program is started.

[0034] In the first watchdog mechanism, if a 10s timeout reset is set, this means that when the system is operating normally, it must complete a "feeding the watchdog" operation every 10 seconds, sending a signal to the watchdog indicating normal operation. If the system fails to "feed the watchdog" within 10 seconds due to various reasons such as software failure or hardware error, the watchdog will determine that the system is abnormal. When the 10-second timeout is reached, the watchdog triggers a reset signal, forcing the CPU to reset. The second watchdog's 20s timeout reset is similar. Setting the second watchdog's timeout reset timer longer than the first watchdog's timeout reset timer means that if the system fails to feed the watchdog, the first watchdog will always time out and reset first.

[0035] In step 304, the system dog feeding timeout occurs.

[0036] Reasons for the system to trigger a CPU reset include but are not limited to: power problems, clock failures, hardware conflicts, etc. When the system fails to send a "feed the dog" signal to the watchdog timer in time due to various reasons, causing the watchdog timer to time out, a reset signal will be generated.

[0037] At step 306, the first watchdog timeout is reset.

[0038] After the system completes feeding the dog once, the timer of the first watchdog starts counting. If the timer reaches 10 seconds and the system still does not feed the dog, the system feeding timeout is triggered, and the first watchdog timeout reset is automatically triggered.

[0039] In step 308, it is determined whether the CPU is reset normally. If not, it means that the first watchdog is abnormal and cannot perform timeout reset.

[0040] Cases where the primary watchdog timer fails include situations where an external power supply causes the CPU to malfunction. For example, a power failure in the CPU causes the primary watchdog timer to fail, and thus the primary watchdog timer. Furthermore, software errors can also cause the primary watchdog timer to fail, or abnormalities in the CPU clock can cause abnormalities in the primary watchdog timer's reference clock.

[0041] At step 310, the second watchdog timeout is reset.

[0042] After the system completes a watchdog feeding, the second watchdog timer starts counting simultaneously with the first watchdog timer. When the timer reaches 10 seconds, the first watchdog timeout reset is automatically triggered, and the second watchdog timer continues counting. If the first watchdog timeout reset fails and the timer reaches 20 seconds, the second watchdog timeout reset is automatically triggered.

[0043] The second watchdog acts as a last resort. When the first watchdog times out and fails to reset the CPU, the second watchdog completely resets the system to reset the CPU.

[0044] According to another aspect of the present invention, Figure 3 FIG. 4 is a block diagram showing a dual watchdog monitoring device 400 according to an embodiment of the present invention. Figure 3 The dual watchdog monitoring device 400 includes a first watchdog 4022 and a second watchdog 4042. The first watchdog 4022 is provided in the central processing unit 402. The second watchdog 4042 is provided in the power controller 404. The power controller 404 is electrically coupled to the central processing unit 402 to control the power supply to the central processing unit 402.

[0045] The first watchdog 4022 is configured to reset the CPU 402 when the CPU 402 is triggered to reset. The second watchdog 4042 is configured to reset the CPU 402 if the CPU 402 fails to be reset by the first watchdog 4022 .

[0046] In some embodiments, the power controller 404 is electrically connected to the second watchdog 4042 and the central processing unit 402. The power controller 404 is configured to control the first watchdog 4022 to reset the central processing unit 402 when a reset of the central processing unit 402 is triggered. The power controller 404 is configured to control the second watchdog 4042 to reset the central processing unit 402 if the first watchdog 4022 fails to reset the central processing unit 402.

[0047] In some embodiments, the second watchdog 4042 is independent of the CPU 402 and is not affected by the CPU 402 and the complex operating system. Therefore, its stability is much higher than that of the first watchdog 4022, and thus serves as the final guarantee.

[0048] According to yet another aspect of the present invention, Figure 4 Schematic diagram of an electronic device 500 according to an embodiment of the present invention. Figure 4 The electronic device 500 includes a memory 502, a processor 504, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the various steps of the dual watchdog monitoring method described above are implemented.

[0049] In summary, in the dual watchdog monitoring method and device, and electronic device provided by the present invention, the first watchdog and the second watchdog are enabled simultaneously in the system. By adjusting the timer lengths of the first watchdog and the second watchdog, the timeout resets of the first watchdog and the second watchdog have a sequential execution order. When the system needs to reset the central processing unit, the first watchdog is given priority to reset the central processing unit. Then, only the central processing unit needs to be restarted, and there is no need to power off the entire system. This avoids the situation where the ordinary system is stuck and triggers the second watchdog, resulting in a momentary power outage process and the DDR cannot maintain the system freeze information. When the first watchdog fails to reset the central processing unit, the second watchdog is used to reset the central processing unit by powering off, providing a guarantee for the self-reset of the central processing unit. When the first watchdog successfully resets the central processing unit, the design of the dog feeding timing length being less than the difference between the timer timing of the first watchdog and the timer timing of the second watchdog ensures that the second watchdog is successfully fed, avoiding the erroneous triggering of the second watchdog timeout reset.

[0050] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's description and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A dual watchdog monitoring method, characterized in that: include: When a central processing unit reset is triggered, resetting the central processing unit through a first watchdog, wherein the first watchdog is set in the central processing unit; as well as If resetting the central processing unit through the first watchdog fails, the central processing unit is reset through the second watchdog, and the second watchdog is set in the power controller, and the power controller is used to control the power supply to the central processing unit.

2. The dual watchdog monitoring method according to claim 1, wherein: Also includes: The watchdog timer of the first watchdog is set to a first duration, and the watchdog timer of the second watchdog is set to a second duration, where the second duration is greater than the first duration.

3. The dual watchdog monitoring method according to claim 2, wherein: Resetting the central processing unit by the first watchdog comprises: If the first watchdog does not receive a feeding signal within the first time period, determining to trigger a reset of the central processing unit; and While keeping the power of the central processing unit, the system of the central processing unit is reset by the first watchdog.

4. The dual watchdog monitoring method according to claim 3, wherein: Also includes: The log file information corresponding to the reset by the first watchdog is stored in the storage unit of the central processing unit for use in problem location.

5. The dual watchdog monitoring method according to claim 2, wherein: Resetting the central processing unit by the second watchdog comprises: If the second watchdog does not receive the dog feeding signal within the second time period, it is determined that resetting the system through the first watchdog has failed; and A reset signal is sent from the power controller to the central processing unit through the second watchdog, so that the central processing unit is powered off and reset to reset the system.

6. The dual watchdog monitoring method according to claim 2, wherein: Also includes: The dog feeding timer is set to a third duration, where the third duration is smaller than a difference between the second duration and the first duration.

7. The dual watchdog monitoring method according to claim 1, wherein: Resetting the central processing unit by the second watchdog comprises: Determining whether the central processing unit fails abnormally; If so, powering off and resetting the central processing unit via the second watchdog; and Otherwise, the first watchdog is controlled by the second watchdog to reset the central processing unit.

8. The dual watchdog monitoring method according to claim 1, wherein: Also includes: Obtain and determine whether the system's operating data meets the preset reset conditions; as well as If so, the CPU is triggered to reset.

9. The dual watchdog monitoring method according to claim 8, wherein: The preset reset condition includes system operation abnormality or receiving an external reset instruction.

10. A dual watchdog monitoring device, characterized in that: include: A first watchdog is provided in the central processing unit and is configured to reset the central processing unit when the central processing unit is triggered to reset; as well as A second watchdog is provided in the power controller and is configured to reset the central processor if the central processor fails to be reset by the first watchdog. The power controller is electrically coupled to the central processor to control power supply to the central processor.

11. An electronic device, characterized in that: include: a memory configured to store an executable program; as well as At least one processor is configured to execute the program to perform the dual watchdog monitoring method according to any one of claims 1 to 9.

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