FPGA signal observation method, system, device and equipment and storage medium

Abstract

The invention relates to the technical field of FPGA debugging, and discloses an FPGA signal observation method, system, device and equipment and a storage medium, and the method comprises the steps: setting a unique identifier for a to-be-observed FPGA function module where a target observation signal is located, and setting the same identifier in an FPGA top module; constructing a signal transmission link between the function module and the top layer module based on the identifier, and realizing transmission of the target observation signal to the top layer module; and the signal is transmitted to a debugging interface through the top layer module, so that online observation is completed. According to the method, through identifier matching and link construction, the problems that in the prior art, signals need to be repeatedly and manually connected, and observation targets cannot be dynamically switched are solved, and the debugging efficiency is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of FPGA debugging technology, and in particular to an FPGA signal observation method, system, device, equipment and storage medium. Background Art

[0002] In the field of FPGA debugging, existing observation methods require manually exporting target signals from functional modules to the debug interface after synthesis is complete, and specifying the signal clock domains one by one. This process has significant drawbacks. First, users must wait for the time-consuming synthesis process to complete before operating, which can lead to debugging interruptions in large projects. Second, when the same functional module is instantiated multiple times, signals must be manually connected repeatedly for each instance, making it impossible to dynamically switch observation targets. Finally, if the functional module's code level changes, resynthesis and reconstruction of the signal connection links are required, greatly increasing debugging complexity.

[0003] Therefore, there is an urgent need for an FPGA signal observation method that can avoid comprehensive waiting time, support dynamic switching of observation targets, and adapt to code level changes, so as to solve the problems of low debugging efficiency and poor flexibility of existing technologies. Summary of the Invention

[0004] In view of this, the present application provides an FPGA signal observation method, system, device, equipment and storage medium to solve the problems of low debugging efficiency and poor flexibility in the existing technology.

[0005] In a first aspect, the present application provides an FPGA signal observation method, the method comprising:

[0006] Set a unique identifier for the FPGA function module to be observed where the target observation signal is located, and set the same unique identifier in the FPGA top-level module;

[0007] Based on the unique identifier, a signal transmission link is constructed between the FPGA function module to be observed and the FPGA top-level module; the signal transmission link is used to transmit the target observation signal to the FPGA top-level module;

[0008] The target observation signal is transmitted to the debugging interface through the FPGA top-level module for signal observation.

[0009] The FPGA signal observation method provided by the present application realizes automatic matching of the target signal group by setting the same unique identifier for the FPGA functional module to be observed and the FPGA top-level module, thereby omitting the manual signal-by-signal mapping operation; by constructing a signal transmission link based on the unique identifier, the link is pre-defined before synthesis, avoiding waiting for synthesis to be completed before manually leading out the signal; by uniformly transmitting the signal to the debugging interface by the FPGA top-level module, it supports switching the observation target by only modifying the identifier in multiple instance scenarios of the same functional module, directly solving the problems of cumbersome manual operations, long synthesis waiting time, and inflexible switching of observation targets in existing FPGA debugging, and significantly improving debugging efficiency and adaptability.

[0010] In an optional implementation, the unique identifier includes a bit width parameter of the target observation signal and an identifier name parameter.

[0011] The FPGA signal observation method provided in this application clearly defines the physical width of the signal through the bit width parameter to avoid observation errors caused by signal truncation or bit width mismatch; and provides globally unique naming through the identifier name parameter to ensure that the synthesis tool accurately identifies the target signal group and prevents mismatching.

[0012] In an optional implementation, establishing a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module includes:

[0013] Parse the hash index value of the unique identifier; and generate a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module according to the mapping relationship indicated by the hash index value.

[0014] The FPGA signal observation method provided in this application converts identifiers into efficient hash values ​​through hash index parsing, accelerating the matching and generation speed of signal links; mapping relationship generation directly locates the physical path through the hash value, reducing the complexity and resource overhead of link construction.

[0015] In an optional embodiment, establishing a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module further includes:

[0016] Set the same driving clock signal as the target observation signal for the FPGA top-level module, and use the driving clock signal to sample the signal through the debug interface to synchronize the timing.

[0017] The FPGA signal observation method provided in this application drives clock synchronization to eliminate cross-clock domain timing risks (such as metastability) and ensure the accuracy of signal capture; multiplexing clock sources avoids additional synchronization circuit design and simplifies the debugging interface configuration process.

[0018] In an optional embodiment, transmitting the target observation signal to the debugging interface through the FPGA top-level module includes:

[0019] The unique identifier is identified by the FPGA synthesis tool, and the physical connection of the target observation signal to the debug interface is completed during the layout and routing stage.

[0020] The FPGA signal observation method provided in this application directly calls the built-in functions of the manufacturer's tools to ensure the reliability of the link connection; no manual intervention is required for physical implementation.

[0021] In an optional embodiment, the method further includes:

[0022] When the FPGA function module to be observed is called multiple times, the value of the unique identifier is modified to switch the observation signal.

[0023] The FPGA signal observation method provided in this application only requires modifying the identifier value without rebuilding the signal transmission link; it can instantly switch between different instances of the same module to improve debugging flexibility.

[0024] In summary, the FPGA signal observation method provided by this application achieves accurate identification and misalignment prevention of target signal groups by setting unique identifiers containing bit width and name for functional modules and top-level modules; further constructs transmission links based on identifier hash indexes, significantly improving link generation efficiency and reducing resource consumption; at the same time, it drives the clock for the top-level module synchronously to eliminate timing risks; then, through the FPGA synthesis tool, it automatically completes the physical connection during the layout and routing phase, seamlessly integrating the standard development process; and finally supports dynamic switching of observation targets by modifying the identifier value. Each technical feature is progressive: the identifier serves as the core link, driving link construction, clock synchronization, and tool automation to achieve a dynamic debugging closed loop, solving the problems of cumbersome manual operations, long waiting times, and inflexible multi-instance switching in traditional FPGA debugging, and achieving efficient and automated observation of the entire process.

[0025] In a second aspect, the present application provides an FPGA signal observation system, the system comprising an FPGA functional module to be observed and an FPGA top-level module;

[0026] A signal marking module with a unique identifier is provided in the FPGA functional module to be observed; an input end of the signal marking module is connected to a target observation signal in the FPGA functional module to be observed;

[0027] A signal output module with the same unique identifier is provided in the FPGA top-level module; an output end of the signal output module is connected to a debugging interface;

[0028] A signal transmission link is provided between the signal marking module and the signal output module; the signal transmission link is constructed based on a unique identifier;

[0029] The signal output module is used to receive the target observation signal through the signal transmission link and transmit it to the debugging interface.

[0030] In a third aspect, the present application provides an FPGA signal observation device, which includes:

[0031] A marking module is used to set a unique identifier for the FPGA function module to be observed where the target observation signal is located, and to set the same unique identifier in the FPGA top-level module;

[0032] A construction module is used to construct a signal transmission link between the FPGA function module to be observed and the FPGA top-level module based on the unique identifier; the signal transmission link is used to transmit the target observation signal to the FPGA top-level module;

[0033] The output module is used to transmit the target observation signal to the debugging interface through the FPGA top-level module for signal observation.

[0034] In an optional embodiment, the building module is specifically configured to:

[0035] Parse the hash index value of the unique identifier; and generate a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module according to the mapping relationship indicated by the hash index value.

[0036] In an optional embodiment, the building module is further configured to:

[0037] Set the same driving clock signal as the target observation signal for the FPGA top-level module, and use the driving clock signal to sample the signal through the debug interface to synchronize the timing.

[0038] In an optional implementation, the output module is specifically configured to:

[0039] The unique identifier is identified by the FPGA synthesis tool, and the physical connection of the target observation signal to the debug interface is completed during the layout and routing stage.

[0040] In an optional embodiment, the device further comprises:

[0041] The modification module is used to modify the value of the unique identifier to switch the observation signal when the FPGA function module to be observed is called multiple times.

[0042] In a fourth aspect, the present application provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, computer instructions being stored in the memory, and the processor executing the computer instructions to thereby execute the FPGA signal observation method of the above-mentioned first aspect or any corresponding embodiment thereof.

[0043] In a fifth aspect, the present application provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the FPGA signal observation method of the above-mentioned first aspect or any corresponding embodiment thereof.

[0044] In a sixth aspect, the present application provides a computer program product, comprising computer instructions, which are used to enable a computer to execute the FPGA signal observation method of the above-mentioned first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 Schematic diagram of the process of the FPGA signal observation method according to an embodiment of the present application;

[0047] Figure 2 is a structural block diagram of an FPGA signal observation device according to an embodiment of the present application;

[0048] Figure 3 It is a schematic diagram of the hardware structure of the computer device of an embodiment of the present application. DETAILED DESCRIPTION

[0049] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0050] In the field of FPGA debugging, observing internal signals requires manual operation after synthesis is completed. Users need to first add anti-optimization mark attributes to the signals to be observed in the code. After the synthesis tool completes the time-consuming circuit conversion, they can manually lead the signals to the debugging interface (such as the logic analyzer) and specify their clock domains one by one. This method has serious flaws. First, the synthesis of large projects takes hours or even days, and users must wait for the synthesis to be completed before they can operate, resulting in an interruption in the debugging process (for example, engineers need to re-operate the next day); second, when the same functional module is called multiple times (such as module A is instantiated 3 times), the signal needs to be manually connected for each instance, and the observation target cannot be switched in real time; third, if the code structure adjustment causes the module hierarchy to change, the signal chain needs to be re-synthesized and rebuilt, which greatly increases the complexity of debugging.

[0051] Therefore, there is an urgent need for an FPGA signal observation method that can eliminate the synthesis waiting time, support dynamic switching of multiple instance targets, and adapt to code level changes to solve the problems of low debugging efficiency and lack of flexibility of existing technologies.

[0052] The present invention provides a method for observing FPGA signals. Figure 1 is a flow chart of the FPGA signal observation method according to an embodiment of the present application, such as Figure 1 As shown, the process includes the following steps:

[0053] S101. Set a unique identifier for the FPGA function module to be observed where the target observation signal is located, and set the same unique identifier in the FPGA top-level module.

[0054] Specifically, in step S101, the target observation signal is essentially a key logic signal within the FPGA functional module that requires real-time monitoring. Signal types of the target observation signal include, but are not limited to, register values, state machine flags, and data buses. The signal has a defined bit width, clock domain affiliation, and physical location (logical coordinates within the FPGA chip).

[0055] The FPGA functional module to be observed is an independent logic unit that implements a specific function in the FPGA design and is instantiated as a submodule by the top-level module. It can include combinational logic, sequential logic, or IP core integration.

[0056] The unique identifier is a globally unique signal group matching label. It can be a custom string and must ensure uniqueness throughout the entire design. Its main function is to mark the target signal group in the functional module and declare the receiving target with the same identifier in the top-level module. This replaces traditional manual signal mapping and realizes automated matching.

[0057] The FPGA top-level module is the highest-level container of the FPGA design, used to instantiate all sub-modules (including the observed functional module); it is also used to manage the signal interconnection between sub-modules; it serves as the end point of the signal transmission link and the starting point of the debug interface.

[0058] S102: Based on the unique identifier, a signal transmission link is established between the FPGA functional module to be observed and the FPGA top-level module.

[0059] Specifically, in step S102, the signal transmission link is a logical channel automatically constructed based on the unique identifier, and is used to transmit the target observation signal to the FPGA top-level module. During the synthesis phase, it is converted into FPGA internal wiring resources.

[0060] S103: Transmit the target observation signal to the debugging interface through the FPGA top-level module for signal observation.

[0061] Specifically, in step S103, the debugging interface is a terminal for signal observation, which is used to capture signal waveforms in real time, trigger specific events, and store and analyze data.

[0062] Optionally, the unique identifier includes the bit width parameter and the identifier name parameter of the target observation signal. The bit width parameter explicitly defines the physical width of the signal to avoid observation errors caused by signal truncation or bit width mismatch. The identifier name parameter provides a globally unique name to ensure that the synthesis tool accurately identifies the target signal group and prevents mismatches.

[0063] Optionally, a signal transmission link is constructed between the FPGA functional module to be observed and the FPGA top-level module, including: parsing the hash index value of the unique identifier; and generating the signal transmission link between the FPGA functional module to be observed and the FPGA top-level module based on the mapping relationship indicated by the hash index value. Hash index parsing converts the identifier into an efficient hash value, accelerating the matching and generation of the signal link. The mapping relationship generation directly locates the physical path through the hash value, reducing the complexity and resource overhead of link construction.

[0064] Optionally, establishing a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module also includes: setting a drive clock signal for the FPGA top-level module that is identical to the target observation signal, and using the drive clock signal for signal sampling through the debug interface to achieve timing synchronization. Drive clock synchronization eliminates cross-clock domain timing risks (such as metastability) and ensures accurate signal capture; multiplexing clock sources avoids the design of additional synchronization circuits and simplifies the debug interface configuration process.

[0065] Optionally, the target observation signal is transmitted to the debug interface through the FPGA top-level module. This involves identifying a unique identifier through the FPGA synthesis tool and physically connecting the target observation signal to the debug interface during the layout and routing phase. This directly calls the vendor tool's built-in functions to ensure link reliability, eliminating the need for manual physical implementation. The FPGA synthesis tool of choice should be based on the specific FPGA model and design requirements, such as Vivado or Synplify / Compiler.

[0066] Optionally, the method further includes modifying the value of a unique identifier to switch the observed signal when the observed FPGA functional module is called multiple times. This requires only modifying the identifier value, eliminating the need to rebuild the signal transmission link. This allows for instant switching between different instances of the same module, improving debugging flexibility.

[0067] In summary, the FPGA signal observation method provided by the embodiment of the present application realizes accurate identification and misalignment prevention of the target signal group by setting a unique identifier containing bit width and name for the functional module and the top-level module; further constructs a transmission link based on the identifier hash index, significantly improving the link generation efficiency and reducing resource consumption; at the same time, it drives the clock for the top-level module synchronously to eliminate timing risks; then automatically completes the physical connection in the layout and routing stage through the FPGA synthesis tool, seamlessly integrating the standard development process; and finally supports dynamic switching of the observation target by modifying the identifier value. The various technical features are progressive: the identifier serves as the core link, driving link construction, clock synchronization, and tool automation to realize a dynamic debugging closed loop, solving the problems of cumbersome manual operations, long waiting times, and inflexible multi-instance switching in traditional FPGA debugging, and achieving efficient and automated observation of the entire process.

[0068] Based on the FPGA signal observation method provided in the above embodiment, the embodiment of the present application further provides an FPGA signal observation system, which includes:

[0069] FPGA functional modules and FPGA top-level modules to be observed;

[0070] A signal marking module with a unique identifier is provided in the FPGA functional module to be observed; an input end of the signal marking module is connected to a target observation signal in the FPGA functional module to be observed;

[0071] A signal output module with the same unique identifier is provided in the FPGA top-level module; an output end of the signal output module is connected to a debugging interface;

[0072] A signal transmission link is provided between the signal marking module and the signal output module; the signal transmission link is constructed based on a unique identifier;

[0073] The signal output module is used to receive the target observation signal through the signal transmission link and transmit it to the debugging interface.

[0074] In the above FPGA signal observation system, the construction method of the signal marking module can be exemplarily referred to the following code:

[0075] PROBE_IN#(

[0076] parameter integer width=1,

[0077] parameter tag="" ) (

[0080] input[width-1:0]probe_in );

[0082] This code indicates that the signal to be observed in the FPGA functional module to be observed is led to the PROBE_IN module, and the PROBE_IN module is the signal marking module.

[0083] Among them, width is the sum of the bit widths of the target observation signals to be introduced, tag is the signal group name of these introduced signals, and is a unique identifier; probe_in is the target observation signal to be introduced.

[0084] The construction method of the signal output module can be exemplified by referring to the following code:

[0085] PROBE_OUT#(

[0086] parameter integer width=1,

[0087] parameter tag="" ) (

[0090] Input clk_in,

[0091] output[width-1:0]probe_out );

[0093] This code indicates that the target observation signal is output to the corresponding debugging interface.

[0094] Among them, width is the sum of the signal bit widths of the probe_in you want to connect, tag is the unique identifier tag of the probe_in you want to connect (based on this unique identifier tag, you can determine which probe_in you need to connect), clk_in is connected to the clock of the clock domain where the referenced signal is located, and probe_out is connected to the signal referenced by probe_in.

[0095] This FPGA signal observation system does not need to wait until synthesis is completed before introducing the signals to be observed. During the code writing stage, a dedicated module can be called to introduce the signals to be observed. After introducing the signals, the project (synthesis, layout and routing, etc.) can be run. The software can determine which probe_in signal to introduce for observation based on the unique identifier.

[0096] When the module where the signal to be observed is located is called multiple times (assuming it is named module_name_a, module_name_b, module_name_c), and you only need to observe the signal in one of the modules (for example, module_name_a), you only need to fill the probe_out tag with the probe_in tag in module_name_a, and at the same time, you only need to connect clk_in to the clock in the clock domain where the referenced signal is located, without having to specify the clock domain for each signal; later, if you want to observe module_name_b, you only need to fill the tag with the probe_in tag name in module_name_b;

[0097] When the module where the signal to be observed is located has undergone a hierarchical change in the entire code structure, there is no need to wait for the synthesis to be completed and then re-introduce the signal. You can directly run the project (synthesis, layout and routing, etc.).

[0098] This embodiment also provides an FPGA signal observation device for implementing the above-mentioned embodiments and preferred embodiments. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0099] This embodiment provides an FPGA signal observation device, such as Figure 2 Shown, including:

[0100] The marking module 201 is used to set a unique identifier for the FPGA function module to be observed where the target observation signal is located, and set the same unique identifier in the FPGA top-level module;

[0101] A construction module 202 is configured to construct a signal transmission link between the FPGA function module to be observed and the FPGA top-level module based on the unique identifier; the signal transmission link is configured to transmit the target observation signal to the FPGA top-level module;

[0102] The output module 203 is used to transmit the target observation signal to the debugging interface through the FPGA top-level module for signal observation.

[0103] In an optional embodiment, the construction module 202 is specifically configured to:

[0104] Parse the hash index value of the unique identifier; and generate a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module according to the mapping relationship indicated by the hash index value.

[0105] In an optional embodiment, the construction module 202 is further configured to:

[0106] Set the same driving clock signal as the target observation signal for the FPGA top-level module, and use the driving clock signal to sample the signal through the debug interface to synchronize the timing.

[0107] In an optional implementation, the output module 203 is specifically configured to:

[0108] The unique identifier is identified by the FPGA synthesis tool, and the physical connection of the target observation signal to the debug interface is completed during the layout and routing stage.

[0109] In an optional embodiment, the device further comprises:

[0110] The modification module 204 is configured to modify the value of the unique identifier to switch the observation signal when the FPGA function module to be observed is called multiple times.

[0111] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0112] The FPGA signal observation device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0113] The present application also provides a computer device having the above Figure 2 The FPGA signal observation device shown.

[0114] See also Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present application. Figure 3 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 3 A processor 10 is taken as an example.

[0115] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0116] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0117] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0118] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0119] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0120] The embodiments of the present application also provide a computer-readable storage medium. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0121] Part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes but is not limited to a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0122] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A FPGA signal observation method, characterized in that: The method comprises: Set a unique identifier for the FPGA function module to be observed where the target observation signal is located, and set the same unique identifier in the FPGA top-level module; Based on the unique identifier, a signal transmission link is constructed between the FPGA function module to be observed and the FPGA top-level module; the signal transmission link is used to transmit the target observation signal to the FPGA top-level module; The target observation signal is transmitted to the debugging interface through the FPGA top-level module for signal observation.

2. The method according to claim 1, characterized in that The unique identifier includes a bit width parameter and an identifier name parameter of the target observation signal.

3. The method according to claim 2, characterized in that The step of constructing a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module includes: Resolving a hash index value of the unique identifier; A signal transmission link between the FPGA function module to be observed and the FPGA top-level module is generated according to the mapping relationship indicated by the hash index value.

4. The method according to claim 3, characterized in that The construction of a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module further includes: A driving clock signal identical to the target observation signal is set for the FPGA top-level module, and the driving clock signal is used to perform signal sampling through the debugging interface to synchronize the timing.

5. The method according to claim 4, characterized in that The method of transmitting the target observation signal to the debugging interface through the FPGA top-level module includes: The unique identifier is identified by an FPGA synthesis tool, and the physical connection of the target observation signal to the debugging interface is completed during the layout and routing stage.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: When the FPGA function module to be observed is called multiple times, the value of the unique identifier is modified to switch the observation signal.

7. An FPGA signal observation system, characterized in that: The system includes an FPGA functional module to be observed and an FPGA top-level module; wherein, A signal marking module with a unique identifier is provided in the FPGA function module to be observed; an input end of the signal marking module is connected to a target observation signal in the FPGA function module to be observed; A signal output module with the same unique identifier is provided in the FPGA top-level module; an output end of the signal output module is connected to a debug interface; A signal transmission link is provided between the signal marking module and the signal output module; the signal transmission link is constructed based on the unique identifier; The signal output module is used to receive the target observation signal through the signal transmission link and transmit it to the debugging interface.

8. An FPGA signal observation device, characterized in that: The device comprises: A marking module is used to set a unique identifier for the FPGA function module to be observed where the target observation signal is located, and to set the same unique identifier in the FPGA top-level module; A construction module is used to construct a signal transmission link between the FPGA function module to be observed and the FPGA top-level module based on the unique identifier; the signal transmission link is used to transmit the target observation signal to the FPGA top-level module; The output module is used to transmit the target observation signal to the debugging interface through the FPGA top-level module for signal observation.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the FPGA signal observation method according to any one of claims 1 to 6 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the FPGA signal observation method according to any one of claims 1 to 6.

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