XDMA IP rapid configuration method and system for PCIe module in FPGA chip based on network port

Abstract

The invention discloses an XDMA IP rapid configuration method and system for a PCIe module in an FPGA chip based on a network interface, and by means of the method, an upper computer can take a selected network protocol as a transmission carrier through the network interface, so that configuration and state monitoring of a DMA register space in an FPGA are achieved. According to the method, a user not only can realize multiple continuous configuration requirements in a short time, but also can carry out remote debugging and maintenance work under the condition that the equipment is inconvenient to directly operate, so that the system development efficiency and the application flexibility are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of communication and network configuration, and in particular to a method and system for quickly configuring a PCIe module XDMA IP in an FPGA chip based on a network port. Background Art

[0002] PCIe is a high-performance, high-speed serial computer expansion bus standard used to connect high-performance devices within computer systems. Its high bandwidth and low latency have made it widely used in a variety of applications. In particular, PCIe interfaces are often used to achieve efficient, high-speed data transfer and system expansion in embedded systems and programmable logic devices such as FPGAs.

[0003] The Xilinx XDMA IP is a high-performance, configurable SG-mode DMA for PCIE 2.0 and PCIE 3.0, suitable for asynchronous transfer of large amounts of data and low-latency data stream transmission. The XDMA IP provides a user-selectable AXI-Lite Slave interface for transmitting configuration and control commands over the bus. This interface complies with the AXI-Lite protocol specification and can be used to configure the DMA register space in the XDMA IP core.

[0004] Existing FPGA chips integrate Ethernet interfaces and PCIe interfaces to achieve efficient data transmission and system expansion functions. However, in actual applications, there are still the following problems in quickly configuring the DMA register space of the XDMA IP core in the PCIe module: First, traditional configuration methods rely on physical contact or dedicated tools, which are often difficult to implement when remote management is required (such as remote device deployment). Second, the configuration efficiency is low. In some application scenarios, especially when the DMA register space needs to be configured multiple times in a short period of time, the existing configuration methods may not meet the real-time requirements. In addition, when the FPGA board is deployed in a remote device or when direct physical contact is not possible (for example, the device is installed at a high position or located in a dangerous area), developers usually find it difficult to complete the DMA configuration or perform troubleshooting.

[0005] Therefore, how to achieve fast and efficient configuration of the DMA register space in the PCIe module through network transmission has become a technical problem that needs to be solved urgently. Summary of the Invention

[0006] In view of this, one of the objectives of the present invention is to provide a method for quickly configuring the XDMA IP address of a PCIe module in an FPGA chip based on a network port, which can achieve fast and efficient configuration of the DMA register space in the PCIe module. A second objective of the present invention is to provide a system for quickly configuring the XDMA IP address of a PCIe module in an FPGA chip based on a network port.

[0007] One of the objectives of the present invention is achieved through the following technical solutions:

[0008] A method for quickly configuring the XDMA IP address of a PCIe module in an FPGA chip based on a network port is characterized in that the method includes a downlink operation and an uplink operation. The downlink operation involves packaging the configuration content of a register into a UDP protocol data packet by a host computer and transmitting it to the FPGA chip via a network. After receiving the data, the internal logic of the FPGA decodes the data and extracts the corresponding configuration content, thereby completing the read and write operations on the DMA register area.

[0009] The uplink operation is when the host computer needs to obtain the FPGA operating status, initiates a read request to the status register, and the FPGA transmits the response result data in the register back to the host computer through the network.

[0010] Further, the specific steps include:

[0011] Step S1: Generate a register configuration instruction sequence using a host computer. The configuration content includes the target address, operation type, and configuration data. Encapsulate the instruction sequence into a UDP protocol data packet, add a sequence number, and send it to the FPGA buffer through the network interface.

[0012] Step S2: After the data enters the FPGA, the received UDP protocol data packet is parsed and split into data packets;

[0013] Step S3: The FPGA's encoding and decoding module further processes the data packet to adapt to specific needs. During downlink operations, it parses the data packet to extract the configuration content to complete the register write operation; during uplink operations, it responds to the read request, obtains the operation result encapsulated as a response data packet in the register, and uploads it to the host computer through the FPGA.

[0014] Furthermore, in step S3, in the downlink operation, the target address and configuration data signals are converted into AXI-lite standard protocol signals using the interface conversion module, and the configuration information is sent to the DMA register space of the IP core.

[0015] Furthermore, a specific format is used to decompose UDP protocol packets. The labels include head, addr, data, wr_en, enable, reserved, and odd_parity. The meanings of each label are as follows:

[0016] head is the fixed frame header 0xAA, addr is the 16-bit DMA reg space configuration address, and data is the 32-bit DMA reg space data. If wr_en is high, it indicates writing to the register through the network port, and if it is low, it indicates reading the register. If enable is valid, it indicates that the current read or write request is a valid request, otherwise the FPGA can ignore it and not respond. odd_parity is the odd parity value of the first 63 bits of data, which is used to determine whether there is an error in the data packet.

[0017] The second object of the present invention is achieved through the following technical solutions:

[0018] A PCIe module XDMA IP fast configuration system in an FPGA chip based on an Internet port, the system includes

[0019] The host computer unit is used to encapsulate the DMA register operation instructions into configuration data packets that comply with the UDP protocol;

[0020] The network transmission unit realizes the downlink transmission of configuration data packets and the uplink transmission of response data packets through the Ethernet physical layer;

[0021] The FPGA unit parses the configuration data packet to extract the configuration content in order to complete the register write operation during the downlink operation; responds to the read request during the uplink operation, obtains the operation result encapsulated as the response data packet in the register and transmits it back to the host computer.

[0022] Furthermore, the FPGA unit comprises:

[0023] The protocol parsing module is used to parse and split the received UDP protocol data packets into data packets;

[0024] The codec module is used to parse the target register address, operation type, and configuration data of the data packet; output the configuration content to the interface conversion module during downlink operation; respond to read requests during uplink operation, obtain the status information stored in the target register transmitted by the interface conversion module, and encode the data into a standardized UDP data packet according to a specific format;

[0025] The interface conversion module converts the target address and configuration data signals into AXI-lite standard protocol signals during downlink operations and sends the configuration information to the DMA register space of the IP core; during uplink operations, it returns the DMA register status value to the codec module.

[0026] Furthermore, the decomposition of the configuration data packet adopts a specific format, and the labels include head, addr, data, wr_en, enable, reserved, and odd_parity in sequence; the meaning of each label is as follows:

[0027] head is the fixed frame header 0xAA, addr is the 16-bit DMA reg space configuration address, and data is the 32-bit DMA reg space data. If wr_en is high, it indicates writing to the register through the network port, and if it is low, it indicates reading the register. If enable is valid, it indicates that the current read or write request is a valid request, otherwise the FPGA can ignore it and not respond. odd_parity is the odd parity value of the first 63 bits of data, which is used to determine whether there is an error in the data packet.

[0028] The beneficial effects of the present invention are:

[0029] This paper takes full advantage of the high performance of the Ethernet interface and combines the simplicity and efficiency of UDP compared to the TCP network protocol to propose an efficient, flexible, and easy-to-implement method for quickly configuring the DMA register space of the PCIe module XDMA IP core in an FPGA chip. This method not only allows users to achieve multiple continuous configuration requirements in a short period of time, but also allows remote debugging and maintenance work when it is inconvenient to directly operate the device, significantly improving system development efficiency and application flexibility.

[0030] Other advantages, objects, and features of the present invention will be described in part in the following description and, in part, will be apparent to those skilled in the art upon examination of the following or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and obtained through the following description and the preceding claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings, in which:

[0032] Figure 1 Schematic diagram of the method flow of the present invention;

[0033] Figure 2 Schematic diagram of the process of configuring XDAM PCIe IP core for PC side;

[0034] Figure 3 This is a schematic diagram of the specific format of the 64-bit data packet protocol used in the present invention. DETAILED DESCRIPTION

[0035] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments are only for illustrating the present invention, and are not intended to limit the scope of protection of the present invention.

[0036] The present invention proposes a specific implementation scheme for data communication and register configuration between the XDMA module in the FPGA and the host computer based on the network port. The core idea is to use the UDP protocol as a transmission carrier through the network interface to realize the configuration and status monitoring of the DMA register space inside the FPGA. The method includes downlink operation and uplink operation. The downlink operation (write operation) is to package the configuration content of the register into a UDP protocol data packet through the host computer and transmit it to the FPGA chip through the network; after receiving the data, the internal logic of the FPGA will decode the data and extract the corresponding configuration content, thereby completing the read and write operations on the DMA register area; the uplink operation (read operation) is when it is necessary to obtain the FPGA operating status, the host computer initiates a read request for the status register, and the FPGA transmits the response result data in the register back to the host computer through the network. At the network layer, the UDP protocol is selected as the main protocol for data transmission. The FPGA involved in this embodiment includes a gigabit network module, a codec module, an interface conversion module and the XDMA module to be configured. Its design block diagram is shown in the attached figure. Figure 2 shown.

[0037] like Figure 1 As shown in the flowchart, the following is the specific implementation plan:

[0038] Step S1: Generate a command sequence containing register configuration content using a host computer. The configuration content includes the target address, operation type, and configuration data. Encapsulate the command sequence into a UDP protocol data packet, add a sequence number, and send it to the FPGA's receiving buffer through the network interface.

[0039] At the network layer, UDP is a connectionless transmission protocol with low latency and high efficiency, making it ideal for applications with high real-time requirements. Its data segments can contain 46 to 1500 bytes of data and can simultaneously transmit multiple XDMA register configuration information. Using UDP, the host computer can send control commands to the FPGA or retrieve status information from it. The FPGA can also transmit collected data back to the host computer via UDP. This communication method eliminates the need to maintain complex connection states, reduces protocol overhead, and thus improves communication efficiency.

[0040] It should be noted that in this embodiment, the FPGA communicates with the host computer's network card via the RGMII interface. The RGMII interface not only supports data transmission rates up to 1 Gbps but also ensures signal stability and reliability over long distances. In this way, the FPGA can establish a direct network connection with the host computer without the need for additional protocol conversion or external equipment.

[0041] Step S2: After the data enters the FPGA, the received UDP protocol data packet is parsed and split into data packets;

[0042] In this embodiment, this step is implemented by the Gigabit Ethernet module of the FPGA. The main functions of the Gigabit Ethernet module include the encapsulation and parsing of network data packets. After the network port enters the FPGA, the Gigabit Ethernet module splits the valid data into 64-bit data packets, or frames the 64-bit status feedback information through the Gigabit Ethernet module and sends it to the host computer. In order to ensure the accuracy and integrity of data transmission, a specific format is used to decompose the UDP data packet, as shown in the attached figure. Figure 3 As shown in the figure, the labels include head, addr, data, wr_en, enable, reserved, and odd_parity in sequence. The meanings of each label are as follows: head is the fixed frame header 0xAA, addr is the 16-bit DMA reg space configuration address, and data is the 32-bit DMA reg space data. If wr_en is high, it means writing to the register through the network port, and if it is low, it means reading the register. If enable is valid, it means the current read or write request is a valid request. Otherwise, the FPGA can ignore it and not respond. odd_parity is the odd parity value of the first 63 bits of data, which is used to determine whether the data packet has errors.

[0043] For example, in a write operation, the host computer generates a data packet containing the target configuration address and target configuration data, and sends it to the FPGA through the UDP protocol. The Gigabit Ethernet module splits the configuration data of multiple registers, and each 64-bit data packet is the configuration data for a single register in the XDMA. In a read operation, a corresponding read request is generated, and the FPGA responds and returns status information. The Gigabit Ethernet module is responsible for framing the multiple 64-bit data packets received according to the UDP communication protocol, and finally transmits them to the host computer through the RGMII interface.

[0044] Step S3: The FPGA's encoding and decoding module further processes the data packet to adapt to specific needs. During downlink operations, it parses the data packet to extract the configuration content to complete the register write operation; during uplink operations, it responds to the read request, obtains the operation result encapsulated as a response data packet in the register, and uploads it to the host computer through the FPGA.

[0045] In the downlink direction (write operation), the module will first parse the 64-bit UDP data packet, extract the address of the target register, the data content to be written, and related control parameters, such as the read / write type and other key information. This decoded information will eventually be passed to the corresponding register for processing to complete the data write operation. In the uplink direction (read operation), when the host computer initiates a read request for a specific status register through the network, the codec module will obtain the information stored in the target address register transmitted by the interface conversion module, and encode this data into a standardized 64-bit UDP data packet according to the established format. Finally, the port number, packet length, checksum, etc. are added to form a complete network upload data frame, which is transmitted to the host computer for further processing.

[0046] Since the DMA register space configuration in the XDMA IP needs to be performed through the standard AXI-lite interface, and the configuration data output by the codec module does not have the ability to directly interface with this interface, effective signal adaptation must be implemented to ensure that the configuration data can be smoothly transmitted to the target AXI-lite interface. In this process, the configuration address and configuration data signals are converted into AXI-lite standard protocol signals by using the interface conversion module, and the configuration information is sent to the DMA register space of the IP core. In other words, the interface conversion module converts the configuration data output by the codec module into AXI-lite interface signals, or converts the AXI-lite interface signals read from the XDMA IP into the data format required by the codec module.

[0047] Based on the design concept of the above method, the present invention also provides a PCIe module XDMA IP fast configuration system in an FPGA chip based on a network port. The system architecture includes:

[0048] (1) A host computer unit, used to encapsulate DMA register operation instructions into configuration data packets that comply with the UDP protocol;

[0049] (2) Network transmission unit, which realizes downlink transmission of configuration data packets and uplink transmission of response data packets through the Ethernet physical layer;

[0050] (3) FPGA unit, when operating downstream, parses the configuration data packet to extract the configuration content in order to complete the register write operation; when operating upstream, responds to the read request, obtains the operation result encapsulated as the response data packet in the register and transmits it back to the host computer.

[0051] Specifically, the FPGA unit includes:

[0052] 1) Protocol parsing module, used to parse and split the received UDP protocol data packets into data packets;

[0053] 2) The codec module is used to parse the target register address, operation type, and configuration data of the data packet; output the configuration content to the interface conversion module during downlink operation; respond to read requests during uplink operation, obtain the status information stored in the target register transmitted by the interface conversion module, and encode the data into a standardized UDP data packet according to a specific format;

[0054] 3) Interface conversion module: during downlink operation, it converts the target address and configuration data signals into AXI-lite standard protocol signals and sends the configuration information to the DMA register space of the IP core; during uplink operation, it transmits the DMA register status information back to the codec module.

[0055] In general, the downlink data flow of the present invention is (from the host computer to the FPGA): the host computer sends the UDP data packet to the RGMII interface through the network transmission, and finally passes it to the inside of the FPGA; the uplink data flow is (from the FPGA to the host computer): after the FPGA processing is completed, the data is transmitted back to the host computer through the same network path;

[0056] The internal processing flow of the FPGA is as follows: after the data enters the FPGA, it is first parsed by the Gigabit Ethernet module. At this time, the received network port data packet is processed according to the standard network protocol and the valid data is decomposed into a fixed-width data format of data[63:0]. The codec module further processes the above data:

[0057] In the downlink direction (write operation), the codec module extracts the read / write register address, the data to be written, and related control information (such as the read / write operation type) from the 64-bit UDP data. Subsequently, the interface conversion module converts the configuration address and configuration data signals into AXI-lite standard protocol signals and sends the configuration information to the DMA register space of the IP core.

[0058] In the upstream direction (read operation), when the host computer initiates a read request for the status register, the codec module encodes the read address, data and other information into a 64-bit UDP data packet, and finally completes the framing and sends it to the host computer through the FPGA upload path.

[0059] This invention aims to overcome the limitations of traditional debugging methods by leveraging network transmission characteristics, providing users with a more flexible and convenient means of operation. It utilizes the network port and the AXI-Lite Slave interface of the XDMA IP to perform continuous and rapid configuration and remote configuration of PCIe modules.

[0060] In actual applications, users can use the host computer to package the register configuration contents into UDP protocol packets and transmit them to the FPGA chip over the network. After receiving the data, the FPGA's internal logic will decode the data, extract the corresponding read and write addresses, operation types, and target data, and thus complete the read and write operations on the DMA register area. At the same time, when the FPGA operating status needs to be obtained, the FPGA can also transmit the data in the status register back to the host computer over the network.

[0061] In addition, the present invention also provides a new idea for remote configuration and debugging. In traditional scenarios, when the FPGA board is deployed on a remote device or cannot be directly physically contacted (for example, the device is installed at a higher position or is located in a dangerous area), it is usually difficult for developers to complete DMA configuration or perform troubleshooting. With the help of the network port transmission channel provided by the present invention, the user can establish a connection with the network port of the FPGA through the network interface of the remote host, thereby realizing rapid debugging and register operations of the PCIe module XDMA IP core. This innovative method can not only effectively solve the problem of inconvenient equipment maintenance, but also provide real-time debugging capabilities when errors occur in PCIe data transmission, thereby significantly improving the reliability and maintainability of the system.

[0062] It should be appreciated that embodiments of the present invention can be implemented or practiced by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The methods can be implemented in a computer program using standard programming techniques, including a non-transitory computer-readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner, according to the methods and figures described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. In addition, the program can be run on a programmed application-specific integrated circuit for this purpose.

[0063] Furthermore, the operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The processes described herein (or variations and / or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, or a combination thereof. The computer program includes a plurality of instructions that can be executed by one or more processors.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should all be included in the scope of the claims of the present invention.

Claims

1. A fast configuration method for the XDMA IP of the PCIe module in the FPGA chip based on the network port, characterized by: The method includes a downlink operation and an uplink operation. The downlink operation is to package the configuration content of the register into a UDP protocol data packet through the host computer and transmit it to the FPGA chip through the network; after receiving the data, the internal logic of the FPGA will decode the data and extract the corresponding configuration content, thereby completing the read and write operations on the DMA register area; The uplink operation is when the host computer needs to obtain the operating status of the FPGA chip, and initiates a read request to the status register. The FPGA chip transmits the response result data in the register back to the host computer through the network.

2. The method for quickly configuring the PCIe module XDMA IP in the network port-based FPGA chip according to claim 1, wherein: The specific steps include: Step S1: Generate a command sequence containing register configuration content using a host computer. The configuration content includes the target address, operation type, and configuration data. Encapsulate the command sequence into a UDP protocol data packet and add a sequence number. Send it to the receiving buffer inside the FPGA chip through the network interface. Step S2: After the data enters the FPGA chip, the received UDP protocol data packet is parsed and split into data packets; Step S3: The FPGA's encoding and decoding module further processes the data packet to adapt to specific needs. During downlink operations, it parses the data packet to extract the configuration content in order to complete the register write operation; during uplink operations, it responds to the read request, obtains the operation result encapsulated as a response data packet in the register, and uploads it to the host computer through the FPGA chip.

3. The method for quickly configuring the PCIe module XDMA IP in the network port-based FPGA chip according to claim 2, wherein: In step S3, in the downlink operation, the target address and configuration data signals are converted into AXI-lite standard protocol signals using the interface conversion module, and the configuration information is sent to the DMA register space of the IP core.

4. The method for quickly configuring the PCIe module XDMA IP in the network port-based FPGA chip according to claim 1 or 2, characterized in that: UDP packets are decomposed using a specific format. The labels include head, addr, data, wr_en, enable, reserved, and odd_parity. The meanings of these labels are as follows: head is the fixed frame header 0xAA, addr is the 16-bit DMA reg space configuration address, and data is the 32-bit DMA reg space data. If wr_en is high, it indicates writing to the register through the network port; if it is low, it indicates reading the register. If enable is valid, it indicates that the current read or write request is a valid request, otherwise the FPGA can ignore it and not respond. odd_parity is the odd parity value of the first 63 bits of data, which is used to determine whether there is an error in the data packet.

5. PCIe module XDMA IP fast configuration system in FPGA chip based on network port, characterized by: The system includes The host computer unit is used to encapsulate the DMA register operation instructions into configuration data packets that comply with the UDP protocol; The network transmission unit realizes the downlink transmission of configuration data packets and the uplink transmission of response data packets through the Ethernet physical layer; The FPGA unit parses the configuration data packet to extract the configuration content in order to complete the register write operation during the downlink operation; responds to the read request during the uplink operation, obtains the operation result encapsulated as the response data packet in the register and transmits it back to the host computer.

6. The PCIe module XDMA IP fast configuration system in the FPGA chip based on the network port according to claim 5, characterized in that: The FPGA unit comprises: The protocol parsing module is used to parse and split the received UDP protocol data packets into data packets; The codec module is used to parse the target register address, operation type, and configuration data of the data packet; output the configuration content to the interface conversion module during downlink operation; respond to read requests during uplink operation, obtain the status information stored in the target register transmitted by the interface conversion module, and encode the data into a standardized UDP data packet according to a specific format; The interface conversion module converts the target address and configuration data signals into AXI-lite standard protocol signals during downlink operations and sends the configuration information to the DMA register space of the IP core; during uplink operations, it returns the DMA register status information to the codec module.

7. The PCIe module XDMA IP fast configuration system in a network port-based FPGA chip according to claim 1, 2 or 3, characterized in that: The decomposition of the configuration data packet adopts a specific format. The labels include head, addr, data, wr_en, enable, reserved, and odd_parity. The meaning of each label is as follows: head is the fixed frame header 0xAA, addr is the 16-bit DMA reg space configuration address, and data is the 32-bit DMA reg space data. If wr_en is high, it indicates writing to the register through the network port; if it is low, it indicates reading the register. If enable is valid, it indicates that the current read or write request is a valid request, otherwise the FPGA can ignore it and not respond. odd_parity is the odd parity value of the first 63 bits of data, which is used to determine whether there is an error in the data packet.

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