Storage and calculation integrated processor and processing method based on POSIT format

Abstract

According to the storage and calculation integrated processor based on the POSIT format and the processing method, the calculation complexity during network training can be greatly reduced by utilizing the improved POSIT data format, meanwhile, due to the fact that the characteristic of dynamic bit width is reserved, the numerical value representation range is widened, the neural network training precision is guaranteed, and the processing efficiency is improved. The problems that in the prior art, low-precision training supports multiple floating points or integer data formats, and POSIT data types are not supported are solved. And a large number of optimization means are needed to ensure the precision, so that the technical scheme is complicated, the data format lacks flexibility, and network parameters cannot be effectively represented.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor storage technology, and in particular to a storage and computing integrated processor and a processing method based on the POSIT format. Background Art

[0002] Traditional processors, due to their von Neumann architecture, which separates computation and storage, frequently move large amounts of data during network training, significantly increasing energy consumption and making it difficult to strike a good balance between high throughput and low power consumption. Consequently, integrated computing and storage technology has emerged. This technology embeds computational functions directly into the storage unit, effectively reducing data movement and improving computing efficiency, becoming a key development direction for new AI chip architectures.

[0003] Low-precision training provides a solution for mobile and edge computing scenarios. It uses FP8 or even INT8 data formats for network training, significantly reducing computational complexity and memory bandwidth requirements. However, it requires relevant optimization measures to ensure network training accuracy.

[0004] IEEE 754 standard floating-point calculations play a crucial role in current network training. Large-bit-width floating-point formats meet the high-precision requirements of network training. The POSIT data format, with its dynamic regime, offers more flexible numerical representation and can represent a wider range of data. However, the uncertainty of its mantissa bit width makes it unsuitable for accelerated computations within a storage-computing architecture.

[0005] Therefore, the present invention proposes an improved POSIT data format, which truncates its mantissa, so that it is suitable for computing acceleration in a storage-computing integrated architecture and can be applied to low-precision network training. Summary of the Invention

[0006] Based on the technical problems existing in the above background technology, the present invention proposes a storage and computing integrated processor and processing method based on the POSIT format, and the technical solutions adopted include: A processing method based on the POSIT format, the method comprising: S1: Encode the neural network parameters according to the standard POSIT data format and divide them according to the benchmark data block size; S2: Calculate the dynamic discreteness of the mantissa of the neural network parameters in each benchmark block and dynamically adjust the data block size; S3: Based on the readjusted data block, extract the maximum exponent as the shared exponent, align the exponents of the remainders to the shared exponent, shift the mantissa accordingly, and truncate the shifted mantissa: fill the low bits with 0 when the bit width is less than 6 bits, and retain the high 6 bits when the bit width is ≥ 6 bits, thereby generating improved POSIT data; S4: Store the improved POSIT data into the storage module; S5: Get activation data, convert it into improved POSIT data using steps S1-S3, and perform multiplication and accumulation operations through the storage array; S6: Encode the multiplication and accumulation result into the standard POSIT format and output it.

[0007] Preferably, the S1 is divided according to the size of the reference data block, including: When the dynamic discreteness of several consecutive reference data blocks is greater than the high discreteness super-block triggering threshold, the several reference data blocks are merged into a super-block, and the super-block is the minimum reference data block.

[0008] Preferably, the S2 dynamically adjusts the data block size, specifically including: If the dynamic discreteness is larger, which means that the mantissa of the neural network parameters in each benchmark block is more dispersed, the data block size should be reduced; If the dynamic discreteness is smaller, it means that the mantissas of the neural network parameters in each benchmark block are more concentrated, so the data block size is increased.

[0009] Preferably, the dynamic discreteness is obtained by: Get the variance and mean of the absolute value of the mantissa of the neural network parameters; Get the logarithm of the number of neural network parameters in each data block; The dynamic dispersion is proportional to the variance and inversely proportional to the mean and the logarithm of the number of neural network parameters.

[0010] Preferably, extracting the maximum index as the shared index in S3 specifically includes: Traverse the Regime domain and exponent domain of all neural network parameters in each adjusted data block and calculate the actual exponent value of each neural network parameter; The largest actual index value is selected as the shared index of the single adjusted data block.

[0011] Preferably, the exponents of the remainder of S3 are aligned to the shared exponent and the mantissa is shifted accordingly, specifically including: For each neural network parameter, calculate the difference between the actual exponent and the shared exponent ; like When it is less than 0, the mantissa of the neural network parameter is shifted right Bit; like When it is greater than 0, the mantissa of the neural network parameter is shifted left Bit; If the mantissa exceeds the 6-bit width after shifting, rounding and overflow saturation are adopted.

[0012] Preferably, the step S5 of performing the multiplication and accumulation operation by using the storage and calculation array specifically includes: The storage array performs parallel multiplication operations on the activation data and weight parameters of the improved POSIT data based on two's complement representation, where: Each computation unit uses bit-level multiplication logic, and activation data is entered into the memory array in a bit-serial manner. The entire memory array performs in-situ multiplication operations synchronously. The results of the in-place multiplication are added stage by stage through the adder tree to obtain the intermediate result of the 6-bit mantissa multiplication; The intermediate results are accumulated in fixed-point form, and the accumulated results are finally output.

[0013] Preferably, the S6 includes: Based on the shared exponent and the mantissa of the neural network parameters corresponding to the accumulated results, the standard POSIT data, Regime domain and exponent domain are reconstructed.

[0014] Preferably, the reconstructed standard POSIT data, Regime domain and index domain specifically include: The Regime field is determined by the numerical range of the sharing index: if the sharing index is positive, the Regime field ends with consecutive 0s; if it is negative, the Regime field ends with consecutive 1s, and the length is determined by the absolute value of the sharing index; The value of the Exponent field is the shared exponent minus the offset corresponding to the Regime field; The mantissa of the standard POSIT data directly uses the high-significant bit of the mantissa of the accumulation result, and fills the insufficient part with 0.

[0015] A storage-computing integrated processor based on the POSIT format, characterized in that the storage-computing integrated processor includes: Parameter encoding and initial block division unit: Encode the neural network parameters according to the standard POSIT data format and divide them according to the benchmark data block size; Dynamic discreteness calculation and block size adjustment unit: calculates the dynamic discreteness of the mantissa of the neural network parameters in each benchmark block and dynamically adjusts the data block size; Exponent alignment and mantissa truncation unit: Based on the readjusted data block, the maximum exponent is extracted as the shared exponent, the exponents of the remainders are aligned to the shared exponent and the mantissa is shifted accordingly, and the shifted mantissa is truncated: when the bit width is less than 6 bits, the low bits are padded with 0, and when the bit width is ≥ 6 bits, the high 6 bits are retained: to generate improved POSIT data; Storage and computing integrated storage unit: stores the improved POSIT data in the storage and computing integrated storage module; Activation data processing and multiplication and accumulation unit: obtain activation data, convert it into improved POSIT data using steps S1-S3, and perform multiplication and accumulation operations through the storage array; Standard format reconstruction unit: encodes the multiplication and accumulation results into standard POSIT format output.

[0016] The present invention has the beneficial effects of significantly reducing the computational complexity of network training by utilizing the improved POSIT data format, and simultaneously increasing the range of numerical representation and ensuring the accuracy of neural network training due to its retention of the dynamic bit width characteristic.

[0017] The storage and computation circuit based on the improved POSIT data format can store weight information in this format and accelerate multiplication and accumulation in this format, significantly reducing computing power consumption, further improving the energy efficiency of low-precision neural network training, and significantly reducing training costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The improved POSIT data of the present invention; Figure 2 The storage and computing integrated processor of the present invention; Figure 3 This is the calculation process of encoding the multiplication and accumulation result into a standard POSIT format output as described in the present invention. DETAILED DESCRIPTION

[0019] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0020] One embodiment of the present invention provides a processing method based on the POSIT format, the method comprising: S1: Encode the neural network parameters according to the standard POSIT data format and divide them according to the size of the benchmark data block; the size of the benchmark data block is ; S2: Calculate the dynamic discreteness of the mantissa of the neural network parameters in each benchmark block and dynamically adjust the data block size; S3: Based on the readjusted data block, extract the maximum exponent as the shared exponent, align the exponents of the remainders to the shared exponent, shift the mantissa accordingly, and truncate the shifted mantissa: fill the low bits with 0 when the bit width is less than 6 bits, and retain the high 6 bits when the bit width is ≥ 6 bits, thereby generating improved POSIT data; S4: Store the improved POSIT data into the storage module; S5: Get activation data, convert it into improved POSIT data using steps S1-S3, and perform multiplication and accumulation operations through the storage array; S6: Encode the multiplication and accumulation result into the standard POSIT format and output it.

[0021] The working principle and effect of the above technical solution are as follows: first, the neural network parameters are encoded in the standard POSIT format and divided into reference data blocks. The data block size is dynamically adjusted by calculating the dynamic discreteness of the parameter mantissas within the block, so that the block size adapts to the parameter distribution characteristics; then, the maximum exponent is extracted from the adjusted data block as the shared exponent, the exponents of other parameters are aligned to the shared exponent and the mantissas are shifted accordingly, and the mantissas are truncated or padded with zeros to 6 bits to generate improved POSIT data to balance accuracy and efficiency; then, the improved data is stored in the integrated storage and computation module, and after performing the same conversion process on the activation data, the parallel multipliers of the storage and computation array are used to perform low-precision multiplication and accumulation operations on the activation data and the weight parameters; finally, the operation results are encoded back to the standard POSIT format for output by reconstructing the Regime field, exponent field and mantissa bits, realizing low-precision optimization of the entire process from parameter storage and computation to result output; This method improves the adaptability of parameter partitioning to data distribution by dynamically adjusting the data block size, avoiding the loss of precision or inefficiency caused by fixed block size; by extracting the maximum exponent as the shared exponent and uniformly aligning the mantissa, it improves the precision retention ability under low-precision representation and avoids truncation errors caused by excessive exponent differences; by using storage and computing arrays to perform multiplication and accumulation operations in parallel, it improves the throughput and energy efficiency of neural network calculations and avoids the energy consumption and delay of data movement in traditional architectures; finally, the results are encoded into standard POSIT format for output, which improves compatibility with downstream systems and avoids the additional conversion overhead caused by inconsistent formats. Overall, while ensuring the accuracy of neural network calculations, it improves the processing efficiency and resource utilization under the storage and computing integrated architecture.

[0022] In one embodiment of the present invention, the S1 is divided according to the size of the reference data block, including: When the dynamic discreteness of several consecutive reference data blocks is greater than the high discreteness super-block triggering threshold, the several reference data blocks are merged into a super-block, and the super-block is the minimum reference data block.

[0023] The working principle and effect of the above technical solution are as follows: when dividing parameters by reference data block size, the dynamic dispersion of adjacent reference data blocks is continuously monitored. When the dynamic dispersion of three consecutive reference data blocks exceeds the high-dispersion super-block trigger threshold, indicating that the mantissa distribution of the parameters within these blocks is highly dispersed, they are merged into a larger super-block. At the same time, to ensure flexibility and accuracy of processing within the super-block, each sub-unit within the super-block is still set to the minimum reference data block size. By merging continuous high-dynamic discreteness benchmark data blocks into super-blocks, the data block management efficiency in high-discrete areas is improved, and the frequent addressing and control overhead caused by a large number of small benchmark blocks is avoided; at the same time, the minimum benchmark data block is retained as the processing unit in the super-block, which improves the local precision control capability and avoids the precision loss caused by the super-block being too large. While ensuring the high discrete parameter processing accuracy, the number of blocks and management complexity are reduced.

[0024] In one embodiment of the present invention, the S2 dynamically adjusts the data block size, specifically including: If the dynamic discreteness is larger, which means that the mantissa of the neural network parameters in each benchmark block is more dispersed, the data block size should be reduced; If the dynamic discreteness is smaller, it means that the mantissas of the neural network parameters in each benchmark block are more concentrated, so the data block size is increased, and the S2 dynamically adjusts the data block size by the following formula: in, Indicates the preset minimum data block size ( =8); Indicates the preset maximum data block size ( =64), Represents the dynamic discreteness weight coefficient, convolutional layer α=1.0, fully connected layer α=0.6, represents the variance weight coefficient, β=0.5 for the convolutional layer and β=0.3 for the fully connected layer; D represents the dynamic discreteness; is the variance of the parameter mantissa within the data block; The working principle and effect of the above technical solution are as follows: In the calculation formula for adjusting the size of the data block, Construct a nonlinear mapping so that the block size responds to the parameter variance with a "slow in, steep out" characteristic. Nonlinear response is more consistent with the physical characteristics of the storage-computing architecture than linear scaling. That is, when the parameter fluctuations are large, the precision loss caused by exponential sharing increases exponentially, and the block size needs to be quickly reduced through a nonlinear mechanism. The calculation result is rounded, which naturally matches the physical structure of the storage array. The storage units are usually organized in powers of 2 (8 / 16 / 32 / 64, etc.), and the discrete block size avoids the padding overhead during hardware alignment. As a volatility indicator, it directly reflects the physical characteristics of the parameter distribution: High variance areas require smaller blocks to reduce exponential sharing errors Low variance regions allow for larger blocks to increase computational parallelism Traditional methods usually use fixed block size and cannot adapt to changes in parameter distribution; the response of segmented adjustment based on threshold is discontinuous and has boundary effects; the global statistical characteristics are adjusted, ignoring local fluctuation characteristics; This formula achieves the coupling of the physical characteristics of parameter distribution and the storage-computing integrated architecture through continuous mapping of variance, nonlinear response and hardware-friendly discretization.

[0025] In one embodiment of the present invention, the dynamic discreteness is obtained by: Get the variance and mean of the absolute value of the mantissa of the neural network parameters; Get the logarithm of the number of neural network parameters in each data block; The dynamic discreteness is proportional to the variance and inversely proportional to the mean and the logarithm of the number of neural network parameters, and the dynamic discreteness is obtained by the following formula: in, The variance of the absolute value of the mantissa representing the neural network parameters, represents the mean of the absolute values ​​of the mantissas of the neural network parameters, Indicates the number of neural network parameters in each data block; The working principle and effect of the above technical solution are as follows: In the calculation formula of the above dynamic discreteness D, and The product relationship forms a nonlinear response, which makes the D value show differential sensitivity to data with different distribution patterns: High discrete data: σ² / μ² increases significantly, D rises rapidly, and the trigger block size shrinks sharply Low-discretion data: σ² / μ² is close to 1, D is dominated by log(N), and the block size is smoothly adjusted Matching nonlinear response characteristics with the physical constraints of a storage-computing architecture Traditional data segmentation methods usually use: fixed block size: cannot adapt to changes in parameter distribution Threshold-based heuristic adjustment: Ignoring the intrinsic distribution characteristics of data Global statistical characteristics adjustment: Ignore local fluctuation characteristics This formula, through the combined design of relative discreteness + block size compensation + nonlinear response, achieves the following: automatic adaptation to the parameter characteristics of different layers and regions, low computational complexity, adaptation to the integrated storage and computing architecture, and maximum accuracy with minimal computational overhead.

[0026] In one embodiment of the present invention, extracting the maximum index as the shared index in S3 specifically includes: Traverse the Regime domain and exponent domain of all neural network parameters in each adjusted data block and calculate the actual exponent value of each neural network parameter; The largest actual index value is selected as the shared index of the single adjusted data block.

[0027] For the i-th parameter in the data block, the actual index Where s represents the sign bit of the Regime field (0 or 1), and r represents the number of consecutive sign bits in the Regime field. Represents the 2-bit binary value of the exponent field (range 0 to 3); The working principle and effect of the above technical solution are as follows: for each neural network parameter in the adjusted data block, the Regime field and Exponent field in its POSIT format are first parsed. The sign bit of the Regime field is used to determine the positive or negative exponent. The contribution of the field to the exponent is calculated by combining the number of consecutive sign bits. The binary value of the Exponent field is then added to obtain the actual exponent value of each parameter. Finally, the largest actual exponent value of all parameters is selected and used as the shared exponent of the current data block, thereby ensuring that the exponents of all parameters in the block are aligned with this largest exponent. By unifying the exponent base within a data block and aligning the exponents of all parameters within the block toward the maximum exponent, the magnitude of mantissa shifts caused by large exponent differences can be reduced, minimizing precision loss when the mantissa is truncated or padded with zeros. The unified shared exponent simplifies the exponent processing logic for multiplication and accumulation operations in the storage array, avoiding complex conversions between different exponents and improving computational efficiency. Using the maximum exponent as a shared base ensures that all parameters will not experience mantissa overflow due to insufficient exponents during the alignment process, thereby improving the integrity of data representation in low-precision (6-bit mantissa) scenarios.

[0028] In one embodiment of the present invention, the exponent of the remainder of S3 is aligned to the shared exponent and the mantissa is shifted accordingly, specifically including: For each neural network parameter, calculate the difference between the actual exponent and the shared exponent ; like When it is less than 0, the mantissa of the neural network parameter is shifted right Bit; like When it is greater than 0, the mantissa of the neural network parameter is shifted left Bit; If the mantissa exceeds the 6-bit width after shifting, rounding and overflow saturation are adopted.

[0029] The working principle and effect of the above technical solution are as follows: for each neural network parameter in the data block, the difference between its actual exponent and the shared exponent is first calculated. If the difference is less than 0, it means that the numerical magnitude represented by the original exponent of the parameter is smaller, and its mantissa needs to be shifted right to increase the exponent. The low bit generated by the right shift is discarded and the more accurate high bit may be retained by rounding; if the difference is greater than 0, it means that the numerical magnitude represented by the original exponent of the parameter is larger, and its mantissa needs to be shifted left to reduce the exponent. The left shift may cause the mantissa to exceed the 6-bit width. At this time, the excess part is truncated and overflow saturation processing is triggered. The overflow saturation processing means that when the mantissa exceeds the 6-bit width after shifting, the truncated low bit is judged. If the highest bit of the truncated part is 1, 1 is added to the lowest bit of the retained 6-bit mantissa. If it is 0, it is directly discarded. For example: the mantissa of a parameter is 7 bits 1011001 after shifting, and the lowest bit of the truncation is 1, so after rounding, 6 The bit mantissa is 101101. Overflow saturation processing means that when the mantissa is shifted left and the value exceeds the maximum range that can be represented by 6 bits, the mantissa is no longer carried. Instead, the mantissa is fixed to the 6-bit maximum value of 111111 to avoid incorrect numerical representation due to overflow. For example, the mantissa of a parameter is 111111. Because the exponent difference needs to be shifted left by 2 bits, the bit width is exceeded after the shift, triggering saturation processing, and the final mantissa remains 111111.

[0030] This solution can not only balance the accuracy and bit width limitations, but also improve the stability of numerical representation, providing a data foundation with unified format and controllable accuracy for efficient multiplication and accumulation operations in subsequent storage and computing arrays to adapt to computing needs in low-precision scenarios.

[0031] In one embodiment of the present invention, the step S5 of performing a multiplication-accumulation operation by using a storage-calculation array specifically includes: The storage array performs parallel multiplication operations on the activation data and weight parameters of the improved POSIT data based on two's complement representation, where: Each computation unit uses bit-level multiplication logic, and activation data is entered into the memory array in a bit-serial manner. The entire memory array performs in-situ multiplication operations synchronously. The results of the in-place multiplication are added stage by stage through the adder tree to obtain the intermediate result of the 6-bit mantissa multiplication; The intermediate results are accumulated in fixed-point form, and the accumulated results are finally output.

[0032] The working principle and effect of the above technical solution are as follows: the storage and calculation array uses two's complement representation to process activation data and weight parameters in the improved POSIT format. Each calculation unit operates through bit-level multiplication logic. After the activation data is input into the storage and calculation array in a bit-serial manner, the entire array synchronously performs in-situ multiplication operations on the activation data and weight parameters. The bit-level results generated by the in-situ multiplication are aggregated and added level by level through the adder tree to obtain the intermediate results of the 6-bit mantissa multiplication. These intermediate results are then accumulated according to the fixed-point number representation rules, and the accumulated result is finally output. The use of bit-level multiplication logic and bit-serial input improves the data throughput efficiency of the storage and computing array and avoids the waste of line resources during parallel input; the in-situ multiplication operation allows data to be directly calculated in the storage unit, which improves the data processing speed and avoids the energy consumption and delay of frequent data transfer between the storage and computing units; the adder tree summarizes the results level by level, improves the integration efficiency of intermediate results and avoids the time overhead of serial accumulation; the final accumulation in the form of fixed-point numbers ensures the accuracy of the results, while improving the parallelism and energy efficiency of multiplication and accumulation operations, ensuring the accuracy of neural network calculations, and adapting to the requirements of the integrated storage and computing architecture for efficient and low-power computing.

[0033] In one embodiment of the present invention, the reconstructed standard POSIT data, Regime domain, and index domain specifically include: The Regime field is determined by the numerical range of the sharing index: if the sharing index is positive, the Regime field ends with consecutive 0s; if it is negative, the Regime field ends with consecutive 1s, and the length is determined by the absolute value of the sharing index; The value of the Exponent field is the shared exponent minus the offset corresponding to the Regime field; The mantissa of the standard POSIT data directly uses the high-significant bit of the mantissa of the accumulation result, and fills the insufficient part with 0.

[0034] The working principle and effect of the above technical solution are as follows: when reconstructing standard POSIT data, the ending characteristics of the Regime field are first determined based on the positive or negative sign of the shared exponent. When the shared exponent is positive, the Regime field ends with consecutive 0s, and when it is negative, it ends with consecutive 1s. At the same time, the length of the Regime field is determined based on the absolute value of the shared exponent. The value of the exponent field is then obtained by subtracting the offset corresponding to the Regime field from the shared exponent. Finally, the high-significant bits of the mantissa of the multiplication and accumulation result are used as the mantissa bits of the standard POSIT data. If the mantissa length is insufficient, the low-significant bits are padded with 0s. In this way, through the coordinated reconstruction of the Regime field, exponent field, and mantissa bits, the low-precision accumulation result is converted back to the standard POSIT format. The accuracy of standard POSIT format reconstruction is improved, and fine-tuning is achieved through dynamic adaptation of the shared exponent range and exponent domain in the Regime domain, avoiding the range limitations of the exponent represented by a single domain. The efficiency of retaining result accuracy is improved, and the mantissa bits are accumulated with the high-significant bits of the result and padded with 0s, avoiding information loss during format conversion. The efficiency of hardware implementation is improved, and the mapping logic from the improved format to the standard format is simplified, avoiding the energy consumption and complexity increase caused by complex conversion.

[0035] One embodiment of the present invention provides a storage-computing integrated processor based on the POSIT format, characterized in that the storage-computing integrated processor includes: Parameter encoding and initial block division unit: Encode the neural network parameters according to the standard POSIT data format and divide them according to the benchmark data block size; Dynamic discreteness calculation and block size adjustment unit: calculates the dynamic discreteness of the mantissa of the neural network parameters in each benchmark block and dynamically adjusts the data block size; Exponent alignment and mantissa truncation unit: Based on the readjusted data block, the maximum exponent is extracted as the shared exponent, the exponents of the remainders are aligned to the shared exponent and the mantissa is shifted accordingly, and the shifted mantissa is truncated: when the bit width is less than 6 bits, the low bits are padded with 0, and when the bit width is ≥ 6 bits, the high 6 bits are retained: to generate improved POSIT data; Storage and computing integrated storage unit: stores the improved POSIT data in the storage and computing integrated storage module; Activation data processing and multiplication and accumulation unit: obtain activation data, convert it into improved POSIT data using steps S1-S3, and perform multiplication and accumulation operations through the storage array; Standard format reconstruction unit: encodes the multiplication and accumulation results into standard POSIT format output.

[0036] The working principle and effects of the above technical solution are: Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A processing method based on the POSIT format, characterized in that: The method comprises: S1: Encode the neural network parameters according to the standard POSIT data format and divide them according to the benchmark data block size; S2: Calculate the dynamic discreteness of the mantissa of the neural network parameters in each benchmark block and dynamically adjust the data block size; S3: Based on the readjusted data block, extract the maximum exponent as the shared exponent, align the exponents of the remainders to the shared exponent, shift the mantissa accordingly, and truncate the shifted mantissa: fill the low bits with 0 when the bit width is less than 6 bits, and retain the high 6 bits when the bit width is ≥ 6 bits, thereby generating improved POSIT data; S4: Store the improved POSIT data into the storage module; S5: Get activation data, convert it into improved POSIT data using steps S1-S3, and perform multiplication and accumulation operations through the storage array; S6: Encode the multiplication and accumulation result into the standard POSIT format and output it.

2. A processing method based on POSIT format according to claim 1, characterized in that: The S1 is divided according to the size of the benchmark data block, including: When the dynamic discreteness of several consecutive reference data blocks is greater than the high discreteness super-block triggering threshold, the several reference data blocks are merged into a super-block, and the super-block is the minimum reference data block.

3. A processing method based on POSIT format according to claim 1, characterized in that: The S2 dynamically adjusts the data block size, specifically including: If the dynamic discreteness is larger, which means that the mantissa of the neural network parameters in each benchmark block is more dispersed, the data block size should be reduced; If the dynamic discreteness is smaller, it means that the mantissas of the neural network parameters in each benchmark block are more concentrated, so the data block size is increased.

4. A processing method based on POSIT format according to claim 2, characterized in that: The dynamic discreteness is obtained by: Get the variance and mean of the absolute value of the mantissa of the neural network parameters; Get the logarithm of the number of neural network parameters in each data block; The dynamic dispersion is proportional to the variance and inversely proportional to the mean and the logarithm of the number of neural network parameters.

5. The processing method based on the POSIT format according to claim 1, characterized in that: Extracting the maximum index as the shared index in S3 specifically includes: Traverse the Regime domain and exponent domain of all neural network parameters in each adjusted data block and calculate the actual exponent value of each neural network parameter; The largest actual index value is selected as the shared index of the single adjusted data block.

6. The processing method based on the POSIT format according to claim 1, characterized in that: The exponent of the remainder of S3 is aligned to the shared exponent and the mantissa is shifted accordingly, specifically including: For each neural network parameter, calculate the difference between the actual exponent and the shared exponent ; like When it is less than 0, the mantissa of the neural network parameter is shifted right Bit; like When it is greater than 0, the mantissa of the neural network parameter is shifted left Bit; If the mantissa exceeds the 6-bit width after shifting, rounding and overflow saturation are adopted.

7. The processing method based on the POSIT format according to claim 1, characterized in that: The step S5 performs a multiplication and accumulation operation through the storage and calculation array, specifically including: The storage array performs parallel multiplication operations on the activation data and weight parameters of the improved POSIT data based on two's complement representation, where: Each computation unit uses bit-level multiplication logic, and activation data is entered into the memory array in a bit-serial manner. The entire memory array performs in-situ multiplication operations synchronously. The results of the in-place multiplication are added stage by stage through the adder tree to obtain the intermediate result of the 6-bit mantissa multiplication; The intermediate results are accumulated in fixed-point form, and the accumulated results are finally output.

8. The processing method based on the POSIT format according to claim 1, characterized in that: The S6 includes: Based on the shared exponent and the mantissa of the neural network parameters corresponding to the accumulated results, the standard POSIT data, Regime domain and exponent domain are reconstructed.

9. The processing method based on the POSIT format according to claim 8, characterized in that: The reconstructed standard POSIT data, Regime domain and index domain specifically include: The Regime field is determined by the numerical range of the sharing index: if the sharing index is positive, the Regime field ends with consecutive 0s; if it is negative, the Regime field ends with consecutive 1s, and the length is determined by the absolute value of the sharing index; The value of the Exponent field is the shared exponent minus the offset corresponding to the Regime field; The mantissa of the standard POSIT data directly uses the high-significant bit of the mantissa of the accumulation result, and fills the insufficient part with 0.

10. A storage and computing integrated processor based on the POSIT format, characterized in that: The storage and computing integrated processor includes: Parameter encoding and initial block division unit: Encode the neural network parameters according to the standard POSIT data format and divide them according to the benchmark data block size; Dynamic discreteness calculation and block size adjustment unit: calculates the dynamic discreteness of the mantissa of the neural network parameters in each benchmark block and dynamically adjusts the data block size; Exponent alignment and mantissa truncation unit: Based on the readjusted data block, the maximum exponent is extracted as the shared exponent, the exponents of the remainders are aligned to the shared exponent and the mantissa is shifted accordingly, and the shifted mantissa is truncated: when the bit width is less than 6 bits, the low bits are padded with 0, and when the bit width is ≥ 6 bits, the high 6 bits are retained: to generate improved POSIT data; Storage and computing integrated storage unit: stores the improved POSIT data in the storage and computing integrated storage module; Activation data processing and multiplication and accumulation unit: obtain activation data, convert it into improved POSIT data using steps S1-S3, and perform multiplication and accumulation operations through the storage array; Standard format reconstruction unit: encodes the multiplication and accumulation results into standard POSIT format output.

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