Automatic verification method and device for chip function security design, equipment and medium

Abstract

The invention discloses an automatic verification method and device for chip function safety design, equipment and a medium, and relates to the technical field of chip design, the method comprises the following steps: reading a misplugging simulation demand table to obtain a simulation test case, running the simulation test case, generating excitation required by FIT simulation, and eliminating an abnormal simulation test case based on the running condition of the simulation test case; detecting an FIT simulation environment file, generating an FIT simulation verification environment, formulating an FIT simulation process and matching required excitation according to an FIT simulation type; fIT simulation is executed, and an FIT simulation result report is generated based on an FIT simulation result or the FIT simulation process is adjusted to execute FIT simulation again. According to the method and the device, the standard, quantifiable, statistical and efficient positioning error insertion simulation process is formulated, so that the manual workload can be effectively reduced, the working efficiency is improved, and errors are avoided.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and specifically to a method, device, equipment and medium for automated verification of chip functional safety design. Background Art

[0002] FIT (fault injection) simulations for each IP (intellectual property) require manual setup of a FUSA (Function Safety) verification environment. Tool commands are then used to run the verification environment and generate a diagnostic yield report. Each IP is individually matched to the multiple stimuli required for simulation, generating an EVCD file (a file format used to record signal changes in digital circuit simulations).

[0003] The stimulus generation file (evcd) is generated during functional simulation and manually ported to the FUSA testbench (a verification tool) before it can be used. Each IP also maintains a separate adaptation observation environment file (strobe.sv). This file is used by the FIT simulation tool to analyze the coverage of the functional safety logic. When a waveform dump (download and store simulation results) is required, each IP maintains a waveform generation script (Dump.sh), along with a list of error information, observation information, and diagnostic information required for FIT simulation.

[0004] The existing simulation methods have the following problems: (1) When performing FIT simulation, each IP needs to be manually written and the FUSA verification environment needs to be debugged. The tool commands need to be manually run to complete the FIT simulation and obtain the results. The results need to be manually judged. When the number of IPs is large, human resources are consumed a lot and the verification efficiency is low. (2) When the list of mis-insertion information, observation information, and diagnostic information required for FIT simulation of each IP is very large, it is easy to miss a set of mis-insertion information, observation information, and diagnostic information when manually using each set of mis-insertion information, observation information, and diagnostic information for FIT simulation; (3) A large amount of manual work easily leads to differences in the execution of the FIT simulation verification process, the workload is difficult to quantify, and the simulation process cannot be managed in a refined manner; (4) It is necessary to manually modify the FIT simulation verification environment and verification process according to the different functional safety designs of large-scale SOC (System On Chip). Summary of the Invention

[0005] The present application provides a chip functional safety design automated verification method, device, equipment and medium. By formulating a standardized, quantifiable, statistical and efficient mis-insertion simulation process, it can effectively reduce manual workload, improve work efficiency and avoid errors.

[0006] In a first aspect, an embodiment of the present application provides a chip functional safety design automation verification method, the chip functional safety design automation verification method comprising: Read the mis-insertion simulation requirement table to obtain simulation test cases and run them to generate the stimulus required for FIT simulation, and eliminate abnormal simulation test cases based on the running status of the simulation test cases; Detect FIT simulation environment files, generate FIT simulation verification environment, formulate FIT simulation process, and match required stimulus according to FIT simulation type; Perform a FIT simulation, generate a FIT simulation result report based on the FIT simulation results, or adjust the FIT simulation process and perform the FIT simulation again.

[0007] In conjunction with the first aspect, in one embodiment, reading the mis-insertion simulation requirement table to obtain simulation test cases and running them to generate the stimulus required for the FIT simulation specifically includes: Read the mis-insertion simulation requirement table through fit_regression and identify the information of each member in the mis-insertion simulation requirement table; Function regression automatically matches and runs simulation test cases based on the simulation stimulus information in the inserted simulation requirement table, and generates the stimulus required for FIT simulation during the simulation test case operation.

[0008] In conjunction with the first aspect, in one embodiment, eliminating abnormal simulation test cases based on the running status of the simulation test cases specifically includes: Sitimulus check checks the running status of each simulation test case. If there is an abnormality in the current simulation test case, a report will be issued and the current simulation test case will be removed from the FIT simulation. Otherwise, the current simulation test case will be retained.

[0009] In conjunction with the first aspect, in one embodiment, performing the FIT simulation, generating a FIT simulation result report based on the FIT simulation result, or adjusting the FIT simulation process and performing the FIT simulation again specifically includes: Perform FIT simulation. According to the FIT simulation results: If the FIT simulation results meet the preset simulation requirements, a FIT simulation result report is generated and published; If the FIT simulation result does not meet the preset simulation requirements, adjust the FIT simulation process and then perform the FIT simulation again.

[0010] In conjunction with the first aspect, in one embodiment, adjusting the FIT simulation process specifically includes: Based on the FIT simulation results, analyze whether the developed FIT simulation process is correct: If not, adjust the FIT simulation process; If yes, analyze whether the FIT simulation verification environment is configured correctly: -If it is incorrect, regenerate the FIT simulation verification environment; -If correct, analyze whether the excitation required for FIT simulation is sufficient. If not, continue to generate the excitation required for FIT simulation. If sufficient, adjust the mis-insertion simulation requirements in the mis-insertion simulation requirement table.

[0011] In conjunction with the first aspect, in one embodiment, When executing FIT simulation according to the established FIT simulation process, isolation technology is used to perform stimulus isolation, top-level qualification of simulation objects, and compilation isolation operations to adapt FIT simulation to the IP level, subsystem level, and SOC level.

[0012] In conjunction with the first aspect, in one embodiment, The stimulus isolation includes configuring the stimulus collection interface level compilation information to isolate the interface stimulus collection, configuring the level of the Dump stimulus file to isolate the high-level interface stimulus, and ensuring that the stimulus file is named uniquely without duplication; The compilation isolation includes defining a compilation module to set a compilation command to specify compilation options, specifying compilation tools and environment variables, and compiling macros to compile top-level specifications; The top-level definition of the simulation object includes specifying the interface information of the top level and setting the monitoring interface of the observation point and the diagnosis point.

[0013] In a second aspect, an embodiment of the present application provides a chip functional safety design automation verification device, the chip functional safety design automation verification device comprising: A reading module is used to read the mis-insertion simulation requirement table to obtain simulation test cases and run them, generate the stimulus required for FIT simulation, and eliminate abnormal simulation test cases based on the running status of the simulation test cases; The generation module is used to detect the FIT simulation environment file, generate the FIT simulation verification environment, formulate the FIT simulation process, and match the required stimulus according to the FIT simulation type; The execution module is used to execute FIT simulation, generate a FIT simulation result report based on the FIT simulation result, or adjust the FIT simulation process to execute FIT simulation again.

[0014] In a third aspect, an embodiment of the present application provides a chip functional safety design automation verification device, which includes a processor, a memory, and a chip functional safety design automation verification program stored on the memory and executable by the processor, wherein when the chip functional safety design automation verification program is executed by the processor, the steps of the above-mentioned chip functional safety design automation verification method are implemented.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a chip functional safety design automation verification program is stored. When the chip functional safety design automation verification program is executed by a processor, the steps of the above-mentioned chip functional safety design automation verification method are implemented.

[0016] The beneficial effects of the technical solutions provided in the embodiments of the present application include: (1) By formulating a standardized, quantifiable, statistical, and efficient insertion error simulation process, we can effectively reduce manual workload, improve work efficiency, and avoid errors; (2) This application can solve the problems of difficult maintenance of FIT verification environments at different levels and high independent development costs in large-scale SOC projects by providing a plug-in error simulation process architecture that can adapt to IP level, subsystem level, and SOC level at the same time; (3) This application is designed to automatically generate a verification environment and operation-related instructions for mis-insertion simulation, and can standardize the statistics and publish the mis-insertion simulation results, so as to provide timely and comprehensive feedback on the operation results, reduce the labor cost of collecting results, and reduce the possibility of making mistakes in the process of collecting results. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flowchart of the automated verification method for chip functional safety design in this application; Figure 2 Adapt isolation diagrams for all levels of FIT; Figure 3 Schematic diagram of the functional modules of the automated verification device for chip functional safety design in this application; Figure 4 Schematic diagram of the hardware structure of the chip functional safety design automation verification equipment for this application. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0020] On the first aspect, the embodiment of the present application provides a chip functional safety design automation verification method. In combination with practical applications, by formulating a standardized, quantifiable, statistical, and efficiently located mis-insertion simulation process, the problem of process execution differences during the FIT simulation process is reduced. The present application provides an mis-insertion simulation process architecture that can be adapted to the IP level, subsystem level, and SOC level at the same time, unifies the construction of FIT simulation environments at various levels, and designs a verification environment that can automatically generate mis-insertion simulations and run-related instructions, and can perform standardized statistics and publish mis-insertion simulation results.

[0021] In one embodiment, referring to Figure 1 , Figure 1 This is a flow chart of the automated verification method for chip functional safety design in this application. Figure 1 As shown in the figure, the chip functional safety design automation verification method includes: S1: Read the mis-insertion simulation requirement table to obtain simulation test cases and run them to generate the stimulus required for FIT simulation, and eliminate abnormal simulation test cases based on the running status of the simulation test cases; S2: Detect the FIT simulation environment file, generate the FIT simulation verification environment, formulate the FIT simulation process, and match the required stimulus according to the FIT simulation type; S3: Execute FIT simulation, generate a FIT simulation result report based on the FIT simulation result, or adjust the FIT simulation process and execute FIT simulation again.

[0022] Specifically, in practical applications, the "fit_regression" command is used as the entry point to first read the fault injection simulation requirements table and then complete the above process by identifying the members in the simulation requirements table. This identification includes setting macro definitions, a list of simulated files, prefix information for the generated directory structure, subsystem path information, suffix information for the generated directory structure, a list of stimulus names, simulation command options for stimulus generation, and the name of the automated script for stimulus file download. The program or device is launched by running the "fitregression" command, where "fit_regression" represents fault injection batch regression.

[0023] Furthermore, in one embodiment, the insertion error simulation requirement table is read to obtain simulation test cases and run them to generate the stimulus required for the FIT simulation, specifically including: S101: read the mis-insertion simulation requirement table through fit_regression, and identify the information of each member in the mis-insertion simulation requirement table; S102: Function regression (functional simulation batch regression) automatically matches and runs simulation test cases based on the simulation stimulus information in the inserted simulation requirement table, and generates the stimulus required for FIT simulation during the simulation test case operation.

[0024] Specifically, function regression automatically matches simulation test cases by inserting the simulation stimulus information in the simulation requirements table and running the simulation test cases. During the simulation test case execution, the stimulus required for FIT simulation is generated. The simulation stimulus information includes the full name of the directory where the simulation stimulus was generated and the test.evcd file.

[0025] Furthermore, in one embodiment, the abnormal simulation test cases are eliminated based on the running status of the simulation test cases, specifically including: The sitimulus check (the checker that generates stimulus) checks the running status of each simulation test case. If there is an abnormality in the current simulation test case, a report is issued and the current simulation test case is removed from the FIT simulation. Otherwise, the current simulation test case is retained.

[0026] Specifically, sitimulus check checks the execution of FIT simulation test cases. If a test case fails during the check, a report is generated and the current test case is removed from the FIT simulation. If the simulation result does not contain the word "PASS" or the word "ERROR" appears during the simulation, it indicates that the current test case has an anomaly.

[0027] Furthermore, in one embodiment, the FIT simulation environment file is detected, and the FIT simulation verification environment is generated, the FIT simulation process is formulated, and the required stimulus is matched according to the FIT simulation type. Specifically, the FIT simulation environment file is checked to confirm whether the FIT simulation environment file is sufficient for FIT simulation. For fit simulation (fault injection simulation), it includes three sub-steps, namely, FIT simulation verification environment generation, fault insertion simulation requirement table analysis, and automatic execution of FIT simulation.

[0028] Furthermore, in one embodiment, performing a FIT simulation, generating a FIT simulation result report based on the FIT simulation result, or adjusting the FIT simulation process and performing the FIT simulation again specifically includes: Perform FIT simulation. According to the FIT simulation results: If the FIT simulation results meet the preset simulation requirements, a FIT simulation result report is generated and published; If the FIT simulation result does not meet the preset simulation requirements, adjust the FIT simulation process and then perform the FIT simulation again.

[0029] Specifically, after executing the FIT simulation and completing it, the FIT simulation results are counted one by one to see whether they meet the requirements (if the actual value of the diagnostic coverage is greater than or equal to the ideal input value, it means that the requirements are met). If they meet the requirements, a FIT simulation result report is generated and published; if they do not meet the requirements, a backtracking process is performed to adjust the FIT simulation process and restart the FIT simulation.

[0030] Furthermore, in one embodiment, the adjustment of the FIT simulation process specifically includes: Based on the FIT simulation results, analyze whether the developed FIT simulation process is correct: If not, adjust the FIT simulation process; If yes, analyze whether the FIT simulation verification environment is configured correctly: -If it is incorrect, regenerate the FIT simulation verification environment; -If correct, analyze whether the excitation required for FIT simulation is sufficient. If not, continue to generate the excitation required for FIT simulation. If sufficient, adjust the mis-insertion simulation requirements in the mis-insertion simulation requirement table.

[0031] The following is a detailed description of the chip functional safety design automation verification method of this application.

[0032] a: Read the mis-insertion simulation requirement table and go to b; b: Generate the stimulus required for FIT simulation according to the requirements and go to c; c: Check whether the FIT simulation environment file meets the FIT simulation conditions, and go to d; d: Generate one or more FIT simulation verification environments and go to e; e: Match the required stimulus according to the FIT simulation type and go to f; f: Personalize the FIT simulation process and go to g; g: Run FIT simulation, go to h; h: Determine whether the FIT simulation results meet expectations. If yes, go to i; if not, go to j. i: Generate FIT simulation result report and publish it, ending; j: Analyze whether the FIT simulation process is correct. If not, go to f; if so, go to k. k: Analyze whether the configuration of the FIT simulation verification environment is correct. If not, go to d; if so, go to l; l: Analyze whether the excitation required for FIT simulation is sufficient. If not, go to b. If so, go to m. m: Adjust the misinsertion simulation requirements in the misinsertion simulation requirements table and go to a.

[0033] For further information, see Figure 2 As shown in the figure, when executing FIT simulation according to the established FIT simulation process, isolation technology is used to perform stimulus isolation, top-level qualification of simulation objects, and compilation isolation operations to adapt FIT simulation to the IP level, subsystem level, and SOC level. In other words, isolation technology is used to adapt the same FIT simulation to the IP level, subsystem level, and SOC level through simulation isolation.

[0034] In this application, the stimulus isolation includes configuring the stimulus collection interface level compilation information to isolate the interface stimulus collection, configuring the level of the Dump stimulus file to isolate the high-level interface stimulus, and ensuring that the stimulus file has a single name without duplication; the compilation isolation includes defining the compilation module to set the compilation command to specify the compilation options, specify the compilation tools and environment variables, and compile macros to compile the top-level specification; the top-level limitation of the simulation object includes specifying the top-level interface information and setting the monitoring interface of the observation point and diagnostic point.

[0035] That is, by placing an isolated structure through the FIT simulation environment file, a reasonable FIT simulation environment can be generated in different levels of circuit design through isolation through directory retrieval.

[0036] The chip functional safety design automation verification method of the embodiment of the present application can effectively reduce manual workload, improve work efficiency, and avoid errors by formulating a standardized, quantifiable, statistical, and efficiently located mis-insertion simulation process; the present application can solve the problems of difficult maintenance of FIT verification environments at different levels and high independent development costs in large-scale SOC projects by providing a mis-insertion simulation process architecture that can simultaneously adapt to the IP level, subsystem level, and SOC level; the present application can automatically generate a verification environment and operation-related instructions for mis-insertion simulation by design, and can standardize and publish mis-insertion simulation results, so as to provide timely and comprehensive feedback on the operation results, reduce the labor cost of collecting results, and reduce the possibility of errors in the process of collecting results.

[0037] In a second aspect, an embodiment of the present application also provides a chip functional safety design automation verification device.

[0038] In one embodiment, referring to Figure 3 , Figure 3 This is a functional module diagram of the automated verification device for chip functional safety design in this application. Figure 3 As shown, the chip functional safety design automation verification device includes: a reading module, a generation module, and an execution module.

[0039] The reading module is used to read the mis-insertion simulation requirement table to obtain the simulation test cases and run them, generate the stimulus required for FIT simulation, and eliminate abnormal simulation test cases based on the running status of the simulation test cases; the generation module is used to detect the FIT simulation environment file, and generate the FIT simulation verification environment, formulate the FIT simulation process, and match the required stimulus according to the FIT simulation type; the execution module is used to execute FIT simulation, generate a FIT simulation result report based on the FIT simulation results, or adjust the FIT simulation process to execute the FIT simulation again.

[0040] In a third aspect, an embodiment of the present application provides a chip functional safety design automation verification device, which can be a personal computer (PC), laptop computer, server, or other device with data processing capabilities.

[0041] Reference Figure 4 , Figure 4 This is a hardware structure diagram of the chip functional safety design automation verification device involved in the embodiment of the present application. In the embodiment of the present application, the chip functional safety design automation verification device may include a processor, a memory, a communication interface, and a communication bus.

[0042] The communication bus may be of any type and is used to interconnect the processor, memory, and communication interface.

[0043] Communication interfaces include input / output (I / O), physical, and logical interfaces, used to interconnect components within the chip functional safety design automation verification equipment, as well as interfaces used to interconnect the chip functional safety design automation verification equipment with other devices (such as other computing devices or user devices). Physical interfaces can be Ethernet, fiber, or ATM interfaces; user devices can be displays or keyboards.

[0044] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0045] The processor may be a general-purpose processor that can call a chip functional safety design automation verification program stored in a memory and execute the chip functional safety design automation verification method provided in the embodiments of the present application. For example, the general-purpose processor may be a central processing unit (CPU). The method executed when the chip functional safety design automation verification program is called can be referred to in the various embodiments of the chip functional safety design automation verification method of the present application and will not be further described here.

[0046] Those skilled in the art will understand that Figure 4 The hardware structure shown in the figure does not constitute a limitation to the present application and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0047] In a fourth aspect, an embodiment of the present application also provides a computer-readable storage medium.

[0048] The computer-readable storage medium of the present application stores a chip functional safety design automation verification program, wherein when the chip functional safety design automation verification program is executed by a processor, the steps of the chip functional safety design automation verification method as described above are implemented.

[0049] Among them, the method implemented when the chip functional safety design automation verification program is executed can refer to the various embodiments of the chip functional safety design automation verification method of this application, and will not be repeated here.

[0050] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit the "first", "second" and "third" to different types.

[0051] In the description of the embodiments of this application, the words "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0052] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0053] In some processes described in the embodiments of the present application, multiple operations or steps are included that appear in a specific order. However, it should be understood that these operations or steps may not be performed in the order in which they appear in the embodiments of the present application or may be performed in parallel. The sequence numbers of the operations are only used to distinguish between different operations, and the sequence numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations or steps may be performed in sequence or in parallel, and these operations or steps may be combined.

[0054] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, or the part that contributes to the existing technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above and includes a number of instructions for enabling a terminal device to execute the methods described in each embodiment of this application.

[0055] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip functional safety design automation verification method, characterized in that: The chip functional safety design automation verification method includes: Read the mis-insertion simulation requirement table to obtain simulation test cases and run them to generate the stimulus required for FIT simulation, and eliminate abnormal simulation test cases based on the running status of the simulation test cases; Detect FIT simulation environment files, generate FIT simulation verification environment, formulate FIT simulation process, and match required stimulus according to FIT simulation type; Perform a FIT simulation, generate a FIT simulation result report based on the FIT simulation results, or adjust the FIT simulation process and perform the FIT simulation again.

2. A chip functional safety design automation verification method according to claim 1, characterized in that: The reading of the mis-insertion simulation requirement table to obtain simulation test cases and running the same to generate the stimulus required for the FIT simulation specifically includes: Read the mis-insertion simulation requirement table through fit_regression and identify the information of each member in the mis-insertion simulation requirement table; Function regression automatically matches and runs simulation test cases based on the simulation stimulus information in the inserted simulation requirement table, and generates the stimulus required for FIT simulation during the simulation test case operation.

3. A chip functional safety design automation verification method according to claim 1, characterized in that: The step of eliminating abnormal simulation test cases based on the running conditions of the simulation test cases specifically includes: Sitimulus check checks the running status of each simulation test case. If there is an abnormality in the current simulation test case, a report will be issued and the current simulation test case will be removed from the FIT simulation. Otherwise, the current simulation test case will be retained.

4. A chip functional safety design automation verification method according to claim 1, characterized in that: The performing of the FIT simulation and generating a FIT simulation result report based on the FIT simulation result or adjusting the FIT simulation process and performing the FIT simulation again specifically includes: Perform FIT simulation. According to the FIT simulation results: If the FIT simulation results meet the preset simulation requirements, a FIT simulation result report is generated and published; If the FIT simulation result does not meet the preset simulation requirements, adjust the FIT simulation process and then perform the FIT simulation again.

5. A chip functional safety design automation verification method according to claim 1, characterized in that: Adjustments to the FIT simulation process include: Based on the FIT simulation results, analyze whether the developed FIT simulation process is correct: If not, adjust the FIT simulation process; If yes, analyze whether the FIT simulation verification environment is configured correctly: -If it is incorrect, regenerate the FIT simulation verification environment; -If correct, analyze whether the excitation required for FIT simulation is sufficient. If not, continue to generate the excitation required for FIT simulation. If sufficient, adjust the mis-insertion simulation requirements in the mis-insertion simulation requirement table.

6. A chip functional safety design automation verification method according to claim 1, characterized in that: When executing FIT simulation according to the established FIT simulation process, isolation technology is used to perform stimulus isolation, top-level qualification of simulation objects, and compilation isolation operations to adapt FIT simulation to the IP level, subsystem level, and SOC level.

7. A chip functional safety design automation verification method according to claim 6, characterized in that: The stimulus isolation includes configuring the stimulus collection interface level compilation information to isolate the interface stimulus collection, configuring the level of the Dump stimulus file to isolate the high-level interface stimulus, and ensuring that the stimulus file is named uniquely without duplication; The compilation isolation includes defining a compilation module to set a compilation command to specify compilation options, specifying compilation tools and environment variables, and compiling macros to compile top-level specifications; The top-level definition of the simulation object includes specifying the interface information of the top level and setting the monitoring interface of the observation point and the diagnosis point.

8. A chip functional safety design automation verification device, characterized in that: The chip functional safety design automation verification device includes: A reading module is used to read the mis-insertion simulation requirement table to obtain simulation test cases and run them, generate the stimulus required for FIT simulation, and eliminate abnormal simulation test cases based on the running status of the simulation test cases; The generation module is used to detect the FIT simulation environment file, generate the FIT simulation verification environment, formulate the FIT simulation process, and match the required stimulus according to the FIT simulation type; The execution module is used to execute FIT simulation, generate a FIT simulation result report based on the FIT simulation result, or adjust the FIT simulation process to execute FIT simulation again.

9. A chip functional safety design automation verification device, characterized in that: The chip functional safety design automation verification device includes a processor, a memory, and a chip functional safety design automation verification program stored on the memory and executable by the processor, wherein when the chip functional safety design automation verification program is executed by the processor, the steps of the chip functional safety design automation verification method as described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a chip functional safety design automation verification program, wherein when the chip functional safety design automation verification program is executed by the processor, the steps of the chip functional safety design automation verification method according to any one of claims 1 to 7 are implemented.

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