Layout method and layout device of chip on wafer and preparation method of silicon capacitor

Abstract

The invention provides a layout method and a layout device of chips on a wafer and a preparation method of a silicon capacitor, in the layout method, an XY two-dimensional rectangular coordinate system is established by taking the circle center of the wafer as an original point, exposure areas are respectively arranged in four wafer areas of the coordinate system, and for each exposure area, each chip is arranged on the silicon capacitor according to the size from large to small. The positions on the exposure area are arranged according to the sequence of the center, the edge four corners, the side lines and the remaining vacancies; and the chips are symmetrically arranged about the center of the exposure area. According to the method, by optimizing the exposure area division and chip arrangement rules, optimal utilization of the center area of the wafer is achieved, the structural strength of the center and the four corners of the exposure area is enhanced, the structural strength of the wafer is remarkably improved, and the risk of wafer warping in the follow-up manufacturing process is effectively reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a layout method and device for chips on a wafer, and a method for preparing a silicon capacitor. Background Art

[0002] In semiconductor manufacturing, various circuit structures are typically fabricated on wafers. For ease of manufacturing, the wafer is divided into several exposure units (shots). These shots, typically the basic unit of production, are periodically arranged on the wafer. Each shot contains one or more chips (dies). After all the silicon capacitors on the wafer are fabricated, the wafer is cut into several chips, each containing an independent circuit structure capable of implementing its intended function.

[0003] However, in order to maximize efficiency, designers arrange chips densely on a wafer, which leads to reliability issues such as excessive warping during the manufacturing process. Summary of the Invention

[0004] The purpose of the present disclosure is to solve the technical problem in the field of semiconductor manufacturing technology that chips densely arranged on a wafer cause warping during the manufacturing process.

[0005] To solve the above problems, the present application provides a method for arranging chips on a wafer, comprising the following steps:

[0006] S1. Acquire layout plan information, where the layout plan information includes wafer specification data and chip specification data, where the chip specification data includes sizes of multiple chips;

[0007] S2. Based on the wafer specification data, establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin; set exposure areas in the four wafer areas of the coordinate system;

[0008] S3. Arrange the chips in each exposure area according to the chip layout rules to complete the layout of the chips on the wafer;

[0009] The chip layout rules refer to:

[0010] The chips are arranged in descending order of size on the exposure area, in the order of center, four corners, sidelines, and remaining spaces.

[0011] The chips are arranged symmetrically around the center of the exposure area.

[0012] In an optional embodiment, the layout plan information further includes exposure field parameters of a lithography machine; and S2 includes:

[0013] According to the wafer specification data, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin;

[0014] According to the regional layout rules, exposure areas are respectively set in the four wafer areas of the coordinate system;

[0015] The regional layout rule means that each exposure region is within an exposure field of view corresponding to an exposure field parameter of a lithography machine, and adjacent exposure regions are axially symmetrical.

[0016] As a further improvement of the present application, the closest distance between each of the exposure areas and the X-axis and the Y-axis is 1 mm to 5 mm.

[0017] As a further improvement of the present application, in the same exposure area, the spacing between adjacent chips is no more than 0.5 mm.

[0018] As a further improvement of the present application, a blank area of ​​at least 1 mm is reserved at the edge area of ​​the wafer.

[0019] As a further improvement of the present application, at least one alignment mark is provided in each exposure area for use in alignment during the photolithography process.

[0020] To achieve the above objectives, the present application provides a device for placing chips on a wafer, comprising:

[0021] A layout plan acquisition module is used to acquire layout plan information, wherein the layout plan information includes wafer specification data and chip specification data, and the chip specification data includes the sizes of multiple chips;

[0022] The exposure area acquisition module is used to establish an XY two-dimensional rectangular coordinate system based on the wafer specification data and the center of the wafer as the origin; the exposure areas are respectively set in the four wafer areas of the coordinate system;

[0023] The chip layout module is used to arrange the chips according to the chip layout rules for each exposure area and complete the layout of the chips on the wafer;

[0024] The chip layout rules refer to:

[0025] The chips are arranged in descending order of size on the exposure area, in the order of center, four corners, sidelines, and remaining spaces.

[0026] The chips are arranged symmetrically around the center of the exposure area.

[0027] As a further improvement of the present application, the layout plan information further includes exposure field parameters of the lithography machine; and the exposure field parameter acquisition module includes:

[0028] A coordinate system establishment unit is used to establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin according to wafer specification data;

[0029] An exposure area setting unit, used to set exposure areas in the four wafer areas of the coordinate system according to the area layout rules;

[0030] The regional layout rule includes: each exposure area is within an exposure field of view corresponding to an exposure field parameter of a lithography machine, and adjacent exposure areas are axially symmetrical.

[0031] As a further improvement of the present application, the closest distance between each of the exposure areas and the X-axis and the Y-axis is 1 mm to 5 mm.

[0032] As a further improvement of the present application, in the same exposure area, the spacing between adjacent chips is no more than 0.5 mm.

[0033] As a further improvement of the present application, a blank area of ​​at least 1 mm is reserved at the edge area of ​​the wafer.

[0034] As a further improvement of the present application, at least one alignment mark is provided in each exposure area for use in alignment during the photolithography process.

[0035] To achieve the above objectives, the present application also provides a method for preparing a silicon capacitor, comprising the following steps:

[0036] A1. Obtaining a chip layout design according to the above-mentioned chip layout method on a wafer;

[0037] A2. Clean the wafer to be processed, grow an oxide layer, apply photoresist, expose and develop according to the layout design;

[0038] A3, temporarily bonding the back surfaces of the two wafers processed in step A2 together;

[0039] A4. Etch deep grooves on the top surfaces of the two wafers according to the layout design to isolate the chips.

[0040] A5. Polysilicon is deposited on the upper surfaces of the two wafers, and multiple electrode structures are formed by photolithography and etching. An insulating dielectric is deposited between the multiple electrode structures, and annealing is performed.

[0041] A6. Based on step A5, a passivation layer and a seed layer are deposited on the upper surfaces of the two wafers, and alloying treatment is performed;

[0042] A7, debonding the two wafers after step A6;

[0043] A8. Finally, arrange the circuits on the wafer surface, complete the passivation, and lead out the electrical signals.

[0044] The beneficial effect of the present application is that the present application provides a method for arranging chips on a wafer, wherein an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin, and exposure areas are respectively set in the four wafer areas of the coordinate system. For each exposure area, the chips are arranged in descending order of size on the exposure area in the order of center, four corners, sidelines, and remaining spaces; and the chips are arranged symmetrically about the center of the exposure area. By optimizing the exposure area division and chip arrangement rules, the present application not only achieves optimal utilization of the central area of ​​the wafer, but also enhances the structural strength of the center and four corners of the exposure area, significantly improving the structural strength of the wafer and effectively reducing the risk of wafer warping in subsequent processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a flow chart of a method for placing chips on a wafer according to an embodiment of the present application;

[0046] Figure 2 is a flow chart of a method for preparing a silicon capacitor according to an embodiment of the present application;

[0047] Figure 3 is a schematic diagram of the layout of the exposure area on the wafer according to an embodiment of the present application;

[0048] Figure 4 is a schematic diagram of the layout of the chip on each exposure area of ​​an embodiment of the present application;

[0049] Figure 5 This is a schematic structural diagram after step A3 in the silicon capacitor preparation process according to an embodiment of the present application;

[0050] Figure 6 This is a schematic structural diagram after step A4 in the silicon capacitor preparation process according to an embodiment of the present application;

[0051] Figure 7 This is a schematic structural diagram after step A5 in the silicon capacitor preparation process according to an embodiment of the present application;

[0052] Figure 8 This is a schematic structural diagram after step A6 in the silicon capacitor preparation process according to an embodiment of the present application;

[0053] Figure 9 This is a schematic structural diagram after step A7 in the silicon capacitor preparation process according to an embodiment of the present application;

[0054] Figure 10 1 is a schematic diagram of the structure after passivation is completed in step A8 during the preparation process of the silicon capacitor according to an embodiment of the present application;

[0055] Figure 11It is a structural diagram after the electrical signal is drawn out in step A8 during the preparation process of the silicon capacitor in an embodiment of the present application. DETAILED DESCRIPTION

[0056] As can be seen from the background technology, in the field of semiconductor manufacturing technology, densely arranging chips on a wafer can easily lead to the technical problem of warping during the process. According to some embodiments of the present disclosure, one embodiment of the present disclosure provides a method for arranging chips on a wafer, which can at least solve the technical problem of warping in subsequent processes.

[0057] The following will clearly and completely describe the technical solutions of the present disclosure in conjunction with the accompanying drawings and embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0058] In order to make the above-mentioned objects, features and advantages of the present disclosure more obvious and easy to understand, the present disclosure is further described in detail below in conjunction with specific implementation methods.

[0059] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0060] In the description of this disclosure, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present disclosure based on the specific circumstances.

[0061] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0062] Figure 1 is a flow chart of a method for placing chips on a wafer according to an embodiment of the present application; Figure 2 is a flow chart of a method for preparing a silicon capacitor according to an embodiment of the present application; Figure 3 is a schematic diagram of the layout of the exposure area on the wafer according to an embodiment of the present application; Figure 4 is a schematic diagram of the layout of the chip on each exposure area of ​​an embodiment of the present application;

[0063] according to Figure 1-Figure 4 The present disclosure provides a method for arranging chips on a wafer, comprising the following steps:

[0064] S1. Acquire layout plan information, where the layout plan information includes wafer specification data and chip specification data, where the chip specification data includes sizes of multiple chips;

[0065] Specifically, wafer specification data includes wafer size, wafer shape, wafer material, wafer surface characteristics, wafer process-related data, etc. Among them:

[0066] Wafer dimensions include diameter and thickness. Common wafer diameters include 200mm and 300mm. Wafer thickness typically ranges from a few hundred microns to several millimeters, such as 750μm and 800μm. Wafers are generally round in shape. Common wafer materials include single crystal silicon and polycrystalline silicon. Wafer surface characteristics include surface roughness, surface defect density, and oxide layer thickness. Wafer process-related data include photolithography resolution, etch depth, and film thickness.

[0067] Specifically, chip specification data includes chip size, chip function, chip layout, etc. Among them:

[0068] Chip size includes chip area, chip shape, chip size range, etc. The chip area is usually expressed in square millimeters (mm 2 ) means, for example, a common chip area can be 1mm 2 , 5mm 2 , 10mm 2 The chip shape is usually square or rectangular, but it may also be other shapes (such as round or irregular shapes). The chip size range refers to the length and width of the chip. For example, the chip size range can be 2mm×2mm, 5mm×3mm, etc.

[0069] Chip functions include functional types, functional modules, performance indicators, etc. Functional types include CPU, GPU, memory, sensor, RF chip, capacitor, etc. Functional modules include logic circuits, analog circuits, storage units, etc. Performance indicators include clock frequency, power consumption, storage capacity, computing speed, etc.

[0070] Chip layout includes chip arrangement, chip spacing, and chip direction. Chip arrangement includes array arrangement, center-symmetrical arrangement, etc. Chip spacing refers to the spacing between adjacent chips, usually expressed in millimeters (mm). For example, the chip spacing can be 0.5mm, 1mm, etc. The chip direction refers to the direction of the chip pins or the direction of the main functional surface, which is usually aligned with the coordinate system of the wafer.

[0071] S2. According to the wafer specification data, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin; exposure areas are respectively set in the four wafer areas of the coordinate system; in this step, the wafer specification data mainly includes the wafer size and wafer shape, and preferably, the wafer shape is circular.

[0072] S3. Arrange the chips in each exposure area according to the chip layout rules to complete the layout of the chips on the wafer; wherein the chip layout rules refer to:

[0073] The chips are arranged in descending order of size on the exposure area in the order of center, four corners, sidelines and remaining spaces; and the chips are arranged symmetrically around the center of the exposure area. In this step, the chips are arranged in descending order of size according to their area. The shape of the chips is mainly square or rectangular, and the area of ​​the chip is calculated by multiplying the length and width of the chip.

[0074] Based on the above technical solution, this application provides a method for arranging chips on a wafer, which significantly improves the overall structural strength and manufacturing efficiency of the wafer by optimizing the arrangement rules of the exposure area and the chips. Specifically,

[0075] First, the layout plan information is obtained. This layout plan information includes wafer and chip specifications. The chip specifications detail the dimensions of multiple chips. This information provides a foundation for subsequent layout design, ensuring that the layout plan accurately matches the actual characteristics of the wafer and chip.

[0076] Secondly, based on the wafer specification data, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin, and exposure areas are set up in the four wafer areas of the coordinate system. This design cleverly divides the entire wafer into four independent exposure areas, providing a clear framework for subsequent chip arrangement. By dividing the entire exposure area into four areas and offsetting them, the center area of ​​the wafer is effectively reserved. This innovative measure greatly improves the structural strength of the wafer and significantly reduces the possibility of wafer warping. The reserved space in the center area of ​​the wafer not only facilitates subsequent process operations, but also enhances the overall stability of the wafer and reduces structural deformation caused by stress concentration.

[0077] Furthermore, for each exposure area, the chips are arranged according to the chip layout rules to complete the overall layout of the chips on the wafer. The chip layout rules clearly state that the chips are arranged in descending order of size, in the order of center, four corners, sidelines and remaining spaces on the exposure area, and the chips are arranged symmetrically around the center of the exposure area. This arrangement not only makes full use of the space in the exposure area, but also balances the warping of a single exposure area by rationally distributing chips of different sizes. Specifically, arranging larger chips in the center of the exposure area can effectively increase the structural strength of the center area; arranging smaller chips in the four corners and sidelines further optimizes the weight distribution of the entire exposure area, thereby reducing the risk of warping of the entire wafer. In addition, the centrally symmetrical arrangement not only ensures the aesthetics and consistency of the chip layout, but also further improves the overall structural stability of the wafer, ensuring that the wafer can maintain good flatness and mechanical properties during subsequent manufacturing and use.

[0078] In summary, this application achieves optimal utilization of the center area of ​​the wafer through innovative exposure area division and chip arrangement rules, significantly improving the structural strength of the wafer and effectively reducing the risk of wafer warpage. At the same time, this layout method also balances the warpage of a single exposure area, enhances the structural strength of the center and four corners of the exposure area, and further reduces the degree of warpage of the entire wafer. These technical effects not only improve the overall quality and reliability of the wafer, but also provide a strong guarantee for high-precision processing in the semiconductor manufacturing process, with significant industrial application value and broad market prospects.

[0079] In an optional embodiment, the layout plan information further includes exposure field parameters of a lithography machine; and S2 includes:

[0080] According to the wafer specification data, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin;

[0081] According to the regional layout rules, exposure areas are respectively set in the four wafer areas of the coordinate system;

[0082] The regional layout rule means that each exposure region is within an exposure field of view corresponding to an exposure field parameter of a lithography machine, and adjacent exposure regions are axially symmetrical.

[0083] This approach further optimizes the layout of chips on the wafer by incorporating the lithography machine's exposure field of view parameters to ensure that each exposure area is within the machine's field of view, while also ensuring that adjacent exposure areas are axially symmetrical. This improvement not only improves the precision and consistency of the lithography process but also further optimizes wafer space utilization. The axisymmetric design ensures more uniform stress distribution during wafer processing, effectively reducing the stress concentration and warping risks associated with asymmetric layouts, significantly enhancing the wafer's overall structural stability and manufacturing quality.

[0084] In an optional embodiment, in step S2, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin, dividing the wafer into four quadrants, each corresponding to an exposure area. Each exposure area is typically fan-shaped or rectangular, with its size and shape determined by the size of the wafer and the exposure field parameters of the lithography machine.

[0085] Determine the boundary coordinates of each exposure area. For example, for a 300mm diameter wafer, if each exposure area is rectangular, its boundary coordinates in the XY coordinate system can be expressed as follows: the upper left exposure area is (-d, d) to (-m, n), the upper right exposure area is (d, d) to (m, n), the lower right exposure area is (m, -n) to (d, -d), and the lower left exposure area is (-d, -d) to (-m, -n), where d is less than the wafer radius (150mm), d is greater than m and greater than n, and m>0, n>0.

[0086] In an optional embodiment, step S3 also includes chip classification and sorting: First, all chips to be arranged are classified and sorted according to their size. The chip area (length × width) is used as the main classification basis, and the chips are arranged in descending order according to their area. For example, if there are three types of chips with sizes of 30mm × 30mm, 30mm × 7.5mm, and 10mm × 10mm, their areas are first calculated to be 1600mm. 2 , 400mm 2 , 400mm 2 , and then sorted by area size, the sorting order is 30mm×30mm, 30mm×7.5mm, and 10mm×10mm.

[0087] When the chips have the same area, the chip shape is further considered. For example, for chips with the same area but different aspect ratios, chips with aspect ratios closer to squares are prioritized because these shapes are more conducive to full space utilization during layout.

[0088] In an optional embodiment, in step S3, a chip position determination algorithm is also provided, which is as follows:

[0089] 1) Determination of the center position

[0090] For each exposure area, place the largest chip first at its geometric center. Calculate the center coordinates of the exposure area. For the upper left exposure area, for example, if d is 100, m is 1, and n is 1, its center coordinates are ((-100mm + (-1mm)) / 2, (100mm + 1mm) / 2) = (-50.5mm, 50.5mm). Align the center of the largest chip (e.g., 30mm x 30mm) with the center of the exposure area to determine the coordinates of its four corner points. The center of the chip is (-50.5mm, 50.5mm), and its half-length and half-width are both 15mm. The coordinates of its four corner points are (-50.5mm+15mm, 50.5mm+15mm), (-50.5mm-15mm, 50.5mm+15mm), (-50.5mm-15mm, 50.5mm-15mm), and (-50.5mm+15mm, 50.5mm-15mm).

[0091] Check whether the coordinates of the chip's four corners are within the exposure area, that is, whether they meet the boundary coordinates of the upper left exposure area (-100mm, 100mm) to (-1mm, 1mm), that is, the x coordinate is between (-100mm, -1mm), and the y coordinate is between (1mm, 100mm). If so, determine that position as the chip's layout position; if not, adjust the chip's position based on the boundary coordinates of the exposure area so that all four corners are within the exposure area, such as appropriately reducing the offset between the chip and the center coordinates, until the conditions are met.

[0092] 2) Determine the position of the four corners of the edge

[0093] Determine the four corners of the exposure area. For the top left exposure area, the coordinates of its four corners are (-d, d), (-m, d), (-m, n), and (-d, n). For example, based on the previous parameters, the coordinates of the four corners of the top left exposure area are (-100mm, 100mm), (-1mm, 100mm), (-1mm, 1mm), and (-100mm, 1mm).

[0094] Arrange the next largest chips at the four corners of the edge. For example, arrange a 30mm×30mm chip at position (-d, d) in the upper left exposure area. Select one edge to place along the negative x-axis or the positive y-axis (the specific direction can be determined based on layout optimization requirements). Assuming one edge of the chip is placed along the negative x-axis, (-d+15mm, d-15mm) = (-100mm+15mm, 100mm-15mm) = (-85mm, 85mm). The coordinates of the four corner points of the chip are (-85mm+15mm, 85mm+15mm), (-85mm-15mm, 85mm+15mm), (-85mm-15mm, 85mm-15mm), and (-85mm+15mm, 85mm-15mm). Check that these four corner points are within the exposure area, with the x coordinates between (-100mm, -1mm) and the y coordinates between (1mm, 100mm). If so, the position is determined to be the arrangement position of the chip; if not, the position of the chip is adjusted according to the boundary coordinates of the exposure area so that its four corner points are all within the exposure area.

[0095] 3) Determine the sideline position

[0096] Determine the edge position of the exposure area. Taking the upper left exposure area as an example, there are two edge lines along the x-axis, the upper and lower edges. Taking the lower edge as an example, first determine the blank area where the chips can be arranged. Since the chips have been arranged in the center and four corners of the exposure area, based on the content determined by the center position and the content determined by the four corner positions described above, the coordinates of the four points of this blank area are calculated as (-31mm, 1mm), (-70mm, 1mm), (-31mm, 35.5mm), and (-70mm, 35.5mm). Along the edge of the lower edge of the upper left exposure area parallel to the x-axis, a 30mm×7.5mm chip is arranged. The long side of the chip is set to be parallel to the x-axis, and the chip spacing is greater than 0.5mm. Taking the chip spacing of 1mm as an example, the coordinates of the four corner points of the chip are calculated as (-32mm, 1mm), (-62mm, 1mm), (-32mm, 8.5mm), and (-62mm, 8.5mm). Check whether the coordinates of the four corner points are within the exposure area, that is, the x coordinate is between (-100mm, -1mm) and the y coordinate is between (1mm, 100mm). At the same time, check whether the coordinates of the four corner points overlap the coordinates of the chip at the center and the four corners. After inspection, the four corner coordinates of the chip are within the exposure area and do not overlap the coordinates of the chip at the center and the four corners. Therefore, this position is determined to be the arrangement position of the chip. If the corner coordinates of the chip exceed the boundary of the exposure area, or overlap the coordinates of the chip at the center and the four corners, the position or orientation of the chip needs to be adjusted so that its corner coordinates meet the boundary conditions.

[0097] 4) Filling the remaining spaces

[0098] After arranging the chips in the center, corners, and edges, fill the remaining spaces in the exposure area. Based on the size and shape of the remaining space, appropriate chips are selected for placement. For irregularly shaped remaining spaces, a greedy algorithm can be used to prioritize the chips that best fill the space.

[0099] Calculate the boundary coordinates of the remaining space and determine the chip's position within the remaining space. For example, if the remaining space is an irregularly shaped area, its boundary coordinates can be approximated by a series of points. Determine whether the center coordinates of the chip are within the remaining space, calculate the coordinates of its four corner points, and check whether they are within the remaining space (i.e., whether they are within the boundary coordinate range of the exposure area and not within the area where the chips are already arranged). If so, determine that position as the arrangement position for the chip; if not, adjust the chip's position or select a chip of a different size for arrangement.

[0100] In an optional embodiment, the closest distance between each exposure area and the X-axis and Y-axis is 1mm to 5mm. By dividing the entire exposure area into four areas and offsetting them, the closest distance between each exposure area and the X-axis and Y-axis is set to 1mm to 5mm. This design not only effectively leaves room for the center area of ​​the wafer, further enhancing the structural strength of the wafer, but also optimizes the overall layout of the wafer through reasonable space allocation. This layout significantly reduces the possibility of wafer warping, while improving the accuracy and consistency of the photolithography process, ensuring high quality and high reliability in the chip manufacturing process.

[0101] In an optional embodiment, the spacing between adjacent chips within the same exposure area is no more than 0.5 mm. This compact chip spacing maximizes wafer utilization while ensuring that the chips do not interfere with each other, thereby improving overall integration.

[0102] In an optional embodiment, a blank area of ​​at least 1 mm is reserved at the edge of the wafer. The reserved edge area facilitates wafer dicing and subsequent packaging, reduces the risk of damage to edge chips, and improves the yield rate.

[0103] In an optional embodiment, at least one alignment mark is provided in each exposure area for alignment in the photolithography process. The alignment mark ensures high-precision alignment in the photolithography process, thereby improving the yield and consistency of chip manufacturing.

[0104] Another embodiment of the present disclosure further provides a device for placing chips on a wafer, comprising:

[0105] A layout plan acquisition module is used to acquire layout plan information, wherein the layout plan information includes wafer specification data and chip specification data, and the chip specification data includes the sizes of multiple chips;

[0106] The exposure area acquisition module is used to establish an XY two-dimensional rectangular coordinate system based on the wafer specification data and the center of the wafer as the origin; the exposure areas are respectively set in the four wafer areas of the coordinate system;

[0107] The chip layout module is used to arrange the chips according to the chip layout rules for each exposure area and complete the layout of the chips on the wafer;

[0108] The chip layout rules refer to:

[0109] The chips are arranged in descending order of size on the exposure area, in the order of center, four corners, sidelines, and remaining spaces.

[0110] The chips are arranged symmetrically around the center of the exposure area.

[0111] Some embodiments of the chip-on-wafer layout device provided in this embodiment and the effects achieved are consistent with some embodiments and beneficial effects recorded in the above-mentioned chip-on-wafer layout method, and some contents are not repeated here.

[0112] In an optional embodiment, the layout plan information further includes exposure field parameters of a lithography machine; and the exposure field parameter acquisition module includes:

[0113] A coordinate system establishment unit is used to establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin according to wafer specification data;

[0114] An exposure area setting unit, used to set exposure areas in the four wafer areas of the coordinate system according to the area layout rules;

[0115] The regional layout rule includes: each exposure area is within an exposure field of view corresponding to an exposure field parameter of a lithography machine, and adjacent exposure areas are axially symmetrical.

[0116] In an optional implementation, the layout plan acquisition module is used to obtain layout plan information from multiple channels to ensure that the chip arrangement can accurately meet the operating requirements of the lithography machine. The following is the specific acquisition method of the layout plan acquisition module:

[0117] Manual Input: This module features a user interface that allows operators to manually input relevant information, including wafer and chip specifications, into the system. For example, by entering wafer specifications such as wafer diameter, thickness, and material, as well as chip specifications such as the size and function of each chip, basic information is provided for subsequent chip layout. Manual input is suitable for small-scale production or customized needs. When the production scale is small or there are special requirements for wafer and chip layout that require flexible adjustments based on specific circumstances, manual input can easily input personalized layout plan information.

[0118] Automatic File Reading: The module automatically reads pre-formatted layout plan files containing key information such as wafer and chip specifications. For example, it reads files in a specific format generated by a lithography machine or design software, extracts data such as wafer dimensions and chip dimensions, and converts them into the format required for chip layout. Automatic file reading is suitable for integration with existing design software or lithography systems. In highly automated production environments, automatic file reading enables seamless integration with design software or lithography machines, improving the efficiency and accuracy of layout plan information acquisition and reducing errors that may be caused by manual input.

[0119] Acquisition from a database or server: The layout plan acquisition module can communicate with an external database or server to retrieve stored layout plan information. For example, it can obtain existing wafer and chip specification data from the company's production database, or download the latest design files from a cloud server to obtain information such as chip size and function. Acquisition from a database or server is suitable for large-scale production and enterprise-level applications. For large semiconductor manufacturers, production data is often stored in a database or server. By obtaining layout plan information from a database or server, production data can be centrally managed and shared, facilitating unified monitoring and optimization of the production process.

[0120] The implementation principle of the layout plan acquisition module is as follows: When acquiring layout plan information, the layout plan acquisition module needs to transmit data from different sources and convert it into a unified format for use by the chip layout module. For example, the data read from the file or database is parsed, the key fields of the wafer specification data and the chip specification data are extracted, and then converted into a format that can be recognized by the chip layout module. In order to realize data transmission and interaction, the layout plan acquisition module needs to communicate with external devices or systems, which involves the design of interfaces and protocols. For example, the communication interface with the lithography machine follows a specific industrial protocol to ensure the stability and reliability of data transmission; the interface with the database needs to support standard database query languages ​​(such as SQL) to retrieve the required data from the database.

[0121] The core structure of a silicon capacitor typically consists of two parallel silicon wafers serving as electrodes, sandwiched between an insulating dielectric layer. This structure is similar to that of a traditional capacitor, but semiconductor technology enables miniaturization and enhanced performance. Due to their high compatibility with semiconductor manufacturing processes, silicon capacitors can be integrated with integrated circuit chips, significantly reducing circuit size and power consumption, and improving system reliability. In modern electronic devices, silicon capacitors are widely used in power management, signal processing, and radio frequency circuits, providing critical support for the efficient operation of semiconductor devices. In semiconductor manufacturing, silicon capacitors are also fabricated on wafers. During the fabrication process, for ease of manufacturing, the wafer is divided into several exposure units (shots). These shot units, typically the basic unit of production, are periodically arranged on the wafer. Each shot contains one or more chips (dies). After all the silicon capacitors on the wafer are fabricated, the wafer is cut into several chips, each containing a separate silicon capacitor capable of performing its intended function.

[0122] However, in order to maximize efficiency, designers also arrange chips densely on a wafer during the preparation of silicon capacitors, resulting in reliability issues such as excessive warping during the manufacturing process.

[0123] Figure 5 This is a schematic structural diagram after step A3 in the silicon capacitor preparation process according to an embodiment of the present application; Figure 6 This is a schematic structural diagram after step A4 in the silicon capacitor preparation process according to an embodiment of the present application; Figure 7 This is a schematic structural diagram after step A5 in the silicon capacitor preparation process according to an embodiment of the present application; Figure 8 This is a schematic structural diagram after step A6 in the silicon capacitor preparation process according to an embodiment of the present application; Figure 9 This is a schematic structural diagram after step A7 in the silicon capacitor preparation process according to an embodiment of the present application; Figure 10 This is a schematic structural diagram of the silicon capacitor after passivation is completed in step A8 during the preparation process of the embodiment of the present application; Figure 11 This is a structural diagram after the electrical signal is drawn out in step A8 during the preparation process of the silicon capacitor in an embodiment of the present application.

[0124] according to Figure 5-Figure 11 Another embodiment of the present disclosure provides a method for preparing a silicon capacitor, comprising the following steps:

[0125] A1. Obtaining a chip layout design according to the chip layout method on a wafer disclosed in the above embodiment;

[0126] A2. Clean the wafer to be processed, grow an oxide layer, apply photoresist, expose and develop according to the layout design;

[0127] A3, temporarily bonding the back surfaces of the two wafers processed in step A2 together;

[0128] A4. Etch deep grooves on the top surfaces of the two wafers according to the layout design to isolate the chips.

[0129] A5. Polysilicon is deposited on the upper surfaces of the two wafers, and multiple electrode structures are formed by photolithography and etching. An insulating dielectric is deposited between the multiple electrode structures, and annealing is performed.

[0130] A6. Based on step A5, a passivation layer and a seed layer are deposited on the upper surfaces of the two wafers, and alloying treatment is performed;

[0131] A7, debonding the two wafers after step A6;

[0132] A8. Finally, arrange the circuits on the wafer surface, complete the passivation, and lead out the electrical signals.

[0133] Based on the above disclosed embodiments, this embodiment mainly applies the above-discussed chip layout method on a wafer to the preparation of silicon capacitors. Some embodiments of this embodiment and the technical effects achieved are the same as those of the above-mentioned embodiments and will not be repeated here.

[0134] In a more specific embodiment, a wafer with a diameter of 300 mm is selected as an example for illustration. First, layout plan information is obtained. The layout plan information includes wafer specification data and chip specification data. The chip specification data includes the sizes of multiple chips. The sizes of the multiple chips selected in this embodiment are divided into three types according to length × width, namely 30 mm × 30 mm, 30 mm × 7.5 mm, and 10 mm × 10 mm. Secondly, according to the wafer specification data, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin, and exposure areas are respectively set in the four wafer areas of the coordinate system, such as Figure 3 As shown; finally, for each exposure area, the chips are arranged according to the chip layout rules to complete the layout of the chips on the wafer; wherein, the chip layout rules are: the chips are arranged in descending order of size on the exposure area in the order of center, edge corners, sidelines and remaining spaces; and the chips are arranged symmetrically around the center of the exposure area, as shown Figure 4 As shown, Figure 4 In the exposure area, 30mm×30mm chips are arranged in the center and four corners of the edge, 30mm×7.5mm chips are arranged at the edge position, and 10mm×10mm chips are arranged in the remaining space. At the same time, the distance between adjacent chips does not exceed 0.5mm.

[0135] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present disclosure. They are not intended to limit the scope of protection of the present disclosure. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for arranging chips on a wafer, characterized in that: The steps include: S1. Acquire layout plan information, where the layout plan information includes wafer specification data and chip specification data, where the chip specification data includes sizes of multiple chips; S2. Based on the wafer specification data, establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin; set exposure areas in the four wafer areas of the coordinate system; S3. Arrange the chips in each exposure area according to the chip layout rules to complete the layout of the chips on the wafer; The chip layout rules refer to: The chips are arranged in descending order of size on the exposure area, in the order of center, four corners, sidelines, and remaining spaces. The chips are arranged symmetrically around the center of the exposure area.

2. The layout method according to claim 1, wherein: The layout plan information also includes the exposure field parameters of the lithography machine; S2 includes: According to the wafer specification data, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin; According to the regional layout rules, exposure areas are respectively set in the four wafer areas of the coordinate system; The regional layout rule means that each exposure region is within an exposure field of view corresponding to an exposure field parameter of a lithography machine, and adjacent exposure regions are axially symmetrical.

3. The layout method according to claim 1, wherein: The closest distance between each exposure area and the X axis and the Y axis is 1 mm to 5 mm.

4. The layout method according to claim 1, wherein: In the same exposure area, the spacing between adjacent chips is no more than 0.5 mm.

5. The layout method according to claim 1, wherein: A blank area of ​​at least 1 mm is reserved at the edge of the wafer.

6. The layout method according to claim 1, characterized in that: At least one alignment mark is provided in each exposure area for use in alignment during a photolithography process.

7. A chip layout device on a wafer, characterized in that: include: A layout plan acquisition module is used to acquire layout plan information, wherein the layout plan information includes wafer specification data and chip specification data, and the chip specification data includes the sizes of multiple chips; The exposure area acquisition module is used to establish an XY two-dimensional rectangular coordinate system based on the wafer specification data and the center of the wafer as the origin; the exposure areas are respectively set in the four wafer areas of the coordinate system; The chip layout module is used to arrange the chips according to the chip layout rules for each exposure area and complete the layout of the chips on the wafer; The chip layout rules refer to: The chips are arranged in descending order of size on the exposure area, in the order of center, four corners, sidelines, and remaining spaces. The chips are arranged symmetrically around the center of the exposure area.

8. The layout device according to claim 7, characterized in that The layout plan information also includes the exposure field parameters of the lithography machine; the exposure field parameter acquisition module includes: A coordinate system establishment unit is used to establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin according to wafer specification data; An exposure area setting unit, used to set exposure areas in the four wafer areas of the coordinate system according to the area layout rules; The regional layout rule includes: each exposure area is within an exposure field of view corresponding to an exposure field parameter of a lithography machine, and adjacent exposure areas are axially symmetrical.

9. The layout device according to claim 7, characterized in that The closest distance between each exposure area and the X axis and the Y axis is 1 mm to 5 mm.

10. A method for preparing a silicon capacitor, characterized in that: The steps include: A1. Obtaining a chip layout design according to the chip layout method on a wafer according to any one of claims 1 to 6; A2. Clean the wafer to be processed, grow an oxide layer, apply photoresist, expose and develop according to the layout design; A3, temporarily bonding the back surfaces of the two wafers processed in step A2 together; A4. Etch deep grooves on the top surfaces of the two wafers according to the layout design to isolate the chips. A5. Polysilicon is deposited on the upper surfaces of the two wafers, and multiple electrode structures are formed by photolithography and etching. An insulating dielectric is deposited between the multiple electrode structures, and annealing is performed. A6. Based on step A5, a passivation layer and a seed layer are deposited on the upper surfaces of the two wafers, and alloying treatment is performed; A7, debonding the two wafers after step A6; A8. Finally, arrange the circuits on the wafer surface, complete the passivation, and lead out the electrical signals.

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