Optimization method for EDA (Electronic Design Automation) layout and wiring

Abstract

The invention relates to the technical field of electronic design automation, and discloses an EDA layout and wiring optimization method, which comprises the following steps of: firstly, finishing layout and wiring according to initial layout and wiring data of an electronic design layout, and then dividing a whole layout and wiring area into a plurality of relatively independent sub-areas; according to the method, the layout and wiring characteristic parameters of each sub-region are extracted respectively, the processed parameters are analyzed after the parameters are normalized, and each sub-region is optimized according to an analysis result, so that the calculation amount is reduced, the optimization efficiency is improved, and finally, the performance of the whole layout and wiring is evaluated. Global performance degradation caused by local optimization is avoided through real-time performance feedback, and it is ensured that the final scheme meets the design target.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation, and in particular to an EDA layout and routing optimization method. Background Art

[0002] Layout and routing are crucial steps in the electronic design automation (EDA) process, with optimization directly impacting key chip metrics such as performance, power consumption, and area. Traditional EDA layout and routing optimization methods rely primarily on empirical analysis and a unified, global approach. This leads to high computational complexity, low optimization efficiency, and difficulty achieving a global optimal solution. With increasing chip integration and design scale, these traditional methods are increasingly unable to meet the layout and routing optimization requirements of modern, large-scale, and complex integrated circuit designs. Therefore, a new EDA layout and routing optimization method is urgently needed to improve both efficiency and quality. Summary of the Invention

[0003] The purpose of the present invention is to provide an EDA layout and routing optimization method to solve the above technical problems.

[0004] The purpose of the present invention can be achieved through the following technical solutions:

[0005] A method for EDA layout and routing optimization, the method comprising the following steps:

[0006] Step S1, obtaining design data: obtaining initial layout and routing data of the electronic design layout to be optimized, including position information, connection relationship information and routing constraints of circuit components;

[0007] Step S2, constructing a topology structure model: constructing a topology structure model between circuit elements based on the acquired initial layout and routing data;

[0008] Step S3, dividing the optimization area: dividing the entire layout and routing area into multiple relatively independent sub-areas;

[0009] Step S4, sub-region local optimization: for each sub-region, extract the characteristic parameters of each region respectively, and normalize the parameters;

[0010] Step S5: Analyze the normalized parameters and generate optimization strategies for each region based on the analysis results;

[0011] Step S6, evaluation and feedback: Evaluate the layout and routing scheme after global collaborative optimization, and determine whether it meets the performance requirements based on the evaluation results. If it does, output the final layout and routing scheme; if it does not, adjust the optimization process based on the evaluation results until a layout and routing scheme that meets the requirements is obtained.

[0012] As a further description of the technical solution of the present invention, the method for obtaining design data in step S1 includes: exporting the initial layout and wiring data of the layout from the EDA design tool, including the coordinate position of each circuit element, the pin connection relationship between the elements, and the wiring width and minimum spacing.

[0013] As a further description of the technical solution of the present invention, the specific process of step S3 includes:

[0014] The layout and routing area is divided into n grid sub-areas using the grid partitioning method. Each sub-area contains a certain number of circuit elements, and each area is numbered in the order of: 1, 2, ..., n.

[0015] As a further description of the technical solution of the present invention, the characteristic parameters of each region in step S4 include: layout parameters and wiring parameters;

[0016] The layout parameters of the i-th region are obtained as follows: average component spacing D i , average pin spacing H i and cell density ρ i ;

[0017] The wiring parameters of the i-th region are obtained as follows: average wiring length L i , average wiring width C i and the number of wiring layers X i .

[0018] As a further description of the technical solution of the present invention, the working process of step S5 includes:

[0019] Construct a mathematical model of the layout optimization coefficient of the i-th region, and the expression is:

[0020]

[0021] Where α and β are the weight coefficients of the average component spacing and the average pin spacing, respectively; k1 is the adjustment coefficient; D i0 The standard average component spacing set for the system, H i0 is the standard average pin spacing set by the system, n>i>0, and i belongs to [1, n], μ i is the layout optimization coefficient of the i-th region;

[0022] Construct a mathematical model of the wiring optimization coefficient of the i-th region, and the expression is:

[0023]

[0024] Where a and b are the weight coefficients of average wiring length and average wiring width respectively, k2 is the adjustment coefficient, Li0 The standard average wiring length set for the system, C i0 is the standard average wiring width set by the system, n>i>0, and i belongs to [1, n], π i is the routing optimization coefficient of the i-th region.

[0025] As a further description of the technical solution of the present invention, the working process of step S5 further includes:

[0026] The layout optimization coefficient μ of the i-th region is respectively i and the routing optimization coefficient π of the i-th region i Compared with the corresponding standard interval set by the system, if μ i and π i If any optimization coefficient does not meet the corresponding standard range, it will be optimized immediately;

[0027] If μ i and π i If all meet the corresponding standard intervals, the mathematical model of the optimization coefficient of the i-th region is constructed, and the expression is:

[0028]

[0029] Where γ and δ are the adjustment factors of layout optimization coefficient and routing optimization coefficient respectively, T i Optimize the coefficient for the i-th region;

[0030] The optimization coefficient T of the i-th region i Compared with the standard interval set by the system, if T i If the corresponding standard interval is not met, the layout and routing of the i-th region will be optimized immediately.

[0031] As a further description of the technical solution of the present invention, the working process of step S6 includes:

[0032] Obtain the performance parameters of the current layout and routing scheme, including signal delay and power consumption;

[0033] Obtain the signal delay DEL and power consumption W of the current layout and routing scheme within the set time period, and construct a mathematical model of the performance index of the current layout and routing scheme. The expression is:

[0034]

[0035] Where k DEL and k W are the weight coefficients corresponding to signal delay and power consumption, Performance indicators for the current layout and routing solution;

[0036] Will Compared with the threshold set by the system, if If the value is greater than or equal to the threshold set by the system, it means that the current layout and routing scheme meets the requirements and the current layout and routing scheme is output. If it is lower than the threshold set by the system, it means that the current layout and routing scheme does not meet the requirements and needs to be further adjusted.

[0037] Beneficial effects of the present invention:

[0038] 1. Decompose complex global problems into multiple sub-problems through partition optimization (such as grid division), significantly reducing the amount of calculation, which is suitable for large-scale integrated circuit design.

[0039] 2. Refined modeling of local parameters (such as wiring length and component density), combined with weight coefficients and adjustment factors, to achieve targeted optimization and reduce signal delay and power consumption.

[0040] 3. Avoid global performance degradation caused by local optimization through real-time performance feedback (step S6) to ensure that the final solution meets the design goals. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention will be further described below with reference to the accompanying drawings.

[0042] Figure 1 This is a partial flow chart of the EDA layout and routing optimization method provided by the present invention. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0044] See also Figure 1 The present invention is a method for optimizing EDA layout and routing, the method comprising the following steps:

[0045] Step S1, obtaining design data: obtaining initial layout and routing data of the electronic design layout to be optimized, including position information, connection relationship information and routing constraints of circuit components;

[0046] Step S2, constructing a topology structure model: constructing a topology structure model between circuit elements based on the acquired initial layout and routing data;

[0047] Step S3, dividing the optimization area: dividing the entire layout and routing area into multiple relatively independent sub-areas;

[0048] Step S4, sub-region local optimization: for each sub-region, extract the characteristic parameters of each region respectively, and normalize the parameters;

[0049] Step S5: Analyze the normalized parameters and generate optimization strategies for each region based on the analysis results;

[0050] Step S6, evaluation and feedback: Evaluate the layout and routing scheme after global collaborative optimization, and determine whether it meets the performance requirements based on the evaluation results. If it does, output the final layout and routing scheme; if it does not, adjust the optimization process based on the evaluation results until a layout and routing scheme that meets the requirements is obtained.

[0051] Through the above technical solution, the present invention first completes the layout and routing based on the initial layout and routing data of the electronic design layout, then divides the entire layout and routing area into multiple relatively independent sub-areas, extracts the layout and routing characteristic parameters of each sub-area respectively, normalizes the parameters, analyzes the processed parameters, and optimizes each sub-area based on the analysis results, thereby reducing the amount of calculation and improving the optimization efficiency. Finally, the performance of the entire layout and routing is evaluated, and global performance degradation caused by local optimization is avoided through real-time performance feedback, ensuring that the final solution meets the design goals.

[0052] As a further description of the technical solution of the present invention, the method for obtaining design data in step S1 includes: exporting the initial layout and wiring data of the layout from the EDA design tool, including the coordinate position of each circuit element, the pin connection relationship between the elements, and the wiring width and minimum spacing.

[0053] As a further description of the technical solution of the present invention, the specific process of step S3 includes:

[0054] The layout and routing area is divided into n grid sub-areas using the grid partitioning method. Each sub-area contains a certain number of circuit elements, and each area is numbered in the order of: 1, 2, ..., n.

[0055] As a further description of the technical solution of the present invention, the characteristic parameters of each region in step S4 include: layout parameters and wiring parameters;

[0056] The layout parameters of the i-th region are obtained as follows: average component spacing D i , average pin spacing H i and cell density ρ i ;

[0057] The wiring parameters of the i-th region are obtained as follows: average wiring length L i , average wiring width C iand the number of wiring layers X i .

[0058] As a further description of the technical solution of the present invention, the working process of step S5 includes:

[0059] Construct a mathematical model of the layout optimization coefficient of the i-th region, and the expression is:

[0060]

[0061] Where α and β are the weight coefficients of the average component spacing and the average pin spacing, respectively; k1 is the adjustment coefficient; D i0 The standard average component spacing set for the system, H i0 is the standard average pin spacing set by the system, n>i>0, and i belongs to [1, n], μ i is the layout optimization coefficient of the i-th region;

[0062] Construct a mathematical model of the wiring optimization coefficient of the i-th region, and the expression is:

[0063]

[0064] Where a and b are the weight coefficients of average wiring length and average wiring width respectively, k2 is the adjustment coefficient, L i0 The standard average wiring length set for the system, C i0 is the standard average wiring width set by the system, n>i>0, and i belongs to [1, n], π i is the routing optimization coefficient of the i-th region.

[0065] As a further description of the technical solution of the present invention, the working process of step S5 further includes:

[0066] The layout optimization coefficient μ of the i-th region is respectively i and the routing optimization coefficient π of the i-th region i Compared with the corresponding standard interval set by the system, if μ i and π i If any optimization coefficient does not meet the corresponding standard range, it will be optimized immediately;

[0067] If μ i and π i If all meet the corresponding standard intervals, the mathematical model of the optimization coefficient of the i-th region is constructed, and the expression is:

[0068]

[0069] Where γ and δ are the adjustment factors of layout optimization coefficient and routing optimization coefficient respectively, T i Optimize the coefficient for the i-th region;

[0070] The optimization coefficient T of the i-th region i Compared with the standard interval set by the system, if T i If the corresponding standard interval is not met, the layout and routing of the i-th region will be optimized immediately.

[0071] Through the above technical solution, it is defined how to achieve fine adjustment of EDA layout and routing through mathematical modeling and dynamic optimization. First, the key parameters are obtained. The layout parameters of the i-th area include: average component spacing D i , average pin spacing H i and cell density ρ i ; The wiring parameters of the i-th area include: average wiring length L i , average wiring width C i and the number of wiring layers X i Then, based on the key parameters, the mathematical model of the layout optimization coefficient of the i-th region and the mathematical model of the wiring optimization coefficient of the i-th region are constructed, which are: and Then, μ i and π i Compared with the preset standard range, if any coefficient does not meet the standard, local optimization is triggered. When the layout and routing meet the standards, the overall performance of the sub-area is further evaluated to ensure that the local optimization does not affect the global goal and prevent the local optimization from causing performance degradation in other areas (such as excessive compression of routing causing signal crosstalk).

[0072] As a further description of the technical solution of the present invention, the working process of step S6 includes:

[0073] Obtain the performance parameters of the current layout and routing scheme, including signal delay and power consumption;

[0074] Obtain the signal delay DEL and power consumption W of the current layout and routing scheme within the set time period, and construct a mathematical model of the performance index of the current layout and routing scheme. The expression is:

[0075]

[0076] Where k DEL and k W are the weight coefficients corresponding to signal delay and power consumption, Performance indicators for the current layout and routing solution;

[0077] Will Compared with the threshold set by the system, if If the value is greater than or equal to the threshold set by the system, it means that the current layout and routing scheme meets the requirements and the current layout and routing scheme is output. If it is lower than the threshold set by the system, it means that the current layout and routing scheme does not meet the requirements and needs to be further adjusted.

[0078] Through the above technical solution, by quantitatively analyzing the overall performance of the current layout and routing scheme, it is dynamically determined whether it meets the design requirements and triggers iterative optimization. First, a mathematical model of the performance indicators of the current layout and routing scheme is constructed. Convert the multi-objective optimization problem (timing, power consumption) into a single objective to facilitate quantitative evaluation. Compared with the threshold set by the system, if If the value is greater than or equal to the threshold set by the system, it means that the current layout and routing scheme meets the requirements and the current layout and routing scheme is output. If it is lower than the threshold set by the system, it means that the current layout and routing scheme does not meet the requirements and needs to be further adjusted.

[0079] It should be noted that the parameters in the present invention are all normalized to a unified standard range for calculation, and the thresholds, standard intervals, weight coefficients and adjustment coefficients mentioned in the present invention are all empirical values, which can be modified in combination with the characteristics of the data type to be evaluated.

[0080] The above is a detailed description of an embodiment of the present invention. However, the content described is only a preferred embodiment of the present invention and should not be considered to limit the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A method for EDA layout and routing optimization, characterized in that: The method comprises the following steps: Step S1, obtaining design data: obtaining initial layout and routing data of the electronic design layout to be optimized, including position information, connection relationship information and routing constraints of circuit components; Step S2, constructing a topology structure model: constructing a topology structure model between circuit elements based on the acquired initial layout and routing data; Step S3, dividing the optimization area: dividing the entire layout and routing area into multiple relatively independent sub-areas; Step S4, sub-region local optimization: for each sub-region, extract the characteristic parameters of each region respectively, and normalize the parameters; Step S5: Analyze the normalized parameters and generate optimization strategies for each region based on the analysis results; Step S6, evaluation and feedback: Evaluate the layout and routing solution after global collaborative optimization, and determine whether it meets the performance requirements based on the evaluation results. If so, output the final layout and routing solution; If the requirements are not met, the optimization process is adjusted according to the evaluation results until a layout and routing solution that meets the requirements is obtained.

2. The EDA layout and routing optimization method according to claim 1, wherein: The method for obtaining design data in step S1 includes: exporting the initial layout and routing data of the layout from the EDA design tool, including the coordinate position of each circuit element, the pin connection relationship between the elements, and the routing width and minimum spacing.

3. The EDA layout and routing optimization method according to claim 1, wherein: The specific process of step S3 includes: The layout and routing area is divided into n grid sub-areas using the grid partitioning method. Each sub-area contains a certain number of circuit elements, and each area is numbered in the order of: 1, 2, ..., n.

4. The EDA layout and routing optimization method according to claim 1, wherein: The characteristic parameters of each region in step S4 include: layout parameters and wiring parameters; The layout parameters of the i-th region are obtained as follows: average component spacing D i , average pin spacing H i and cell density ρ i ; The wiring parameters of the i-th region are obtained as follows: average wiring length L i , average wiring width C i and the number of wiring layers X i .

5. The EDA layout and routing optimization method according to claim 1, wherein: The working process of step S5 includes: Construct a mathematical model of the layout optimization coefficient of the i-th region, and the expression is: Where α and β are the weight coefficients of the average component spacing and the average pin spacing, respectively; k1 is the adjustment coefficient; D i0 The standard average component spacing set for the system, H i0 is the standard average pin spacing set by the system, n>i>0, and i belongs to [1, n], μ i is the layout optimization coefficient of the i-th region; Construct a mathematical model of the wiring optimization coefficient of the i-th region, and the expression is: Where a and b are the weight coefficients of average wiring length and average wiring width respectively, k2 is the adjustment coefficient, L i0 The standard average wiring length set for the system, C i0 is the standard average wiring width set by the system, n>i>0, and i belongs to [1, n], π i is the routing optimization coefficient of the i-th region.

6. The EDA layout and routing optimization method according to claim 5, wherein: The working process of step S5 also includes: The layout optimization coefficient μ of the i-th region is respectively i and the routing optimization coefficient π of the i-th region i Compared with the corresponding standard interval set by the system, if μ i and π i If any optimization coefficient does not meet the corresponding standard range, it will be optimized immediately; If μ i and π i If all meet the corresponding standard intervals, the mathematical model of the optimization coefficient of the i-th region is constructed, and the expression is: Where γ and δ are the adjustment factors of layout optimization coefficient and routing optimization coefficient respectively, T i Optimize the coefficient for the i-th region; The optimization coefficient T of the i-th region i Compared with the standard interval set by the system, if T i If the corresponding standard interval is not met, the layout and routing of the i-th region will be optimized immediately.

7. The EDA layout and routing optimization method according to claim 1, wherein: The working process of step S6 includes: Obtain the performance parameters of the current layout and routing scheme, including signal delay and power consumption; Obtain the signal delay DEL and power consumption W of the current layout and routing scheme within the set time period, and construct a mathematical model of the performance index of the current layout and routing scheme. The expression is: Where k DEL and k W are the weight coefficients corresponding to signal delay and power consumption, Performance indicators for the current layout and routing solution; Will Compared with the threshold set by the system, if If the value is greater than or equal to the threshold set by the system, it means that the current layout and routing scheme meets the requirements and the current layout and routing scheme is output. If it is lower than the threshold set by the system, it means that the current layout and routing scheme does not meet the requirements and needs to be further adjusted.

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