Memory and memory system
By combining a multi-terminal device voltage divider circuit and a transistor switching circuit, the reference voltage is dynamically adjusted, which solves the adjustment complexity and inaccuracy problems of low-voltage difference linear regulators in high-precision scenarios, achieves fast and accurate voltage regulation, and improves the performance and applicability of the regulator.
Patent Information
- Application Number
- CN202410317213.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-19
- Publication Date
- 2025-09-19
AI Technical Summary
In existing low-dropout linear regulators (LDOs) that require high precision and fast response, the fixed-step adjustment method cannot meet the accuracy and stability requirements of the output voltage, resulting in increased adjustment complexity and time cost.
A voltage divider circuit structure with a multi-terminal device is adopted. By combining the first and second voltage divider circuits with a voltage modulation circuit, multiple transistor switching circuits and error amplifiers are used to achieve dynamic adjustment of the reference voltage, thereby enhancing the flexibility and accuracy of voltage regulation.
It achieves fast and precise adjustment of the output voltage, improves the response speed and stability of the voltage regulator, meets the needs of high precision and multiple application scenarios, and reduces the adjustment complexity and time cost.
Smart Images
Figure CN120673814A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a memory and a memory system. Background Art
[0002] A low-dropout (LDO) regulator is an electronic device that converts a high input voltage into a low, stable output voltage. Widely used in storage devices, LDOs are characterized by their low voltage dropout. This means the voltage difference between the input and output voltages is very small. Therefore, LDOs can operate even when the input voltage is close to the output voltage, reducing energy waste and improving efficiency. Summary of the Invention
[0003] The embodiments disclosed herein provide a memory and a memory system. The embodiments disclosed herein adopt the following technical solutions:
[0004] In a first aspect, a memory is provided, comprising a memory array and a peripheral circuit coupled to the memory array, the peripheral circuit comprising a voltage stabilizing circuit, the voltage stabilizing circuit being configured to provide a bias voltage to the memory array, the voltage stabilizing circuit comprising: a first voltage divider circuit, wherein a first end of the first voltage divider circuit is used to input a first voltage, a second end of the first voltage divider circuit is coupled to a ground end, the first voltage divider circuit is configured to provide an adjustment voltage to a second voltage divider circuit according to the first voltage, a second voltage divider circuit, wherein a first end of the second voltage divider circuit is used to input a second voltage, a second end of the second voltage divider circuit is coupled to a ground end, a third end of the second voltage divider circuit is coupled to a voltage modulation circuit, and a fourth end of the second voltage divider circuit is coupled to the first voltage divider circuit, wherein the second voltage divider circuit is configured to adjust the voltage of a reference voltage provided to the voltage modulation circuit according to the second voltage and the adjustment voltage, and a voltage modulation circuit, wherein the voltage modulation circuit is configured to output a bias voltage according to the reference voltage.
[0005] In some embodiments, the first voltage divider circuit includes a first resistor string, a first transistor and a first switch circuit, the first resistor string includes N resistor units connected in series in sequence, an Mth voltage node is arranged between the N-1th resistor unit and the Nth resistor unit, the first end of the first transistor is coupled to the first end of the first voltage divider circuit, and the second end of the first transistor is coupled to the first end of the first resistor string; the second end of the first resistor string is coupled to the second end of the first voltage divider circuit, the first end of the first switch circuit is coupled to the voltage node of any one of the first resistor strings, and the second end of the first switch circuit is coupled to the fourth end of the second voltage divider circuit.
[0006] In some embodiments, the first switching circuit includes a second transistor, the first end of the second transistor is coupled to the first end of the first switching circuit, and the second end of the second transistor is coupled to the second end of the first switching circuit; the first switching circuit is configured to: when providing an adjustment voltage to the second voltage divider circuit, connect the voltage node of any one of the first resistor strings and the fourth end of the second voltage divider circuit.
[0007] In some embodiments, there is at least one second transistor, and the first end of each second transistor is coupled to a voltage node of a different first resistor string. When different second transistors are turned on, different adjustment voltages are provided to the second voltage divider circuit.
[0008] In some embodiments, the first voltage and the second voltage satisfy:
[0009] VO=a*V1+b*V2
[0010] Wherein, VO is the reference voltage, V1 is the first voltage, V2 is the second voltage, a is the adjustment coefficient of the first voltage divider circuit, and b is the adjustment coefficient of the second voltage divider circuit.
[0011] In some embodiments, the second voltage divider circuit includes a second resistor string, a third transistor, a fourth transistor and a second switch circuit, the second resistor string includes N resistor units connected in series in sequence, and an Mth voltage node is arranged between the N-1th resistor unit and the Nth resistor unit; the first end of the third transistor is coupled to the first end of the second voltage divider circuit, and the second end of the third transistor is coupled to the first end of the second resistor string; the first end of the fourth transistor and the second end of the second resistor string are coupled to the fourth end of the second voltage divider circuit, and the second end of the fourth transistor is coupled to the second end of the second voltage divider circuit; the first end of the second switch circuit is coupled to the voltage node of any one of the second resistor strings, and the second end of the second switch circuit is coupled to the third end of the second voltage divider circuit.
[0012] In some embodiments, the second switching circuit includes a fifth transistor, the first end of the fifth transistor is coupled to the first end of the second switching circuit, the second end of the fifth transistor is coupled to the second end of the second switching circuit, and the second switching circuit is configured to: when providing a reference voltage to the voltage modulation circuit, connect the voltage node of any one of the second resistor strings with the voltage modulation circuit.
[0013] In some embodiments, the number of the fifth transistor is one or more.
[0014] In some embodiments, the number of the second switch circuit is one or more.
[0015] In some embodiments, the voltage modulation circuit includes: a sixth transistor, the first end of the sixth transistor is used to input a third voltage, and the second end of the sixth transistor is used to output a bias voltage; and a third resistor string, the first end of the third resistor string is coupled to the second end of the sixth transistor, the second end of the third resistor string is coupled to the ground end, the third end of the third resistor string is coupled to the first input end of the error amplifier, a compensation capacitor, the first end of the compensation capacitor is coupled to the second end of the sixth transistor, the second end of the compensation capacitor is coupled to the ground end, the second input end of the error amplifier is coupled to the third end of the second voltage divider circuit, and the output end of the error amplifier is coupled to the controlled end of the sixth transistor.
[0016] In some embodiments, the first voltage is less than the second voltage.
[0017] In some embodiments, the first voltage is provided by a first voltage source, and the second voltage is provided by a second voltage source or a third voltage source.
[0018] In some embodiments, the number of the first voltage divider circuit is one or more.
[0019] In a second aspect, a memory system is provided. The memory system includes a memory controller and the memory according to the first aspect. The memory controller is configured to control the memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 A block diagram of an electronic device provided for an embodiment of the present disclosure;
[0021] Figure 2 A block diagram of a storage system provided in an embodiment of the present disclosure;
[0022] Figure 3 A block diagram of a memory provided for an embodiment of the present disclosure;
[0023] Figure 4 A block diagram of a peripheral circuit provided for an embodiment of the present disclosure;
[0024] Figure 5 A circuit diagram of a voltage stabilizing circuit provided in an embodiment of the present disclosure;
[0025] Figure 6 A circuit diagram of another voltage stabilizing circuit provided in an embodiment of the present disclosure;
[0026] Figure 7 A circuit diagram of another voltage stabilizing circuit provided in an embodiment of the present disclosure;
[0027] Figure 8 A circuit diagram of another voltage stabilizing circuit provided in an embodiment of the present disclosure;
[0028] Figure 9A circuit diagram of another voltage stabilizing circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0029] The following will be combined with the figures to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.
[0030] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.
[0031] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
[0032] When describing some embodiments, the term "coupled" and its derivatives may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.
[0033] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C,” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
[0034] "A and / or B" includes the following three combinations: A only, B only, and the combination of A and B. The use of "suitable for" or "configured to" herein is intended to be open and inclusive, and does not exclude devices that are suitable for or configured to perform additional tasks or steps. Furthermore, the use of "based on" is intended to be open and inclusive, as a process, step, calculation, or other action "based on" one or more conditions or values may, in practice, be based on additional conditions or values beyond those specified.
[0035] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.
[0036] The embodiments of the present disclosure provide an electronic device, which may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc. Figure 1 , Figure 1 A schematic diagram of an electronic device 10 provided in an embodiment of the present disclosure is shown. The electronic device 10 includes a host 100 and a storage system 110. The host 100 is coupled to the storage system 110 to write data to the storage system 110 or read data stored in the storage system 110. The host is also called a master device, and the storage system is also called a slave device. In an electronic device, a slave device can be accessed by different master devices. For example, taking a mobile phone as an example, the central processing unit (CPU) and digital signal processing (DSP) of the mobile phone can all access the storage system as hosts.
[0037] For example, see Figure 2 , Figure 2 FIG1 shows a schematic diagram of a storage system 110 provided in an embodiment of the present disclosure. The storage system 110 includes a memory controller 111 and a memory 112. The memory controller 111 is coupled to the memory 112 to control the memory 112 to store data. The memory 112 can be a two-dimensional (2D) memory or a three-dimensional (3D) memory.
[0038] The storage system 110 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package). That is, the storage system 110 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.
[0039] In some embodiments, the storage system 110 includes a memory controller 111 and multiple memories 112. The storage system 110 may be integrated into a memory card. The memory card includes any one of a personal computer memory card international association (PCMCIA) card (abbreviated as PC card), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital-memory (SD) card, and a UFS.
[0040] Figure 3 1 shows a schematic diagram of a memory 112, which may include a peripheral circuit 200 and a memory array 300.
[0041] Figure 4 FIG. 3 shows a schematic structural diagram of a memory array 300 and a peripheral circuit 200 . Figure 4 In the embodiment, the peripheral circuit 200 includes an I / O interface 210, a control logic unit 220, a row decoder 230, a voltage generator 240, a column decoder 260, a page buffer 250, a data bus 270 and a register 280. It should be understood that in some examples, the peripheral circuit 200 may also include Figure 4 Additional circuitry not shown.
[0042] The I / O interface 210 may be coupled to the control logic unit 220 and act as a control buffer to buffer data from a memory controller (eg, Figure 2The I / O interface 210 receives control commands received from the memory controller 111 in the memory array 300 and relays them to the control logic unit 220, and buffers status information received from the control logic unit 220 and relays it to the host. The I / O interface 210 may also be coupled to the page buffer 250 via the data bus 270 and function as both a data I / O interface 210 and a data buffer to buffer data and relay it to or from the memory array 300.
[0043] The control logic unit 220 may be coupled to the voltage generator 240, the page buffer 250, the column decoder 260, the row decoder 230, and the I / O interface 210, and may be configured to control the operation of the various peripheral circuits. The control logic unit 220 may generate an operation signal to control the operation of the row decoder 230, the column decoder 260, the page buffer 250, and the voltage generator 240 in response to a command (CMD) or control signal from the memory controller 111; the command may be a program command, a read command, or the like.
[0044] The row decoder 230 may supply the word line voltage generated from the voltage generator 240 to the selected word lines and unselected word lines of the memory array 300 in response to the control of the control logic unit 220. As described in detail below, the row decoder 230 is configured to perform a program operation on the memory cells coupled to one or more selected word lines in the memory cell array 300.
[0045] The voltage generator 240 may use an external power supply voltage or an internal power supply voltage to generate various voltages for performing operations such as erasing, programming, reading, and verifying on the memory array 300 .
[0046] The column decoder 260 may be controlled in response to the control logic unit 220 and select one or more memory cell strings 310 in the memory array 300 by applying a bit line voltage generated from the voltage generator 240 .
[0047] The page buffer 250 can read data from the memory array 300 and program (write) data to the memory array 300 according to the control signal from the control logic unit 220. In one example, the page buffer 250 can store the program data (write data) to be programmed into the memory array 300. In another example, the page buffer 250 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cells coupled to the selected word line. In yet another example, the page buffer 250 can also detect a low-power signal from the bit line representing the data bit stored in the memory cell and amplify the small voltage swing to a recognizable logic level during a read operation.
[0048] The register 280 may be coupled to the control logic unit 220 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.
[0049] Those skilled in the art will appreciate that the operations performed by the row decoder 230, the page buffer 250, the control logic unit 220, and the voltage generator 240 described in this disclosure may be performed by a processing circuit. The processing circuit may include, but is not limited to, hardware such as a logic circuit or a hardware / software combination such as a processor that executes software.
[0050] In one feasible embodiment, voltage generator 240 may include a voltage stabilization circuit 2401. When voltage generator 240 provides a bias voltage to the memory array, voltage stabilization circuit 2401 can convert a high voltage input into a stable low voltage output. For example, voltage stabilization circuit 2401 can be a low-dropout linear regulator (LDO), which is a circuit that converts a high input voltage into a low, stable output voltage. When the load at the output of the voltage stabilization circuit remains unchanged, but the bias voltage needs to be increased or decreased to improve the output performance, this can be achieved by adjusting the reference voltage.
[0051] In one possible implementation, when adjusting the reference voltage, a fixed adjustment step size can be used. The adjustment step size refers to the amount by which the reference voltage changes during each adjustment operation. For example, the adjustment step size can be 0.5V, so the reference voltage can be adjusted from 2.0V to 1.5V, and then from 1.5V to 1.0V.
[0052] However, a fixed adjustment step size may not provide sufficient accuracy, especially when a very precise output value is required. Secondly, sometimes more bits may be needed to represent and process the small changes brought about by such fixed-step adjustments to obtain accurate results. For example, the reference voltage is 2V and the adjustment step size is 0.5V. If the output value needs to be adjusted to 5.3V, multiple adjustments may be required to reach the target value, because each adjustment can only change the output value by 0.5V. Moreover, if the output value needs to be adjusted more precisely, such as to 2.32V, more steps and smaller adjustment steps may be required, which increases the complexity and time cost of the adjustment. Therefore, the fixed adjustment step size adjustment method may not be sufficient to meet the output accuracy and stability requirements of some applications, especially in scenarios where small adjustments or high-precision output are required.
[0053] See Figure 5 , the overall structure of the voltage stabilizing circuit provided by the present disclosure is described, see Figure 5The voltage stabilization circuit can be divided into three sub-circuits, including a first voltage divider circuit, a second voltage divider circuit, and a voltage modulation circuit. The first voltage divider circuit can be a multi-terminal device, wherein a first terminal (S1A) of the first voltage divider circuit can be connected to a first voltage source (VP1), the first terminal (S1A) of the first voltage divider circuit being used to input a first voltage, a second terminal (S1B) of the first voltage divider circuit being connected to a ground terminal (GND), and a third terminal (S1C) of the first voltage divider circuit being connected to the second voltage divider circuit.
[0054] The primary function of the first voltage divider circuit may be to provide an adjustment voltage to the second voltage divider circuit based on a first voltage inputted at its first terminal (S1A), thereby raising the voltage at the connection node between the second voltage divider circuit and the first voltage divider circuit. The first voltage divider circuit adjusts the voltage at the connection node based on the inputted first voltage, thereby achieving precise control of the voltage at the connection node.
[0055] The second voltage divider circuit can be a multi-terminal device, and the first terminal (S2A) of the second voltage divider circuit can be used to input a second voltage, which can be provided by a second voltage source (VP2) or a third voltage source (VP3), that is, at the same time, only one of the second voltage source (VP2) and the third voltage source (VP3) is in the connected state. The first terminal (S2A) of the second voltage divider circuit can be connected to the output terminal (VP2) of the second voltage source and the output terminal (VP3) of the third voltage source for inputting the second voltage. The second terminal (S2B) of the second voltage divider circuit can be connected to the ground terminal (GND), the third terminal (S2C) of the second voltage divider circuit is connected to the voltage modulation circuit for providing a reference voltage to the voltage modulation circuit, and the fourth terminal (S2D) of the second voltage divider circuit is connected to the third terminal (S1C) of the first voltage divider circuit.
[0056] The second voltage divider circuit may mainly function to adjust the reference voltage provided to the voltage modulation circuit according to the second voltage input to the first terminal ( S2A) thereof and the adjustment voltage provided by the first voltage divider circuit.
[0057] The voltage modulation circuit can be a multi-terminal device for providing a bias voltage to the memory array based on a reference voltage provided by the second voltage divider circuit. A first terminal (S3A) of the voltage modulation circuit can be used to input a modulation voltage, a second terminal (S3B) of the voltage modulation circuit can be connected to a ground terminal (GND), a third terminal (S3C) of the voltage modulation circuit can be connected to a third terminal (S2C) of the second voltage divider circuit for inputting a reference voltage, and a fourth terminal (S3D) of the voltage modulation circuit can be connected to a load terminal for outputting a bias voltage. The main function of the voltage modulation circuit can be to adjust the bias voltage provided to the memory array based on the reference voltage input to its third terminal (S2C).
[0058] The following will be combined Figure 6, for a detailed description of the structure and working principle of the first voltage divider circuit, see Figure 6 The first voltage divider circuit may include a first resistor string, a first transistor, and a first switch circuit. The first resistor string includes a plurality of resistor units connected in series, with a voltage node provided between any two adjacent resistor units. For example, a first voltage node is provided between the first resistor unit and the second resistor unit, and a second voltage node is provided between the second resistor unit and the third resistor unit. The first transistor may be an N-channel MOS transistor or a P-channel MOS transistor. For the purpose of illustration, the first transistor is an N-channel MOS transistor. The drain (Q1A) of the first transistor is coupled to the first terminal (S1A) of the first voltage divider circuit, the source (Q1B) of the first transistor is coupled to the first terminal of the first resistor string, the gate of the first transistor is connected to the control terminal, and the first transistor is in an on state when the voltage difference between the gate and the source is greater than or equal to a threshold voltage. The second terminal of the first resistor string is coupled to the second terminal (S1B) of the first voltage divider circuit. The first terminal of the first switch circuit may be coupled to any voltage node on the first resistor string, and the second terminal of the first switch circuit is coupled to the fourth terminal (S2D) of the second voltage divider circuit and the third terminal (S1C) of the first voltage divider circuit. The first switch circuit is used to control the on / off state of the connection between the first voltage divider circuit and the second voltage divider circuit. That is, the first switch circuit can be configured to connect the voltage node of any one of the first resistor strings to the fourth terminal (S2D) of the second voltage divider circuit when providing an adjustment voltage to the second voltage divider circuit.
[0059] The first switch circuit can have multiple circuit implementation methods. In a feasible embodiment, the first switch circuit may include a second transistor. The second transistor may be an N-channel MOS transistor or a P-channel MOS transistor. The second transistor is described as an N-channel MOS transistor. The drain (Q2A) of the second transistor is coupled to the first end of the first switch circuit, the source (Q2B) of the second transistor is coupled to the second end of the first switch circuit, the gate of the second transistor is connected to the control end, and the second transistor is in an on state when the voltage difference between the gate and the source is greater than or equal to the threshold voltage.
[0060] We will continue to combine Figure 6 , for a detailed description of the structure and working principle of the second voltage divider circuit, see Figure 6The second voltage divider circuit may include a second resistor string, a third transistor, a fourth transistor, and a second switch circuit. The second resistor string includes a plurality of resistor units connected in series, with a voltage node provided between any two adjacent resistor units. For example, a first voltage node is provided between the first resistor unit and the second resistor unit from top to bottom, and a second voltage node is provided between the second resistor unit and the third resistor unit. The third transistor may be an N-channel MOS transistor or a P-channel MOS transistor. The third transistor is described as an N-channel MOS transistor. The drain (Q3A) of the third transistor is coupled to the first end (S2A) of the second voltage divider circuit, and the source (Q3B) of the third transistor is coupled to the first end of the second resistor string. The drain (Q4A) of the fourth transistor and the second end of the second resistor string are coupled to the fourth end (S2D) of the second voltage divider circuit. The fourth transistor can be an N-channel MOS transistor or a P-channel MOS transistor. The fourth transistor is described as an N-channel MOS transistor. The source (Q4B) of the fourth transistor is coupled to the second end (S2B) of the second voltage divider circuit. The first end of the second switch circuit is coupled to the voltage node of any second resistor string, and the second end of the second switch circuit is coupled to the third end (S2C) of the second voltage divider circuit. The second switch circuit is used to control the on / off state of the connection between the second voltage divider circuit and the voltage modulation circuit. That is, the second switch circuit is configured to conduct the voltage node of any second resistor string and the third end (S3C) of the voltage modulation circuit when providing a reference voltage to the voltage modulation circuit.
[0061] The second switch circuit can have multiple circuit implementation methods. In a feasible implementation, the second switch circuit may include a fifth transistor. The fifth transistor may be an N-channel MOS transistor or a P-channel MOS transistor. The fifth transistor is described as an N-channel MOS transistor. The drain (Q5A) of the fifth transistor is coupled to the first end of the second switch circuit, and the source (Q5B) of the fifth transistor is coupled to the second end of the second switch circuit. The fifth transistor is in an on state when the voltage difference between the gate and the source is greater than or equal to the threshold voltage.
[0062] We will continue to combine Figure 6 , for a detailed description of the structure and working principle of the voltage modulation circuit, see Figure 6The voltage modulation circuit may include: a sixth transistor, which may be an N-channel MOS transistor or a P-channel MOS transistor. The sixth transistor is described as an N-channel MOS transistor. The gate (Q6C) of the sixth transistor is used to connect to the output terminal of the error amplifier, and the source (Q6B) of the sixth transistor is used to output a bias voltage. A third resistor string, wherein the first end of the third resistor string is coupled to the source (Q6B) of the sixth transistor, and the second end of the third resistor string is coupled to the ground terminal (GND). A compensation capacitor, wherein the first end of the compensation capacitor is coupled to the source (Q6B) of the sixth transistor, and the second end of the compensation capacitor is coupled to the ground terminal (GND); the second input terminal of the error amplifier is coupled to the third end (S3C) of the voltage modulation circuit, and the first input terminal of the error amplifier is coupled to the third end of the third resistor string. The compensation capacitor can suppress resonance, thereby improving the stability and response speed of the entire voltage stabilization circuit.
[0063] In the voltage modulation circuit, the third resistor string can be used to collect the voltage output from the source of the sixth transistor and feed the collected voltage back to the error amplifier. The error amplifier can be used to compare the voltage fed back from the third resistor string with a reference voltage and then adjust the control voltage provided to the sixth transistor based on the comparison result. Through closed-loop voltage feedback control, the voltage output by the sixth transistor has high stability.
[0064] When the output end (Vout) of the voltage modulation circuit causes the voltage to drop due to load changes, the voltage across the third resistor string will also drop, thereby causing the voltage at the midpoint of the third resistor string to drop. Furthermore, the error amplifier feeds back the voltage information of the midpoint of the third resistor string to the error amplifier. The error amplifier compares the potential of the midpoint of the third resistor string with the reference voltage of the first input end of the error amplifier. Then, the error amplifier increases the control voltage output to the sixth transistor, causing the source (Q6B) potential of the sixth transistor to rise, and the current of the sixth transistor will increase. The increase in the current of the sixth transistor will cause the voltage of the output end (Vout) of the voltage modulation circuit to rise, completing a feedback control, so that the output end (Vout) of the voltage modulation circuit returns to the normal potential.
[0065] When the voltage at the output end (Vout) of the voltage modulation circuit increases due to a load change, the voltage across the third resistor string will also increase, thereby causing the voltage at the midpoint of the third resistor string to increase. Furthermore, the error amplifier compares the potential at the midpoint of the third resistor string with the reference voltage at the first input end of the error amplifier. The error amplifier will reduce the control voltage output to the sixth transistor, causing the potential of the source (Q6B) of the sixth transistor to decrease, and the current of the sixth transistor will decrease. The decrease in the current of the sixth transistor will cause the voltage at the output end (Vout) of the voltage modulation circuit to decrease, completing a feedback control, so that the voltage at the output end (Vout) of the voltage modulation circuit returns to a normal potential.
[0066] When the number of the second transistor is one and the connection position with the voltage node on the first resistor string is fixed, the voltage value of the adjustment voltage provided by the first voltage divider circuit to the second voltage divider circuit is also fixed, so that the adjustment voltage provided by the first voltage divider circuit to the second voltage divider circuit is dynamically adjustable. In a feasible embodiment, refer to Figure 7 The number of second transistors can be multiple, and the drain of each second transistor can be coupled to a different voltage node on the first resistor string. When different second transistors are turned on, the first voltage divider circuit can provide different adjustment voltages to the second voltage divider circuit. For example, when the second transistor connected to the voltage node A on the first resistor string is turned on, and the other second transistors are not turned on, the adjustment voltage provided by the first voltage divider circuit to the second voltage divider circuit can be V A When the second transistor connected to the voltage node B on the first resistor string is turned on and the other second transistors are not turned on, the adjustment voltage provided by the first voltage divider circuit to the second voltage divider circuit can be V B .
[0067] By coupling different second transistors to different voltage nodes on the first resistor string, the first voltage divider circuit can provide different adjustment voltages as needed, so that the entire voltage divider circuit can adapt to different working conditions or application requirements. Secondly, by increasing the number of second transistors, the flexibility and scalability of the entire voltage divider circuit can be enhanced. When higher precision or a larger range is required, it can be met by increasing the number of transistors. In addition, since each second transistor can be controlled independently, more precise circuit control can be achieved.
[0068] When there is only one fifth transistor and its connection position with the voltage node on the second resistor string is fixed, the voltage value of the reference voltage provided by the second voltage divider circuit to the voltage modulation circuit is also fixed. In order to make the reference voltage provided by the second voltage divider circuit to the voltage modulation circuit flexible and adjustable, multiple fifth transistors can be provided.
[0069] In a feasible implementation, the number of the fifth transistor can be multiple. Figure 7 By coupling different fifth transistors to different voltage nodes on the second resistor string, the second voltage divider circuit can provide different reference voltages for the voltage modulation circuit according to its needs. By providing an adjustment voltage to the second voltage divider circuit through the first voltage divider circuit, the terminal voltage of the fourth end (S2D) of the second voltage divider circuit can be raised. Since the first voltage and the second voltage are different, there can be two adjustment steps when the voltage divider circuit provides a reference voltage to the voltage modulation circuit. In this way, when adjusting the reference voltage, the required voltage change can be achieved more quickly and accurately. Improve the response speed and stability of the entire voltage stabilization circuit, and provide a more reliable voltage regulation function for various application scenarios.
[0070] In a feasible implementation, one second switch circuit may correspond to one voltage modulation circuit, or multiple second switch circuits may correspond to one voltage modulation circuit. The reference voltage of one voltage modulation circuit may be adjusted jointly by the cooperation of multiple second switch circuits.
[0071] In a feasible implementation, the first voltage, the second voltage, and the reference voltage satisfy the relationship shown in formula (1).
[0072] VO=a*V1+b*V2(1)
[0073] In formula (1), VO is the reference voltage, V1 is the first voltage, V2 is the second voltage, a is the adjustment coefficient of the first voltage divider circuit, and b is the adjustment coefficient of the second voltage divider circuit.
[0074] When the fourth terminal (S2D) of the second voltage divider circuit is connected to different voltage nodes of the first resistor string, the corresponding adjustment coefficient a of the first voltage divider circuit is different. When the third terminal (S3C) of the voltage modulation circuit is connected to different voltage nodes of the second resistor string, the corresponding adjustment coefficient b of the second voltage divider circuit is different. By controlling the on and off states of different voltage nodes on the first and second voltage divider circuits, the voltage divider circuits can provide reference voltages with different adjustment steps to the voltage modulation circuit.
[0075] In a feasible embodiment, the first voltage is less than the second voltage. The first voltage is less than the second voltage, that is, the voltage adjustment granularity of the first voltage divider circuit is less than the voltage adjustment granularity of the second voltage divider circuit, that is, the reference voltage is roughly adjusted by the second voltage divider circuit, and then the reference voltage is accurately adjusted by the first voltage divider circuit. Through the mutual cooperation of the first voltage divider circuit and the second voltage divider circuit, the reference voltage is accurately adjusted. For example, the first voltage can be 0.5V, the second voltage can be 3V, the voltage adjustment step size of the first voltage divider circuit can be 0.1V, and the voltage adjustment step size of the second voltage divider circuit can be 0.5V. If the reference voltage needs to be adjusted from 1.5V to 3.1V, the reference voltage can be adjusted from 1.5V to 3.0V by first adjusting the connection status of the voltage modulation circuit and the voltage node of the second resistor string, and then adjusting the reference voltage from 3.0V to 3.1V by adjusting the connection status of the second voltage divider circuit and the voltage node of the first resistor string.
[0076] First, the reference voltage is roughly adjusted through the second voltage divider circuit. Its larger voltage adjustment step size allows the voltage to be quickly adjusted to a value close to the target value, thereby reducing the time consumption of the overall adjustment. Secondly, the reference voltage is precisely adjusted through the first voltage divider circuit. Its smaller voltage adjustment step size allows fine-tuning when it is close to the target value, ensuring the accuracy and stability of the reference voltage and meeting the high-precision requirements for circuit performance. This not only improves the efficiency of adjustment, but also ensures the accuracy of adjustment, allowing the circuit to operate stably and reliably in different working scenarios. At the same time, by coordinating the adjustment circuits, the stability and reliability of the system are also enhanced, and the overall performance of the circuit is improved.
[0077] In order to provide reference voltages for multiple voltage modulation circuits at the same time, in a feasible implementation, refer to Figure 8 , the number of the second switching circuit is one or more.
[0078] By matching the number of second switching circuits with the number of voltage modulation circuits, each voltage modulation circuit can be guaranteed to have a corresponding switching circuit to control its reference voltage supply. This allows different reference voltages to be provided to multiple voltage modulation circuits simultaneously without interfering with or affecting each other. This parallel reference voltage supply approach improves system efficiency and performance, while also enhancing the system's suitability and flexibility for multi-channel or multi-path signal processing, thereby better meeting the needs of various application scenarios.
[0079] In order to achieve more accurate adjustment of the reference voltage, in a feasible implementation, refer to Figure 9The number of the first voltage divider circuits may be one or more. The voltage adjustment step size of each first voltage divider circuit may be different, and the step adjustment levels of each first voltage divider circuit may be the same or different. By combining different voltage adjustment step sizes, a more precise adjustment of the reference voltage can be achieved.
[0080] For example, there are two first voltage divider circuits A and B. The voltage adjustment step of the first voltage divider circuit A can be 0.03V, the voltage adjustment step of the first voltage divider circuit B can be 0.02V, and the voltage adjustment step of the second voltage divider circuit can be 0.5V. If the reference voltage needs to be adjusted from 1.5V to 3.05V, the reference voltage can be adjusted from 1.5V to 3.0V by first adjusting the connection status of the voltage modulation circuit and the voltage node of the second resistor string, and then adjusting the reference voltage from 3.0V to 3.03V by adjusting the connection status of the voltage node of the first resistor string of the first voltage divider circuit A, and then adjusting the reference voltage from 3.03V to 3.05V by adjusting the connection status of the voltage node of the first resistor string of the first voltage divider circuit B.
[0081] The memory provided by the embodiment of the present disclosure achieves more precise adjustment of the reference voltage provided by the entire voltage divider circuit through the cooperation between voltage divider circuits with different voltage adjustment steps, thereby achieving precise adjustment of the bias voltage output by the regulator, making the adjustment process more flexible and precise while also improving the adjustment speed, and can meet the requirements for the bias voltage output by the regulator in different application scenarios.
[0082] The present disclosure also provides a storage system. For example, the storage system includes the memory and the controller as described in the above embodiment, and the memory is coupled to the controller. Figure 2 The storage system shown.
[0083] The present disclosure also provides an electronic device, which includes a host and the aforementioned storage system, wherein the host and the storage system are connected. Figure 1 The electronic device shown.
[0084] Those skilled in the art will clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases. For the parts that are not described in detail in a certain embodiment, reference can be made to the corresponding process in the aforementioned method embodiment and will not be repeated here.
[0085] It should be understood that the embodiments provided herein can be implemented in other ways. For example, the division of a module is merely a logical functional division, and in actual implementation, other division methods may be used, such as multiple units or components may not be combined or may be integrated into another system, or some features may be ignored or not implemented.
[0086] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.
[0087] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.
Claims
1. A memory, characterized in that: The device comprises a memory array and a peripheral circuit coupled to the memory array, wherein the peripheral circuit comprises a voltage stabilizing circuit; The voltage stabilization circuit is configured to provide a bias voltage to the memory array; The voltage stabilizing circuit comprises: a first voltage divider circuit, wherein a first terminal of the first voltage divider circuit is used to input a first voltage, a second terminal of the first voltage divider circuit is coupled to a ground terminal, and the first voltage divider circuit is configured to provide an adjustment voltage to a second voltage divider circuit according to the first voltage; a second voltage divider circuit, wherein a first terminal of the second voltage divider circuit is used to input a second voltage, a second terminal of the second voltage divider circuit is coupled to a ground terminal, a third terminal of the second voltage divider circuit is coupled to a voltage modulation circuit, and a fourth terminal of the second voltage divider circuit is coupled to the first voltage divider circuit; wherein the second voltage divider circuit is configured to adjust a voltage of a reference voltage provided to the voltage modulation circuit according to the second voltage and the adjustment voltage; A voltage modulation circuit is configured to output the bias voltage according to the reference voltage.
2. The memory according to claim 1, wherein The first voltage divider circuit includes a first resistor string, a first transistor, and a first switch circuit, wherein the first resistor string includes N resistor units connected in series, and an Mth voltage node is provided between the N-1th resistor unit and the Nth resistor unit; A first terminal of the first transistor is coupled to a first terminal of the first voltage divider circuit, and a second terminal of the first transistor is coupled to a first terminal of the first resistor string; The second end of the first resistor string is coupled to the second end of the first voltage divider circuit; A first end of the first switch circuit is coupled to a voltage node of any one of the first resistor strings, and a second end of the first switch circuit is coupled to a fourth end of the second voltage divider circuit.
3. The memory according to claim 2, wherein: The first switch circuit includes a second transistor, a first terminal of the second transistor is coupled to the first terminal of the first switch circuit, and a second terminal of the second transistor is coupled to the second terminal of the first switch circuit; The first switching circuit is configured as follows: When the adjustment voltage is provided to the second voltage-dividing circuit, the voltage node of any one of the first resistor strings is connected to the fourth end of the second voltage-dividing circuit.
4. The memory according to claim 3, wherein: There is at least one second transistor, and a first end of each second transistor is coupled to a different voltage node of the first resistor string. When different second transistors are turned on, different adjustment voltages are provided to the second voltage divider circuit.
5. The memory according to any one of claims 1 to 4, characterized in that: The first voltage and the second voltage satisfy: VO=a*V1+b*V2 In the formula, VO is the reference voltage, V1 is the first voltage, V2 is the second voltage, a is the adjustment coefficient of the first voltage divider circuit, and b is the adjustment coefficient of the second voltage divider circuit. The memory according to claim 1 , wherein: The second voltage divider circuit includes a second resistor string, a third transistor, a fourth transistor, and a second switch circuit, wherein the second resistor string includes N resistor units connected in series, and an Mth voltage node is provided between the N-1th resistor unit and the Nth resistor unit; A first terminal of the third transistor is coupled to a first terminal of the second voltage divider circuit, and a second terminal of the third transistor is coupled to a first terminal of the second resistor string; The first terminal of the fourth transistor and the second terminal of the second resistor string are coupled to the fourth terminal of the second voltage divider circuit, and the second terminal of the fourth transistor is coupled to the second terminal of the second voltage divider circuit; A first terminal of the second switch circuit is coupled to a voltage node of any one of the second resistor strings, and a second terminal of the second switch circuit is coupled to a third terminal of the second voltage divider circuit.
7. The memory according to claim 6, wherein: The second switch circuit includes a fifth transistor, a first terminal of the fifth transistor is coupled to the first terminal of the second switch circuit, and a second terminal of the fifth transistor is coupled to the second terminal of the second switch circuit; The second switching circuit is configured as follows: When a reference voltage is provided to the voltage modulation circuit, a voltage node of any one of the second resistor strings is connected to the voltage modulation circuit.
8. The memory according to claim 7, wherein: The number of the fifth transistor is one or more.
9. The memory according to claim 8, wherein: The number of the second switch circuit is one or more.
10. The memory according to any one of claims 1 to 9, characterized in that: The voltage modulation circuit comprises: a sixth transistor, a first terminal of the sixth transistor being configured to input a third voltage, and a second terminal of the sixth transistor being configured to output the bias voltage; and a third resistor string, wherein a first end of the third resistor string is coupled to the second end of the sixth transistor, a second end of the third resistor string is coupled to the ground, and a third end of the third resistor string is coupled to the first input end of the error amplifier; a compensation capacitor, wherein a first end of the compensation capacitor is coupled to the second end of the sixth transistor, and a second end of the compensation capacitor is coupled to the ground end; The second input terminal of the error amplifier is coupled to the third terminal of the second voltage divider circuit, and the output terminal of the error amplifier is coupled to the controlled terminal of the sixth transistor.
11. The memory according to any one of claims 1 to 9, characterized in that: The first voltage is lower than the second voltage.
12. The memory according to claim 11, wherein: The first voltage is provided by a first voltage source, and the second voltage is provided by a second voltage source or a third voltage source.
13. The memory according to any one of claims 1 to 9, characterized in that: The number of the first voltage divider circuit is one or more.
14. A storage system, characterized in that: The invention comprises a memory controller and the memory according to any one of claims 1 to 13, wherein the memory controller is configured to control the memory.