Laminated ceramic electronic component

Abstract

The present invention provides a laminated ceramic electronic component capable of suppressing the occurrence of interface peeling. In an LT cross-section, the first lead-out portion has a bent portion. If a straight line which is a tangent line to the first end surface and extends parallel to the stacking direction is set as a first end surface-side reference line, a straight line which is a tangent line to the first main surface and extends parallel to the longitudinal direction is set as a first main surface-side reference line, and the distance between the bent portion and the first end surface-side reference line is set as x, x is a positive integer greater than or equal to 1. The distance between the bent portion and the first main surface side reference line is set as y, and a region on the first main surface side and on the first end surface side among regions divided into four parts by a straight line passing through the central portion of the laminate in the lamination direction and a straight line passing through the central portion of the laminate in the longitudinal direction is set as a first reference region. When a regression line derived on the basis of x and y values relating to the curved portion in the first reference region is defined as a virtual connecting line, the virtual connecting line intersects the effective layer portion.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component. Background Art

[0002] Conventionally, multilayer ceramic capacitors are known as multilayer ceramic electronic components. Generally speaking, a multilayer ceramic capacitor comprises a laminated body composed of a plurality of dielectric layers and internal electrode layers alternately stacked, and external electrodes disposed on both end surfaces of the laminated body. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the aforementioned structure, wherein the external electrodes include a base electrode layer formed by sintering.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2003-243249

[0006] In multilayer ceramic capacitors, for example, during the dicing process of the laminated chips, internal electrodes may peel off from adjacent dielectrics (a phenomenon known as "interfacial peeling"). This interfacial peeling reduces product yield. Summary of the Invention

[0007] Problems to be solved by the invention

[0008] An object of the present invention is to provide a multilayer ceramic electronic component capable of suppressing the occurrence of interface delamination.

[0009] Technical solutions to solve problems

[0010] In order to solve the above-mentioned problems, the multilayer ceramic electronic component of the present invention comprises: a stacked body having an inner layer portion including alternately stacked ceramic layers and internal electrodes, a first main surface and a second main surface opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a width direction which is a direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction which is a direction perpendicular to the stacking direction and the width direction; and external electrodes arranged in pairs on each of the end surfaces, wherein the internal electrodes have opposing portions opposing adjacent internal electrodes in the stacking direction. , and a lead portion led out from the opposing portion and connected to the external electrode, the stacked body having an effective layer portion, the effective layer portion including each of the opposing portions and a portion of each of the ceramic layers sandwiched by the adjacent opposing portions, if the direction of each of the main surfaces observed from the center of the stacked direction in the stacking direction is set as the outside of the stacking direction, the direction of the center of the stacked direction in the stacked direction is set as the center side of the stacking direction, and the section parallel to the stacking direction and the longitudinal direction is set as the LT section, then in the LT section In the surface, the lead portion has a first inclined portion that is led out from the opposing portion and inclined toward the center side of the stacking direction as it moves from the opposing portion side toward the side separated from the opposing portion, a second inclined portion that extends from the first inclined portion to the side separated from the opposing portion and inclined toward the outside of the stacking direction as it moves from the opposing portion side toward the side separated from the opposing portion, and a bent portion connecting the first inclined portion and the second inclined portion. If a straight line that is a tangent to the end face and extends parallel to the stacking direction is set as an end face side reference line, a straight line that is a tangent to the main surface and extends parallel to the long side is set as a reference line on the end face side. A straight line extending parallel to the degree direction is set as the main surface side reference line, the distance between the bent portion and the end surface side reference line is set as x, the distance between the bent portion and the main surface side reference line is set as y, one of the areas in the stacked body divided into four parts by a straight line passing through the central part in the stacking direction of the stacked body and a straight line passing through the central part in the length direction of the stacked body is set as a reference area, and a regression straight line derived based on the values ​​of x and y related to the bent portion in the reference area is set as an imaginary connecting line, and the imaginary connecting line intersects with the effective layer portion.

[0011] Effects of the Invention

[0012] According to the present invention, it is possible to provide a multilayer ceramic electronic component capable of suppressing the occurrence of interface delamination. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic perspective view of a multilayer ceramic capacitor according to the first embodiment.

[0014] Figure 2 yes Figure 1 II-II sectional view.

[0015] Figure 3 yes Figure 2 An enlarged view of the vicinity of the first benchmark area in FIG.

[0016] Figure 4 is a diagram showing a multilayer ceramic capacitor according to a second embodiment. Figure 2 The corresponding figure.

[0017] Figure 5 is a diagram showing a multilayer ceramic capacitor according to a third embodiment. Figure 3 The corresponding figure.

[0018] Description of Reference Numerals

[0019] 1: Multilayer ceramic capacitor;

[0020] 2: laminate;

[0021] 3: external electrode;

[0022] 10: effective layer;

[0023] 14: dielectric layer (ceramic layer);

[0024] 15: internal electrode;

[0025] 16: Opposing part;

[0026] 17A: 1st lead-out portion (lead-out portion);

[0027] 17B: 2nd lead-out portion (lead-out portion);

[0028] 18A: 1st inclined portion;

[0029] 19A: second inclined portion;

[0030] 20A: bending part;

[0031] 21A: outermost curved portion;

[0032] 151A: outermost inner electrode on the first main surface side (outermost inner electrode);

[0033] 151B: outermost inner electrode on the second main surface side (outermost inner electrode);

[0034] AA: 1st main side;

[0035] AB: 2nd main side;

[0036] BA: lateral aspect 1;

[0037] BB: lateral 2;

[0038] CA: 1st end face;

[0039] CB: 2nd end face;

[0040] A1: 1st benchmark area (benchmark area);

[0041] A2: 2nd benchmark area (benchmark area);

[0042] A3: 3rd benchmark area (benchmark area);

[0043] A4: 4th benchmark area (benchmark area);

[0044] LA1: 1st principal surface side reference line (principal surface side reference line);

[0045] LC1: The first end face side reference line (end face side reference line);

[0046] VL: Virtual Link Line. DETAILED DESCRIPTION

[0047] <First embodiment>

[0048] Below, refer to Figure 1 as well as Figure 2 A multilayer ceramic capacitor 1 according to a first embodiment of the present invention will be described. The multilayer ceramic capacitor 1 corresponds to a multilayer ceramic electronic component.

[0049] (Multilayer ceramic capacitor 1)

[0050] like Figure 1 As shown, a multilayer ceramic capacitor 1 is a so-called two-terminal multilayer ceramic capacitor. It includes a laminate 2 and a pair of external electrodes 3. The laminate 2 is a substantially rectangular parallelepiped with six external surfaces. The laminate 2 includes an inner layer 11 in which a dielectric layer 14 and internal electrodes 15 are stacked.

[0051] In this specification, the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 is referred to as the stacking direction T. One of the directions orthogonal to the stacking direction T is referred to as the longitudinal direction L. The directions orthogonal to the longitudinal direction L and the stacking direction T are referred to as the width direction W. The direction in the stacking direction T from the center of the stack 2 in the stacking direction T toward each principal surface A is referred to as the "stacking direction outer side T1," and the direction in the stacking direction T from each principal surface A toward the center of the stack 2 in the stacking direction T is referred to as the "stacking direction center side T2."

[0052] A cross section parallel to the stacking direction T and the longitudinal direction L is referred to as an “LT cross section”. Figure 2The cross section is a cross section passing through the center portion in the width direction W of the multilayer ceramic capacitor 1 .

[0053] Of the six outer surfaces of the laminate 2, a pair of outer surfaces disposed on both sides in the stacking direction T are referred to as the first principal surface AA and the second principal surface AB. A pair of outer surfaces extending in the stacking direction T and disposed on both sides in the width direction W are referred to as the first side surface BA and the second side surface BB. A pair of outer surfaces extending in the stacking direction T and disposed on both sides in the length direction L are referred to as the first end surface CA and the second end surface CB. The first principal surface AA and the second principal surface AB are sometimes collectively referred to as "each principal surface A." The first side surface BA and the second side surface BB are sometimes collectively referred to as "each side surface B." The first end surface CA and the second end surface CB are sometimes collectively referred to as "each end surface C."

[0054] In addition, a pair of external electrodes 3 is provided on each end surface C. The external electrodes 3 are arranged in the longitudinal direction L.

[0055] The lengthwise dimension L of the multilayer ceramic capacitor 1 is preferably 0.2 mm to 10 mm, more preferably 0.2 mm to 6 mm. The stacking dimension T of the multilayer ceramic capacitor 1 is preferably 0.05 mm to 10 mm, more preferably 0.1 mm to 5 mm. The widthwise dimension W of the multilayer ceramic capacitor 1 is preferably 0.1 mm to 10 mm, more preferably 0.1 mm to 5 mm.

[0056] (Laminate 2)

[0057] like Figure 2 As shown, the laminate 2 includes an inner layer portion 11 and a pair of outer layer portions 12 arranged to sandwich the inner layer portion 11 in the stacking direction T. The laminate 2 preferably has rounded corners and ridges. A corner is defined as a portion where three surfaces of the laminate intersect. A ridge is defined as a portion where two surfaces of the laminate intersect.

[0058] The longitudinal dimension L of the laminate 2 is preferably 0.2 mm or more and 10 mm or less, more preferably 0.2 mm or more and 6 mm or less. The stacking direction T dimension of the laminate 2 is preferably 0.05 mm or more and 10 mm or less, more preferably 0.1 mm or more and 5 mm or less. The width direction W dimension of the laminate 2 is preferably 0.1 mm or more and 10 mm or less, more preferably 0.1 mm or more and 5 mm or less.

[0059] (Inner layer 11)

[0060] The inner layer portion 11 includes a plurality of dielectric layers 14 as ceramic layers and a plurality of internal electrodes 15. The dielectric layers 14 and the internal electrodes 15 are alternately stacked.

[0061] Dielectric layer 14 is formed, for example, from a dielectric ceramic primarily composed of BaTiO3. The dielectric ceramic may also contain Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, and the like as minor components. The dimension T of dielectric layer 14 in the stacking direction is preferably 0.2 μm to 15 μm, and more preferably 0.5 μm to 2.0 μm.

[0062] The internal electrodes 15 are formed of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. The internal electrodes 15 include a plurality of first internal electrodes 15A and a plurality of second internal electrodes 15B. The first internal electrodes 15A are exposed only at the first end surface CA. The second internal electrodes 15B are exposed only at the second end surface CB. The first internal electrodes 15A and the second internal electrodes 15B are arranged alternately.

[0063] The first inner electrode 15A includes a first opposing portion 16A and a first lead portion 17A. The first opposing portion 16A is the portion of the first inner electrode 15A that opposes the adjacent second inner electrode 15B in the stacking direction T. The first opposing portion 16A is located in the center between the end faces C. The first lead portion 17A is the portion of the first inner electrode 15A that extends from the first opposing portion 16A toward the first end face CA. The first lead portion 17A is exposed on the first end face CA.

[0064] The second inner electrode 15B includes a second opposing portion 16B and a second lead portion 17B. The second opposing portion 16B is the portion of the second inner electrode 15B that opposes the adjacent first inner electrode 15A (first opposing portion 16A). The second opposing portion 16B is located in the center between the end faces C. The second lead portion 17B is the portion of the second inner electrode 15B that extends from the second opposing portion 16B toward the second end face CB. The second lead portion 17B is exposed on the second end face CB.

[0065] The first internal electrode 15A and the second internal electrode 15B may be collectively referred to as “internal electrodes 15 .” The first opposing portion 16A and the second opposing portion 16B may be collectively referred to as “opposing portion 16 .”

[0066] The dimension T in the stacking direction of the internal electrode 15 is preferably 0.2 μm to 2.0 μm. The total number of first internal electrodes 15A and second internal electrodes 15B is preferably 10 to 1000, more preferably 15 to 700.

[0067] The opposing portions 16 and the portions of the dielectric layer 14 sandwiched between adjacent opposing portions 16 are collectively referred to as the "effective layer portion 10." In other words, the laminate 2 includes the effective layer portion 10, which includes each opposing portion 16 and the portion of the dielectric layer 14 sandwiched between adjacent opposing portions 16. The effective layer portion 10 is the portion that contributes to the capacitance of the capacitor.

[0068] (Outer layer 12)

[0069] The outer layer portion 12 is formed of the same material as the dielectric layer 14 of the inner layer portion 11. Furthermore, the internal electrode 15 is not provided on the outer layer portion 12. The total number of dielectric layers 14 and outer layer portions 12 is preferably 10 or more and 1200 or less, and more preferably 15 or more and 700 or less.

[0070] (External electrode 3)

[0071] Each external electrode 3 is disposed on each end surface C. Each external electrode 3 covers not only the end surface C but also a portion of the main surface A and a portion of the side surface B. One of the first internal electrode 15A and the second internal electrode 15B is connected to each external electrode 3. The external electrodes 3 include a base electrode layer 31 formed in contact with the surface of the laminate 2, a first plating layer 32 disposed on the base electrode layer 31, and a second plating layer 33 disposed on the first plating layer 32.

[0072] The base electrode layer 31 is a sintered layer containing, for example, a conductive metal such as Cu (copper) and glass. The first plating layer 32 is, for example, a Ni (nickel) plating layer. The second plating layer 33 is, for example, a Sn (tin) plating layer.

[0073] The thickness of the portion of the foundation electrode layer 31 located on the end surface C is preferably 2 μm or more and 220 μm or less, more preferably 3 μm or more and 200 μm or less. The thickness of the portion of the foundation electrode layer 31 located on either the principal surface A or the side surface B is preferably 3 μm or more and 40 μm or less, more preferably 4 μm or more and 25 μm or less. The thickness of the first plating layer 32 and the thickness of the second plating layer 33 are each preferably 1 μm or more and 15 μm or less, more preferably 2 μm or more and 10 μm or less.

[0074] Alternatively, the external electrode 3 may include a conductive resin layer. In this case, the thickness of the conductive resin layer is preferably 10 μm to 150 μm. The base electrode layer 31 may also be a thin film layer such as a sputtered electrode. The base electrode layer 31 is not essential; for example, the first plating layer 32 may be disposed directly on the laminate 2.

[0075] Here, the laminate 2 is divided into four regions by a straight line passing through the center of the laminate 2 in the stacking direction T and a straight line passing through the center of the laminate 2 in the longitudinal direction L. Of these four regions, the region on the first principal surface AA side and the first end surface CA side is designated as the "first reference region A1," the region on the first principal surface AA side and the second end surface CB side is designated as the "second reference region A2," the region on the second principal surface AB side and the first end surface CA side is designated as the "third reference region A3," and the region on the second principal surface AB side and the second end surface CB side is designated as the "fourth reference region A4." The first reference region A1, the second reference region A2, the third reference region A3, and the fourth reference region A4 each correspond to a reference region.

[0076] The multilayer ceramic capacitor 1 has a substantially symmetrical structure when viewed in the longitudinal direction L. Therefore, the first reference area A1 and the second reference area A2 have a substantially symmetrical structure when viewed in the longitudinal direction L. The third reference area A3 and the fourth reference area A4 also have a substantially symmetrical structure when viewed in the longitudinal direction L.

[0077] like Figure 3 As shown, in the LT cross-section of the first reference area A1, the first lead-out portion 17A has: a first inclined portion 18A, which is led out from the first opposing portion 16A and inclined toward the center side T2 in the stacking direction as it moves from the side of the first opposing portion 16A toward the side separated from the first opposing portion 16A; a second inclined portion 19A, which extends from the first inclined portion 18A toward the side separated from the first opposing portion 16A and inclines toward the outer side T1 in the stacking direction as it moves from the side of the first opposing portion 16A toward the side separated from the first opposing portion 16A; and a bent portion 20A, which connects the first inclined portion 18A and the second inclined portion 19A.

[0078] A straight line that is a tangent to the first end surface CA and extends parallel to the stacking direction T is referred to as "first end surface side reference line LC1." A straight line that is a tangent to the first principal surface AA and extends parallel to the longitudinal direction L is referred to as "first principal surface side reference line LA1." The distance from the first end surface side reference line LC1 is referred to as "x." The distance from the first principal surface side reference line LA1 is referred to as "y." The position of the bent portion 20A can be expressed using x and y coordinates, respectively.

[0079] A regression line derived based on the x and y values ​​associated with the curved portion 20A in the first reference area A1 is referred to as a virtual connecting line VL. The least squares method is used as a method for deriving the regression line.

[0080] The imaginary connection line VL intersects the effective layer portion 10. Of the internal electrodes 15 adjacent in the stacking direction T, the bent portion 20A located closer to the effective layer portion 10 than the bent portion 20A located closer to the stacking direction outer side T1.

[0081] The imaginary connecting line VL only needs to intersect the effective layer portion 10 on the LT cross section and does not need to intersect the effective layer portion 10 within the first reference area A1. For example, the imaginary connecting line VL may intersect the effective layer portion 10 within the third reference area A3. Furthermore, the imaginary connecting line VL does not need to actually connect all of the curved portions 20A within the first reference area A1.

[0082] The bend 20A located most to the outside T1 in the stacking direction is referred to as the outermost bend 21A. The bend angle of the outermost bend 21A is smaller than the bend angle of the bend 20A located closer to the center T2 in the stacking direction than the outermost bend 21A. Figure 3 , the bending angle of the outermost curved portion 21A is shown as “θ1”, and the bending angle of the curved portion 20A located closer to the center side T2 in the stacking direction than the outermost curved portion 21A is shown as “θt”.

[0083] When measuring distances and angles inside the laminate 2, the laminate 2 is polished to expose a predetermined cross section passing through the center of the LT cross section in the width direction W of the laminate 2. The exposed cross section is then observed with a scanning electron microscope to measure various values.

[0084] Furthermore, in the LT cross section of the third reference area A3, the first lead portion 17A may or may not have a curved portion. However, if the first lead portion 17A of the third reference area A3 has a curved portion, the first lead portion 17A of the third reference area A3 preferably has a structure corresponding to the first lead portion 17A of the first reference area A1.

[0085] (Method for Manufacturing Multilayer Ceramic Capacitor 1)

[0086] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the aforementioned requirements are met. However, a preferred manufacturing method includes the following steps. Details of each step are described below.

[0087] A dielectric sheet for dielectric layer 14 and a conductive paste for internal electrode 15 are prepared. The dielectric sheet and the conductive paste for internal electrode contain a binder and a solvent. The binder and solvent may be known binders and solvents.

[0088] For example, conductive paste for the internal electrodes 15 is printed in a predetermined pattern on the dielectric sheet by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern for the first internal electrodes 15A and a dielectric sheet having a pattern for the second internal electrodes 15B are prepared.

[0089] A predetermined number of dielectric sheets without internal electrode patterns printed thereon are stacked to form the portion on the first principal surface AA side that will become the first principal surface side outer layer portion 12A. A dielectric sheet with a pattern printed thereon for the first internal electrode 15A and a dielectric sheet with a pattern printed thereon for the second internal electrode 15B are sequentially stacked thereon to form the portion that will become the inner layer portion 11. A predetermined number of dielectric sheets without internal electrode patterns are stacked on top of the portion that will become the inner layer portion 11 to form the portion on the second principal surface AB side that will become the second principal surface side outer layer portion 12B. In this manner, a laminated sheet is produced.

[0090] The laminated sheets are pressed in the stacking direction by isostatic pressing or other means to produce a laminated block. Furthermore, during isostatic pressing, the laminated sheets are sandwiched between metal plates having a convex shape at a location corresponding to a region in the longitudinal direction L (the lead-out region) where the lead-out portions of the internal electrodes are located. This increases the density of the central portion of the lead-out region in the stacking direction relative to the rest of the lead-out region, avoiding this region and causing the lead-out region to bend, resulting in the structure of this embodiment.

[0091] The stacked block is cut into a predetermined size to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0092] The stacked small pieces are fired to produce the stacked body 2. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode 15, but is preferably 900°C or higher and 1400°C or lower.

[0093] A conductive paste, which will become the base electrode layer 31, is applied to both end surfaces of the laminate 2. In this embodiment, the base electrode layer 31 is a sintered layer. For example, a conductive paste containing a glass component and a metal is applied to the laminate 2 by a method such as dipping. A sintering process is then performed to form the base electrode layer 31. The sintering process temperature is preferably between 700°C and 950°C.

[0094] In this embodiment, the impregnation is performed so that the base electrode layer 31 on the first end face CA side is arranged to extend from the first end face CA to the first principal surface AA and a portion of the second principal surface AB. Furthermore, the impregnation is performed so that the base electrode layer 31 on the second end face CB side is arranged to extend from the second end face CB to the first principal surface AA and a portion of the second principal surface AB. Furthermore, it is preferable that the impregnation is performed simultaneously at this time so that the base electrode layer on the first end face CA side is arranged to extend to a portion of the first side face BA and the second side face BB. Furthermore, it is preferable that the impregnation is performed so that the base electrode layer 31 on the second end face CB side is arranged to extend to a portion of the first side face BA and the second side face BB.

[0095] Alternatively, the pre-fired laminated pieces and the conductive paste applied to the laminated pieces may be fired simultaneously. In this case, the sintered layer is preferably formed by sintering a paste to which a ceramic material has been added in place of the glass component. In this case, the added ceramic material is preferably the same type as that of the dielectric layer 14. In this case, the conductive paste is applied to the pre-fired laminated pieces, and the laminated pieces and the conductive paste applied to the laminated pieces are sintered simultaneously, thereby forming a laminate 2 having a sintered layer formed thereon.

[0096] Then, a plating layer is formed on the surface of the base electrode layer 31. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially using electrolytic plating. As a plating method, barrel plating is preferably used, for example.

[0097] Through the above, we can get Figure 1 The multilayer ceramic capacitor 1 is shown.

[0098] (Effects of the First Embodiment)

[0099] According to this embodiment, the following effects can be obtained.

[0100] According to the present embodiment, in the LT cross section, the first lead-out portion 17A includes: a first inclined portion 18A, which is led out from the opposing portion 16 and inclined toward the center side in the stacking direction as it moves from the opposing portion 16 side toward the side separated from the opposing portion 16; a second inclined portion 19A, which extends from the first inclined portion 18A toward the side separated from the opposing portion 16 and inclines toward the outer side T1 in the stacking direction as it moves from the opposing portion 16 side toward the side separated from the opposing portion 16; and a bent portion 20A, which connects the first inclined portion 18A and the second inclined portion 19A. If a straight line that is a tangent to the first end face CA and extends parallel to the stacking direction T is set as the first end face side reference line LC1, a straight line that is a tangent to the first main surface AA and extends parallel to the stacking direction T is set as the first end face side reference line LC1. A straight line extending parallel to the longitudinal direction L is set as the first main surface side reference line LA1, the distance between the bending portion 20A and the first end surface side reference line LC1 is set as x, the distance between the bending portion 20A and the first main surface side reference line LA1 is set as y, the area in the stack 2 which is divided into four parts by a straight line passing through the central part in the stacking direction T of the stack 2 and a straight line passing through the central part in the longitudinal direction L of the stack 2, the area on the side of the first main surface AA and the side of the first end surface CA is set as the first reference area A1, the regression straight line derived based on the values ​​of x and y related to the bending portion 20A in the first reference area A1 is set as an imaginary connecting line VL, and the imaginary connecting line VL intersects with the effective layer portion 10.

[0101] With this structure, the bent portion 20A of the first inner electrode 15A tends to separate further from the first end face CA as it approaches the center side T2 in the stacking direction. This prevents the bent portion 20A from being cut during the dicing step, thereby suppressing the occurrence of interface delamination during the manufacturing process.

[0102] According to this embodiment, if the bent portion 20A located most outside in the stacking direction T1 is defined as the outermost bent portion 21A, the bending angle of the outermost bent portion 21A is smaller than the bending angle of the bent portion 20A located closer to the center in the stacking direction T2 than the outermost bent portion 21A.

[0103] In the laminate 2, the closer to the first end surface CA, the more likely stress is applied during cutting, and thus, interfacial delamination is more likely to occur. With this structure, the closer the internal electrode 15 is to the first main surface AA, the smaller the bend angle of the curved portion 20A. As the bend angle of the curved portion 20A decreases, the greater the adhesion between the internal electrode 15 and the dielectric layer 14. This effectively suppresses interfacial delamination during the manufacturing process.

[0104] <Second embodiment>

[0105] Next, based on Figure 4A multilayer ceramic capacitor 1 according to a second embodiment of the present invention will be described. Hereinafter, the differences from the first embodiment will be mainly described, and the same components as those in the first embodiment will be denoted by the same reference numerals and their description may be omitted.

[0106] like Figure 4 As shown in FIG. 1 , in the second embodiment, the shape of the internal electrode 15 is different from that in the first embodiment.

[0107] The internal electrode 15 closest to the first principal surface AA is referred to as the "first principal surface outermost internal electrode 151A." The internal electrode 15 closest to the second principal surface AB is referred to as the "second principal surface outermost internal electrode 151B." In other words, the first principal surface outermost internal electrode 151A is the internal electrode 15 located furthest outward (T1) in the stacking direction in the region of the stack 2 on the first principal surface AA side. The second principal surface outermost internal electrode 151B is the internal electrode 15 located furthest outward (T1) in the stacking direction in the region of the stack 2 on the second principal surface AB side.

[0108] The first principal surface outermost inner electrode 151A and the second principal surface outermost inner electrode 151B are sometimes collectively referred to as "each outermost inner electrode 151." The first principal surface outermost inner electrode 151A is, for example, the first inner electrode 15A. The second principal surface outermost inner electrode 151B is, for example, the second inner electrode 15B.

[0109] The length of the outline of the stacking direction outer side T1 of the facing portion 16 is defined as "D1". The distance between the ends of the facing portion 16 in the longitudinal direction L is defined as "D2". The value obtained by dividing D1 by D2 is defined as "undulation amount".

[0110] The amount of undulation of the opposing portion 16 of the first principal surface side outermost internal electrode 151A is greater than the amount of undulation of the opposing portion 16 of the internal electrode 15 adjacent to the first principal surface side outermost internal electrode 151A. The amount of undulation of the opposing portion 16 of the second principal surface side outermost internal electrode 151B is greater than the amount of undulation of the opposing portion 16 of the internal electrode 15 adjacent to the second principal surface side outermost internal electrode 151B.

[0111] When measuring D1 and D2, the laminate 2 is polished to expose a predetermined cross section passing through the center of the LT cross section in the width direction W of the laminate 2. Next, D1 and D2 are measured on the exposed cross section. D1 is measured using a profile measuring instrument. D2 is measured using a scanning electron microscope.

[0112] The multilayer ceramic capacitor 1 according to the second embodiment can be manufactured by the following method.

[0113] First, a dielectric sheet printed with a pattern for the first internal electrode 15A and a dielectric sheet printed with a pattern for the second internal electrode 15B are stacked in this order to form the portion that will become the inner layer 11. This portion, which will become the inner layer 11, is sandwiched between highly fluid dielectric sheets not printed with internal electrode patterns, thereby producing a laminated sheet. When this laminated sheet is isostatically pressed, the highly fluid dielectric sheets forming the outer layer flow, causing the internal electrodes in the inner layer to deform, resulting in the structure of this embodiment.

[0114] (Effects of the Second Embodiment)

[0115] According to this embodiment, the following effects can be obtained.

[0116] According to this embodiment, the amount of undulation of the opposing portion 16 of the first principal-surface-side outermost internal electrode 151A is greater than the amount of undulation of the opposing portion 16 of the internal electrode 15 adjacent to the first principal-surface-side outermost internal electrode 151A. Furthermore, the amount of undulation of the opposing portion 16 of the second principal-surface-side outermost internal electrode 151B is greater than the amount of undulation of the opposing portion 16 of the internal electrode 15 adjacent to the second principal-surface-side outermost internal electrode 151B.

[0117] The outer layer portion 12 and the inner layer portion 11 have different elastic moduli. Therefore, during the manufacturing process of the multilayer ceramic capacitor, when stress is applied to the laminated chips, the stress is easily applied to the interface between the outer layer portion 12 and the inner layer portion 11. As a result, interfacial peeling is likely to occur between the outer layer portion 12 and the inner layer portion 11. However, according to such a structure, by increasing the undulation of each outermost internal electrode 151, the contact area between each outermost internal electrode 151 and the outer layer portion 12 can be increased, thereby improving the adhesion between each outermost internal electrode 151 and the outer layer portion 12. As a result, interfacial peeling between the outer layer portion 12 and the inner layer portion 11 can be suppressed.

[0118] <Third embodiment>

[0119] Next, based on Figure 5 A multilayer ceramic capacitor 1 according to a third embodiment of the present invention will be described. Hereinafter, the differences from the first embodiment will be mainly described, and the same components as those in the first embodiment will be denoted by the same reference numerals and their description may be omitted.

[0120] like Figure 5 As shown, in the third embodiment, the bending angle of the outermost bent portion 21A of the first principal surface side outermost internal electrode 151A is smaller than that of the above-described embodiments.

[0121] The bending angle of the outermost bent portion 21A is smaller than 30°.

[0122] The multilayer ceramic capacitor 1 according to the third embodiment can be manufactured by the following method.

[0123] During isostatic pressing, similar to the first embodiment, the laminate is sandwiched between metal plates having a convex shape at positions corresponding to the lead-out regions of the laminate. By adjusting the convex shape of the metal plates and increasing the isostatic pressing pressure, the bending is enhanced, resulting in the structure of this embodiment.

[0124] (Effects of the Third Embodiment)

[0125] According to this embodiment, the following effects can be obtained.

[0126] The bending angle of the outermost bent portion 21A is smaller than 30°.

[0127] This structure allows the outer layer portion 12 to be deeply embedded in the outermost internal electrode. Consequently, the adhesion between the outer layer portion 12 and the first principal surface-side outermost internal electrode 151A can be improved. Consequently, if the outer layer portion 12 attempts to peel from the first end surface CA, the progress of the peeling of the outer layer portion 12 can be suppressed at the location of the outermost curved portion 21A. Consequently, delamination at the interface between the outer layer portion 12 and the inner layer portion 11 can be suppressed.

[0128] As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, Various changes and deformation|transformation are possible.

[0129] In the above embodiment, a laminated ceramic capacitor using a dielectric layer 14 composed of dielectric ceramic as a ceramic layer is exemplified as a laminated ceramic electronic component. However, the laminated ceramic electronic component disclosed herein is not limited thereto. For example, the ceramic electronic component disclosed herein can also be applied to various laminated ceramic electronic components such as piezoelectric components using piezoelectric ceramics as a ceramic layer, thermistors using semiconductor ceramics as a ceramic layer, and inductors using magnetic ceramics as a ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ferrite ceramics.

Claims

1. A multilayer ceramic electronic component comprising: A laminate having an inner layer portion including alternately stacked ceramic layers and internal electrodes, a first main surface and a second main surface opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; and External electrodes are arranged in pairs on each of the end faces, in, The internal electrode includes: an opposing portion opposing the adjacent internal electrode in the stacking direction; and a lead portion extending from the opposing portion and connected to the external electrode. The stacked body includes an effective layer portion including each of the facing portions and a portion of each of the ceramic layers sandwiched between adjacent facing portions. If the direction of each principal surface observed from the center of the stacking direction of the stacked body in the stacking direction is set as the outside of the stacking direction, the direction of the central part of the stacking direction of the stacked body observed from each principal surface in the stacking direction is set as the center side of the stacking direction, and the section parallel to the stacking direction and the longitudinal direction is set as the LT section, then In the LT cross-section, the lead-out portion includes: a first inclined portion that is led out from the opposing portion and is inclined toward the center side of the stacking direction as it moves from the opposing portion side toward the side separated from the opposing portion; a second inclined portion that extends from the first inclined portion toward the side separated from the opposing portion and is inclined toward the outside of the stacking direction as it moves from the opposing portion side toward the side separated from the opposing portion; and a bent portion that connects the first inclined portion and the second inclined portion. If a straight line that is a tangent to the end face and extends parallel to the stacking direction is set as an end face side reference line, a straight line that is a tangent to the main face and extends parallel to the longitudinal direction is set as a main face side reference line, the distance between the curved portion and the end face side reference line is set as x, the distance between the curved portion and the main face side reference line is set as y, one of the regions in the stacked body that is divided into four parts by a straight line passing through the center of the stacked body in the stacking direction and a straight line passing through the center of the stacked body in the longitudinal direction is set as a reference region, and a regression straight line derived based on the values ​​of x and y related to the curved portion in the reference region is set as an imaginary connecting line, then The imaginary connection line intersects the effective layer portion.

2. The multilayer ceramic electronic component according to claim 1, wherein If the bent portion located most outside the stacking direction in the reference region is defined as the outermost bent portion, then The bending angle of the outermost bent portion is smaller than the bending angle of the bent portion located closer to the center in the stacking direction than the outermost bent portion.

3. The multilayer ceramic electronic component according to claim 2, wherein The bending angle of the outermost curved portion is less than 30°.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein If the inner electrode located most outside in the stacking direction is defined as the outermost inner electrode, and the length of the outer contour line of the opposing portion in the stacking direction is divided by the distance between the ends of the opposing portion in the longitudinal direction is defined as the undulation amount, then The amount of undulation of the opposing portion of the outermost inner electrode is greater than the amount of undulation of the opposing portion of the inner electrode adjacent to the outermost inner electrode.

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