Method for testing key structure and detecting defect of wafer

Abstract

A method of detecting a defect of a wafer includes applying a first potential to a first low conductive layer, applying a second potential different from the first potential to a first high conductive layer, the first high conductive layer being connected to a second low conductive layer through a first via, the second low conductive layer being adjacent to the first low conductive layer, when a second potential is applied to the first high conductive layer, one side of the first high conductive layer is provided with a dummy conductive layer, and the distance between the dummy conductive layer and the first high conductive layer is provided with a second width. Wherein the second width is 1-3 times of the first width, detecting a voltage difference between the first low conductive layer and the first high conductive layer, and determining whether the wafer has a defect according to the voltage difference. Therefore, if the defect is detected, subsequent processing can be carried out on the defect, so that the overall wafer yield is improved.

Description

Technical Field

[0001] Some embodiments of the present invention relate to a test key structure and a method for detecting wafer defects using the test key structure. Background Art

[0002] In the semiconductor industry, the formation of circuits in the back-end process can be divided into a trench-first damascene process and a via-first damascene process. The difference between the two is that when the circuit is made with the trench-first damascene process, the range of the trench is defined first, and then the range of the via component is defined. When the circuit is made with the via-first damascene process, the range of the via component is defined first, and then the range of the trench is defined. Among them, when the circuit is made with the trench-first damascene process, the position of the via component is aligned with reference to the position of the trench. Therefore, if the position of the trench deviates, the position of the via component may also deviate. This position deviation of the via component may cause a short circuit in the wire below. Therefore, there is a need for a method to test this type of wire short circuit to avoid wafer defects. Summary of the Invention

[0003] Some embodiments of the present invention provide a method for detecting defects in a wafer using a test key structure, comprising applying a first potential to a first lower conductive layer, applying a second potential different from the first potential to a first upper conductive layer, wherein the first upper conductive layer is connected to the second lower conductive layer through a first through-hole component, the second lower conductive layer is adjacent to the first lower conductive layer, and the spacing between the first lower conductive layer and the second lower conductive layer has a first width, wherein when the second potential is applied to the first upper conductive layer, a dummy conductive layer is provided on one side of the first upper conductive layer, and the spacing between the dummy conductive layer and the first upper conductive layer has a second width, wherein the second width is between 1 and 3 times the first width, detecting the voltage difference between the first lower conductive layer and the first upper conductive layer, and judging whether the wafer has defects based on the voltage difference.

[0004] In some embodiments, when the voltage difference is less than a preset voltage difference, it is determined that the wafer has a defect.

[0005] In some embodiments, when the wafer has defects, a horizontal distance between the first via and the first lower conductive layer is smaller than a horizontal distance between the first lower conductive layer and the second lower conductive layer.

[0006] In some embodiments, when the second potential is applied to the first upper conductive layer, the first upper conductive layer is further connected to the third lower conductive layer through the second through-hole member, and the second lower conductive layer and the third lower conductive layer are on opposite sides of the first lower conductive layer.

[0007] In some embodiments, when the second potential is applied to the first upper conductive layer, the first upper conductive layer is further connected to the second lower conductive layer through a third via, and the third via is adjacent to the first via.

[0008] Some embodiments of the present invention provide a test key structure comprising a first lower conductive layer, a second lower conductive layer, a first upper conductive layer, a first through-hole component, and a dummy conductive layer. The first lower conductive layer is configured to be connected to a first potential. The second lower conductive layer is adjacent to the first lower conductive layer, and the spacing between the first lower conductive layer and the second lower conductive layer has a first width. The first upper conductive layer is on the second lower conductive layer, and the first upper conductive layer is configured to be connected to a second potential different from the first potential. The first through-hole component connects the second lower conductive layer and the first upper conductive layer. The dummy conductive layer is adjacent to the first upper conductive layer, and the spacing between the dummy conductive layer and the first upper conductive layer has a second width, wherein the second width is between 1 and 3 times the first width.

[0009] In some embodiments, the dummy conductive layer electrically isolates the first upper conductive layer, the first lower conductive layer, and the second lower conductive layer.

[0010] In some embodiments, the test key structure further includes a third lower conductive layer, a second upper conductive layer, and a second through-hole member. The third lower conductive layer is adjacent to the first lower conductive layer, and the second lower conductive layer and the third lower conductive layer are on opposite sides of the first lower conductive layer. The second upper conductive layer is on the third lower conductive layer, and the second upper conductive layer is configured to be connected to a second potential. The second through-hole member connects the third lower conductive layer and the second upper conductive layer.

[0011] In some embodiments, the first upper conductive layer and the second upper conductive layer are an integrated structure, and the third upper conductive layer composed of the first upper conductive layer and the second upper conductive layer spans the first lower conductive layer, the second lower conductive layer, and the third lower conductive layer.

[0012] In some embodiments, the test key structure further includes a third through-hole member adjacent to the first through-hole member and connecting the second lower conductive layer and the first upper conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A top view of a test key structure according to some embodiments of the present invention is shown.

[0014] Figure 2 Some embodiments of the present invention are shown Figure 1 Cross-sectional view of section AA'.

[0015] Figure 3 A method for detecting wafer defects using a test key structure according to some embodiments of the present invention is illustrated.

[0016] Figure 4 A cross-sectional view is shown illustrating a method for manufacturing a high conductive layer and a through-hole device according to some embodiments of the present invention.

[0017] Figure 5 Detailed top views of test key structures according to other embodiments of the present invention are shown.

[0018] Figure 6 Detailed top views of test key structures according to other embodiments of the present invention are shown. DETAILED DESCRIPTION

[0019] Some embodiments of the present invention utilize a test key structure to detect shorts in the back-end of line (BOL) of a wafer. Shorts can be caused by inaccurate alignment of vias manufactured using a trench-first damascene process. If a short is detected in a BOL fabricated circuit using the test key structure, further action can be taken to address the problem and improve wafer yield.

[0020] Figure 1 A top view of a test key structure 100 according to some embodiments of the present invention is shown. Test key structure 100 includes lower conductive layers 112, 114, and 116, upper conductive layers 122 and 124, dummy conductive layers 132 and 134, and through-hole elements 142 and 144. Lower conductive layers 112, 114, and 116 are located on the same layer. Upper conductive layers 122 and 124, and dummy conductive layers 132 and 134 are located on the same layer and above the same layer as lower conductive layers 112, 114, and 116. In other words, lower conductive layers 112, 114, and 116 are fabricated in the same process. Upper conductive layers 122 and 124, and dummy conductive layers 132 and 134 are also fabricated in the same process. In some embodiments, the lower conductive layers 112, 114, and 116, the upper conductive layers 122 and 124, the dummy conductive layers 132 and 134, and the vias 142 and 144 may serve as back-end-of-line (BEOL) components of a semiconductor wafer. The semiconductor wafer may have front-end-of-line (FEOL) components located below the BEOL components. The FEOL components may include suitable active devices, such as one or more transistors. In some embodiments, the transistors may be electrically connected to some of the BEOL components.

[0021] The lower conductive layer 112 is configured to be connected to a first potential. Lower conductive layers 114 and 116 are respectively adjacent to the lower conductive layer 112, and are on opposite sides of the lower conductive layer 112. The spacing between the lower conductive layers 112 and 114 has a width W1, and the spacing between the lower conductive layers 112 and 116 has a width W2. Widths W1 and W2 represent the minimum line width (critical dimension, CD) of a process technology. The lower conductive layers 114 and 116 are not directly provided with a potential. An upper conductive layer 122 is located on the lower conductive layer 114 and is configured to be connected to a second potential different from the first potential. A via 142 connects the lower conductive layer 114 and the upper conductive layer 122. The upper conductive layer 124 is located on the lower conductive layer 116 and has the second potential. Via 144 connects lower conductive layer 116 and upper conductive layer 124. In some embodiments, the first potential of lower conductive layer 112 can be provided by an underlying transistor, and lower conductive layers 114 and 116 are not directly connected to the underlying transistor. In some embodiments, the lower surfaces of lower conductive layers 114 and 116 do not contact other conductive materials. Upper conductive layers 122 and 124 are connected to a common electrode.

[0022] exist Figure 1 In the embodiment, the upper conductive layers 122 and 124 do not extend above the lower conductive layer 112. In order to increase the contact area between the through-hole members 142 and 144 and the lower conductive layers 114 and 116, respectively, the ends of the upper conductive layers 122 and 124 will still be at least flush with or exceed the boundaries of the lower conductive layers 114 and 116 in the top view. That is, the ends of the upper conductive layers 122 and 124 may protrude toward the lower conductive layer 112. In order to make the ends of the upper conductive layers 122 and 124 at least flush with or exceed the boundaries of the lower conductive layers 114 and 116 in the top view, dummy conductive layers 132 and 134 may be used to perform optical proximity correction (OPC). The dummy conductive layers 132 and 134 are adjacent to the upper conductive layers 122 and 124. For example, Figure 1The upper conductive layers 122 and 124 are disposed opposite each other, while the dummy conductive layer 132 is located on one side of the upper conductive layers 122 and 124, and the dummy conductive layer 134 is located on the other side of the upper conductive layers 122 and 124. The dummy conductive layers 132 and 134 are used only for optical proximity correction, and therefore electrically isolate the upper conductive layers 122 and 124 from the lower conductive layers 112, 114, and 116. In some embodiments, the dummy conductive layers 132 and 134 are not electrically connected to other components. In other words, the upper and lower surfaces of the dummy conductive layers 132 and 134 do not contact other conductive materials. The spacing between the dummy conductive layer 132 and the upper conductive layer 122 has a width W3, and the spacing between the dummy conductive layer 134 and the upper conductive layer 122 has a width W4. Widths W3 and W4 can be between 1 and 3 times the widths W1 and W2. When the width W3 and the width W4 exceed the aforementioned disclosed ranges, the dummy conductive layers 132 and 134 may fail to provide ideal optical proximity correction.

[0023] Figure 2 Some embodiments of the present invention are shown Figure 1 A cross-sectional view of section A-A'. Figure 2 In the embodiment, the lower conductive layers 112, 114 and 116 are formed in the dielectric layer 150, and the upper conductive layers 122 and 124 and the through-hole components 142 and 144 are formed in the dielectric layer 155. The through-hole components 142 and 144 contact the lower conductive layers 114 and 116, respectively. An etch stop layer 152 is provided between the dielectric layers 150 and 155, and the etch stop layer surrounds a portion of the through-hole components 142 and 144 and covers the lower conductive layer 112 and a portion of the lower conductive layers 114 and 116. In some embodiments, the through-hole components may be misaligned by the trench-first process, which may cause a short circuit between the through-hole components and the lower conductive layer. For example, in Figure 2 In the cross-sectional view, if the through hole member 142 is offset (for example, toward Figure 2 If the horizontal distance between the through-hole member 142 and the lower conductive layer 112 is too short, a short circuit may occur.

[0024] Figure 3 FIG2 illustrates a method for detecting wafer defects using the test key structure 100 according to some embodiments of the present invention. Figure 2 and Figure 3In step S100, a first potential is applied to the lower conductive layer 112. In step S200, a second potential, different from the first potential, is applied to the upper conductive layer 122, wherein the upper conductive layer 122 is connected to the lower conductive layer 114 via the via 142, and the lower conductive layer 114 is adjacent to the lower conductive layer 112. In step S200, a second potential is also applied to the upper conductive layer 124, wherein the upper conductive layer 124 is connected to the lower conductive layer 116 via the via 144, and the lower conductive layer 116 is adjacent to the lower conductive layer 112.

[0025] Next, in step S300, the voltage difference between the lower conductive layer 112 and the upper conductive layer 122 is detected. Next, in step S400, it is determined whether the wafer has a defect based on the voltage difference. This defect is the short circuit condition caused by the failure of the through-hole alignment mentioned above. Specifically, under normal circumstances (such as Figure 2 As shown in FIG, the upper conductive layer 122 is connected to the lower conductive layer 114 through the through-hole component 142, and the through-hole component 142 does not contact the lower conductive layer 112. That is, the upper conductive layer 122 and the lower conductive layer 112 are electrically isolated. Therefore, under normal conditions, there will be an expected voltage difference between the lower conductive layer 112 and the upper conductive layer 122, such as the voltage difference between the first potential and the second potential. On the other hand, when the through-hole component 142 is not aligned with the lower conductive layer 114, the through-hole component 142 is closer to the lower conductive layer 112. That is, the horizontal distance between the through-hole component 142 and the lower conductive layer 112 is smaller than the horizontal distance between the lower conductive layer 112 and the lower conductive layer 114 (i.e. Figure 1 The closer the through-hole member 142 is to the lower conductive layer 112, the smaller the measured voltage difference. When the voltage difference is less than the predetermined voltage difference, the wafer is determined to be defective. This allows for subsequent processing to address this defect. For example, if a wafer is determined to be defective, it can be discarded. This improves the overall wafer yield. Figure 3 The method can also be used as an indicator of continuous improvement process (CIP). For example, Figure 3 The results of the test method further improved the back-end process and obtained wafers with higher yield.

[0026] Figure 3 The method can also be used to test the time dependent dielectric breakdown (IMD TDDB) of the inter-metal dielectric (IMD) layer to determine the reliability of the dielectric layer 150. The reliability of the dielectric layer is affected by the spacing width between the conductive layers of the same layer. For example, Figure 2 For example, under normal circumstances, the distance between the lower conductive layers 112 and 114 is within the normal range, and the electric field near this area is small, so it is not easy to cause dielectric breakdown. However, when the through-hole member 142 cannot be aligned with the lower conductive layer 114, as shown in FIG. Figure 2 As shown, the horizontal distance between the through-hole member 142 and the lower conductive layer 112 is smaller than the horizontal distance between the lower conductive layer 112 and the lower conductive layer 114, and dielectric breakdown is likely to occur. Figure 1 The reliability of the dielectric layer 150 is determined by testing the key structure 100 .

[0027] Figure 4 A cross-sectional view illustrating the manufacturing method of the upper conductive layer and the through-hole device in some embodiments of the present invention is shown. The upper conductive layer and the through-hole device are formed by a trench-first process, that is, the shape and range of the upper conductive layer are defined first, and then the shape and range of the through-hole device are defined. Figure 4 In step S1, a dielectric layer 155 is formed on the etching stop layer 152. The etching stop layer 152 and the dielectric layer 155 are Figure 2 The etch stop layer 152 and the dielectric layer 155 are formed, and the etch stop layer 152 is formed on the lower conductive layer. Then, hard mask layers HM1 and HM2 and a photoresist layer PR1 are formed on the dielectric layer 155. The hard mask layers HM1 and HM2 are made of different materials to provide a sufficient etching selectivity. The photoresist layer PR1 has an opening for defining the upper conductive layer. Next, referring to Figure 4 In step S2, the hard mask layer HM2 is etched using the photoresist layer PR1 as a mask and an opening is formed in the hard mask layer HM2, and then the photoresist layer PR1 is removed. The size and profile of the opening of the hard mask layer HM2 are substantially the same as those of the opening of the photoresist layer PR1. Then, a bottom anti-reflective coating BARC and a photoresist layer PR2 are formed on the hard mask layer HM2. The photoresist layer PR2 has an opening for defining a through-hole component, and the opening of the photoresist layer PR2 is smaller than the opening of the hard mask layer HM2. The opening of the photoresist layer PR2 is aligned with reference to the position of the opening of the hard mask layer HM2. Therefore, when the position of the opening of the hard mask layer HM2 deviates, the position of the opening of the photoresist layer PR2 will also deviate, resulting in a failure to align with the lower conductive layer and form a short circuit, such as Figure 2 Next, refer to Figure 4In step S3, the bottom anti-reflective coating (BARC), the hard mask layers HM1 and HM2, the dielectric layer 155, and the etch stop layer 152 are first etched using the photoresist layer PR2 as a mask to form a through hole V exposing the lower conductive layer below. Next, the photoresist layer PR2 and the bottom anti-reflective coating (BARC) are removed, and the hard mask layer HM1 and the dielectric layer 155 are etched using the hard mask layer HM2 as a mask to form a trench T in the dielectric layer 155. The depth of the trench T is shallower than the depth of the through hole V. Finally, a conductive material is filled in the trench T and the through hole V, and the hard mask layers HM1 and HM2 are removed to form a high conductive layer (e.g., Figure 2 and forming a through-hole member (e.g., Figure 2 through-hole members 142 and 144).

[0028] Figure 5 FIG2 shows a top view of a test key structure 100 according to some other embodiments of the present invention. Figure 5 , Figure 5 The test key structure 100 is Figure 1 The test key structure 100 is similar, the difference is Figure 5 In the test key structure 100, the upper conductive layer 122 and the upper conductive layer 124 are an integrated structure. For example, the upper conductive layer 122 and the upper conductive layer 124 can be combined into the upper conductive layer 120, wherein the upper conductive layer 120 spans the lower conductive layers 112, 114, and 116. The through-hole component 142 connects the lower conductive layer 114 and the upper conductive layer 120. The through-hole component 144 connects the lower conductive layer 116 and the upper conductive layer 120. There is no through-hole component between the lower conductive layer 112 and the upper conductive layer 120. Figure 5 Method for testing wafer defects using a test key structure 100 Figure 3 The methods shown are similar except that Figure 5 The test key structure 100 corresponds to Figure 3 In step S200, when the second potential is applied to the upper conductive layer 120, the upper conductive layer 120 is also connected to the lower conductive layer 116 through the through-hole member 144, and the lower conductive layer 114 and the lower conductive layer 116 are on opposite sides of the lower conductive layer 112. Figure 4 The same, so I will not repeat it here. Specifically, Figure 5 In the structure, the testing method can test whether the through-hole component 142 is short-circuited with the underlying component (such as the lower conductive layer 112), and can also simultaneously test whether the through-hole component 144 is short-circuited with other underlying components (not shown).

[0029] Figure 6 FIG2 shows a top view of a test key structure 100 according to some other embodiments of the present invention. Figure 6 , Figure 6 The test key structure 100 is Figure 1 The test key structure 100 is similar, the difference is Figure 6 The test key structure 100 may include a plurality of through-holes 146, 147, 148, and 149. Through-hole 146 is adjacent to through-hole 142, through-hole 148 is adjacent to through-hole 146, and through-holes 146 and 148 connect the lower conductive layer 114 and the upper conductive layer 122. Through-hole 147 is adjacent to through-hole 144, and through-hole 149 is adjacent to through-hole 147, and through-holes 147 and 149 connect the lower conductive layer 116 and the upper conductive layer 124. Figure 6 Method for testing wafer defects using a test key structure 100 Figure 3 The methods shown are similar except that Figure 6 The test key structure 100 corresponds to Figure 3 In step S200, when the second potential is applied to the upper conductive layer 122, the upper conductive layer 122 is further connected to the lower conductive layer 114 through the vias 146 and 148, and the via 146 is adjacent to the via 142, and the via 148 is adjacent to the via 146. Furthermore, when the second potential is applied to the upper conductive layer 124, the upper conductive layer 124 is further connected to the lower conductive layer 116 through the vias 147 and 149, and the via 147 is adjacent to the via 144, and the via 149 is adjacent to the via 147. Other relevant details are as follows. Figure 3 The same, so no further description is given here.

[0030] In summary, the present invention provides a test key structure and a method for detecting wafer defects using the same. Specifically, different potentials can be provided to the upper conductive layer and the lower conductive layer, and the voltage difference between the two can be detected. Whether the wafer has defects is determined based on the resulting voltage difference. In this way, if a defect is detected, subsequent processing can be performed on the defect to improve the overall wafer yield. In addition, the test key structure of the present invention also includes a dummy conductive layer for providing optical proximity correction. In this way, the upper conductive layer of the dummy conductive layer can have a more ideal pattern, so that the contact area between the through-hole component and the lower conductive layer is larger.

[0031] The above descriptions are only some embodiments of the present invention, not all embodiments. Any equivalent changes made to the technical solution of the present invention by ordinary technicians in this field after reading the specification of the present invention are covered by the claims of the present invention.

[0032]

Explanation of symbols

[0033] 100: Test key structure

[0034] 112, 114, 116: lower conductive layer

[0035] 120, 122, 124: High conductive layer

[0036] 132, 134: dummy conductive layer

[0037] 142, 144, 146, 147, 148, 149: Through-hole parts

[0038] 150, 155: Dielectric layer

[0039] 152: Etch stop layer

[0040] A-A': cross section

[0041] BARC: Bottom Anti-Reflective Coating

[0042] HM1, HM2: Hard mask layers

[0043] PR1, PR2: photoresist layer

[0044] S1, S2, S3, S100, S200, S300, S400: Steps

[0045] T: Groove

[0046] W1, W2, W3, W4: Width

[0047] V: Through hole.

Claims

1. A method for detecting defects in a wafer, characterized in that: Include: applying a first potential to the first lower conductive layer; Applying a second potential different from the first potential to the first upper conductive layer, the first upper conductive layer being connected to the second lower conductive layer through a first through-hole member, the second lower conductive layer being adjacent to the first lower conductive layer, and a distance between the first lower conductive layer and the second lower conductive layer having a first width, wherein when the second potential is applied to the first upper conductive layer, a dummy conductive layer is provided on one side of the first upper conductive layer, and a distance between the dummy conductive layer and the first upper conductive layer having a second width, wherein the second width is between 1 and 3 times the first width; detecting a voltage difference between the first lower conductive layer and the first upper conductive layer; Whether the wafer has defects is determined based on the voltage difference.

2. The method according to claim 1, characterized in that When the voltage difference is less than a preset voltage difference, it is determined that the wafer has a defect.

3. The method according to claim 1, characterized in that When the wafer has defects, a horizontal distance between the first through-hole member and the first lower conductive layer is smaller than a horizontal distance between the first lower conductive layer and the second lower conductive layer.

4. The method according to claim 1, wherein When the second potential is applied to the first upper conductive layer, the first upper conductive layer is further connected to the third lower conductive layer through the second through-hole, and the second lower conductive layer and the third lower conductive layer are on opposite sides of the first lower conductive layer.

5. The method according to claim 1, wherein When the second potential is applied to the first upper conductive layer, the first upper conductive layer is further connected to the second lower conductive layer through a third through-hole component, and the third through-hole component is adjacent to the first through-hole component.

6. A test key structure, characterized in that: Include: A first lower conductive layer, wherein the first lower conductive layer is configured to be connected to a first potential; A second lower conductive layer is adjacent to the first lower conductive layer, and a distance between the first lower conductive layer and the second lower conductive layer has a first width; A first upper conductive layer is on the second lower conductive layer, and the first upper conductive layer is configured to be connected to a second potential different from the first potential; a first through-hole member connecting the second lower conductive layer and the first upper conductive layer; as well as The dummy conductive layer is adjacent to the first high portion conductive layer, and the distance between the dummy conductive layer and the first high portion conductive layer has a second width, wherein the second width is between 1 and 3 times the first width.

7. The test key structure according to claim 6, characterized in that: The dummy conductive layer electrically isolates the first high conductive layer, the first low conductive layer, and the second low conductive layer.

8. The test key structure according to claim 6, characterized in that: Also includes: A third lower conductive layer is adjacent to the first lower conductive layer, and the second lower conductive layer and the third lower conductive layer are on opposite sides of the first lower conductive layer; A second high conductive layer is on the third low conductive layer, and the second high conductive layer is configured to be connected to the second potential; The second through-hole component connects the third lower conductive layer and the second upper conductive layer.

9. The test key structure according to claim 6, characterized in that: The first high conductive layer and the second high conductive layer are integrated into one structure, and the third high conductive layer composed of the first high conductive layer and the second high conductive layer spans the first low conductive layer, the second low conductive layer and the third low conductive layer.

10. The test key structure according to claim 6, characterized in that: Also includes: The third through-hole component is adjacent to the first through-hole component and connects the second lower conductive layer and the first upper conductive layer.

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