Semiconductor structure and manufacturing method thereof

Abstract

The semiconductor structure includes a substrate, an active element, at least one discharge structure, a gate pad, a plurality of interconnection metal layers, and a fuse structure. The substrate has an active region and a dummy region. The active element is arranged in the active area of the substrate. The discharge structure is disposed in the dummy region of the substrate. The gate pad is disposed over the active device and the discharge structure. The multi-layer interconnection metal layer is arranged above the substrate and located among the grid electrode connecting pad, the discharging structure and the grid electrode connecting pad, and the active component is electrically connected with the grid electrode connecting pad through the multi-layer interconnection metal layer. The fuse structure is provided with a first part and a second part which are separated from each other, the first part is connected with the multiple interconnection metal layers, and the second part is connected with the at least one discharge structure. The invention further provides a manufacturing method of the semiconductor structure, which has the advantage of reducing the antenna effect.

Description

Technical Field

[0001] The present invention provides a semiconductor structure and a method for manufacturing the semiconductor structure, and more particularly relates to a semiconductor structure for preventing antenna effect and a method for manufacturing the semiconductor structure. Background Art

[0002] Integrated circuits and other semiconductor devices are formed to include numerous individual transistors coupled together and to various other components to form a functional device. If any one transistor fails, the device function can be disrupted. In advanced semiconductor device manufacturing and production, plasma chemical operations are often used multiple times in the sequence of manufacturing operations used to form almost all integrated circuits and other semiconductor devices. Plasma operations include plasma etching operations and plasma deposition operations. Plasma vapor deposition and plasma-enhanced chemical vapor deposition represent only two of the many types of plasma deposition operations.

[0003] Plasma operations utilize excited ions, and these ions are often directed toward the substrate surface with high bias. The excited, accelerated ions in the plasma can cause damage to previously formed components. Reactive-Ion Etching (RIE) operations and other operations utilizing ion bombardment can also damage existing components, and damage to existing components is collectively referred to as plasma-induced damage.

[0004] High-sensitivity transistors used in integrated circuits and other semiconductor devices typically include a polysilicon or metal gate positioned above a gate dielectric layer, which can be an oxide or other gate dielectric material. Plasma-induced damage to the gate dielectric layer, often referred to as the antenna effect, is an effect that damages the transistor gate and the transistor gate dielectric material and can potentially cause yield and reliability issues during MOS integrated circuit manufacturing. If the gate dielectric layer is severely damaged, it can disrupt device functionality. Therefore, it is desirable and preferred to provide a structure that eliminates or mitigates any plasma-induced damage to the gate dielectric layer. Summary of the Invention

[0005] One aspect of the present invention provides a semiconductor structure comprising a substrate, an active device, at least one discharge structure, a gate pad, a multilayer interconnect metal layer, and a fuse structure. The substrate has an active region and a dummy region. The active device is disposed in the active region of the substrate. The discharge structure is disposed in the dummy region of the substrate. The gate pad is disposed above the active device and the discharge structure. The multilayer interconnect metal layer is disposed above the substrate and between the gate pad, the discharge structure, and the gate pad, wherein the active device is electrically connected to the gate pad via the multilayer interconnect metal layer. The fuse structure has a first portion and a second portion, wherein the first portion is connected to the multilayer interconnect metal layer, and the second portion is connected to the at least one discharge structure.

[0006] Another aspect of the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a substrate, wherein the substrate has an active region and a dummy region; forming an active device in the active region of the substrate; forming at least one discharge structure in the dummy region of the substrate; forming a fuse connected to the at least one discharge structure; forming a multilayer interconnect metal layer above the active device, the at least one discharge structure, and the fuse; and forming a gate pad above the multilayer interconnect metal layer, wherein the gate pad is electrically connected to the active device and the fuse through the multilayer interconnect metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will become more fully apparent from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 FIG. 1 is a top view schematically illustrating a semiconductor structure according to an embodiment of the present invention.

[0009] Figure 2 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

[0010] Figure 3 FIG. 1 is a top view schematically illustrating a process stage of manufacturing a semiconductor structure according to an embodiment of the present invention.

[0011] Figure 4 FIG. 1 is a schematic cross-sectional view of a semiconductor structure fabricated at a certain process stage according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following drawings and detailed descriptions clearly illustrate the spirit of the present invention. After understanding the preferred embodiments of the present invention, any person skilled in the art can make changes and modifications based on the techniques taught by the present invention without departing from the spirit and scope of the present invention.

[0013] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Throughout the specification, the same reference numerals represent the same elements. In addition, relative terms such as "lower" and "upper" may be used herein to describe the relationship of one element to another element. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one drawing is flipped, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the specific orientation of the drawing.

[0014] One aspect of the present invention is to provide a semiconductor structure, such as semiconductor structure 10 , that can effectively introduce charges generated during plasma processing into a substrate material. Figure 1 FIG1 is a top view schematically illustrating a semiconductor structure 10 according to an embodiment of the present invention. Figure 2 is a cross-sectional view of a semiconductor structure 10 according to an embodiment of the present invention. Figure 1 and Figure 2 The semiconductor structure 10 includes a substrate 110 , an active device 120 , at least one discharge structure 130 , a gate pad 140 , a multi-layer interconnection metal layer 150 , and a fuse structure 160 .

[0015] In some embodiments, substrate 110 may include a silicon substrate. In some other embodiments, substrate 110 may be made of other suitable elemental semiconductors (such as germanium or diamond), suitable compound semiconductors (such as gallium arsenide, indium arsenide, indium phosphide or silicon carbide), or suitable alloy semiconductors (silicon germanium carbide, gallium indium phosphide or gallium arsenic phosphide). Substrate 110 may further include other features, such as various doped regions, buried regions and / or epitaxial layers. In addition, substrate 110 may be a semiconductor-on-insulator, such as silicon on insulator (SOI) or silicon on sapphire (SOS). In some other embodiments, substrate 110 may include a doped epitaxial layer, a gradient semiconductor layer and / or may further include a semiconductor layer stacked on another semiconductor layer of a different type, such as a silicon layer covering a silicon germanium layer. In other examples, the compound semiconductor substrate may include a multi-layer silicon structure, or the silicon substrate may include a multi-layer compound semiconductor structure. In one embodiment, the substrate 110 includes a doped well 113 (such as an n-well and / or a p-well).

[0016] The active device 120 is disposed in the active region 112 of the substrate 110. In some embodiments, the active device 120 may be a field effect transistor, a bipolar transistor, a diode, or may be combined with corresponding passive circuit elements (e.g., a resistor, a capacitor, etc.). Generally, any such active device may be formed in the semiconductor structure 10 according to specific design criteria based on a specific process technology (e.g., CMOS technology, etc.) to form a specific integrated circuit with a well-defined function. For convenience, from these many circuit elements that are typically present in the semiconductor structure 10, Figure 1 and Figure 2 A transistor element is depicted, which may be provided in the form of a field effect transistor having an SOI architecture.

[0017] In embodiments where the active device 120 is a transistor device, the transistor may represent a device using very thin semiconductor materials, such as silicon materials, silicon / germanium materials, etc. However, it should be understood that while the principles of the present invention provide specific operational advantages and excellent process control for complex CMOS technology, they can be applied to any semiconductor device and manufacturing process where plasma-induced charge needs to be discharged during the corresponding processing based on the following principles: specially designed protection structures, such as discharge structures, etc.

[0018] At least in a generally advanced manufacturing stage of the semiconductor structure 10, the transistor element may include at least a gate structure 122 and source / drain regions 121 having corresponding highly doped and / or lowly doped semiconductor materials above the substrate 110. The source / drain regions 121 may be disposed within the substrate 110. In some embodiments, the gate structure 122 may include a complex material system, such as a gate dielectric layer based on a high-k dielectric material, a metal substance including a barrier layer and an electrode material, etc.

[0019] In some embodiments, an insulating structure 132 may be formed in the substrate 110 to isolate the various active devices 120. The insulating structure 132 may utilize an insulating technique such as shallow trench isolation (STI) or local oxidation of silicon (LOCOS) to define and electrically isolate the active devices 120. In one embodiment, the insulating structure 132 is STI. The insulating structure 132 may include silicon nitride, silicon oxide, silicon oxynitride, fluorinated silicate glass (FSG), a low-k material, other suitable materials, and / or combinations thereof.

[0020] The discharge structure 130 is disposed in the dummy area 114 of the substrate 110. In some embodiments, the discharge structure 130 is embedded within the substrate 110. In some embodiments, the top surface 130S of the discharge structure 130 is flush with the top surface 110S of the substrate 110. In some embodiments, the discharge structure 130 comprises a metallic conductive material, such as silver, aluminum, gold, copper, tin, and / or alloys thereof. In some embodiments, there are multiple discharge structures 130, and these discharge structures 130 are arranged in an array. In some embodiments, the discharge structure 130 may be a metal pillar. The size of the discharge structure 130 will vary depending on the density and / or number of metal layers in the subsequent multi-layer interconnect.

[0021] The gate pad 140 is disposed above the active device 120 and the discharge structure 130. The gate pad 140 is electrically connected to the gate electrode of the active device 120 (i.e., the transistor). In some embodiments, there are multiple discharge structures 130, and these discharge structures 130 are arranged at intervals within the orthographic projection of the gate pad 140 onto the substrate 110. In some embodiments, there are multiple discharge structures 130, and these discharge structures 130 are disposed along the edge of the gate pad 140.

[0022] The multi-layer interconnect metal layer 150 is disposed above the substrate 110 and is located between the gate pad 140, the discharge structure 130, and the active device 120. Specifically, the gate electrode of the active device 120 is electrically connected to the gate pad 140 via the multi-layer interconnect metal layer 150. In some embodiments, the number of layers of the multi-layer interconnect metal layer 150 can be arranged according to actual needs, for example, one, two, three, four, or more layers.

[0023] The fuse structure 160 has a first portion 161 and a second portion 162. The first portion 161 is connected to the multi-layer interconnect metal layer 150, and the second portion 162 is connected to the discharge structure 130. In some embodiments, the fuse structure 160 is disposed on and contacts the substrate 110. In some embodiments, the first portion 161 of the fuse structure 160 directly contacts the multi-layer interconnect metal layer 150, while the second portion 162 of the fuse structure 160 directly contacts the discharge structure 130. In some embodiments, the second portion 162 of the fuse structure 160 covers the top surface 130S of the discharge structure 130. It is worth noting that the first portion 161 and the second portion 162 of the fuse structure 160 are disconnected. In other words, the first portion 161 and the second portion 162 of the fuse structure 160 are electrically insulated. In embodiments where there are multiple discharge structures 130, there are also multiple fuse structures 160, and the number of fuse structures 160 corresponds to the number of discharge structures 130.

[0024] In some embodiments, the dummy region 114 of the substrate 110 may also include a well 113, and the well 113 surrounds the discharge structure 130. The well 113 can provide a path for the discharge structure 130 to discharge faster to the substrate 110.

[0025] Another aspect of the present invention is to provide a method for manufacturing the semiconductor structure 10 . Figure 3 FIG. 1 is a top view schematically illustrating a process stage of manufacturing a semiconductor structure 10 according to an embodiment of the present invention. Figure 4FIG1 is a schematic cross-sectional view of a semiconductor structure 10 at a certain stage of fabrication according to one embodiment of the present invention. First, a substrate 110 is provided, having an active region 112 and a dummy region 114. An active device 120 is formed in the active region 112 of the substrate 110. For example, the active device 120 may be a transistor.

[0026] At least one discharge structure 130 is formed in the dummy region 114 of the substrate 110. It should be noted that the discharge structure 130 can be formed simultaneously with the active device 120 in the same process, or in a different process. In some embodiments, the discharge structure 130 is formed within the substrate 110. In some embodiments, the top surface 130S of the discharge structure 130 is flush with the top surface 110S of the substrate 110. In some embodiments, the discharge structure 130 comprises a metallic conductive material, as described above. In some embodiments, there are multiple discharge structures 130, and the discharge structures 130 are arranged in an array. In some embodiments, a well 113 is formed in the substrate 110, and the discharge structure 130 is formed within the well 113.

[0027] like Figure 3 and Figure 4 As shown, the fuse 160 is formed to connect to the discharge structure 130. More specifically, the fuse 160 directly contacts the discharge structure 130. In some embodiments, the fuse 160 is directly formed on the substrate 110.

[0028] A multi-layer interconnect metal layer 150 is formed above the active device 120, the discharge structure 130, and the fuse 160. It should be noted that the discharge structure 130 and the fuse 160 must be formed before the multi-layer interconnect metal layer 150. In some embodiments, a plasma process is used to form the multi-layer interconnect metal layer 150. Charge generated during the plasma process is conducted away from the substrate 110 via the fuse 160 and the discharge structure 130, thereby preventing undue damage to the active devices 120 in the active region 112. More specifically, during the fabrication of the multi-layer interconnect metal layer 150 (e.g., a plasma etching process), charge accumulated during the process can be discharged to a ground terminal (e.g., the substrate 110) via the fuse 160 and the discharge structure 130.

[0029] A gate pad 140 is formed above the multi-layer interconnect metal layer 150, wherein the gate pad 140 is electrically connected to the active device 120 and the fuse 160 through the multi-layer interconnect metal layer 150. In some embodiments, there are multiple discharge structures 130, and these discharge structures 130 are arranged at intervals within the orthographic projection of the gate pad 140 on the substrate 110.

[0030] In some embodiments, the method for manufacturing the semiconductor structure 10 further includes providing a specific bias voltage to the fuse 160 to blow the fuse 160, thereby obtaining Figure 1 and Figure 2 The semiconductor structure 10 is shown. It should be noted that, since capacitance and / or leakage current are not part of the actual circuit design, the purpose of blowing the fuse 160 is to ensure that the gate pad 140 is electrically isolated from the ground when the semiconductor structure 10 is in normal operation. In other words, it is used to prevent current from being conducted to the substrate 110 through the fuse 160 and the discharge structure 130. In addition, the fuse can be appropriately configured so that the fuse 160 can be blown by applying corresponding stimuli and / or current bias at any subsequent manufacturing stage, wherein the application of each stimulus can be performed at the wafer level or even in the packaged state of the corresponding semiconductor structure.

[0031] In summary, the semiconductor structure of the present invention, through the design of the fuse and discharge structure, can effectively protect key areas where the antenna effect is enhanced during plasma processing, such as the gate electrode structure, the drain and source regions of the SOI transistor element, etc., during the manufacturing process, and the corresponding majority of areas (for example, other active elements located in the active region) can also be effectively protected. The fuse can then be disconnected at a negligible capacitive coupling between the disconnected portions, thereby significantly improving device performance due to reduced parasitic capacitance and / or leakage current. Therefore, the semiconductor structure design of the present invention does not have additional conductive path load, and all protection structures (including the fuse and discharge structure) are disposed in a dummy region below the gate pad.

[0032] Although the present invention has been disclosed above in terms of embodiments, this is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0033]

Explanation of symbols

[0034] 10: Semiconductor structure

[0035] 110:Substrate

[0036] 110S: Top surface

[0037] 112: Active Zone

[0038] 113: Trap

[0039] 114: Imaginary District

[0040] 120: Active components

[0041] 121: Source / drain region

[0042] 122: Gate structure

[0043] 130: discharge structure

[0044] 130S: Top surface

[0045] 132: Insulation structure

[0046] 140: Gate pad

[0047] 150:Multi-layer interconnect metal layer

[0048] 160: Fuse

[0049] 161: Part 1

[0050] 162: Part 2.

Claims

1. A semiconductor structure, characterized in that include: a substrate having an active region and a dummy region; An active component is disposed in the active region of the substrate; At least one discharge structure is disposed in the dummy area of ​​the substrate; A gate pad is disposed above the active element and the at least one discharge structure; a multi-layer interconnect metal layer disposed above the substrate and between the gate pad, the at least one discharge structure, and the gate pad, wherein the active device is electrically connected to the gate pad through the multi-layer interconnect metal layer; as well as The fuse structure has a first portion and a second portion separated from each other, wherein the first portion is connected to the multi-layer interconnect metal layer, and the second portion is connected to the at least one discharge structure. 2 . The semiconductor structure according to claim 1 , wherein the at least one discharge structure is embedded in the substrate. 3 . The semiconductor structure according to claim 2 , wherein a top surface of the at least one discharge structure is flush with a surface of the substrate. The semiconductor structure according to claim 1 , wherein the at least one discharge structure comprises a metallic conductive material. 5 . The semiconductor structure according to claim 1 , wherein the at least one discharge structure is plural in number, and the plurality of discharge structures are arranged at intervals within an orthographic projection of the gate pad onto the substrate. The semiconductor structure according to claim 1 , wherein the second portion of the fuse structure directly contacts the at least one discharge structure.

7. The semiconductor structure according to claim 1, wherein Also includes: The well is located in the substrate, and the well surrounds the at least one discharge structure.

8. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate having an active area and a dummy area; forming an active device on the active region of the substrate; forming at least one discharge structure in the dummy area of ​​the substrate; forming a fuse connected to the at least one discharge structure; forming a multi-layer interconnect metal layer over the active device, the at least one discharge structure, and the fuse; as well as A gate pad is formed above the multi-layer interconnection metal layer, wherein the gate pad is electrically connected to the active device and the fuse through the multi-layer interconnection metal layer.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: Also includes: A bias voltage is provided to the fuse to blow the fuse. 10 . The method for manufacturing a semiconductor structure according to claim 8 , wherein forming the multi-layer interconnect metal layer comprises performing a plasma process, and charges in the plasma process are conducted out of the substrate through the fuse and the at least one discharge structure.

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