A common-mode voltage elimination method for a five-level open-circuit motor drive system

Abstract

This invention discloses a common-mode voltage elimination method for a five-level open-winding motor drive system. The method involves a motor drive system consisting of six five-level diode-clamped inverter bridge arms connected to the three-phase stator windings of an AC asynchronous motor via an open winding connection. The aim is to solve the problem of high common-mode voltage in five-level open-winding motor drive systems, which leads to shortened motor lifespan. Compared with existing technologies, the significant advantages of this invention are: it is not limited by the original control strategy of the five-level open-winding inverter. The modulation signals of each fully controlled device calculated under any control mode, and the drive signals of each fully controlled device generated using the modulation method provided by this invention, can effectively suppress the common-mode voltage of the five-level open-winding motor drive system to zero.

Description

Technical Field

[0001] This invention belongs to the field of medium and high voltage variable frequency speed control technology, and more specifically, relates to a common mode voltage elimination method for a five-level open winding motor drive system. Background Technology

[0002] In recent years, multilevel converters have seen increasing success in applications such as high-voltage, high-power variable frequency speed control, active power filtering, high-voltage direct current (HVDC) transmission, and reactive power compensation in power systems. Among these, diode-clamped multilevel converters have been widely used in industrial production due to their superior performance. However, as voltage levels increase, the number of voltage levels in diode-clamped converters also increases, leading to a gradual increase in the difficulty of balancing the DC-side capacitor voltage. Therefore, under the same operating conditions, motor drive systems with lower DC bus voltages can utilize diode-clamped converters with a lower number of voltage levels, thereby reducing the difficulty of balancing the DC-side capacitor voltage. Based on this technological background, multilevel motor drive systems with open-winding connections have attracted widespread attention. One typical drive scheme is a motor drive system consisting of six five-level diode-clamped inverter arms connected to the three-phase stator windings of an AC asynchronous motor via an open-winding connection. Six five-level diode-clamped inverter bridge arms can be combined with three, two, or one DC-side power supplies to form three different five-level open-winding motor drive systems. Compared to traditional three-phase common DC bus motor drive systems, the DC bus voltage of the five-level open-winding motor drive system can be reduced to half that of the common DC bus motor drive system; within one power frequency cycle, each phase of the five-level open-winding motor drive system can output nine levels; and the open-winding motor drive system has stronger fault tolerance.

[0003] Despite the significant advantages of five-level open-circuit motor drive systems, some problems still need to be addressed in practical engineering applications. For example, the switching action of power semiconductor devices in the inverter generates common-mode voltage. Without appropriate measures to suppress this common-mode voltage, it will be superimposed on the phase (line-to-midpoint) voltage of the motor, leading to accelerated aging of the motor winding insulation and premature failure. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a common-mode voltage elimination method for a five-level open-circuit winding motor drive system, which aims to solve the problem of large common-mode voltage in the five-level open-circuit winding motor drive system, resulting in shortened motor life.

[0005] To achieve the above objectives, the present invention provides a common-mode voltage elimination method for a five-level open-winding motor drive system. The five-level open-winding motor drive system is a motor drive system consisting of six five-level diode clamped inverter bridge arms and three-phase stator windings of an AC asynchronous motor connected in an open-winding configuration.

[0006] A common-mode voltage elimination method for a five-level open-circuit motor drive system, characterized by comprising the following steps:

[0007] Step 1: Define the drive signal of all fully controlled devices in the five-level open-winding motor drive system as consisting of four continuous level segments within one switching cycle. The first level segment is high, the second level segment is low, the third level segment is high, and the fourth level segment is low. H1 represents the duty cycle of the first level segment, L1 represents the duty cycle of the second level segment, H2 represents the duty cycle of the third level segment, and L2 represents the duty cycle of the fourth level segment.

[0008] The duty cycle of the fourth level is calculated using the following formula;

[0009] L2 = 1 - H1 - L1 - H2

[0010] Step 2: Define the per-unit modulation signal of U-phase bridge arm 1 of the inverter stage as u su The fully controllable devices, from top to bottom, are S u1 S u2 S u3 S u4 S u1' S u2' S u3' S u4' The per-unit modulated wave signal of phase U-arm 2 is u su' The fully controllable devices, from top to bottom, are S u'1 S u'2 S u'3 S u'4 S u'1' S u'2' S u'3' S u'4' The per-unit modulated wave signal of phase V bridge arm 1 is u sv The fully controllable devices, from top to bottom, are S v1 S v2 S v3 S v4 S v1' S v2' S v3' S v4' The per-unit modulated wave signal of phase V bridge arm 2 is u sv' The fully controllable devices, from top to bottom, are S v'1 Sv'2 S v'3 S v'4 S v'1' S v'2' S v'3' S v'4' The per-unit modulated wave signal of phase W bridge arm 1 is u sw The fully controllable devices, from top to bottom, are S w1 S w2 S w3 S w4 S w1' S w2' S w3' S w4' The per-unit modulated wave signal of phase W bridge arm 2 is u sw' The fully controllable devices, from top to bottom, are S w'1 S w'2 S w'3 S w'4 S w'1' S w'2' S w'3' S w'4' Define the fully controllable inverter stage device S u1 S u2 S u3 S u4 S u1' S u2' S u3' S u4' S u'1 S u'2 S u'3 S u'4 S u'1' S u'2' S u'3' S u'4' S v1 S v2 S v3 S v4 S v1' S v2' S v3' S v4' S v'1 S v'2 S v'3 S v'4 S v'1' S v'2' S v'3' S v'4' S w1 S w2 S w3 S w4 S w1' Sw2' S w3' S w4' S w'1 S w'2 S w'3 S w'4 S w'1' S w'2' S w'3' S w'4' The driving signals are as follows: G u1 G u2 G u3 G u4 G u1' G u2' G u3' G u4' G u'1 G u'2 G u'3 G u'4 G u'1' G u'2' G u'3' G u'4' G v1 G v2 G v3 G v4 G v1' G v2' G v3' G v4' G v'1 G v'2 G v'3 G v'4 G v'1' G v'2' G v'3' G v'4' G w1 G w2 G w3 G w4 G w1' G w2' G w3' G w4' G w'1 G w'2 G w'3 G w'4 G w'1' G w'2' G w'3' G w'4' The modulated wave signals are u su1 u su2 u su3 u su4 u su1' u su2' u su3', u su4' , u su'1 , u su'2 , u su'3 , u su'4 , u su'1' , u su'2' , u su'3' , u su'4' , u sv1 , u sv2 , u sv3 , u sv4 , u sv1' , u sv2' , u sv3' , u sv4' , u sv'1 , u sv'2 , u sv'3 , u sv'4 , u sv'1' , u sv'2' , u sv'3' , u sv'4' , u sw1 , u sw2 , u sw3 , u sw4 , u sw1' , u sw2' , u sw3' , u sw4' , u sw'1 , u sw'2 , u sw'3 , u sw'4 , u sw'1' , u sw'2' , u sw'3' , u sw'4' ; Define d su1H1 , d su1L1 , d su1H2 , d su1L2 , d su2H1 , d su2L1 , d su2H2 , d su2L2 , d su3H1 , d su3L1 , d su3H2 , d su3L2 , d su4H1 , d su4L1 , d su4H2 , d su4L2 , d su1'H1 , d su1'L1 , d su1'H2 , d su1'L2 , d su2'H1 , d su2'L1 , d su2'H2 , d su2'L2 , d su3'H1 , dsu3'L1 、d su3'H2 、d su3'L2 ,d su4'H1 、d su4'L1 、d su4'H2 、d su4'L2 ,d su'1H1 、d su'1L1 、d su'1H2 、d su'1L2 ,d su'2H1 、d su'2L1 、d su'2H2 、d su'2L2 ,d su'3H1 、d su'3L1 、d su'3H2 、d su'3L2 ,d su'4H1 、d su'4L1 、d su'4H2 、d su'4L2 ,d su'1'H1 、d su'1'L1 、d su'1'H2 、d su'1'L2 ,d su'2'H1 、d su'2'L1 、d su'2'H2 、d su'2'L2 ,d su'3'H1 、d su'3'L1 、d su'3'H2 、d su'3'L2 ,d su'4'H1 、d su'4'L1 、d su'4'H2 、d su'4'L2 ,d sv1H1 、d sv1L1 、d sv1H2 、d sv1L2 ,d sv2H1 、d sv2L1 、d sv2H2 、d sv2L2 ,d sv3H1 、d sv3L1 、d sv3H2 、d sv3L2 ,d sv4H1 、d sv4L1 、d sv4H2 、d sv4L2 ,d sv1'H1 、d sv1'L1 、d sv1'H2 、d sv1'L2 ,d sv2'H1 、d sv2'L1 、d sv2'H2 、d sv2'L2 ,d sv3'H1 、d sv3'L1 、d sv3'H2 、d sv3'L2,d sv4'H1 、d sv4'L1 、d sv4'H2 、d sv4'L2 ,d sv'1H1 、d sv'1L1 、d sv'1H2 、d sv'1L2 ,d sv'2H1 、d sv'2L1 、d sv'2H2 、d sv'2L2 ,d sv'3H1 、d sv'3L1 、d sv'3H2 、d sv'3L2 ,d sv'4H1 、d sv'4L1 、d sv'4H2 、d sv'4L2 ,d sv'1'H1 、d sv'1'L1 、d sv'1'H2 、d sv'1'L2 ,d sv'2'H1 、d sv'2'L1 、d sv'2'H2 、d sv'2'L2 ,d sv'3'H1 、d sv'3'L1 、d sv'3'H2 、d sv'3'L2 ,d sv'4'H1 、d sv'4'L1 、d sv'4'H2 、d sv'4'L2 ,d sw1H1 、d sw1L1 、d sw1H2 、d sw1L2 ,d sw2H1 、d sw2L1 、d sw2H2 、d sw2L2 ,d sw3H1 、d sw3L1 、d sw3H2 、d sw3L2 ,d sw4H1 、d sw4L1 、d sw4H2 、d sw4L2 ,d sw1'H1 、d sw1'L1 、d sw1'H2 、d sw1'L2 ,d sw2'H1 、d sw2'L1 、d sw2'H2 、d sw2'L2 ,d sw3'H1 、d sw3'L1 、d sw3'H2 、d sw3'L2 ,d sw4'H1 、d sw4'L1 、dsw4'H2 、d sw4'L2 ,d sw'1H1 、d sw'1L1 、d sw'1H2 、d sw'1L2 ,d sw'2H1 、d sw'2L1 、d sw'2H2 、d sw'2L2 ,d sw'3H1 、d sw'3L1 、d sw'3H2 、d sw'3L2 ,d sw'4H1 、d sw'4L1 、d sw'4H2 、d sw'4L2 ,d sw'1'H1 、d sw'1'L1 、d sw'1'H2 、d sw'1'L2 ,d sw'2'H1 、d sw'2'L1 、d sw'2'H2 、d sw'2'L2 ,d sw'3'H1 、d sw'3'L1 、d sw'3'H2 、d sw'3'L2 ,d sw'4'H1 、d sw'4'L1 、d sw'4'H2 、d sw'4'L2 ,respectively the drive signals G u1 、G u2 、G u3 、G u4 、G u1' 、G u2' 、G u3' 、G u4' ,G u'1 、G u'2 、G u'3 、G u'4 、G u'1' 、G u'2' 、G u'3' 、G u'4' ,G v1 、G v2 、G v3 、G v4 、G v1' 、G v2' 、G v3' 、G v4' ,G v'1 、G v'2 、G v'3 、G v'4 、G v'1' 、G v'2' 、G v'3' 、G v'4' ,Gw1 G w2 G w3 G w4 G w1' G w2' G w3' G w4' G w'1 G w'2 G w'3 G w'4 G w'1' G w'2' G w'3' G w'4' The duty cycle of the first level, the duty cycle of the second level, the duty cycle of the third level, and the duty cycle of the fourth level;

[0011] Step 3: Calculate d using the following formula sy1H1 d sy1L1 d sy1H2 d sy2H1 d sy2L1 d sy2H2 d sy3H1 d sy3L1 d sy3H2 d sy4H1 d sy4L1 d sy4H2 The value of (y = u, v, w, u', v', w');

[0012]

[0013] Step 4: Calculate d using the following formula sy1L2 d sy2L2 d sy3L2 d sy4L2 The value of (y = u, v, w, u', v', w');

[0014]

[0015] Step 5: Based on the calculated duty cycle d su1H1 d su1L1 d su1H2 d su1L2 d su2H1 d su2L1 d su2H2 d su2L2 d su3H1 d su3L1 d su3H2 d su3L2 d su4H1 d su4L1 d su4H2 d su4L2 d sv1H1 dsv1L1 d sv1H2 d sv1L2 d sv2H1 d sv2L1 d sv2H2 d sv2L2 d sv3H1 d sv3L1 d sv3H2 d sv3L2 d sv4H1 d sv4L1 d sv4H2 d sv4L2 d sw1H1 d sw1L1 d sw1H2 d sw1L2 d sw2H1 d sw2L1 d sw2H2 d sw2L2 d sw3H1 d sw3L1 d sw3H2 d sw3L2 d sw4H1 d sw4L1 d sw4H2 d sw4L2 Get the drive signal G u1 G u2 G u3 G u4 G v1 G v2 G v3 G v4 G w1 G w2 G w3 G w4 Drive signal G u1' G u2' G u3' G u4' G v1' G v2' G v3' G v4' G w1' G w2' G w3' G w4' respectively with drive signal G u1 G u2 G u3 G u4 G v1 G v2 G v3 G v4 G w1 G w2 G w3G w4 Conversely; based on the calculated level duty cycle d su'1H1 d su'1L1 d su'1H2 d su'1L2 d su'2H1 d su'2L1 d su'2H2 d su'2L2 d su'3H1 d su'3L1 d su'3H2 d su'3L2 d su'4H1 d su'4L1 d su'4H2 d su'4L2 d sv'1H1 d sv'1L1 d sv'1H2 d sv'1L2 d sv'2H1 d sv'2L1 d sv'2H2 d sv'2L2 d sv'3H1 d sv'3L1 d sv'3H2 d sv'3L2 d sv'4H1 d sv'4L1 d sv'4H2 d sv'4L2 d sw'1H1 d sw'1L1 d sw'1H2 d sw'1L2 d sw'2H1 d sw'2L1 d sw'2H2 d sw'2L2 d sw'3H1 d sw'3L1 d sw'3H2 d sw'3L2 d sw'4H1 d sw'4L1 d sw'4H2 d sw'4L2 Get the drive signal G u'1 G u'2 G u'3 G u'4 G v'1 G v'2 G v'3 G v'4 G w'1 G w'2 G w'3 G w'4 Drive signal G u'1' G u'2' G u'3' G u'4' Gv'1' G v'2' G v'3' G v'4' G w'1' G w'2' G w'3' G w'4' respectively with drive signal G u'1 G u'2 G u'3 G u'4 G v'1 G v'2 G v'3 G v'4 G w'1 G w'2 G w'3 G w'4 on the contrary.

[0016] Compared with the prior art, the significant advantage of the above-described technical solution conceived by this invention is that: this invention is not limited by the original control strategy of the five-level open-circuit inverter. The modulation signals of each fully controlled device calculated under any control mode, and the driving signals of each fully controlled device generated by the modulation method provided by this invention, can effectively suppress the common mode voltage of the five-level open-circuit motor drive system to zero.

[0017] The following will provide a detailed explanation with reference to examples and accompanying diagrams. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a five-level open-winding motor drive system in an embodiment of the present invention;

[0019] Figure 2 This is the four-segment level-based drive signal generation method used in this invention;

[0020] Figure 3 These are the common-mode voltage waveforms of the five-level open-circuit inverter provided by this invention before and after applying the proposed common-mode voltage elimination method;

[0021] Figure 4 The multi-level voltage waveforms of the U-phase before and after applying the proposed common-mode voltage elimination method to the five-level open-winding inverter provided by this invention;

[0022] Figure 5 This is the common-mode voltage waveform of the five-level open-winding inverter provided by this invention during constant voltage-frequency ratio startup after adopting the proposed common-mode voltage elimination method;

[0023] Figure 6 This is the U-phase multi-level voltage waveform of the five-level open-winding inverter provided by this invention during constant voltage-frequency ratio startup after adopting the proposed common-mode voltage elimination method;

[0024] Figure 7 This is the U-phase current waveform of the five-level open-circuit inverter provided by this invention during constant voltage-frequency ratio startup after adopting the proposed common-mode voltage elimination method. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0026] like Figure 1 As shown in the figure, the embodiment provides a schematic diagram of one of the three five-level open-winding motor drive systems, which consists of three sets of DC power supplies and three single-phase five-level diode clamped five-level inverters connected to an AC asynchronous motor in an open-winding configuration.

[0027] This invention provides a common-mode voltage elimination method for a five-level open-winding motor drive system. The five-level open-winding motor drive system is a motor drive system consisting of six five-level diode clamped inverter bridge arms and three-phase stator windings of an AC asynchronous motor connected in an open-winding configuration.

[0028] A common-mode voltage elimination method for a five-level open-circuit motor drive system, characterized by comprising the following steps:

[0029] Step 1: Define the drive signal of all fully controlled devices in the five-level open-circuit motor drive system as consisting of four consecutive level segments within one switching cycle. Figure 2 The four-segment level drive signal generation method used in this invention is given. The first segment level is high, the second segment level is low, the third segment level is high, and the fourth segment level is low. H1 represents the duty cycle of the first segment level, L1 represents the duty cycle of the second segment level, H2 represents the duty cycle of the third segment level, and L2 represents the duty cycle of the fourth segment level.

[0030] The duty cycle of the fourth level is calculated using the following formula;

[0031] L2 = 1 - H1 - L1 - H2

[0032] Step 2: Define the per-unit modulation signal of U-phase bridge arm 1 of the inverter stage as u su The fully controllable devices, from top to bottom, are S u1 S u2 S u3 S u4 S u1' S u2' S u3' S u4' The per-unit modulated wave signal of phase U-arm 2 is usu' The fully controllable devices, from top to bottom, are S u'1 S u'2 S u'3 S u'4 S u'1' S u'2' S u'3' S u'4' The per-unit modulated wave signal of phase V bridge arm 1 is u sv The fully controllable devices, from top to bottom, are S v1 S v2 S v3 S v4 S v1' S v2' S v3' S v4' The per-unit modulated wave signal of phase V bridge arm 2 is u sv' The fully controllable devices, from top to bottom, are S v'1 S v'2 S v'3 S v'4 S v'1' S v'2' S v'3' S v'4' The per-unit modulated wave signal of phase W bridge arm 1 is u sw The fully controllable devices, from top to bottom, are S w1 S w2 S w3 S w4 S w1' S w2' S w3' S w4' The per-unit modulated wave signal of phase W bridge arm 2 is u sw' The fully controllable devices, from top to bottom, are S w'1 S w'2 S w'3 S w'4 S w'1' S w'2' S w'3' S w'4' Define the fully controllable inverter stage device S u1 S u2 S u3 S u4 S u1' S u2' S u3' S u4' S u'1 S u'2 S u'3 S u'4 S u'1' Su'2' , S u'3' , S u'4' , S v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' , S v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' , S w1 , S w2 , S w3 , S w4 , S w1' , S w2' , S w3' , S w4' , S w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' The drive signals of w'4' are respectively: G u1 , G u2 , G u3 , G u4 , G u1' , G u2' , G u3' , G u4' , G u'1 , G u'2 , G u'3 , G u'4 , G u'1' , G u'2' , G u'3' , G u'4' , G v1 , G v2 , G v3 , G v4 , G v1' , G v2' , G v3' , G v4' , G v'1 , G v'2 , G v'3 , G v'4 , G v'1' , G v'2' , G v'3' , Gv'4' , G w1 , G w2 , G w3 , G w4 , G w1' , G w2' , G w3' , G w4' , G w'1 , G w'2 , G w'3 , G w'4 , G w'1' , G w'2' , G w'3' , G w'4' , the modulation wave signals are respectively u su1 , u su2 , u su3 , u su4 , u su1' , u su2' , u su3' , u su4' , u su'1 , u su'2 , u su'3 , u su'4 , u su'1' , u su'2' , u su'3' , u su'4' , u sv1 , u sv2 , u sv3 , u sv4 , u sv1' , u sv2' , u sv3' , u sv4' , u sv'1 , u sv'2 , u sv'3 , u sv'4 , u sv'1' , u sv'2' , u sv'3' , u sv'4' , u sw1 , u sw2 , u sw3 , u sw4 , u sw1' , u sw2' , u sw3' , u sw4' , u sw'1 , u sw'2 , u sw'3 , u sw'4 , u sw'1' , u sw'2' , u sw'3' , u sw'4' ; define d su1H1 , dsu1L1 、d su1H2 、d su1L2 ,d su2H1 、d su2L1 、d su2H2 、d su2L2 ,d su3H1 、d su3L1 、d su3H2 、d su3L2 ,d su4H1 、d su4L1 、d su4H2 、d su4L2 ,d su1'H1 、d su1'L1 、d su1'H2 、d su1'L2 ,d su2'H1 、d su2'L1 、d su2'H2 、d su2'L2 ,d su3'H1 、d su3'L1 、d su3'H2 、d su3'L2 ,d su4'H1 、d su4'L1 、d su4'H2 、d su4'L2 ,d su'1H1 、d su'1L1 、d su'1H2 、d su'1L2 ,d su'2H1 、d su'2L1 、d su'2H2 、d su'2L2 ,d su'3H1 、d su'3L1 、d su'3H2 、d su'3L2 ,d su'4H1 、d su'4L1 、d su'4H2 、d su'4L2 ,d su'1'H1 、d su'1'L1 、d su'1'H2 、d su'1'L2 ,d su'2'H1 、d su'2'L1 、d su'2'H2 、d su'2'L2 ,d su'3'H1 、d su'3'L1 、d su'3'H2 、d su'3'L2 ,d su'4'H1 、d su'4'L1 、d su'4'H2 、d su'4'L2 ,d sv1H1 、d sv1L1 、d sv1H2 、d sv1L2,d sv2H1 、d sv2L1 、d sv2H2 、d sv2L2 ,d sv3H1 、d sv3L1 、d sv3H2 、d sv3L2 ,d sv4H1 、d sv4L1 、d sv4H2 、d sv4L2 ,d sv1'H1 、d sv1'L1 、d sv1'H2 、d sv1'L2 ,d sv2'H1 、d sv2'L1 、d sv2'H2 、d sv2'L2 ,d sv3'H1 、d sv3'L1 、d sv3'H2 、d sv3'L2 ,d sv4'H1 、d sv4'L1 、d sv4'H2 、d sv4'L2 ,d sv'1H1 、d sv'1L1 、d sv'1H2 、d sv'1L2 ,d sv'2H1 、d sv'2L1 、d sv'2H2 、d sv'2L2 ,d sv'3H1 、d sv'3L1 、d sv'3H2 、d sv'3L2 ,d sv'4H1 、d sv'4L1 、d sv'4H2 、d sv'4L2 ,d sv'1'H1 、d sv'1'L1 、d sv'1'H2 、d sv'1'L2 ,d sv'2'H1 、d sv'2'L1 、d sv'2'H2 、d sv'2'L2 ,d sv'3'H1 、d sv'3'L1 、d sv'3'H2 、d sv'3'L2 ,d sv'4'H1 、d sv'4'L1 、d sv'4'H2 、d sv'4'L2 ,d sw1H1 、d sw1L1 、d sw1H2 、d sw1L2 ,d sw2H1 、d sw2L1 、dsw2H2 , d sw2L2 , d sw3H1 , d sw3L1 , d sw3H2 , d sw3L2 , d sw4H1 , d sw4L1 , d sw4H2 , d sw4L2 , d sw1'H1 , d sw1'L1 , d sw1'H2 , d sw1'L2 , d sw2'H1 , d sw2'L1 , d sw2'H2 , d sw2'L2 , d sw3'H1 , d sw3'L1 , d sw3'H2 , d sw3'L2 , d sw4'H1 , d sw4'L1 , d sw4'H2 , d sw4'L2 , d sw'1H1 , d sw'1L1 , d sw'1H2 , d sw'1L2 , d sw'2H1 , d sw'2L1 , d sw'2H2 , d sw'2L2 , d sw'3H1 , d sw'3L1 , d sw'3H2 , d sw'3L2 , d sw'4H1 , d sw'4L1 , d sw'4H2 , d sw'4L2 , d sw'1'H1 , d sw'1'L1 , d sw'1'H2 , d sw'1'L2 , d sw'2'H1 , d sw'2'L1 , d sw'2'H2 , d sw'2'L2 , d sw'3'H1 , d sw'3'L1 , d sw'3'H2 , d sw'3'L2 , d sw'4'H1 , d sw'4'L1 , d sw'4'H2 , d sw'4'L2 , are the drive signals G u1 , G u2 , G u3 , G u4 , G u1' , G u2' , G u3' , G u4' , Gu'1 G u'2 G u'3 G u'4 G u'1' G u'2' G u'3' G u'4' G v1 G v2 G v3 G v4 G v1' G v2' G v3' G v4' G v'1 G v'2 G v'3 G v'4 G v'1' G v'2' G v'3' G v'4' G w1 G w2 G w3 G w4 G w1' G w2' G w3' G w4' G w'1 G w'2 G w'3 G w'4 G w'1' G w'2' G w'3' G w'4' The duty cycle of the first level, the duty cycle of the second level, the duty cycle of the third level, and the duty cycle of the fourth level;

[0033] Step 3: Calculate d using the following formula sy1H1 d sy1L1 d sy1H2 d sy2H1 d sy2L1 d sy2H2 d sy3H1 d sy3L1 d sy3H2 d sy4H1 d sy4L1 d sy4H2 The value of (y = u, v, w, u', v', w');

[0034]

[0035] Step 4: Calculate d using the following formula sy1L2 d sy2L2 d sy3L2 d sy4L2The value of (y = u, v, w, u', v', w');

[0036]

[0037] Step 5: Based on the calculated duty cycle d su1H1 d su1L1 d su1H2 d su1L2 d su2H1 d su2L1 d su2H2 d su2L2 d su3H1 d su3L1 d su3H2 d su3L2 d su4H1 d su4L1 d su4H2 d su4L2 d sv1H1 d sv1L1 d sv1H2 d sv1L2 d sv2H1 d sv2L1 d sv2H2 d sv2L2 d sv3H1 d sv3L1 d sv3H2 d sv3L2 d sv4H1 d sv4L1 d sv4H2 d sv4L2 d sw1H1 d sw1L1 d sw1H2 d sw1L2 d sw2H1 d sw2L1 d sw2H2 d sw2L2 d sw3H1 d sw3L1 d sw3H2 d sw3L2 d sw4H1 d sw4L1 d sw4H2 d sw4L2 Get the drive signal G u1 G u2 G u3 G u4 G v1 G v2 G v3 G v4 G w1 G w2 G w3 Gw4 Drive signal G u1' G u2' G u3' G u4' G v1' G v2' G v3' G v4' G w1' G w2' G w3' G w4' respectively with drive signal G u1 G u2 G u3 G u4 G v1 G v2 G v3 G v4 G w1 G w2 G w3 G w4 Conversely; based on the calculated level duty cycle d su'1H1 d su'1L1 d su'1H2 d su'1L2 d su'2H1 d su'2L1 d su'2H2 d su'2L2 d su'3H1 d su'3L1 d su'3H2 d su'3L2 d su'4H1 d su'4L1 d su'4H2 d su'4L2 d sv'1H1 d sv'1L1 d sv'1H2 d sv'1L2 d sv'2H1 d sv'2L1 d sv'2H2 d sv'2L2 d sv'3H1 d sv'3L1 d sv'3H2 d sv'3L2 d sv'4H1 d sv'4L1 d sv'4H2 d sv'4L2 d sw'1H1 d sw'1L1 d sw'1H2 d sw'1L2 d sw'2H1 d sw'2L1 d sw'2H2 d sw'2L2 dsw'3H1 d sw'3L1 d sw'3H2 d sw'3L2 d sw'4H1 d sw'4L1 d sw'4H2 d sw'4L2 Get the drive signal G u'1 G u'2 G u'3 G u'4 G v'1 G v'2 G v'3 G v'4 G w'1 G w'2 G w'3 G w'4 Drive signal G u'1' G u'2' G u'3' G u'4' G v'1' G v'2' G v'3' G v'4' G w'1' G w'2' G w'3' G w'4' respectively with drive signal G u'1 G u'2 G u'3 G u'4 G v'1 G v'2 G v'3 G v'4 G w'1 G w'2 G w'3 G w'4 on the contrary.

[0038] Figure 3 The common-mode voltage waveforms of the five-level open-circuit inverter provided by this invention before and after applying the proposed common-mode voltage elimination method are shown. It can be seen that after applying the proposed common-mode voltage elimination method for 0.3 seconds, the common-mode voltage is effectively suppressed to 0, except for a very small number of voltage glitches.

[0039] Figure 4 The waveforms of the multi-level voltage of phase U in the five-level open-winding inverter provided by this invention before and after applying the proposed common-mode voltage elimination method are shown. It can be seen that after applying the proposed common-mode voltage elimination method for 0.3 seconds, the multi-level voltage of phase U changes from five levels to three levels.

[0040] Figure 5The waveform of the common-mode voltage during constant voltage-frequency ratio startup of the five-level open-circuit inverter provided by this invention after adopting the proposed common-mode voltage elimination method can be seen. It can be seen that the common-mode voltage of the inverter remains at 0 throughout the entire constant voltage-frequency ratio startup period. That is, the proposed common-mode voltage elimination method can achieve the effect of common-mode voltage elimination across the entire frequency and modulation ratio range.

[0041] Figure 6 This is the U-phase multi-level voltage waveform of the five-level open-winding inverter provided by this invention during constant voltage-frequency ratio startup after adopting the proposed common-mode voltage elimination method.

[0042] Figure 7 The waveform of the U-phase current during constant voltage-frequency ratio startup of the five-level open-circuit inverter provided by this invention after adopting the proposed common-mode voltage elimination method shows that the output current can maintain good sinusoidal characteristics across the entire frequency and modulation ratio range.

[0043] pass Figures 3-7 It can be seen that the proposed common-mode voltage suppression method can achieve the effect of eliminating common-mode voltage under different operating conditions and maintain the stable operation of the system.

[0044] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A common-mode voltage elimination method for a five-level open-winding motor drive system, wherein the five-level open-winding motor drive system is a motor drive system consisting of six five-level diode clamped inverter bridge arms and three-phase stator windings of an AC asynchronous motor connected by open windings; A common-mode voltage elimination method for a five-level open-circuit motor drive system, characterized in that, Includes the following steps: Step 1: Define the drive signal of all fully controlled devices in the five-level open-winding motor drive system as consisting of four continuous level segments within one switching cycle. The first level segment is high, the second level segment is low, the third level segment is high, and the fourth level segment is low. H1 represents the duty cycle of the first level segment, L1 represents the duty cycle of the second level segment, H2 represents the duty cycle of the third level segment, and L2 represents the duty cycle of the fourth level segment. The duty cycle of the fourth level is calculated using the following formula; Step 2: Define the per-unit modulation signal of U-phase bridge arm 1 of the inverter stage as u su The fully controllable devices, from top to bottom, are S u1 S u2 S u3 S u4 S u1' S u2' S u3' S u4' The per-unit modulated wave signal of phase U-arm 2 is u su' The fully controllable devices, from top to bottom, are S u'1 S u'2 S u'3 S u'4 S u'1' S u'2' S u'3' S u'4' The per-unit modulated wave signal of phase V bridge arm 1 is u sv The fully controllable devices, from top to bottom, are S v1 S v2 S v3 S v4 S v1' S v2' S v3' S v4' The per-unit modulated wave signal of phase V bridge arm 2 is u sv' The fully controllable devices, from top to bottom, are S v'1 S v'2 S v'3 S v'4 S v'1' S v'2' S v'3' S v'4' The per-unit modulated wave signal of phase W bridge arm 1 is u sw The fully controllable devices, from top to bottom, are S w1 S w2 S w3 S w4 S w1' S w2' S w3' S w4' The per-unit modulated wave signal of phase W bridge arm 2 is u sw' The fully controllable devices, from top to bottom, are S w'1 S w'2 S w'3 S w'4 S w'1' S w'2' S w'3' S w'4' Define the fully controllable inverter stage device S u1 , S u2 , S u3 , S u4 , S u1' , S u2' , S u3' , S u4' , S u'1 , S u'2 , S u'3 , S u'4 , S u'1' , S u'2' , S u'3' , S u'4' , S v1 , S v2 , S v3 , S v4 , S v1' , S v2' , S v3' , S v4' , S v'1 , S v'2 , S v'3 , S v'4 , S v'1' , S v'2' , S v'3' , S v'4' , S[[ID=*64]] w1 , S w2 , S[[ID=*68]] w3 , S w4 , S w1' , S w2' '' , S w3' , S w4' , S w'1 , S w'2 , S w'3 , S w'4 , S w'1' , S w'2' , S w'3' , S w'4' The drive signals of u1 , G u2 , G u3 , G u4 , G u1' , G<* u2' , G u3' , G u4' , G u'1 , G u'2 , G u'3 , G u'4 , G '' u'1' , G u'2' , G u'3' , G u'4' , G v1 , G v2 , G Notes: There are some unclear parts in the original text (such as the repeated "S" and the asterisked lines). The translation is done as accurately as possible based on the given rules. If there are any specific clarifications or corrections needed for the original text, it would help to improve the translation quality. v3 , G v4 , G v1' , G v2' , G v3' , G v4' , G v'1 , G v'2 , G v'3 , G v'4 , G v'1' , G v'2' , G v'3' , G v'4' , G w1 , G w2 , G w3 , G w4 , G w1' , G w2' , G w3' , G w4' , G w'1 , G w'2 , G w'3 , G w'4 , G w'1' , G w'2' , G w'3' , G w'4' , the modulation wave signals are respectively u su1 , u su2 , u su3 , u su4 , u su1' , u su2' , u su3' , u su4' , u su'1 , u su'2 , u su'3 , u su'4 , u su'1' , u su'2' , u su'3' , u su'4' , u sv1 , u sv2 , u sv3 , u sv4 , u sv1' , u sv2' , u sv3' , u sv4' , u sv'1 , u sv'2 , u sv'3 , u sv'4 , u sv'1' , u sv'2' , u sv'3' , u sv'4' , u sw1 , u sw2 , u sw3 , u sw4 , u sw1' and u sw2' and u sw3' and u sw4' and u sw'1 and u sw'2 and u sw'3 and u sw'4 and u sw'1' and u sw'2' and u sw'3' and u sw'4' ; Define d su1H1 and d su1L1 and d su1H2 and d su1L2 and d su2H1 and d su2L1 and d su2H2 and d su2L2 and d[[ID=第40行]] su3H1 and d su3L1 and d su3H2 and d su3L2 and d su4H1 and d su4L1 and d su4H2 and d su4L2 and d su1'H1 and d su1'L1 and d su1'H2 and d su1'L2 [[ID=6३]] and d su2'H1 and d su2'L1 and d su2'H2 and d su2'L2 and d su3'H1 and d su3'L1 and d su3'H2 and d su3'L2 and d su4'H1 and d su4'L1 and d su4'H2 and d su4'L2 and d su'1H1 and d su'1L1 and d su'1H2 and d su'1L2 and d su'2H1 and d su'2L1 and d su'2H2 and d su'2L2 and d su'3H1 and d su'3L1 and d su'3H2 and d su'3L2 and d su'4H1 and d su'4L1 and d su'4H2 and d su'4L2 and d su'1'H1 and d su'1'L1 and d su'1'H2 and d su'1'L2 and d su'2'H1 and d su'2'L1 and d su'2'H2 、d su'2'L2 ,d su'3'H1 、d su'3'L1 、d su'3'H2 、d su'3'L2 ,d su'4'H1 、d su'4'L1 、d su'4'H2 、d su'4'L2 ,d sv1H1 、d sv1L1 、d sv1H2 、d sv1L2 ,d sv2H1 、d sv2L1 、d sv2H2 、d sv2L2 ,d sv3H1 、d sv3L1 、d sv3H2 、d sv3L2 ,d sv4H1 、d sv4L1 、d sv4H2 、d sv4L2 ,d sv1'H1 、d sv1'L1 、d sv1'H2 、d sv1'L2 ,d sv2'H1 、d sv2'L1 、d sv2'H2 、d sv2'L2 ,d sv3'H1 、d sv3'L1 、d sv3'H2 、d sv3'L2 ,d sv4'H1 、d sv4'L1 、d sv4'H2 、d sv4'L2 ,d sv'1H1 、d sv'1L1 、d sv'1H2 、d sv'1L2 ,d sv'2H1 、d sv'2L1 、d sv'2H2 、d sv'2L2 ,d sv'3H1 、d sv'3L1 、d sv'3H2 、d sv'3L2 ,d sv'4H1 、d sv'4L1 、d sv'4H2 、d sv'4L2 ,d sv'1'H1 、d sv'1'L1 、d sv'1'H2 、d sv'1'L2 ,d sv'2'H1 、d sv'2'L1 、d sv'2'H2 、d sv'2'L2 ,d sv'3'H1 、d sv'3'L1 、d sv'3'H2 、d sv'3'L2 ,d sv'4'H1 、d sv'4'L1 、d sv'4'H2 、d sv'4'L2 ,d sw1H1 、d sw1L1 、d sw1H2 、d sw1L2 ,d sw2H1 、d sw2L1 、d sw2H2 、d sw2L2 ,d sw3H1 、d sw3L1 、d sw3H2 、d sw3L2 ,d sw4H1 、d sw4L1 、d sw4H2 、d sw4L2 ,d sw1'H1 、d sw1'L1 、d sw1'H2 、d sw1'L2 ,d sw2'H1 、d sw2'L1 、d sw2'H2 、d sw2'L2 ,d sw3'H1 、d sw3'L1 、d sw3'H2 、d sw3'L2 ,d sw4'H1 、d sw4'L1 、d sw4'H2 、d sw4'L2 ,d sw'1H1 、d sw'1L1 、d sw'1H2 、d sw'1L2 ,d sw'2H1 、d sw'2L1 、d sw'2H2 、d sw'2L2 ,d sw'3H1 、d sw'3L1 、d sw'3H2 、d sw'3L2 ,d sw'4H1 、d sw'4L1 、d sw'4H2 、d sw'4L2 ,d sw'1'H1 、d sw'1'L1 、d sw'1'H2 、d sw'1'L2 ,d sw'2'H1 、d sw'2'L1 、d sw'2'H2 、d sw'2'L2 ,d sw'3'H1 、d sw'3'L1 、d sw'3'H2 、d sw'3'L2 d sw'4'H1 d sw'4'L1 d sw'4'H2 d sw'4'L2 The driving signals G are respectively u1 G u2 G u3 G u4 G u1' G u2' G u3' G u4' G u'1 G u'2 G u'3 G u'4 G u'1' G u'2' G u'3' G u'4' G v1 G v2 G v3 G v4 G v1' G v2' G v3' G v4' G v'1 G v'2 G v'3 G v'4 G v'1' G v'2' G v'3' G v'4' G w1 G w2 G w3 G w4 G w1' G w2' G w3' G w4' G w'1 G w'2 G w'3 G w'4 G w'1' G w'2' G w'3' G w'4' The duty cycle of the first level, the duty cycle of the second level, the duty cycle of the third level, and the duty cycle of the fourth level; Step 3: Calculate d using the following formula sy1H1 d sy1L1 d sy1H2 d sy2H1 d sy2L1 d sy2H2 d sy3H1 d sy3L1 d sy3H2 d sy4H1 d sy4L1 d sy4H2 The value of (y=u,v,w,u',v',w'); where u sy1 u sy2 u sy3 u sy4 S, a fully controllable device y1 S y2 S y3 S y4 The modulated wave signal (y=u,v,w,u',v',w'); Step 4: Calculate d using the following formula sy1L2 d sy2L2 d sy3L2 d sy4L2 The value of (y=u,v,w,u',v',w'); Step 5: Based on the calculated duty cycle d su1H1 d su1L1 d su1H2 d su1L2 d su2H1 d su2L1 d su2H2 d su2L2 d su3H1 d su3L1 d su3H2 d su3L2 d su4H1 d su4L1 d su4H2 d su4L2 d sv1H1 d sv1L1 d sv1H2 d sv1L2 d sv2H1 d sv2L1 d sv2H2 d sv2L2 d sv3H1 d sv3L1 d sv3H2 d sv3L2 d sv4H1 d sv4L1 d sv4H2 d sv4L2 d sw1H1 d sw1L1 d sw1H2 d sw1L2 d sw2H1 d sw2L1 d sw2H2 d sw2L2 d sw3H1 d sw3L1 d sw3H2 d sw3L2 d sw4H1 d sw4L1 d sw4H2 d sw4L2 Get the driving signal G u1 G u2 G u3 G u4 G v1 G v2 G v3 G v4 G w1 G w2 G w3 G w4 Drive signal G u1' G u2' G u3' G u4' G v1' G v2' G v3' G v4' G w1' G w2' G w3' G w4' respectively with drive signal G u1 G u2 G u3 G u4 G v1 G v2 G v3 G v4 G w1 G w2 G w3 G w4 Conversely; based on the calculated level duty cycle d su'1H1 d su'1L1 d su'1H2 d su'1L2 d su'2H1 d su'2L1 d su'2H2 d su'2L2 d su'3H1 d su'3L1 d su'3H2 d su'3L2 d su'4H1 d su'4L1 d su'4H2 d su'4L2 d sv'1H1 d sv'1L1 d sv'1H2 d sv'1L2 d sv'2H1 d sv'2L1 d sv'2H2 d sv'2L2 d sv'3H1 d sv'3L1 d sv'3H2 d sv'3L2 d sv'4H1 d sv'4L1 d sv'4H2 d sv'4L2 d sw'1H1 d sw'1L1 d sw'1H2 d sw'1L2 d sw'2H1 d sw'2L1 d sw'2H2 d sw'2L2 d sw'3H1 d sw'3L1 d sw'3H2 d sw'3L2 d sw'4H1 d sw'4L1 d sw'4H2 d sw'4L2 Get the driving signal G u'1 G u'2 G u'3 G u'4 G v'1 G v'2 G v'3 G v'4 G w'1 G w'2 G w'3 G w'4 Drive signal G u'1' G u'2' G u'3' G u'4' G v'1' G v'2' G v'3' G v'4' G w'1' G w'2' G w'3' G w'4' respectively with drive signal G u'1 G u'2 G u'3 G u'4 G v'1 G v'2 G v'3 G v'4 G w'1 G w'2 G w'3 G w'4 on the contrary.

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