Method and system for converting flexbus interface to PCIe interface based on FPGA

Abstract

The invention provides a method and a system for converting a FlexBus interface to a PCIe (Peripheral Component Interconnect Express) interface based on an FPGA (Field Programmable Gate Array). The method comprises the following steps of: receiving 16-bit data by a FlexBus interface DRAM controller, converting the 16-bit data into 32-bit data through dynamic bit width switching and time-sharing output logic, and storing the 32-bit data into a DRAM; the AXI protocol conversion module encapsulates 32-bit data into AXI burst transmission and writes the AXI burst transmission into a DDR specified address; the PCIe BAR space mapping module is used for mapping the DDR address to a PCIe BAR space; and the PCIe equipment initiates a read-write request through the BAR space and converts the read-write request into an AXI signal to interact with the DDR, so that efficient data transmission is achieved. By means of clock domain crossing synchronization, bit width switching, burst transmission optimization and the like, data transmission efficiency and system stability are remarkably improved, and efficient data interaction requirements in the fields of embedded systems and data acquisition are met.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded system interface protocol conversion, and in particular to a method and system for converting a FlexBus interface to a PCIe interface based on FPGA. Background Art

[0002] In the prior art, the FlexBus interface used in some embedded systems and data acquisition devices limits the data transmission rate due to its fixed data bit width (e.g., 16 bits) and lack of support for higher data bit widths. In addition, direct connections between the FlexBus interface and modern high-speed interfaces (e.g., PCIe) suffer from clock domain conflicts and data synchronization issues, resulting in data loss or address misalignment. Traditional solutions typically rely on dedicated interface chips or complex hardware designs, which are not only costly but also inflexible and difficult to adapt to different application scenarios. Therefore, an efficient, flexible, and cost-effective interface conversion method is needed to address these problems in the prior art. Summary of the Invention

[0003] The purpose of the present invention is to provide a method and system for converting a FlexBus interface to a PCIe interface based on FPGA, so as to solve the technical problems raised in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solution: a method for converting a FlexBus interface to a PCIe interface based on FPGA, comprising the following steps:

[0005] Step 1: The FlexBus interface DRAM controller receives 16-bit data from the FlexBus interface, converts the data to 32-bit width through dynamic data width switching and time-sharing output logic, and then stores it in DRAM;

[0006] Step 2: The AXI protocol conversion module receives the 32-bit data from the DRAM controller, encapsulates it into an AXI burst transmission, and writes it to the specified address area of ​​the DDR storage medium;

[0007] Step 3: The PCIe BAR space mapping module maps the DDR physical address segment to the PCIe BAR space through the AXItoPCIe bridge logic;

[0008] Step 4: The PCIe device initiates read and write requests through the BAR space, converts them into AXI signals and interacts with the DDR storage medium to achieve efficient data transmission.

[0009] Preferably, step 1 further includes the sub-steps of implementing dynamic data bit width switching and time-sharing output logic:

[0010] Sub-step 11: The FlexBus signal processing module detects the FlexBus clock edge and the falling edge of the chip select signal, captures the rising and falling edges of the clock through a two-stage delay register chain, and calculates the corresponding edge flags;

[0011] Sub-step 12: Simultaneously synchronize the chip select signal with two registers to ensure cross-clock domain stability;

[0012] Sub-step 13: The bidirectional data bus control module dynamically switches the data direction according to the control signal: receiving 16-bit data in write mode and outputting 32-bit DRAM data in two stages in read mode.

[0013] Preferably, an asynchronous FIFO is inserted into the DRAM read path to isolate the FlexBus and DRAM clock domains.

[0014] Preferably, the AXI protocol conversion module performs protocol conversion based on signal mapping rules, and the signal mapping rules are: FlexBus data is converted into 32-bit AXI data by time-sharing high and low 16-bit splicing, and the FlexBus address is mapped to AXI write address and read address after address alignment and burst length configuration, and the FlexBus clock is synchronized with the AXI clock through cross-clock domain asynchronous FIFO buffering.

[0015] Preferably, the address mapping mechanism based on which the DDR physical address segment is mapped to the PCIe BAR space in step 3 is as follows: mapping the DDR physical address segment (such as 0x80000000~0x8FFFFFFF) to the PCIe device BAR0 space, supporting direct addressing on the PCIe side, and generating TLP packets through AXItoPCIe bridging logic to achieve DDR access.

[0016] Preferably, in step 2, when the AXI protocol conversion module encapsulates 32-bit data into AXI burst transmission, it preloads data into the PCIe transmission queue according to the AXI burst length to reduce link delay; and splits large blocks of AXI data into PCIe maximum payload (such as 256B) to adapt the link layer efficiency and improve data transmission efficiency.

[0017] Preferably, in step 3, the built-in clock domain conversion logic of the PCIe IP core (such as Xilinx XDMA) is used to achieve seamless conversion between the AXI clock domain and the PCIe clock domain without additional design, ensuring stable transmission of data between different clock domains.

[0018] The present invention also provides a system for converting a FlexBus interface to a PCIe interface based on FPGA, the system comprising:

[0019] FlexBus-DRAM controller for cross-clock domain synchronization and dynamic data bit width switching;

[0020] AXI protocol conversion engine, used to map FlexBus timing to AXI channel signals (AR / AW / W / R);

[0021] PCIe BAR space mapping module, used to configure DDR physical addresses to PCIe BAR space, supporting end-to-end access;

[0022] The DRAM controller includes the following functional modules:

[0023] Clock and reset module, used to generate DRAM high-frequency clock (ram_clk) and global reset signal;

[0024] FlexBus signal processing module, used to detect the FlexBus clock edge (FLEXBUS_clk_p / n) and the chip select signal falling edge (FLEXBUS_cs_n);

[0025] Bidirectional data bus control module, used to dynamically switch data direction (receive data in write mode, and output high and low 16 bits in read mode in time-sharing);

[0026] DRAM read and write control module, used to generate write enable (wr_en), address (wr_addr / rd_addr) and data path (wr_data / rd_data).

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] This invention expands the data transmission capacity of a 16-bit physical bus to an equivalent 32-bit through dynamic data bit width switching, significantly improving data transmission rates. Furthermore, thanks to a cross-clock domain synchronization mechanism, the system can operate stably under clocks of different frequencies, effectively suppressing metastable state propagation and enhancing timing robustness. Furthermore, in burst transmission mode, automatic address incrementing reduces bus switching overhead, thereby reducing transmission latency and further improving the efficiency of data exchange. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 :A flow chart of a method for converting a FlexBus interface to a PCIe interface based on FPGA provided by the present invention;

[0030] Figure 2 : A structural block diagram of a system for converting FlexBus interface to PCIe interface based on FPGA provided by the present invention. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0032] See also Figure 1-2 The present invention provides a technical solution: a system for converting flexbus interface to PCIe interface based on FPGA, the system includes

[0033] FlexBus-DRAM controller for cross-clock domain synchronization and dynamic data width switching AXI protocol conversion engine for mapping FlexBus timing to AXI channel signals (AR / AW / W / R)

[0034] PCIe BAR space mapping module, used to configure DDR physical addresses to PCIe BAR space, supporting end-to-end access

[0035] The DRAM controller includes the following functional modules:

[0036] The clock and reset module is used to generate the DRAM high-frequency clock (ram_clk) and the global reset signal.

[0037] FlexBus signal processing module, used to detect the FlexBus clock edge (FLEXBUS_clk_p / n) and the chip select signal falling edge (FLEXBUS_cs_n).

[0038] Bidirectional data bus control module, used to dynamically switch data direction (receive data in write mode, output high and low 16 bits in read mode in time-sharing).

[0039] DRAM read and write control module, used to generate write enable (wr_en), address (wr_addr / rd_addr) and data path (wr_data / rd_data)

[0040] Based on the above-mentioned FPGA-based FlexBus interface to PCIe interface system, the present invention provides an FPGA-based FlexBus interface to PCIe interface method, the method comprising the following steps:

[0041] 1. The clock and reset module in the system generates the DRAM high-frequency clock (ram_clk) and the global reset signal. This provides a stable clock and reset foundation for subsequent operations, ensuring system initialization and synchronization.

[0042] 2.FlexBus signal processing module: The FlexBus signal processing module in the system receives the clock signal (FLEXBUS_clk_p / n) and chip select signal (FLEXBUS_cs_n) of the FlexBus interface and performs the following operations:

[0043] Detects the FlexBus clock edge (FLEXBUS_clk_p / n) and the chip select signal falling edge (FLEXBUS_cs_n).

[0044] The rising edge (FLEXBUS_clk_p) and falling edge (FLEXBUS_clk_n) of FLEXBUS_clk are captured through a two-stage delay register chain.

[0045] Calculate the rising edge flag: ~FLEXBUS_clk_delay[1]∧FLEXBUS_clk_delay[0].

[0046] Calculate the falling edge flag: FLEXBUS_clk_delay[1]∧~FLEXBUS_clk_delay[0].

[0047] The FLEXBUS_cs signal is synchronized through a two-level register chain to generate a falling edge flag, FLEXBUS_cs_n, to ensure cross-clock domain stability and effectively suppress metastable propagation.

[0048] Bidirectional data bus control module: The bidirectional data bus control module in the system dynamically switches the data direction according to the control signal:

[0049] When the control signal control=0, the data bus is set to a high-impedance state (16'bzzzzzzzzzzzzzzzz) to receive 16-bit data sent by the MCU.

[0050] When control=1, 32-bit DRAM data is output in two stages:

[0051] Low 16-bit stage: control_rd_addr = 0, output rd_data[15:0].

[0052] High 16-bit stage: control_rd_addr = 1 or the falling edge of the FlexBus clock is detected (FLEXBUS_clk_n = 1), and rd_data[31:16] is output.

[0053] By splicing the high and low 16 bits in time-sharing mode, the FlexBus data is converted into 32-bit AXI data to adapt to the timing requirements of the FlexBus and ensure the correct transmission of the data.

[0054] DRAM read / write control module: After the bidirectional data bus control module completes the data direction switching, the DRAM read / write control module in the system performs the following operations according to the control signal:

[0055] Write operation:

[0056] When FLEXBUS_clk_p is valid and chip select is invalid (FLEXBUS_cs=0), a single-cycle write enable pulse (wr_en) is generated.

[0057] The write address counter (wr_addr) is automatically incremented on the rising edge of ram_clk to support burst writes.

[0058] The input data (FLEXBUS_data) is latched into the wr_data register on the rising edge of FLEXBUS_clk_p.

[0059] Read operation:

[0060] In read mode (control=1), the falling edge of FLEXBUS_clk triggers the read address (rd_addr) to increment.

[0061] The control_rd_addr state machine switches the high and low 16-bit data to adapt to the FlexBus timing requirements and ensure the flexibility and efficiency of the read operation.

[0062] 5. The AXI protocol conversion module receives 32-bit data from the DRAM controller, encapsulates it into an AXI burst transfer (Burst Length = 2), and writes it to the specified address area of ​​the DDR storage medium. During this process, it generates an AXI write channel signal (AW) and a data channel signal (W), sends the data to the DDR storage medium, and confirms the data write via the AXI write response channel (B). Simultaneously, it preloads data into the PCIe transmission queue based on the AXI burst length, reducing link latency and significantly improving data transmission efficiency.

[0063] 6.FlexBus data (FLEXBUS_data) is converted into 32-bit AXI data (WDATA / RDATA) by splicing the high and low 16 bits in time-sharing. The FlexBus address (FlexBUS_addr) is mapped to the AXI write address (AWADDR) and read address (ARADDR) after address alignment and burst length configuration (ARLEN / AWLEN). The FlexBus clock (FlexBUS_clk) is synchronized with the AXI clock (ACLK) through a cross-clock domain asynchronous FIFO buffer to ensure data integrity and stability.

[0064] 7. The DDR storage medium receives AXI burst data and writes it to the specified address area. When the PCIe device initiates a read request, the PCIe BAR space mapping module converts the read request into an AXI read request signal (AR). The DDR storage medium reads the data from the specified address and returns it, supporting efficient read and write operations.

[0065] 8. The PCIe BAR space mapping module maps the DDR physical address segment to the BAR0 space of the PCIe device, supporting direct addressing. When the PCIe device initiates a read or write request, the mapping module converts the request address (e.g., 0x80000000 to 0x8FFFFFFF) into a DDR physical address, generates a TLP packet through the AXItoPCIe bridge logic, splits the large block of AXI data into the PCIe maximum payload (e.g., 256B) to achieve DDR access, and adapts the link layer efficiency. After the adaptation signal is sent to the DDR storage medium, the return data is converted into a PCIe signal and sent to the PCIe device to ensure efficient PCIe interaction.

[0066] 9. PCIe devices initiate read and write requests through the BAR space. During read operations, the mapping module converts the read request into an AXI read request. The DDR storage medium returns the data, which the mapping module converts into a PCIe signal and sends to the PCIe device. During write operations, the mapping module converts the write request into an AXI write request. The DDR storage medium writes the data and returns a write response signal, supporting efficient PCIe read and write operations.

[0067] Through the above steps, efficient conversion from the FPGA-based FlexBus interface to the PCIe interface is achieved, ensuring smooth data transmission and processing between different interfaces, while optimizing data transmission efficiency and system stability.

[0068] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for converting a FlexBus interface to a PCIe interface based on FPGA, characterized in that: The following steps are involved: Step 1: The FlexBus interface DRAM controller receives 16-bit data from the FlexBus interface, converts the data to 32-bit width through dynamic data width switching and time-sharing output logic, and then stores it in DRAM; Step 2: The AXI protocol conversion module receives the 32-bit data from the DRAM controller, encapsulates it into an AXI burst transmission, and writes it to the specified address area of ​​the DDR storage medium; Step 3: The PCIe BAR space mapping module maps the DDR physical address segment to the PCIe BAR space through the AXItoPCIe bridge logic; Step 4: The PCIe device initiates read and write requests through the BAR space, converts them into AXI signals and interacts with the DDR storage medium to achieve efficient data transmission.

2. The method for converting a FlexBus interface to a PCIe interface based on FPGA according to claim 1, wherein: Step 1 also includes the sub-steps of implementing dynamic data bit width switching and time-sharing output logic: Sub-step 11: The FlexBus signal processing module detects the FlexBus clock edge and the falling edge of the chip select signal, captures the rising and falling edges of the clock through a two-stage delay register chain, and calculates the corresponding edge flags; Sub-step 12: Simultaneously synchronize the chip select signal with two registers to ensure cross-clock domain stability; Sub-step 13: The bidirectional data bus control module dynamically switches the data direction according to the control signal: receiving 16-bit data in write mode and outputting 32-bit DRAM data in two stages in read mode.

3. The method for converting a FlexBus interface to a PCIe interface based on FPGA according to claim 2, wherein: Insert an asynchronous FIFO in the DRAM read path to isolate the FlexBus and DRAM clock domains.

4. The method for converting a FlexBus interface to a PCIe interface based on FPGA according to claim 1, wherein: The AXI protocol conversion module performs protocol conversion based on signal mapping rules. The signal mapping rules are as follows: FlexBus data is converted into 32-bit AXI data by splicing the high and low 16 bits in time-sharing. The FlexBus address is mapped to the AXI write address and read address after address alignment and burst length configuration. The FlexBus clock is synchronized with the AXI clock through a cross-clock domain asynchronous FIFO buffer.

5. The method for converting FlexBus interface to PCIe interface based on FPGA according to claim 1, characterized in that: The address mapping mechanism based on which the DDR physical address segment is mapped to the PCIe BAR space in step 3 is as follows: mapping the DDR physical address segment to the PCIe device BAR0 space, supporting direct addressing on the PCIe side, and generating TLP packets through the AXItoPCIe bridge logic to achieve DDR access.

6. The method for converting a FlexBus interface to a PCIe interface based on FPGA according to claim 1, wherein: In step 2, when the AXI protocol conversion module encapsulates 32-bit data into AXI burst transmission, it preloads data into the PCIe transmission queue according to the AXI burst length to reduce link latency; and splits large blocks of AXI data into the PCIe maximum payload (such as 256B) to adapt to the link layer efficiency and improve data transmission efficiency.

7. The method for converting a FlexBus interface to a PCIe interface based on FPGA according to claim 1, wherein: In step 3, the built-in clock domain conversion logic of the PCIe IP core is used to achieve seamless conversion between the AXI clock domain and the PCIe clock domain without the need for additional design, ensuring stable data transmission between different clock domains.

8. A system for converting a FlexBus interface to a PCIe interface based on an FPGA, the system comprising: FlexBus-DRAM controller for cross-clock domain synchronization and dynamic data bit width switching; AXI protocol conversion engine, used to map FlexBus timing to AXI channel signals; PCIe BAR space mapping module, used to configure DDR physical addresses to PCIe BAR space, supporting end-to-end access; The DRAM controller includes the following functional modules: Clock and reset module, used to generate DRAM high-frequency clock and global reset signal; FlexBus signal processing module, used to detect the FlexBus clock edge and chip select signal falling edge; The bidirectional data bus control module is used to dynamically switch the data direction, where the write mode receives data and the read mode outputs the high and low 16 bits in a time-sharing manner; DRAM read / write control module, used to generate write enable, address and data paths.

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