Bus interface with polarity correction function and polarity correction method

Abstract

The invention discloses a bus interface with a polarity correction function and a polarity correction method. The bus interface comprises a DCR measurement circuit used for applying voltage to an X1 unknown line network and an X2 unknown line network based on a backup power supply, a first resistor and a second resistor in a standby power state, measuring DCR parameters of the X1 unknown line network and the X2 unknown line network, and obtaining a first DCR measurement result and a second DCR measurement result respectively; the comparison circuit is used for comparing numerical values of the first DCR measurement result and the second DCR measurement result to obtain a polarity detection result signal; the state latch circuit is used for latching the polarity detection result signal when the main power supply network is activated; and the line sequence switching circuit is used for switching the connection and disconnection of the X1 unknown line network and the X2 unknown line network with the preceding-stage A line network and the preceding-stage B line network based on the polarity detection result signal in a constant electric state. Therefore, polarity detection and correction of the two introduced unknown line networks are realized.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a bus interface with a polarity correction function, a polarity correction method, and a communication node device. Background Art

[0002] EIA-485 (also known as RS-485) is a standard for multipoint communication within the physical layer of the OSI model, specifying electrical characteristics for two-wire, half-duplex, balanced transmission lines. Digital communication networks that implement this standard can efficiently communicate over long distances in environments with electronic noise, making it ideal for use in industrial automation environments.

[0003] EIA-485 uses the differential mode voltage between two transmission cables, line A (positive differential end) and line B (negative differential end). ( ) represents bus logic, when the differential mode voltage between AB lines is greater than When the bus logic is 1, the differential mode voltage between the AB lines is is less than When the bus logic is 0, the differential mode voltage between the AB lines is When the value is near zero, it indicates that the bus logic is uncertain. Because EIA-485 uses differential signaling to transmit data, it has extremely strong common-mode interference immunity. Furthermore, because the common-mode voltage range on the EIA-485 bus is only -7.0V to +12.0V (RS-232 is -15.0V to +15.0V), EIA-485 also offers strong electrical safety, making its interface circuits less susceptible to damage. For these reasons, the EIA-485 communication standard is often used in industrial environments with harsh electromagnetic environments to meet on-site communication needs such as data transmission and process control.

[0004] However, the EIA-485 standard only specifies electrical characteristics and signal functions, and does not restrict the order or names of the connector's A and B pins. When interconnecting devices from different manufacturers that adhere to the EIA-485 standard, wire A must be connected to wire A and wire B to wire B; otherwise, normal communication will not occur. Equipment manufacturers typically design the EIA-485 physical interface based on company standards or internal design practices. For example, some devices define their interfaces as A / B, while others as + / -. This can easily lead to bus malfunctions due to incorrect wire sequence correspondence during interconnection, making manual error correction difficult.

[0005] Therefore, how to provide a circuit for automatically detecting and correcting the line sequence correspondence between line A and line B is a key research topic for those skilled in the art. Summary of the Invention

[0006] In a first aspect, the present application provides a bus interface with a polarity correction function, the bus interface comprising: a power management circuit, a DC resistance (DCR) measurement circuit, a comparison circuit, a state latch circuit, and a line sequence switching circuit; the power management circuit is configured to use a backup power supply network to power the DCR measurement circuit, the comparison circuit, and the state latch circuit when the bus interface is in a backup power state, and use a main power supply network to power the state latch circuit and the line sequence switching circuit when the bus interface is in a normal power state; the DCR measurement circuit, the comparison circuit, the state latch circuit, and the line sequence switching circuit are cascaded, the DCR measurement circuit includes an X1 unknown line network and an X2 unknown line network for docking with an external bus network, and the line sequence switching circuit includes docking components for connecting to the A line network and the B line network of the preceding stage of the bus interface respectively; the backup power supply network is connected to one end of a first resistor, and the other end of the first resistor is connected to the X1 unknown line network, the backup power supply network is connected to one end of a second resistor, and the other end of the second resistor is connected to the The X2 unknown line network is connected; the DCR measurement circuit is used to apply voltage to the X1 unknown line network and the X2 unknown line network based on the backup power supply, the first resistor, and the second resistor in the backup power state, and measure the DCR parameters of the X1 unknown line network and the X2 unknown line network to obtain a first DCR measurement result and a second DCR measurement result respectively; the comparison circuit is used to compare the numerical values ​​of the first DCR measurement result and the second DCR measurement result to obtain a polarity detection result signal, and the polarity detection result signal is used to indicate The unknown line corresponding to the DCR measurement result with a larger value is connected to the A-line network of the preceding stage, and the unknown line corresponding to the DCR measurement result with a smaller value is connected to the B-line network of the preceding stage; the state latch circuit is used to latch the polarity detection result signal when the main power network is activated, and continuously output the polarity detection result signal to the line sequence switching circuit; the line sequence switching circuit is used to switch the connection and disconnection of the X1 unknown line network and the X2 unknown line network with the A-line network and the B-line network of the preceding stage based on the polarity detection result signal in the normal power state.

[0007] It should be noted that according to the requirements of the fault protection circuit in the EIA-485 bus standard, the bus should be equipped with a fault protection circuit, that is, a bias resistor pull-up (a resistor is connected between the A line network and the positive power supply) and a bias resistor pull-down (a resistor is connected between the B line network and the ground GND) should be set on the A and B lines of the bus respectively to reduce the bus differential mode voltage in the idle state. Forced to a certain voltage difference range (above 200mV).

[0008] The bus interface provided in this application is based on the characteristics of the external bus network connected to the bus interface via the X1 docking component and the X2 docking component, in which the A line is provided with a pull-up bias resistor and the B line is provided with a pull-down bias resistor. In the backup power state, a DCR measurement circuit is used to measure the DCR parameters of each of the X1 unknown line network and the X2 unknown line network. In the unknown line network belonging to the B line, a loop is formed between the backup power supply, the additional resistor, the pull-down bias resistor, and the GND network. Due to the voltage divider effect of the additional resistor and the pull-down bias resistor, a stable and low voltage value is obtained at the unknown line network belonging to the B line (for example, assuming the backup power supply is 3.0V, this voltage value is generally between 0.1V and 0.3V). In the unknown line network belonging to line A, since line A does not have a pull-down bias resistor (that is, it is not grounded), a loop cannot be formed. Therefore, the unknown line network belonging to line A obtains a stable voltage value that is higher than the unknown line network belonging to line B (for example, assuming the backup power supply is 3.0V, the voltage value is generally around 3.0V), thereby distinguishing whether the X1 unknown line network and the X2 unknown line network connected to the bus interface belong to line A or line B.

[0009] It should be noted that in the actual deployment of the EIA-485 standard bus network, the bias circuit (bias resistor pull-up and bias resistor pull-down are set on the A and B lines of the bus respectively) is usually configured by the system integrator at the end of the bus segment. It should be noted that the external bias circuit does not fall within the scope of the bus interface provided in this application. The bus interface provided in this application is the minimum achievable product independent of the external bias circuit, which is in line with the deployment method of the bias resistor circuit in the EIA-485 standard bus network.

[0010] The embodiment of the present application provides a bus interface with a polarity correction function. In the standby power state, based on a DCR measurement circuit and a comparison circuit, the difference in DCR parameters between the A-line network and the B-line network is used to detect the polarity of two introduced unknown line networks. After power-on (normal power state), based on a state latch circuit and a line sequence switching circuit, the polarity connection relationship between the two unknown bus line networks and the internal A-line and B-line is automatically corrected.

[0011] Therefore, on the one hand, the problem of inconsistent order, position or name of the A-line pins and the B-line pins of EIA-485 standard equipment from different manufacturers, which leads to interconnection errors, is solved, and communication equipment equipped with the bus interface provided by this application is supported to be blindly connected to the bus network in any line sequence.

[0012] On the other hand, by using a backup power supply to complete polarity detection before the equipment is powered on, the detection time after power-on can be omitted, which is relatively shortening the polarity correction time after power-on; and, when the main power supply is activated, the state latch circuit is used to latch the polarity detection result, so that the state latch circuit continuously outputs the polarity detection result signal to drive the line sequence switching circuit, which can avoid the state latch circuit latching the continuous output drive signal in advance, resulting in continuous power consumption of the backup power supply and insufficient power supply of the backup power supply; and, after the main power network is powered on, the line sequence switching circuit performs a correction action based on the main power supply and maintains the corrected state, avoiding premature execution of correction and maintaining the corrected state, which causes continuous power consumption of the backup power supply.

[0013] In some possible implementations, the power management circuit is further configured to use the main power network to power the DCR measurement circuit and the comparison circuit in the normal power state; the DCR measurement circuit is further configured to disable a measurement function of the DCR measurement circuit in the normal power state; and the comparison circuit is further configured to disable a comparison function of the comparison circuit in the normal power state.

[0014] In this manner, after the main power supply is powered on and the polarity detection result is latched, the measurement function of the DCR measurement circuit and the comparison function of the comparison circuit are disabled, thereby reducing ineffective power consumption.

[0015] In some possible implementations, the state latch circuit includes a capacitor, which is used to delay the input signal of the state latch circuit so that when the comparison circuit switches from a self-powered state to a normal power state, the state latch circuit stably receives the polarity detection result signal.

[0016] This method perfectly solves the signal synchronization problem through the combination of capacitor delay and edge triggering, avoiding the use of expensive non-volatile memory.

[0017] In some possible implementations, the power management circuit is further configured to use the main power network to charge the backup power network after the main power network is activated.

[0018] In some possible implementations, the power management circuit includes: a resistor R101, a diode D101, and a battery BT101; wherein, one end of the resistor R101 is connected to the main power network, and the other end is connected to the anode of the diode D101, the cathode of the diode D101 is connected to the backup power network and the positive electrode of the above-mentioned battery BT101, and the negative electrode of the battery BT101 is connected to the GND network.

[0019] In some possible implementations, the DCR measurement circuit includes: a resistor R201, a resistor R202, a resistor R203, a resistor R204, a resistor R205, a transistor Q201, and a transistor Q202; one end of the resistor R201 is connected to the main power supply network, and the other end is connected to one end of the resistor R202 and one end of the resistor R203 respectively; the other end of the resistor R203 is connected to the GND network; the other end of the resistor R202 is connected to the base of the transistor Q201 and the base of the transistor Q202 respectively; the emitter of the transistor Q201 and the emitter of the transistor Q202 are both connected to the backup power supply network; the collector of the transistor Q201 and the collector of the transistor Q202 are connected to the X1 unknown line network and the X2 unknown line network respectively through the resistor R204 and the resistor R205.

[0020] In some possible implementations, the comparison circuit includes an analog switch chip U301, an analog switch chip U303, a voltage comparator chip U302, a resistor R301, a resistor R302, and a resistor R303, wherein the first DCR measurement result and the second DCR measurement result are respectively reflected as voltage signals in the X1 unknown line network and the X2 unknown line network in the backup power state, the comparison circuit is connected to the X2 unknown line network through the common terminal pin 5 of the analog switch chip U301 to obtain the second DCR measurement result, and the comparison circuit is connected to the X1 unknown line network through the common terminal pin 5 of the analog switch chip U303 to obtain the first DCR measurement result; the input terminal pin 1 of the analog switch chip U301 and the input terminal pin 1 of the analog switch chip U303 are both connected to the main power supply network, and the power terminal pin 2 of the power supply terminal of the analog switch chip U301 and the power terminal pin 2 of the analog switch chip U303 are both connected to the backup power supply network. The GND terminal pin 3 of the analog switch chip U301 and the GND terminal pin 3 of the analog switch chip U303 are both connected to the GND network, the normally closed terminal pin 4 of the analog switch chip U301 and the normally closed terminal pin 4 of the analog switch chip U303 are respectively connected to one end of the resistor R302 and one end of the resistor R303, and the other end of the resistor R302 and the other end of the resistor R303 are respectively connected to the non-inverting input of the voltage comparator chip U302. The first pin of the GND terminal and the third pin of the inverting input terminal of the voltage comparator chip U302, the second pin of the GND terminal of the voltage comparator chip U302 is connected to the GND network, the fifth pin of the power terminal of the voltage comparator chip U302 is connected to the backup power supply network, the resistor R301 is connected between the fifth pin of the power terminal of the voltage comparator chip U302 and the fourth pin of the output terminal of the voltage comparator chip U302, and the fourth pin of the output terminal of the voltage comparator chip U302 is connected to the first signal output network.

[0021] In some possible implementations, the state latch circuit includes a D-type trigger chip U401, a resistor R401, and a capacitor C401, wherein the data terminal pin 1 of the D-type trigger chip U401 is connected to the first signal output network of the comparison circuit, and is simultaneously connected to the GND network through the capacitor C401, the clock terminal pin 2 of the D-type trigger chip U401 is connected to the main power supply network, the GND terminal pin 3 of the D-type trigger chip U401 is connected to the GND network, the output terminal pin 4 of the D-type trigger chip U401 is connected to the second signal output network through the resistor R401, and the power terminal pin 5 of the D-type trigger chip U401 is connected to the backup power supply network.

[0022] In some possible implementations, the line sequence switching circuit includes: an ultra-small signal electromagnetic relay U501, a transistor Q501, a resistor R501, and a resistor R502, wherein one end of the resistor R501 is connected to the second signal output network of the state latch circuit, the other end of the resistor R501 is respectively connected to one end of the resistor R502 and the base of the transistor Q501, the other end of the resistor R502 is connected to the GND network, the emitter of the transistor Q501 is connected to the GND network, the collector of the transistor Q501 is connected to the first pin of the control a terminal of the ultra-small signal electromagnetic relay U501, and the ultra-small signal The 8th pin of the control b end of the electromagnetic relay U501 is connected to the main power supply network, the 2nd pin of the normally closed end of channel 1 of the ultra-miniature signal electromagnetic relay U501 and the 5th pin of the normally open end of channel 2 of the ultra-miniature signal electromagnetic relay U501 are both connected to the X1 unknown line network, the 4th pin of the normally open end of channel 1 of the ultra-miniature signal electromagnetic relay U501 and the 7th pin of the normally closed end of channel 2 of the ultra-miniature signal electromagnetic relay U501 are both connected to the X2 unknown line network, the 3rd pin of the common end of channel 1 of the ultra-miniature signal electromagnetic relay U501 is connected to the A line network, and the 6th pin of the common end of channel 2 of the ultra-miniature signal electromagnetic relay U501 is connected to the B line network.

[0023] In a second aspect, the present application further provides a polarity correction method, which is applied to the bus interface with a polarity correction function according to any one of the first aspects, the method comprising: in a standby power state, based on a DCR measurement circuit, measuring the DCR parameters of each of the X1 unknown line network and the X2 unknown line network to obtain a first DCR measurement result and a second DCR measurement result; in the standby power state, based on a comparison circuit, comparing the numerical values ​​of the first DCR measurement result and the second DCR measurement result to obtain a polarity detection result signal, the polarity detection result signal being used to indicate that the unknown line corresponding to the larger DCR measurement result is connected to the A line of the preceding stage of the bus interface, and the unknown line corresponding to the smaller DCR measurement result is connected to the B line of the preceding stage; when the main power network is activated, based on a state latch circuit, latching the polarity detection result signal and continuously outputting the polarity detection result signal to the line sequence switching circuit; in a normal power state, the polarity detection result signal drives the line sequence switching circuit to switch the X1 unknown line network and the X2 unknown line network on and off with the A line and B line of the preceding stage.

[0024] In a third aspect, the present application provides a bus interface with a polarity correction function, the bus interface comprising: Power management circuit, DCR measurement circuit, comparison circuit, and line sequence switching circuit; The power management circuit is used to use a backup power supply network to supply power to the bus interface when the bus interface is in a backup power state; The DCR measurement circuit, the comparison circuit, and the line sequence switching circuit are cascaded. The DCR measurement circuit includes docking components for an X1 unknown line network and an X2 unknown line network connected to an external bus network. The line sequence switching circuit includes docking components for communicating with an A line network and a B line network of a preceding stage of the bus interface, respectively. The DCR measurement circuit also includes a first resistor and a second resistor. The backup power supply network is connected to one end of the first resistor, and the other end of the first resistor is connected to the X1 unknown line network. The backup power supply network is connected to one end of the second resistor, and the other end of the second resistor is connected to the X2 unknown line network. The DCR measurement circuit is configured to, in the backup power state, apply a voltage to the X1 unknown line network and the X2 unknown line network based on the backup power supply, the first resistor, and the second resistor, and measure DCR parameters of the X1 unknown line network and the X2 unknown line network to obtain a first DCR measurement result and a second DCR measurement result, respectively; The comparison circuit is configured to compare the numerical values ​​of the first DCR measurement result and the second DCR measurement result in the standby power state to obtain a polarity detection result signal, wherein the polarity detection result signal is configured to instruct the unknown line corresponding to the DCR measurement result with the larger numerical value to be connected to the A-line network of the preceding stage, and to instruct the unknown line corresponding to the DCR measurement result with the smaller numerical value to be connected to the B-line network of the preceding stage; The line sequence switching circuit is used to switch the conduction and disconnection of the X1 unknown line network and the X2 unknown line network with the A line network and the B line network of the previous stage based on the polarity detection result signal in the standby power state.

[0025] This approach allows the bus interface to detect the polarity of two unknown bus lines before powering up the device and in standby mode, using the difference in DCR parameters between the A-line network and the B-line network, using a DCR measurement and comparison circuit. Furthermore, the line sequence switching circuit automatically calibrates the polarity of the two unknown bus lines with the internal A-line and B-line networks, respectively. This solves the problem of inconsistent order or names of the A-line and B-line pins on EIA-485-compliant devices from different manufacturers, which can lead to interconnection errors.

[0026] In some possible implementations, the power management circuit in the bus interface provided by the third aspect also includes a main power network, and the power management circuit is further used to use the main power network to charge the backup power network after the main power network is activated.

[0027] In a fourth aspect, the present application also provides a communication node device, which includes a core controller, an EIA-485 bus transceiver circuit, and a bus interface (the bus interface is a bus interface of any implementation method in the first aspect or the third aspect), the core controller and the EIA-485 bus transceiver circuit are connected through a transmit data line TX and a receive data line RX, and the EIA-485 bus transceiver circuit is connected to the bus interface through an A line and a B line.

[0028] It is understood that the polarity correction method and communication node device provided above, each of which has a polarity correction function, are implemented based on the bus interface of any one of the first or third aspects of the embodiments of this application. Therefore, the beneficial effects achieved by the method can be referenced to the beneficial effects of the corresponding bus interface and will not be further described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a hardware circuit topology diagram of a bus interface with a polarity correction function provided by an embodiment of the present application; Figure 2 is a circuit schematic diagram of a power management circuit provided in an embodiment of the present application; Figure 3 1 is a circuit schematic diagram of a DCR measurement circuit provided in an embodiment of the present application; Figure 4 is a circuit schematic diagram of a comparison circuit provided in an embodiment of the present application; Figure 5 is a circuit schematic diagram of a state latch circuit provided in an embodiment of the present application; Figure 6 This is a circuit schematic diagram of a line sequence switching circuit provided in an embodiment of the present application; Figure 7 This is a hardware circuit topology diagram of an embodiment of the present application, which shows a bus interface with a polarity correction function provided by the present application being applied to an EIA-485 communication node device; Figure 8 This is a schematic diagram of a typical EIA-485 communication bus network structure topology provided in an embodiment of the present application; Figure 9 This is a circuit schematic diagram of an EIA-485 bus configuration device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the invention objectives, technical features, and beneficial effects of this application clearer and easier to understand, the specific implementation methods and examples of this application will be clearly and completely described below in conjunction with some drawings. Obviously, the specific implementation methods and examples described below are only part of the concrete presentation methods of this application, and are not the entire content of this application. Based on this part of the content, all other concrete presentation methods obtained by ordinary technicians in this field without making creative work are within the scope of protection of the claims of this application.

[0031] The present application will be further described below with reference to the accompanying drawings.

[0032] See also Figure 1 , Figure 1 This is a flow chart of a bus interface with polarity correction function provided by an embodiment of the present application. Figure 1 As shown, the bus interface includes: Power management circuit, DCR measurement circuit, comparison circuit, status latch circuit, and line sequence switching circuit; The power management circuit is used to use the backup power network (shown as Backup_Power in the figure) to power the DCR measurement circuit, the comparison circuit, and the status latch circuit when the bus interface is in the backup power state, and to use the main power network (shown as Main_Power in the figure) to power the status latch circuit and the line sequence switching circuit when the bus interface is in the normal power state; The DCR measurement circuit, the comparison circuit, the state latch circuit, and the line sequence switching circuit are cascaded. The DCR measurement circuit includes a docking component for accessing the X1 unknown line network and the X2 unknown line network of the external bus network (in Figure 1 (shown as X1 and X2 docking components in the figure), the line sequence switching circuit includes docking components for respectively communicating with the positive differential end A line network and the negative differential end B line network of the preceding stage of the bus interface; the DCR measurement circuit also includes a first resistor and a second resistor, the backup power supply network is directly or indirectly connected to one end of the first resistor, the other end of the first resistor is connected to the X1 unknown line network, the backup power supply network is directly or indirectly connected to one end of the second resistor, and the other end of the second resistor is connected to the X2 unknown line network; a DCR measurement circuit for applying a voltage to the X1 unknown line network and the X2 unknown line network based on a backup power supply, a first resistor, and a second resistor in a backup power state, and measuring DCR parameters of the X1 unknown line network and the X2 unknown line network to obtain a first DCR measurement result and a second DCR measurement result, respectively; a comparison circuit, configured to compare the numerical values ​​of the first DCR measurement result and the second DCR measurement result to obtain a polarity detection result signal, wherein the polarity detection result signal is configured to instruct to connect the unknown line corresponding to the larger DCR measurement result to the A-line network of the preceding stage, and to connect the unknown line corresponding to the smaller DCR measurement result to the B-line network of the preceding stage; A state latch circuit, used for latching a polarity detection result signal when the main power network is activated, and continuously outputting the polarity detection result signal to the line sequence switching circuit; The line sequence switching circuit is used to switch the conduction and disconnection of the X1 unknown line network and the X2 unknown line network and the previous stage A line network and B line network based on the polarity detection result signal in the normal power state.

[0033] In the embodiment of the present application, the DCR measurement circuit, the comparison circuit, the state latch circuit, and the line sequence switching circuit are connected in series according to the signal flow direction.

[0034] In an embodiment of the present application, the X1 unknown line network and the X2 unknown line network are divided into two channels after being introduced into the bus interface, wherein the first channel is connected to the DCR measurement circuit, and the second channel is connected to the line sequence switching circuit. Specifically, the first channel of the X1 unknown line network and the X2 unknown line network is connected to the DCR measurement circuit to measure the DCR parameters of the X1 unknown line network and the X2 unknown line network, respectively. The measurement results are transmitted to the comparison circuit for comparison, and the comparison result signal is transmitted to the state latch circuit. Finally, the line sequence switching circuit completes the line sequence switching operation of the second channel X1 unknown line network and the X2 unknown line network and the previous stage A line network and B line network based on the drive signal output by the state latch circuit.

[0035] In an embodiment of the present application, in a backup power state, the DCR measurement circuit applies a voltage to the X1 unknown line network based on the backup power supply and the first resistor, and applies a voltage to the X2 unknown line network based on the backup power supply and the second resistor, so as to measure the DCR parameters at the two unknown line networks. It can be understood that the additional resistors (the first resistor and the second resistor) are used to prevent the unknown line network from being directly connected to the backup power supply, resulting in the voltage at the unknown line network always being the backup power supply voltage, and the DCR parameter of the unknown line network cannot be truly measured.

[0036] In the embodiment of the present application, the connection relationship between the backup power supply network and one end of the first resistor means that there is a direct or indirect connection relationship between the backup power supply and the first resistor. As an example, the backup power supply is directly conductively connected to the first resistor, and the DCR measurement circuit can provide a voltage signal to the X1 unknown line network based on the backup power supply in both the backup power state and the normal power state, and the measurement function of the DCR measurement circuit continues to operate. As another example, the backup power supply and the first resistor are indirectly connected through a transistor (or other suitable switching component) to activate the measurement function of the DCR measurement circuit in the backup power state (that is, provide a voltage signal to the X1 unknown line network based on the backup power supply and the first resistor), and deactivate the measurement function of the DCR measurement circuit in the normal power state (that is, disconnect the conductive relationship between the backup power supply and the first resistor). The connection relationship between the backup power supply and the second resistor is similar and will not be described in detail.

[0037] It is understandable that the essence of direct current resistance (DCR) measurement is indirectly achieved through voltage drop. The DCR parameter measured by the DCR measurement circuit provided in this application can be a voltage signal parameter or an impedance signal parameter, where the voltage signal parameter is proportional to the impedance signal parameter. For ease of understanding and description, the DCR parameter is shown as a voltage signal parameter as an example.

[0038] The embodiment of the present application provides a bus interface with a polarity correction function. In the standby power state, based on a DCR measurement circuit and a comparison circuit, the difference in DCR parameters between the A-line network and the B-line network is used to detect the polarity of two introduced unknown line networks. After power-on (normal power state), based on a state latch circuit and a line sequence switching circuit, the polarity connection relationship between the two unknown bus line networks and the internal A-line and B-line is automatically corrected.

[0039] The bus interface provided in this application is applicable to any two-wire bus network that complies with the EIA-485 standard. The bus network must comply with the EIA-485 standard and be equipped with a fault protection circuit, that is, the A and B lines of the bus are pulled up and down respectively through bias resistors to reduce the bus differential mode voltage in the idle state to Forced to be above 200mV. In addition, the pull-up and pull-down bias resistor parameters should be calculated and configured in accordance with the contents of the EIA-485 standard. For example, the pull-up and pull-down bias resistor parameters are generally consistent and range from 680Ω to 1000Ω. Preferably, this application is applicable to any two-wire bus network that complies with the EIA-485 standard, but each node connected to the bus network must comply with the EIA-485 standard to limit the common-mode voltage and ground potential difference, that is, the reference ground potential of each bus node must be kept consistent.

[0040] In some possible implementations, the backup power supply network is indirectly connected to the first resistor and the second resistor, respectively. The power management circuit is further configured to use the main power supply network to power the DCR measurement circuit and the comparison circuit in a normal power state. The DCR measurement circuit is further configured to disable a measurement function of the DCR measurement circuit in a normal power state. The comparison circuit is further configured to disable a comparison function of the comparison circuit in a normal power state.

[0041] In this manner, after the main power supply is powered on and the polarity detection result is latched, the measurement function of the DCR measurement circuit and the comparison function of the comparison circuit are disabled, thereby reducing ineffective power consumption.

[0042] In some possible implementations, the state latch circuit includes a capacitor for delaying the input signal of the state latch circuit so that when the comparison circuit switches from the self-powered state to the normal power state, the state latch circuit stably receives the polarity detection result signal.

[0043] In this way, a capacitor is used to delay the input signal of the state latch circuit, ensuring that the circuit stably and reliably receives valid input signals, avoiding the problem that the output level changes instantly when the comparison circuit switches from the self-powered state to the normal power state, making it difficult for the state latch circuit to receive valid input signals.

[0044] In some possible implementations, the power management circuit is further configured to use the main power network to charge the backup power network after the main power network is activated.

[0045] The following is an example of the structure of each circuit in the bus interface.

[0046] In some possible implementations, the circuit schematic diagram of the power management circuit provided in this application is as follows: Figure 2 As shown, it includes a resistor R101, a diode D101, and a battery BT101.

[0047] One end of the resistor R101 is connected to the main power network, and the other end is connected to the anode of the diode D101. The cathode of the diode D101 is connected to the backup power network and the positive electrode of the battery BT101. The negative electrode of the battery BT101 is connected to the GND network.

[0048] In the backup power state, the main power network loses power, the diode D101 is in the cut-off state, and the battery BT101 starts to supply power to the backup power network.

[0049] In the normal power state, the main power network is powered on, and the main power network charges the battery BT101 through the current limiting effect of the resistor R101 and the unidirectional conduction effect of the diode D101, while supplying power to the backup power network.

[0050] As an example, the resistance of the resistor R101 is 10k ohms, or it may be other suitable values, which are not limited in this document.

[0051] Preferably, to ensure compatibility of the subsequent circuits with the voltages of the main power network and the backup power network, as well as the safety of the main power supply charging the battery BT101, the voltage of the battery BT101 is equal to the voltage of the main power network, or the voltage of the main power network is slightly greater than the voltage of the battery BT101. As an example, if the voltage standard of the battery BT101 is 3.0V, the main power network should adopt a DC 3.3V standard to ensure compatibility of the subsequent circuits with the voltages of the main power network and the backup power network, as well as the safety of the main power supply charging the battery BT101.

[0052] Preferably, the main power network should be connected to the front-stage low-voltage DC power supply. For example, if the present application is used as a submodule in a device, the main power supply should be connected to the low-voltage DC power supply inside the device.

[0053] It should be noted that the power management circuit can also be other suitable circuit structures, which are not limited in this document. For example, the diode D101 in the power management circuit can also adopt other alternative designs such as logic gates, analog switch chips, etc., which are not limited in this document.

[0054] In some possible implementations, the circuit schematic diagram of the DCR measurement circuit provided in this application is as follows: Figure 3 As shown, it includes: a resistor R201, a resistor R202, a resistor R203, a resistor R204 (also called a first resistor), a resistor R205 (also called a second resistor), a transistor Q201, and a transistor Q202.

[0055] Among them, one end of resistor R201 is connected to the main power supply network, and the other end is connected to one end of resistors R202 and R203 respectively. The other end of resistor R203 is connected to the GND network. The other end of resistor R202 is connected to the base (pin 1) of transistor Q201 and the base (pin 1) of transistor Q202 respectively. The emitter (pin 2) of transistor Q201 and the emitter (pin 2) of transistor Q202 are both connected to the backup power supply network. The collector (pin 3) of transistor Q201 and the collector (pin 3) of transistor Q202 are connected to the X1 unknown line network and the X2 unknown line network through resistor R204 and resistor R205 respectively.

[0056] In the normal power state, the main power network is powered on. The main power network makes the base voltage and emitter voltage of transistor Q201 and transistor Q202 equal to each other through the voltage division of resistors R201 and R203. Neither transistor Q201 nor transistor Q202 will be turned on, and the DCR measurement function will be disabled.

[0057] In the backup power state, the main power network loses power. A closed loop is formed starting from the backup power network, passing through the emitters of transistors Q201 and Q202, resistors R202 and R203, and finally to the GND network. A forward DC current flows in the closed loop, causing transistors Q201 and Q202 to turn on and operate in the saturation region, and the DCR measurement function is activated.

[0058] When the measurement function of the DCR measurement circuit is activated, the voltages at the collectors of transistors Q201 and Q202 are transmitted from resistors R204 and R205 to the X1 unknown line network and the X2 unknown line network, respectively, to implement the DCR measurement function of the GND network, and obtain a first DCR measurement result and a second DCR measurement result, respectively.

[0059] Assuming the X1 unknown line network represents the B line in the external EIA-485 bus network, and the X2 unknown line network represents the A line in the bus network, the voltage excitation from transistor Q201's emitter, the voltage divider from resistor R204, and the voltage divider from the B line pull-down bias resistor in the bus network, the X1 unknown line network achieves a stable, low voltage, typically between 0.1V and 0.3V, due to the X1 unknown line being a single conductor with very low internal resistance. Since there is no ground loop between transistor Q202's emitter, resistor R205, the A line pull-up bias resistor in the bus network, and the X2 unknown line network, there is no voltage drop. Therefore, the X2 unknown line network achieves a stable, high voltage, typically around 3.0V. Similarly, assuming that the X1 unknown line network is line A in the external EIA-485 bus network and the X2 unknown line network is line B in the bus network, the X1 unknown line network obtains a stable and higher voltage value, and the X2 unknown line network obtains a stable and lower voltage value.

[0060] As an example, the resistance values ​​of resistors R201, R202, R203, R204, and R205 are 1k, 10R, 10k, 10k, and 10k, respectively, or other suitable values, which are not limited in this document.

[0061] With this DCR measurement circuit, the DCR measurement function is activated in the standby power state. After the main power is powered on and the polarity detection result is latched, the measurement function of the DCR measurement circuit is disabled, thereby reducing ineffective power consumption.

[0062] It should be noted that the DCR measurement circuit may also have other suitable circuit structures, which are not limited herein. For example, transistors Q201 and Q202 in the DCR measurement circuit may also use other alternative designs, such as logic gates or analog switch chips, which are not limited herein.

[0063] In some possible implementations, the first and second DCR measurement results can be represented by voltage signals (also understood as impedance signals) in the X1 unknown line network and the X2 unknown line network, respectively, in the standby power state. The comparison circuit obtains the first and second DCR measurement results by connecting the DCR measurement circuit to the same X1 unknown line network and X2 unknown line network. This approach eliminates the need for quantizing the specific numerical values ​​of the DCR measurement results. Instead, the comparison circuit obtains the DCR measurement results of the two unknown line networks by connecting to the unknown line networks. Using analog voltage signals instead of quantized values ​​eliminates intermediate links in the signal chain, reduces costs, and improves reliability.

[0064] It should be noted that in some other possible implementations, the DCR measurement result can be quantified (for example, quantized into a voltage reading, or converted into an impedance value based on the voltage reading) and then transmitted to a comparison circuit for comparison. This document does not limit this.

[0065] In some possible implementations, the circuit schematic diagram of the comparison circuit provided in this application is as follows: Figure 4 As shown, it includes: an analog switch chip U301, an analog switch chip U303, a voltage comparator chip U302, a resistor R301, a resistor R302, and a resistor R303.

[0066] The first DCR measurement result and the second DCR measurement result are respectively reflected as voltage signals in the X1 unknown line network and the X2 unknown line network in the standby power state. The comparison circuit is connected to the X2 unknown line network through the common terminal (pin 5) of the analog switch chip U301 to obtain the above-mentioned second DCR measurement result corresponding to the X2 unknown line network. The comparison circuit is connected to the X1 unknown line network through the common terminal (pin 5) of the analog switch chip U303 to obtain the above-mentioned first DCR measurement result corresponding to the X1 unknown line network. The input terminal (pin 1) of the analog switch chip U301 and the input terminal (pin 1) of the analog switch chip U303 are both connected to the main power supply network, the power terminal (pin 2) of the analog switch chip U301 and the power terminal (pin 2) of the analog switch chip U303 are both connected to the backup power supply network, the GND terminal (pin 3) of the analog switch chip U301 and the GND terminal (pin 3) of the analog switch chip U303 are both connected to the GND network, the normally open terminal (pin 6) of the analog switch chip U301 and the normally open terminal (pin 6) of the analog switch chip U303 are not connected, and the normally closed terminal (pin 4) of the analog switch chip U301 and the normally closed terminal (pin 4) of the analog switch chip U303 are respectively connected to the resistor R302 One end of the resistor R301 and one end of the resistor R303, the other end of the resistor R302 and the other end of the resistor R303 are respectively connected to the non-inverting input terminal (pin 1) of the voltage comparator chip U302 and the inverting input terminal (pin 3) of the voltage comparator chip U302, the GND terminal (pin 2) of the voltage comparator chip U302 is connected to the GND network, the power supply terminal (pin 5) of the voltage comparator chip U302 is connected to the backup power supply network, the resistor R301 is connected between the power supply terminal (pin 5) of the voltage comparator chip U302 and the output terminal (pin 4) of the voltage comparator chip U302, and the output terminal (pin 4) of the voltage comparator chip U302 is connected to the COMP_1 network (also called the first signal output network).

[0067] In the normal power state, driven by the DC voltage of the main power network, the common end (pin 5) of the analog switch chip U301 and the normally closed end (pin 4) of the analog switch chip U301 are disconnected, and the common end (pin 5) of the analog switch chip U303 and the normally closed end (pin 4) of the analog switch chip U303 are disconnected. The first DCR measurement result and the second DCR measurement result will not affect the comparison circuit, so that the comparison function of the comparison circuit is disabled.

[0068] In the standby power state, there is no DC voltage in the main power network, the common end (pin 5) of the analog switch chip U301 and the normally closed end (pin 4) of the analog switch chip U301 are closed, the common end (pin 5) of the analog switch chip U303 and the normally closed end (pin 4) of the analog switch chip U303 are closed, and the DC signal on the X2 unknown line network (the second DCR measurement result) and the DC signal on the X1 unknown line network (the first DCR measurement result) are respectively transmitted to the voltage comparator chip U302 through the analog switch chip U301 and the analog switch chip U303, and respectively through the resistor R302 and the resistor R303 for comparison.

[0069] During the comparison process, if the DC voltage on the X2 unknown line network (the second DCR measurement result) is significantly lower than the DC voltage on the X1 unknown line network (the first DCR measurement result), the output end (pin 4) of the voltage comparator chip outputs a low level (for example, 0V) (also called the first polarity detection result) to the COMP_1 network (also called the first signal output network), indicating that the externally connected X1 unknown line network belongs to the A line and the X2 unknown line network belongs to the B line, connecting the X1 unknown line network to the A line of the preceding stage of the bus interface and connecting the X2 unknown line network to the B line of the preceding stage.

[0070] If the DC voltage on the X2 unknown line network is significantly higher than that on the X1 unknown line network, since the voltage comparator chip U302 uses an open collector OC output mode internally, under the pull-up bias of the resistor R301, the output end (pin 4) of the voltage comparator chip outputs a high level (specifically equal to the backup power supply voltage, for example, if the backup power supply voltage is 3V, the high level is 3V) to the COMP_1 network (also known as the second polarity detection result), which is used to indicate that the X2 unknown line network is connected to the A line of the preceding stage of the bus interface, and the X1 unknown line network is connected to the B line of the preceding stage.

[0071] As an example, the resistance values ​​of the resistor R302 , the resistor R303 , and the resistor R301 are 1k, 1k, and 10k, respectively, or may be other appropriate values, which are not limited herein.

[0072] This comparator circuit, on the one hand, directly accesses the unknown line network to obtain the DCR measurement results of two unknown lines. This uses analog voltage signals instead of quantized values, eliminating intermediate links in the signal chain, reducing costs and improving reliability. Furthermore, the comparison function is activated in the standby power state. After the main power is applied and the polarity detection result is latched, the comparison circuit's comparison function is disabled, reducing inefficient power consumption.

[0073] It should be noted that the comparison circuit may also have other suitable circuit structures, which are not limited herein. For example, the voltage comparison chip in the comparison circuit may also be a device using other voltage comparison principles that meet the requirements, and the analog switch chip may also be a device using other switch design principles that meet the requirements.

[0074] In some possible implementations, the circuit schematic diagram of the state latch circuit provided in this application is as follows: Figure 5 As shown, it includes: a D-type trigger chip U401, a resistor R401, and a capacitor C401, Among them, the data end (pin 1) of the D-type trigger chip U401 is connected to the COMP_1 network of the comparison circuit, and is also connected to the GND network through the capacitor C401. The clock end (pin 2) of the D-type trigger chip U401 is connected to the main power supply network. The GND end (pin 3) of the D-type trigger chip U401 is connected to the GND network. The output end (pin 4) of the D-type trigger chip U401 is connected to the RELAY_CTRL network (also called the second signal output network) through the resistor R401. The power end (pin 5) of the D-type trigger chip U401 is connected to the backup power supply network.

[0075] Exemplarily, the resistance of the resistor R401 is 10R, or may be other suitable values, which are not limited herein.

[0076] In both the normal power state and the backup power state, the clock end (pin 2) of the D-type trigger chip U401 is a stable voltage signal. Since the D-type trigger chip U401 is a rising edge triggered mode, the output of the D-type trigger U401 will not change. When and only when the bus interface switches from the backup power state to the normal power state, the clock end (pin 2) of the D-type trigger chip U401 is affected by the power-on operation of the main power network and receives a voltage rising edge. The polarity detection result signal (TTL level state) of the COMP_1 network at this time is then transmitted to the output end (pin 4) of the D-type trigger and maintained in this state. In the normal power state, the backup power network and the RELAY_CTRL network are used to continuously output the polarity detection result signal to the line sequence switching circuit.

[0077] However, when the pre-stage comparator circuit switches from its self-powered state to its normal powered state, analog switch chips U301 and U303 switch the connections between the X1 unknown line network and the X2 unknown line network and voltage comparator chip U302, causing a momentary change in the output level and making it difficult for the circuit to receive valid input signals. Therefore, capacitor C401 is used to delay the input signal of this circuit to ensure stable and reliable reception of valid input signals.

[0078] For example, the parameters of capacitor C401 should be 100nF. For the more common MLCC (chip capacitor) product model CC0603KRX7R9BB104 designed and produced by YAGEO, according to the nominal parameters in its datasheet, when a 3.0V voltage is applied to its two ends and it is saturated with charge, the applied 3.0V voltage is disconnected, and it takes about 2.3ms for the voltage at both ends to drop from 3.0V to 0.6V (80% drop). This delay time is long enough for the state latch circuit to effectively recognize the input signal and respond.

[0079] This state latch circuit, after the main power supply is powered on, latches the polarity detection result using the state latch circuit, causing the state latch circuit to continuously output the polarity detection result signal to drive the line sequence switching circuit. This can prevent the state latch circuit from prematurely latching and continuously outputting the drive signal, which could cause the backup power supply to continue consuming power and causing insufficient backup power supply. Furthermore, a capacitor is used to delay the input signal of the state latch circuit, ensuring that the circuit stably and reliably receives valid input signals. This avoids the problem of the output level changing momentarily when the comparison circuit switches from the self-powered state to the normal power state, making it difficult for the state latch circuit to receive valid input signals.

[0080] It should be noted that the state latch circuit provided in this application may also have other structures, which are not limited in this document. For example, the latch function of the state latch circuit may also be implemented based on a non-volatile memory, which is not limited in this document.

[0081] In some possible implementations, the circuit schematic diagram of the line sequence switching circuit provided in this application is as follows: Figure 6 As shown, it includes: an ultra-small signal electromagnetic relay U501, a transistor Q501, a resistor R501 and a resistor R502.

[0082] Among them, one end of the resistor R501 is connected to the RELAY_CTRL network of the status latch circuit, the other end of the resistor R501 is respectively connected to one end of the resistor R502 and the base (pin 1) of the transistor Q501, the other end of the resistor R502 is connected to the GND network, the emitter (pin 2) of the transistor Q501 is connected to the GND network, the collector (pin 3) of the transistor Q501 is connected to the control a terminal (pin 1) of the ultra-small signal electromagnetic relay U501, and the control b terminal (pin 8) of the ultra-small signal electromagnetic relay U501 is connected to the main power supply network. The normally closed end of channel 1 (pin 2) of the ultra-small signal electromagnetic relay U501 and the normally open end of channel 2 (pin 5) of the ultra-small signal electromagnetic relay U501 are both connected to the X1 unknown line network, the normally open end of channel 1 (pin 4) of the ultra-small signal electromagnetic relay U501 and the normally closed end of channel 2 (pin 7) of the ultra-small signal electromagnetic relay U501 are both connected to the X2 unknown line network, the common end of channel 1 (pin 3) of the ultra-small signal electromagnetic relay U501 is connected to the A line network, and the common end of channel 2 (pin 6) of the ultra-small signal electromagnetic relay U501 is connected to the B line network.

[0083] In the backup power state, no power voltage is present in the main power supply network. Therefore, regardless of the signal input to RELAY_CTRL, ultra-miniature signal electromagnetic relay U501 remains inactive. The common terminal (pin 3) of ultra-miniature signal electromagnetic relay U501's channel 1 and the normally closed terminal (pin 2) of ultra-miniature signal electromagnetic relay U501's channel 1 remain closed. The common terminal (pin 6) of ultra-miniature signal electromagnetic relay U501's channel 2 and the normally closed terminal (pin 7) of ultra-miniature signal electromagnetic relay U501's channel 2 remain closed. In other words, in the default state, the preceding stage's A-line network (indicated by EIA-485_A in the diagram) is connected to the unknown line network X1, and the preceding stage's B-line network (indicated by EIA-485_B in the diagram) is connected to the unknown line network X2.

[0084] In the normal power state, a DC power supply voltage, such as 3.3V, is present in the main power supply network. When a low-level (0V) signal is input to the RELAY_CTRL network, no forward current flows between the base and emitter of transistor Q501. Therefore, transistor Q501 is not turned on. Consequently, no current flows between the collector and emitter of transistor Q501, and no current flows through the coil of ultra-miniature signal electromagnetic relay U501. Ultra-miniature signal electromagnetic relay U501 does not operate, and the common terminal (pin 3) of channel 1 and the normally closed terminal (pin 2) of channel 1 of ultra-miniature signal electromagnetic relay U501 remain closed. The common terminal (pin 6) of channel 2 and the normally closed terminal (pin 7) of channel 2 of ultra-miniature signal electromagnetic relay U501 remain closed. This means that the A-line network of the preceding stage is connected to the unknown line network X1, and the B-line network of the preceding stage is connected to the unknown line network X2.

[0085] When a 3.0V signal is input to the RELAY_CTRL network, a forward current flows between the base and emitter of the transistor Q501, and the transistor Q501 is turned on and operates in the saturation region. Affected by the DC 3.3V power supply voltage in the main power supply network, a forward current flows through the independent power supply network, the control b terminal (pin 8) of the ultra-small signal electromagnetic relay U501, the control a terminal (pin 1) of the ultra-small signal electromagnetic relay U501, the collector of the transistor Q501, the emitter of the transistor Q501 and the GND network, and the ultra-small signal electromagnetic relay U501 is actuated. The common terminal (pin 3) of channel 1 of the ultra-small signal electromagnetic relay U501 and the normally open terminal (pin 4) of channel 1 of the ultra-small signal electromagnetic relay U501 remain closed, and the common terminal (pin 6) of channel 2 of the ultra-small signal electromagnetic relay U501 and the normally open terminal (pin 5) of channel 2 of the ultra-small signal electromagnetic relay U501 remain closed. That is, the A-line network of the preceding stage is connected to the unknown line network X2, and the B-line network of the preceding stage is connected to the unknown line network X1.

[0086] Exemplarily, the resistance of the resistor R501 and the resistance of the resistor R502 are both 10k, or other suitable values, which are not limited herein.

[0087] In a typical embodiment, the bus interface provided by the present application is deployed in an EIA-485 communication node device as a subsequent circuit of an EIA-485 bus transceiver circuit. Figure 7 As shown, the hardware circuit topology structure diagram of the EIA-485 communication node device includes a core controller, an EIA-485 bus transceiver circuit, a bus interface provided by this application (hereinafter referred to as the bus interface), and other circuits.

[0088] The core controller is responsible for data acquisition, command issuance, calculations, and logic drive for other circuits. The core controller drives the EIA-485 bus transceiver circuit via a TTL-level standard UART communication interface. The TX line is used to send data to the EIA-485 bus transceiver circuit, and the RX line is used to receive data returned from the EIA-485 bus transceiver circuit. The EIA-485 bus transceiver circuit converts the TTL-level standard data sent by the core controller via the TX line into EIA-485-standard data, and converts the EIA-485-standard data returned by the bus interface into TTL-standard data.

[0089] The bus interface is connected to the EIA-485 bus transceiver circuit, where the A line and the B line are strictly corresponding. The bus interface serves as the final circuit of the EIA-485 communication power-saving device, exposing the X1 unknown line network interface and the X2 unknown line network interface to the outside of the device, and is used to access the EIA-485 two-wire bus in any line sequence.

[0090] It should be noted that the front stage of the bus interface may be a bus transceiver circuit, or may be other EIA-485 circuits including A-line and B-line ports, which is not limited in this document.

[0091] In the embodiment of the present application, the DCR measurement circuit includes docking components for the X1 unknown line network and the X2 unknown line network for docking with the external bus network (that is, the docking components of the X1 unknown line network and the X2 unknown line network exposed to the outside of the bus interface for docking with the external bus network), and the line sequence switching circuit includes docking components for respectively communicating with the A-line network and the B-line network of the preceding stage of the bus interface (that is, the docking components exposed to the outside of the bus interface for communicating with the A-line network and the B-line network of the preceding stage). Both can be active ends (plugs) or interface ends, and this document does not limit this.

[0092] In a typical embodiment, the EIA-485 communication node device including the bus interface provided by the present application can form a typical EIA-485 communication bus network. The topology diagram of the communication bus network is as follows: Figure 8 shown.

[0093] Figure 8 In the embodiment, EIA-485 communication node device 1 acts as a master device in the communication bus structure, and EIA-485 communication node device 2, EIA-485 communication node device 3, EIA-485 communication node device 4, EIA-485 communication node device 5, EIA-485 communication node device 6, and EIA-485 communication node device 7 act as slave devices in the communication network. The number of slave devices can also be any other number as required, and this document does not limit this number.

[0094] In addition, an EIA-485 bus configuration device is also deployed at the end of the bus network. The circuit schematic diagram of the EIA-485 bus configuration device is as follows: Figure 9 The EIA-485 bus configuration device includes potentiometer RP601 and potentiometer RP602.

[0095] Among them, the 1st terminal (pin 1) of the potentiometer RP601 is connected to the 3.3V DC power network, the 2nd terminal (pin 3) of the potentiometer RP601 is floating, and the wiper terminal (pin 2) of the potentiometer RP601 is connected to the X1 unknown line network. The wiper terminal (pin 2) of the potentiometer RP602 is connected to the X2 unknown line network, the 1st terminal (pin 1) of the potentiometer RP602 is connected to the GND network, and the 3rd terminal (pin 3) of the potentiometer RP602 is floating.

[0096] It is clear that a typical EIA-485 communication bus network consisting of several EIA-485 communication node devices using the bus interface of this application and a single EIA-485 bus configuration device has significant technical advantages over traditional device networking: any device in the bus network can access the bus in any line sequence, and communication between all devices is guaranteed to be stable and reliable without anomalies. The specific mechanism of operation is as follows.

[0097] According to the EIA-485 standard, "the EIA-485 two-wire communication bus should be equipped with a fault protection circuit, that is, the A and B lines of the bus should be pulled up and down respectively through bias resistors to reduce the bus differential mode voltage in the idle state to Force it to be above 200mV". Figure 8 The circuit diagram of the bus configuration device is shown in Figure 9 As shown, Figure 8In a communication bus network, the lower line shown in the figure to which the end EIA-485 bus configuration device is connected is the EIA-485_A line, and the upper line shown in the figure to which the EIA-485 bus configuration device is connected is the EIA-485_B line.

[0098] For the EIA-485 communication node device, since its internal design is equipped with the bus interface of the present application, no matter what line sequence the EIA-485 communication node device uses to access the bus network, its polarity correction function can always make the bus network work normally. The following is a specific explanation using 'EIA-485 communication node device 1' as an example.

[0099] like Figure 8 As shown, the X1 port of EIA-485 communication node device 1 is connected to the upper wire (EIA-485_B wire) and the X2 port of EIA-485 communication node device 1 is connected to the lower wire (EIA-485_A wire). When the bus network loses power, the bus interface within EIA-485 communication node device 1 operates in a backup power state. Therefore, the bus interface first measures the voltage of the X1 unknown line network and the X2 unknown line network relative to the GND network. Based on the operating principle of the DCR measurement circuit, the X2 line is the A line and has a higher DCR parameter, while the X1 line is the B line and has a lower DCR parameter. The measurement result is transmitted to the comparator circuit. Based on the operating principle of the comparator circuit, the comparator circuit outputs a high-level signal to the state latch circuit. Based on the operating principle of the state latch circuit, the output signal of the state latch circuit does not change temporarily. When the bus network switches from a power-off state to a power-on working state, the bus interface inside the EIA-485 communication node device 1 also switches from a standby power state to a normal power state. Based on the working principle of the state latch circuit, the state latch circuit outputs a high-level signal and maintains it; based on the working principle of the line sequence switching circuit, the high-level signal causes the line sequence switching circuit to connect the EIA-485_A line to the X2 line, and at the same time, connect the EIA-485_B line to the X1 line, thereby realizing the polarity correction function.

[0100] Typically, RS-232 deployments adhere to the electrical characteristics, mechanical interface, signal functions, connector pin order, and connector mechanical dimensions specified in TIA / EIA-232-F, ITU-T V.24, and ISO2110. The EIA-485 standard, however, specifies only electrical characteristics and signal functions, without any restrictions on connector pin order or mechanical dimensions. In actual manufacturing, equipment manufacturers typically design EIA-485 physical interfaces (connectors) based on company standards or internal design practices. However, subsequent device integration and electrical deployment often encounter issues with incorrect A- and B-line connections when interconnecting the EIA-485 physical interfaces (connectors). This is particularly true when deploying large-scale, system-level EIA-485 bus networks. If several devices within the bus network have incorrect line order, manual error correction during post-deployment debugging can be complex and difficult.

[0101] To address these issues and overcome the difficulty of manual error correction associated with bus malfunctions caused by incorrect line sequence alignment in actual EIA-485 standard bus deployments, some industrial automation equipment manufacturers, both domestically and internationally, have proposed solutions. For example, the utility model patent publication number CN 214125285 U provides an RS485 non-polarity communication circuit, comprising an interface line A, an interface line B, an interface line first identification line, an interface line second identification line, a first controlled switch, a second controlled switch, a third controlled switch, a fourth controlled switch, and a comparison module. Compared to traditional technologies, this patent utilizes extremely low cost and ensures communication regardless of whether the interface lines are connected forward or reverse. However, the bus wiring system is increased from two to four, significantly increasing its complexity and significantly reducing its operational stability, making it less practical.

[0102] However, the embodiment of the present application provides a bus interface with a polarity correction function. In the standby power state, based on the DCR measurement circuit and the comparison circuit, the difference in the DCR parameters of the A-line network and the B-line network is used to detect the polarity of the two introduced unknown line networks. After power-on (normal power state), based on the state latch circuit and the line sequence switching circuit, the polarity connection relationship between the two bus unknown line networks and the internal A-line and B-line is automatically corrected. This does not require an increase in the number of buses and is very practical.

[0103] It should be noted that at least one (item) involved in this application indicates one (item) or more (items). More than one (item) refers to two (items) or more than two (items). "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, it should be understood that although the terms first, second, etc. may be used to describe each object in this application, these objects should not be limited to these terms. These terms are only used to distinguish each object from each other. The terms "include" and "have" mentioned above and any variations thereof are intended to cover non-exclusive inclusions.

Claims

1. A bus interface with a polarity correction function, characterized in that: The bus interface comprises: Power management circuit, DC resistance DCR measurement circuit, comparison circuit, state latch circuit, and line sequence switching circuit; The power management circuit is configured to use a backup power supply network to supply power to the DCR measurement circuit, the comparison circuit, and the status latch circuit when the bus interface is in a backup power state, and to use a main power supply network to supply power to the status latch circuit and the line sequence switching circuit when the bus interface is in a normal power state; The DCR measurement circuit, the comparison circuit, the state latch circuit, and the line sequence switching circuit are cascaded. The DCR measurement circuit includes docking components for an X1 unknown line network and an X2 unknown line network connected to an external bus network. The line sequence switching circuit includes docking components for communicating with an A line network and a B line network of a preceding stage of the bus interface, respectively. The DCR measurement circuit also includes a first resistor and a second resistor. The backup power supply network is connected to one end of the first resistor, and the other end of the first resistor is connected to the X1 unknown line network. The backup power supply network is connected to one end of the second resistor, and the other end of the second resistor is connected to the X2 unknown line network. The DCR measurement circuit is configured to, in the backup power state, apply voltages to the X1 unknown line network and the X2 unknown line network based on the backup power supply, the first resistor, and the second resistor, measure DCR parameters of the X1 unknown line network and the X2 unknown line network, and obtain a first DCR measurement result and a second DCR measurement result, respectively; The comparison circuit is configured to compare the numerical values ​​of the first DCR measurement result and the second DCR measurement result to obtain a polarity detection result signal, wherein the polarity detection result signal is configured to instruct the unknown line corresponding to the DCR measurement result with the larger numerical value to be connected to the A-line network of the preceding stage, and the unknown line corresponding to the DCR measurement result with the smaller numerical value to be connected to the B-line network of the preceding stage; The state latch circuit is configured to latch the polarity detection result signal when the main power network is activated, and continuously output the polarity detection result signal to the line sequence switching circuit; The line sequence switching circuit is used to switch the conduction and disconnection of the X1 unknown line network and the X2 unknown line network with the A line network and the B line network of the previous stage based on the polarity detection result signal in the normal power state.

2. The bus interface according to claim 1, wherein: The power management circuit is further configured to use the main power network to supply power to the DCR measurement circuit and the comparison circuit in the normal power state; The DCR measurement circuit is further configured to disable a measurement function of the DCR measurement circuit in the normal power state; The comparison circuit is further configured to disable a comparison function of the comparison circuit in the normal power state.

3. The bus interface according to claim 1 or 2, wherein: The state latch circuit includes a capacitor, The capacitor is used to delay the input signal of the state latch circuit so that when the comparison circuit switches from the self-powered state to the normal power state, the state latch circuit stably receives the polarity detection result signal.

4. The bus interface according to claim 3, wherein: The power management circuit is further configured to use the main power network to charge the backup power network after the main power network is activated.

5. The bus interface according to claim 4, wherein: The power management circuit includes: a resistor R101, a diode D101, and a battery BT101; Among them, one end of the resistor R101 is connected to the main power network, and the other end is connected to the anode of the diode D101. The cathode of the diode D101 is connected to the backup power network and the positive electrode of the above-mentioned battery BT101, and the negative electrode of the battery BT101 is connected to the GND network.

6. The bus interface according to claim 5, wherein: The DCR measurement circuit includes: a resistor R201, a resistor R202, a resistor R203, a resistor R204, a resistor R205, a transistor Q201, and a transistor Q202; One end of the resistor R201 is connected to the main power supply network, and the other end is connected to one end of the resistor R202 and the resistor R203 respectively. The other end of the resistor R203 is connected to the GND network. The other end of the resistor R202 is connected to the base of the transistor Q201 and the base of the transistor Q202 respectively. The emitter of the transistor Q201 and the emitter of the transistor Q202 are both connected to the backup power supply network. The collector of the transistor Q201 and the collector of the transistor Q202 are connected to the X1 unknown line network and the X2 unknown line network respectively through the resistor R204 and the resistor R205.

7. The bus interface according to claim 6, wherein: The comparison circuit includes an analog switch chip U301, an analog switch chip U303, a voltage comparator chip U302, a resistor R301, a resistor R302, and a resistor R303. The first DCR measurement result and the second DCR measurement result are respectively reflected as voltage signals in the X1 unknown line network and the X2 unknown line network in the standby power state. The comparison circuit is connected to the X2 unknown line network through the common terminal pin 5 of the analog switch chip U301 to obtain the second DCR measurement result. The comparison circuit is connected to the X1 unknown line network through the common terminal pin 5 of the analog switch chip U303 to obtain the first DCR measurement result. The first input terminal pin of the analog switch chip U301 and the first input terminal pin of the analog switch chip U303 are both connected to the main power supply network, the second power supply terminal pin of the analog switch chip U301 and the second power supply terminal pin of the analog switch chip U303 are both connected to the backup power supply network, the third GND terminal pin of the analog switch chip U301 and the third GND terminal pin of the analog switch chip U303 are both connected to the GND network, the fourth normally closed terminal pin of the analog switch chip U301 and the fourth normally closed terminal pin of the analog switch chip U303 are respectively connected to one end of the resistor R302 and one end of the resistor R303. The other end of the resistor R302 and the other end of the resistor R303 are respectively connected to the non-inverting input pin 1 of the voltage comparator chip U302 and the inverting input pin 3 of the voltage comparator chip U302, the GND pin 2 of the voltage comparator chip U302 is connected to the GND network, the power supply pin 5 of the voltage comparator chip U302 is connected to the backup power supply network, the resistor R301 is connected between the power supply pin 5 of the voltage comparator chip U302 and the output pin 4 of the voltage comparator chip U302, and the output pin 4 of the voltage comparator chip U302 is connected to the first signal output network.

8. The bus interface according to claim 7, wherein: The state latch circuit includes a D-type trigger chip U401, a resistor R401, and a capacitor C401. Among them, the data end pin 1 of the D-type trigger chip U401 is connected to the first signal output network of the comparison circuit, and is also connected to the GND network through the capacitor C401. The clock end pin 2 of the D-type trigger chip U401 is connected to the main power supply network. The GND end pin 3 of the D-type trigger chip U401 is connected to the GND network. The output end pin 4 of the D-type trigger chip U401 is connected to the second signal output network through the resistor R401. The power end pin 5 of the D-type trigger chip U401 is connected to the backup power supply network.

9. The bus interface according to claim 8, wherein: The line sequence switching circuit includes: an ultra-small signal electromagnetic relay U501, a transistor Q501, a resistor R501 and a resistor R502. Among them, one end of the resistor R501 is connected to the second signal output network of the state latch circuit, the other end of the resistor R501 is respectively connected to one end of the resistor R502 and the base of the transistor Q501, the other end of the resistor R502 is connected to the GND network, the emitter of the transistor Q501 is connected to the GND network, the collector of the transistor Q501 is connected to the control a terminal pin 1 of the ultra-small signal electromagnetic relay U501, the control b terminal pin 8 of the ultra-small signal electromagnetic relay U501 is connected to the main power supply network, the ultra The second pin of the normally closed end of channel 1 of the small signal electromagnetic relay U501 and the fifth pin of the normally open end of channel 2 of the ultra-small signal electromagnetic relay U501 are both connected to the X1 unknown line network, the fourth pin of the normally open end of channel 1 of the ultra-small signal electromagnetic relay U501 and the seventh pin of the normally closed end of channel 2 of the ultra-small signal electromagnetic relay U501 are both connected to the X2 unknown line network, the third pin of the common end of channel 1 of the ultra-small signal electromagnetic relay U501 is connected to the A-line network, and the sixth pin of the common end of channel 2 of the ultra-small signal electromagnetic relay U501 is connected to the B-line network.

10. A polarity correction method, characterized in that: The method is applied to the bus interface with polarity correction function according to any one of claims 1 to 9, and the method comprises: In a standby power state, based on a DCR measurement circuit, measuring DCR parameters of the X1 unknown line network and the X2 unknown line network to obtain a first DCR measurement result and a second DCR measurement result; In the standby power state, comparing the numerical values ​​of the first DCR measurement result and the second DCR measurement result based on a comparison circuit to obtain a polarity detection result signal, wherein the polarity detection result signal is used to instruct to connect the unknown line corresponding to the DCR measurement result with a larger numerical value to the A line of the preceding stage of the bus interface, and to connect the unknown line corresponding to the DCR measurement result with a smaller numerical value to the B line of the preceding stage; When the main power network is activated, based on the state latch circuit, latching the polarity detection result signal, and continuously outputting the polarity detection result signal to the line sequence switching circuit; In a normal power state, the polarity detection result signal drives the line sequence switching circuit to switch the conduction and disconnection of the X1 unknown line network and the X2 unknown line network with the A line and the B line of the previous stage.

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