Circuit board, preparation method thereof and chip packaging structure

Abstract

The invention discloses a circuit board, a preparation method thereof and a chip packaging structure, and relates to the field of chips. The circuit board comprises a circuit board body, a plurality of bonding pad structures and a plurality of connecting circuits, the plurality of bonding pad structures are arranged on the circuit board body in an array mode to form a bonding pad area, and the plurality of connecting circuits are arranged on the circuit board body and connected with the plurality of bonding pad structures in a one-to-one correspondence mode; the bonding pad structure is characterized in that the bonding pad structure comprises a first connecting bonding pad and a wiring forbidding area, and the wiring forbidding area is arranged on at least one side of the connecting bonding pad; wherein the connecting solder ball of the chip is at least welded with the first connecting bonding pad, and the connecting circuit is connected to the chip through the first connecting bonding pad; through the design, the welding success rate is increased.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a circuit board and a preparation method thereof, and a chip packaging structure. Background Art

[0002] Packaging is the process of assembling integrated circuits into final chips. Foundry-produced IC dies are placed on a supporting circuit board, with the pins connected. The chips are then secured together to form a complete package. Flip-chip packaging, a type of bare chip packaging technology, is commonly used for chip packaging. Metal bumps are formed on the chip's electrode areas, and solder balls are placed beneath them. These balls are then bonded to copper pads on the printed circuit board.

[0003] like Figure 1 As shown, the copper circuits fan out from underneath the connection pads on existing circuit boards, causing the entire connection pad to be larger than the chip's solder balls. This results in a larger active area for the chip, and excessive tin diffusion on the connection pads, resulting in insufficient bonding strength between the connection pads and the chip's solder balls, which can easily lead to false solder joints and cold solder joints. Therefore, the above problems need to be addressed urgently. Summary of the Invention

[0004] The purpose of this application is to provide a circuit board and its preparation method, as well as a chip packaging structure that improves welding accuracy.

[0005] The present application discloses a circuit board for chip packaging, wherein the circuit board includes a circuit board body, multiple pad structures, and multiple connecting circuits. The multiple pad structures are arranged in an array on the circuit board body to form a pad area. The multiple connecting circuits are provided on the circuit board body and are connected to the multiple pad structures in a one-to-one correspondence. The pad structure includes a first connecting pad and a prohibited wiring area. The prohibited wiring area is provided on at least one side of the connecting pad. The connecting solder ball of the chip is welded to at least the first connecting pad, and the connecting circuit is connected to the chip through the first connecting pad.

[0006] Optionally, the plurality of pad structures are arranged according to a preset arrangement rule.

[0007] Optionally, the area of ​​the orthographic projection of the first connecting pad on the circuit board body is smaller than the area of ​​the orthographic projection of the connecting solder ball on the circuit board body.

[0008] Optionally, the pad structure also includes a pad window area, and the prohibited wiring area includes a first prohibited wiring area and a second prohibited wiring area. The first prohibited wiring area, the second prohibited wiring area and the first connecting pad are all arranged above the pad window area, the first connecting pad is arranged in the middle of the pad window area, the first prohibited wiring area and the second prohibited wiring area are respectively arranged on both sides of the first connecting pad, and the orthographic projections of the first prohibited wiring area and the second prohibited wiring area on the circuit board body partially overlap with the orthographic projection of the pad window area on the circuit board body.

[0009] Optionally, the pad window area is an elliptical structure, and the first prohibited wiring area and the second prohibited wiring area are respectively arranged corresponding to the long sides of the pad window area; wherein, the first connecting pad is a cylindrical structure, and the setting direction is consistent with the setting direction of the pad window area; the length of the first connecting pad is less than the length of the pad window area; the pad window area does not overlap with the first connecting pad, the first prohibited wiring area and the second prohibited wiring area to form a second connecting pad and a third connecting pad; the first connecting pad, the second connecting pad and the third connecting pad cooperate to form an "I"-shaped connecting pad, and the connecting solder ball is welded to the connecting pad.

[0010] Optionally, the first keep-out wiring area and the second keep-out wiring area are both semicircular structures, and the arcuate edges of the first keep-out wiring area and the arcuate edges of the second keep-out wiring area are both set in a direction away from the first connecting pad and partially protrude from the pad window area.

[0011] Optionally, the two long sides of the first connecting pad are respectively arranged to overlap with one side of the first prohibited wiring area and one side of the second prohibited wiring area; the two ends of the first connecting pad do not overlap with the connecting solder ball to form a first bump and a second bump, and the length of the first bump is 1 / 3-1 / 2 of the length of the second connecting pad; the length of the second bump is 1 / 3-1 / 2 of the length of the third connecting pad.

[0012] Optionally, the circuit board also includes an opening window area, which is arranged on the circuit board body, located on the outer circle of the pad area, and overlaps with part of the connecting circuit; the opening window area and the pad area form a chip welding area, and the size of the chip welding area is larger than the size of the chip.

[0013] The present application also discloses a chip packaging structure, including a chip, a packaging glue and the circuit board as described above, the chip including a chip body, a plurality of bosses and a plurality of connecting solder balls, the plurality of bosses being formed on the surface of the chip body, the plurality of connecting solder balls being arranged one by one on the side of the plurality of bosses away from the chip body, the connecting solder balls being fixedly connected to the first connecting pad, the second connecting pad and the third connecting pad of the circuit board through solder to form a welding structure, the packaging glue being arranged between the chip body and the circuit board, and wrapping the welding structure and the bosses.

[0014] The present application also discloses a method for preparing a circuit board, which is used to prepare the circuit board as described above, comprising the steps of:

[0015] Providing a circuit board body;

[0016] forming a connection circuit area on the circuit board body;

[0017] forming a plurality of pad window areas on the connection circuit area;

[0018] forming a keep-out area on the pad window area, the keep-out area partially overlapping the pad window area;

[0019] forming a first connecting pad on the pad window area at a position that does not overlap with the keep-out area to form a complete pad structure;

[0020] forming a plurality of connection circuits in the connection circuit area;

[0021] The plurality of pad structures are arranged in an array to form a pad area, the plurality of connection circuits are provided in a one-to-one correspondence with the plurality of pad structures, and the connection circuits are connected to the connection solder balls of the chip at least through the first connection pads.

[0022] Optionally, after the step of forming a first connecting pad at a position on the pad window area that does not overlap with the keep-out area to form a complete pad structure, the method further includes:

[0023] forming an open window area on the circuit board corresponding to the outer circle of the pad area;

[0024] The opening window area and the pad area form a chip welding area, and the size of the chip welding area is larger than the size of the chip.

[0025] Compared to the solution in which copper circuits fan out from under the connection pads on the circuit board, resulting in the size of the entire connection pad being larger than the size of the connection solder ball in the chip, and excessive tin diffusion on the connection pad resulting in insufficient bonding strength between the connection pad and the chip connection solder ball, the circuit board of the present application includes a circuit board body, multiple pad structures, and multiple connection circuits. The multiple pad structures are arranged in an array on the circuit board body to form a pad area. The multiple connection circuits are provided on the circuit board body and are connected one-to-one with the multiple pad structures. The pad structure includes a first connection pad and a keep-out wiring area, and the keep-out wiring area is provided on at least one side of the first connection pad. The connection circuit is connected to the connection solder ball of the chip at least through the first connection pad. In this way, the irregular shape of the connection pad caused by the irregular fan-out of the copper circuit is reduced. At the same time, the connection area of ​​the entire pad structure that can be connected to the chip connection solder ball is reduced, thereby reducing the space in which the connection solder ball can move, so that the connection solder ball on the chip can be more accurately aligned with the first connection pad on the circuit board, with a high welding success rate, avoiding the problems of false welding and cold welding. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0027] Figure 1 This is a schematic diagram of the structure of the first connecting pad on the circuit board and the connecting solder ball on the chip in the prior art;

[0028] Figure 2 This is a schematic diagram of the partial structure of a circuit board provided in an embodiment of the present application;

[0029] Figure 3 yes Figure 2 Specific structural diagram of the pad structure;

[0030] Figure 4 yes Figure 3 A schematic structural diagram of the connection pad formed in FIG.

[0031] Figure 5 This is a schematic diagram of the structure of the chip and circuit board welding provided in an embodiment of the present application;

[0032] Figure 6 is a schematic cross-sectional view of the chip packaging structure provided by this application;

[0033] Figure 7This is a schematic diagram of the steps of the method for preparing a circuit board provided in this application;

[0034] Figure 8 yes Figure 7 A further flow diagram of step S3 in FIG.

[0035] Figure 9 This is a schematic diagram of the steps of the chip packaging method provided in this application.

[0036] Among them: 10, circuit board; 100, circuit board body; 110, pad structure; 111, first connecting pad; 112, no-wiring zone; 113, pad window area; 114, first no-wiring zone; 115, second no-wiring zone; 116, first long side; 117, second long side; 118, first short side; 119, second short side; 120, third long side; 121, fourth long side; 122, third short side; 123, fourth short side; 124, first bump; 125, second bump; 126, second connecting pad; 127, third connecting pad; 128, connecting pad; 130, connecting circuit; 140, window area; 150, chip welding area; 20, chip; 200, chip body; 210, boss; 220, connecting solder ball; 30, packaging glue; 40, plastic package; 50, welding structure. DETAILED DESCRIPTION

[0037] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative. However, the present application can be implemented in many alternative forms and should not be construed as being limited to the embodiments described herein.

[0038] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, features specified as "first" and "second" may explicitly or implicitly include one or more of such features; "plurality" means two or more. The term "including" and any variations thereof are intended to be non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may be present or added. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0039] The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0040] Figure 2 is a schematic diagram of a partial structure of a circuit board provided in an embodiment of the present application, Figure 3 yes Figure 2 The specific structural diagram of the pad structure is as follows: Figure 2-3 As shown, the present application discloses a circuit board 10 for chip 20 packaging, wherein the circuit board 10 includes a circuit board body 100, a plurality of pad structures 110 and a plurality of connecting circuits 130, wherein the plurality of pad structures 110 are arranged in an array on the circuit board body 100 to form a pad area, and the plurality of connecting circuits 130 are provided on the circuit board body 100 and are connected one-to-one with the plurality of pad structures 110; the pad structure 110 includes a first connecting pad 111 and a prohibited wiring area 112, wherein the prohibited wiring area 112 is provided on at least one side of the first connecting pad 111; wherein the connecting circuit 130 is connected to the connecting solder ball 220 of the chip 20 at least through the first connecting pad 111.

[0041] Compared with the solution in which the copper circuits fan out from the bottom of the connection pads on the circuit board 10, resulting in the size of the entire connection pad being larger than the size of the connection solder ball 220 in the chip 20, and excessive tin diffusion on the connection pad resulting in insufficient bonding strength between the connection pad and the connection solder ball 220 of the chip 20, the circuit board 10 of the present application includes a circuit board body 100, a plurality of solder pad structures 110 and a plurality of connection circuits 130, the plurality of solder pad structures 110 are arranged in an array on the circuit board body 100 to form a solder pad area, the plurality of connection circuits 130 are provided on the circuit board body 100, and are connected one-to-one with the plurality of solder pad structures 110; the solder pad structure 110 includes a first connection solder pad 111 and a prohibited arrangement The wiring area 112 and the prohibited wiring area 112 are arranged on at least one side of the first connecting pad 111; wherein, the connecting solder ball 220 of the chip 20 is welded to at least the first connecting pad 111, and the connecting line is connected to the chip 20 through the first connecting pad 111; in this way, the irregular shape of the connecting pad is reduced due to the irregular fan-out of the copper line in an irregular direction, and at the same time, the connection area of ​​the entire pad structure 110 that can connect the solder ball 220 to the chip 20 is reduced, thereby reducing the space in which the connecting solder ball 220 can move, so that the connecting solder ball 220 on the chip 20 can be more accurately aligned with the first connecting pad 111 on the circuit board 10, with a high welding success rate, avoiding the problems of false welding and cold welding.

[0042] Among them, such as Figure 3 As shown, the area of ​​the orthographic projection of the first connecting pad 111 on the circuit board body 100 is smaller than the area of ​​the orthographic projection of the connecting solder ball 220 on the circuit board body 100, so that the connecting solder ball 220 on the chip 20 can at least be completely soldered to the first connecting pad 111, further ensuring the effectiveness of the soldering between the chip 20 and the circuit board 10.

[0043] like Figure 3As shown, the pad structure 110 also includes a pad window area 113, the forbidden wiring area 112 includes a first forbidden wiring area 114 and a second forbidden wiring area 115, the first forbidden wiring area 114, the second forbidden wiring area 115 and the first connecting pad 111 are all arranged above the pad window area 113, the first connecting pad 111 is arranged in the middle of the pad window area 113, the first forbidden wiring area 114 and the second forbidden wiring area 115 are respectively arranged on both sides of the first connecting pad 111, and the orthographic projections of the first forbidden wiring area 114 and the second forbidden wiring area 115 on the circuit board body 100 partially overlap with the orthographic projection of the pad window area 113 on the circuit board body 100, combined with Figure 2 That is, the prohibited wiring area 112 occupies part of the pad window area 113, and the connecting pad is located in the pad window area 113. The two adjacent pad structures 110 are separated by the prohibited wiring area 112, so that the overall area of ​​the entire pad structure 110 is not increased as much as possible, so that the volume of the entire pad structure 110 can be minimized.

[0044] The pad window area 113 is an elliptical structure and includes a first long side 116, a first short side 118, a second long side 117, and a second short side 119 that are interconnected. The first long side 116 is disposed opposite the second long side 117, and the first short side 118 is disposed opposite the second short side 119. The first keep-out area 114 is disposed corresponding to the first long side 116, and the second keep-out area 115 is disposed corresponding to the second long side 117. This allows the entire pad structure 110 to be made relatively narrower, further reducing the area occupied by the pad structure 110.

[0045] The first connecting pad 111 is a cylindrical structure, and its orientation is consistent with the orientation of the pad window area 113. Specifically, the connecting pad includes a third long side 120, a third short side 122, a fourth long side 121, and a fourth short side 123 that are interconnected. The third long side 120 extends in the same direction as the first long side 116, the fourth long side 121 extends in the same direction as the second long side 117, the third short side 122 extends in the same direction as the first short side 118, and the fourth short side 123 extends in the same direction as the second short side 119. This does not increase the overall area of ​​the pad window area 113, so the entire pad structure 110 does not need to be larger in size to achieve better soldering between the connecting pad and the solder ball 220 of the chip 20.

[0046] Figure 4 yes Figure 3The structural diagram of the connection pad formed in Figure 4 As shown, combined Figure 3 , the length of the first connecting pad 111 is less than the length of the pad window area 113; the pad window area 113 and the first connecting pad 111, the first prohibited wiring area 114 and the second prohibited wiring area 115 do not overlap to form a second connecting pad 126 and a third connecting pad 127; the first connecting pad 111, the second connecting pad 126 and the third connecting pad 127 cooperate to form an "I"-shaped connecting pad 128, and the connecting solder ball 220 is welded to the connecting pad. In this way, when welding, the connecting solder ball 220 on the chip 20 contacts the first connecting pad 111. When welding with solder, the solder can wrap the first connecting pad 111 and the connecting solder ball 220 through the second connecting pad 126 and the third connecting pad 127, so that the welding area extends toward the second connecting pad 126 and the third connecting pad 127. While the welding is stable, it will not increase the welding volume of the pad structure 110 and the connecting solder ball 220.

[0047] Figure 5 Schematic diagram of the structure of the chip 20 and the circuit board 10 provided in the embodiment of the present application. Figure 5 As shown, the cross-section of the welding structure 50 is a trapezoidal structure, and the connecting solder ball 220 and the first connecting pad 111 are obviously fully welded. In addition, auxiliary welding is provided on both sides by the second connecting pad 126 and the third connecting pad 127 to form arc-shaped side edges, further improving the stability of the welding.

[0048] In addition, the welding structure 50 as a whole is a flat structure that is narrow at the top and wide at the bottom. In this way, when the packaging glue 30 is filled, especially between two adjacent welding structures 50, the flat structure can enable the packaging glue 30 to be fully leveled between the chip 20 and the circuit board 10, and fully contact with the welding structure 50 to avoid the formation of voids here, thereby improving the packaging uniformity of the packaging glue 30.

[0049] Furthermore, both the first keep-out area 114 and the second keep-out area 115 are semicircular in structure, with the arcuate edges of the first keep-out area 114 and the second keep-out area 115 both oriented away from the first connection pad 111 and partially protruding beyond the pad window area 113. With the arcuate edges on both sides, along the direction from the first keep-out area 114 to the second keep-out area 115, within the same area, the areas of the first keep-out area 114 and the second keep-out area 115 are smaller than those of rectangular or square structures. This allows for a wider spacing between adjacent pad structures 110, allowing copper traces to fan out in different directions from the area between adjacent pad structures 110, thereby reducing trace accumulation.

[0050] The third long side 120 of the first connecting pad 111 can be arranged to overlap with the straight side of the first keep-out wiring area 114, and the fourth long side 121 of the connecting pad can be arranged to overlap with the straight side of the second keep-out wiring area 115, so that the area within the connecting pad is adjacent to the connecting circuit 130, so as to ensure that the connecting solder ball 220 of the chip 20 is welded to the connecting pad, the circuit can be connected.

[0051] like Figure 4 As shown, the entire pad structure 110 is an elliptical structure. Therefore, in order to better enlarge the area between two adjacent pad structures 110 where wiring is possible except for the prohibited wiring area 112, the pad structure 110 can be arranged according to a certain preset arrangement rule. For example, the entire pad area can be divided into a plurality of sub-pad areas. Figure 2 , Figure 2 Area A is the first sub-pad area, and area B is the second sub-pad area, wherein the pad structure 110 in the first sub-pad area is arranged in a first direction, and the pad structure 110 in the second sub-pad area is arranged in a second direction. The first direction and the second direction can be mirror-image arrangement directions, so that the prohibited wiring areas 112 between adjacent pad structures 110 can be staggered to further avoid the accumulation of internal circuits.

[0052] The two ends of the connecting solder ball 220 do not overlap with the pad window area 113 to form a first window area and a second window area, and the two ends of the connecting solder pad do not overlap with the connecting solder ball 220 to form a first bump 124 and a second bump 125. Figure 4As shown, assuming that the length of the first bump 124 is h1, the length of the second bump 125 is h2, the length of the first window area is H1, and the length of the second window area is H2, the length h1 of the first bump 124 is 1 / 3-1 / 2 of the length H1 of the first window area; the length h2 of the second bump 125 is 1 / 3-1 / 2 of the length H2 of the second window area.

[0053] Specifically, the length dimension of the first connecting pad 111 is equal to: the width of the connecting solder ball 220 + etching compensation amount * 2. The etching compensation amount here is a value pre-adjusted to ensure that the size of the first connecting pad 111 meets the design requirements after etching. In order to ensure sufficient alignment space when welding the connecting solder ball 220 and the first connecting pad 111, the inventors conducted experiments and set the length dimension of the first connecting pad 111 to the width of the connecting solder ball 220 plus twice the etching compensation amount, which achieved relatively optimal welding stability. In addition, the length dimension of the pad window area 113 is equal to: the width of the connecting solder ball 220 + etching compensation amount * 2 + offset tolerance * 2, where offset tolerance refers to the range in this field that allows a part or component to deviate from the ideal state in terms of position, size, etc.

[0054] Correspondingly, the etching compensation amount is generally set at 10um to 18um, and the offset tolerance is generally set at 12.5um to 18um. Taking the etching compensation amount of 10um and the offset tolerance of 12.5um as an example, the length direction of the chip in forming the first connecting pad 111 is equal to: the width of the connecting solder ball 220 + 10*2; the length direction of the solder pad window area 113 is equal to: the width of the connecting solder ball 220 + 10*2 + 12.5*2. According to the size of the connecting solder ball 220 of the specific chip, the corresponding size values ​​of the first connecting pad 111 and the solder pad window area 113 can be calculated to carry out the corresponding board manufacturing process. The etching compensation amount and the offset tolerance can be specifically adjusted during the production process according to the size of the required circuit board 10, and are not limited here.

[0055] The circuit board 10 also includes an open window area 140, which is arranged on the circuit board body 100, located in the outer circle of the pad area, and overlaps with part of the connecting circuit 130; the open window area 140 and the pad area form a chip welding area 150, and the size of the chip welding area 150 is larger than the size of the chip 20. Specifically, the open window area 140 can expand outward by 150um-200um according to the size of the packaged chip 20, providing more injection space for the bottom filling packaging glue 30, so as to facilitate the flow filling and injection of the packaging glue 30, and the filling is uniform, and it is not easy to produce void problems, so that the packaging glue 30 plays a role of buffering and stress release between the chip 20 and the circuit board 10, reduces the generation of thermal stress, and further ensures the yield of the chip 20 welding.

[0056] Table 1 below is a statistical table of defective rate in comparative experiments. As shown in Table 1, the product yield of the improved circuit board 10 is significantly improved compared with the circuit board 10 before the improvement.

[0057]

[0058] Table 1

[0059] Figure 6 is a schematic diagram of the cross-sectional structure of the chip packaging structure provided by this application, such as Figure 6 As shown, the present application also discloses a chip 20 packaging structure, including a chip 20, a packaging glue 30 and the circuit board 10 as described above, the chip 20 includes a chip body 200, a plurality of bosses 210 and a plurality of connecting solder balls 220, the plurality of bosses 210 are formed on the surface of the chip body 200, and the plurality of connecting solder balls 220 are arranged one by one on the side of the plurality of bosses 210 away from the chip body 200, the connecting solder balls 220 are fixedly connected to the first connecting pad 111, the second connecting pad 126 and the third connecting pad 127 of the circuit board 10 through solder to form a welding structure 50, the packaging glue 30 is arranged between the chip body 200 and the circuit board 10, and wraps the welding structure 50 and the bosses 210.

[0060] In this way, the encapsulation glue 30 can be evenly leveled, improving the packaging reliability. The chip 20 packaging structure also includes a plastic package 40, which is arranged on the side of the chip 20 away from the circuit board 10 and wraps the chip 20, forming a complete package.

[0061] Figure 7 This is a schematic diagram of the steps of the method for preparing a circuit board provided in this application, such as Figure 7 As shown, the present application also discloses a method for preparing a circuit board, which is used to prepare the circuit board as described above, comprising the steps of:

[0062] S1: Provide a circuit board body;

[0063] S2: forming a connection circuit area on the circuit board body;

[0064] S3: forming a plurality of pad window areas on the connection circuit area;

[0065] S4: forming a keep-out area on the pad window area, the keep-out area partially overlapping the pad window area;

[0066] S5: forming a first connecting pad at a position on the pad window area that does not overlap with the keep-out area to form a complete pad structure;

[0067] S6: forming a plurality of connection circuits in the connection circuit area;

[0068] The plurality of pad structures are arranged in an array to form a pad area, the plurality of connection circuits are provided in a one-to-one correspondence with the plurality of pad structures, and the connection circuits are connected to the connection solder balls of the chip at least through the first connection pads.

[0069] A layer of dry film is first formed on the circuit board body. The dry film is made of copper. As for the subsequent production of connecting circuits, multiple connecting circuits are exposed and developed by ultraviolet light to transfer the design pattern to the dry film of the circuit board body. The prohibited wiring area can be formed by etching away the connecting circuits in the corresponding area using chemical solutions. In addition, when multiple connecting circuits are formed in the connecting circuit area, chemical solutions are used to etch the corresponding non-circuit area, retaining only the connecting circuits connected to the pad structure. The circuit board manufacturing process also includes the formation of inner layer circuits, mechanical drilling, solder mask, anti-gold plating and other process flows, which are not the focus of the invention of this application and will not be described here.

[0070] Figure 8 yes Figure 7 A further flow chart of step S3 in FIG. Figure 8 As shown, the keep-out area includes a first keep-out area and a second keep-out area arranged opposite to each other, and the step of forming a keep-out area partially overlapping the pad window area on the pad window area includes the steps of:

[0071] S31: forming a first keep-out area and a second keep-out area opposite to each other on the pad window area;

[0072] S32: forming a first connection pad between the first keep-out area and the keep-out area.

[0073] After the step of forming a first connecting pad at a position on the pad window area that does not overlap with the keep-out area to form a complete pad structure, the method further includes:

[0074] forming an open window area on the circuit board corresponding to the outer circle of the pad area;

[0075] The opening window area and the pad area form a chip welding area, and the size of the chip welding area is larger than the size of the chip. The above circuit board and chip are packaged to improve the reliability of welding.

[0076] Figure 9 This is a schematic diagram of the chip packaging method steps provided by this application, such as Figure 9 As shown, the present application also discloses a chip packaging method for packaging between the chip and the circuit board as described above, comprising the steps of:

[0077] S1: Provide a chip;

[0078] S2: Soldering the connecting solder balls of the chip to the first connecting pads of the circuit board through solder, and cooperating with the second connecting pads and the third connecting pads of the circuit board to form a welding structure;

[0079] S3: injecting packaging glue into the opening window area of ​​the circuit board so that the packaging glue fills the area between the chip and the circuit board;

[0080] The cross section of the welding structure is a regular trapezoidal structure, so that the solder ball and the first connection pad are clearly fully welded, and auxiliary welding is provided on both sides by the second connection pad and the third connection pad, further improving the stability of the welding.

[0081] When welding, a vacuum nitrogen reflow oven can be used to cure the package. A BTU12 temperature zone vacuum nitrogen reflow oven is used, with a peak sealing temperature of 270°C and a chain speed of 45cm / min. After filling the encapsulation glue, it needs to be cured in a pressure oven. The pressure oven temperature can be 165°C, the pressure is set to 5.6kg, and the baking time is 6 hours. Of course, cutting and cleaning steps are also included, but they are not the focus of the invention of this application and will not be detailed here.

[0082] It should be noted that the limitations on the steps involved in this solution do not limit the order of the steps without affecting the implementation of the specific solution. The steps written in front can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be deemed to fall within the scope of protection of this application.

[0083] It should be noted that the inventive concept of this application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the various embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the various embodiments or technical features are combined, the original technical effects will be enhanced.

[0084] The above content is a further detailed description of the present application in conjunction with specific optional implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered to fall within the scope of protection of the present application.

Claims

1. A circuit board for chip packaging, comprising a circuit board body, a plurality of pad structures, and a plurality of connecting circuits, wherein the plurality of pad structures are arranged in an array on the circuit board body to form a pad area, and the plurality of connecting circuits are provided on the circuit board body and connected to the plurality of pad structures in a one-to-one correspondence; characterized in that: The pad structure includes a first connecting pad and a keep-out area, wherein the keep-out area is provided on at least one side of the connecting pad; The connection solder balls of the chip are soldered to at least the first connection pads, and the connection circuit is connected to the chip via the first connection pads.

2. The circuit board according to claim 1, wherein: The plurality of pad structures are arranged according to a preset arrangement rule.

3. The circuit board according to claim 1, wherein: The area of ​​the orthographic projection of the first connecting pad on the circuit board body is smaller than the area of ​​the orthographic projection of the connecting solder ball on the circuit board body.

4. The circuit board according to claim 3, wherein: The pad structure also includes a pad window area, and the prohibited wiring area includes a first prohibited wiring area and a second prohibited wiring area. The first prohibited wiring area, the second prohibited wiring area and the first connecting pad are all arranged above the pad window area, the first connecting pad is arranged in the middle of the pad window area, the first prohibited wiring area and the second prohibited wiring area are respectively arranged on both sides of the first connecting pad, and the orthographic projections of the first prohibited wiring area and the second prohibited wiring area on the circuit board body partially overlap with the orthographic projection of the pad window area on the circuit board body.

5. The circuit board according to claim 4, characterized in that The pad window area is an elliptical structure, and the first keep-out wiring area and the second keep-out wiring area are respectively arranged corresponding to the long sides of the pad window area; Among them, the first connecting pad is a cylindrical structure, and the setting direction is consistent with the setting direction of the pad window area; the length of the first connecting pad is less than the length of the pad window area; the pad window area and the first connecting pad, the first prohibited wiring area and the second prohibited wiring area do not overlap to form a second connecting pad and a third connecting pad; the first connecting pad, the second connecting pad and the third connecting pad cooperate to form an "I"-shaped connecting pad, and the connecting solder ball is welded to the connecting pad.

6. The circuit board according to claim 5, characterized in that The first keep-out zone and the second keep-out zone are both semicircular structures, and the arcuate edges of the first keep-out zone and the second keep-out zone are both arranged in a direction away from the first connection pad and partially protrude from the pad window area.

7. The circuit board according to claim 6, wherein: Two long sides of the first connection pad are respectively overlapped with one side of the first keep-out area and one side of the second keep-out area; The two ends of the first connecting pad do not overlap with the connecting solder ball to form a first bump and a second bump, and the length of the first bump is 1 / 3-1 / 2 of the length of the second connecting pad; the length of the second bump is 1 / 3-1 / 2 of the length of the third connecting pad.

8. The circuit board according to claim 6, wherein: The circuit board also includes an opening window area, which is arranged on the circuit board body, located in the outer circle of the pad area, and overlaps with part of the connecting circuit; the opening window area and the pad area form a chip welding area, and the size of the chip welding area is larger than the size of the chip.

9. A chip packaging structure, characterized in that: It includes a chip, packaging glue and a circuit board as described in any one of claims 1 to 8, the chip includes a chip body, a plurality of bosses and a plurality of connecting solder balls, the plurality of bosses are formed on the surface of the chip body, the plurality of connecting solder balls are arranged one by one on the side of the plurality of bosses away from the chip body, the connecting solder balls are fixedly connected to the first connecting pad, the second connecting pad and the third connecting pad of the circuit board through solder to form a welding structure, the packaging glue is arranged between the chip body and the circuit board, and wraps the welding structure and the bosses.

10. A method for preparing a circuit board, for preparing the circuit board according to any one of claims 1 to 8, characterized in that: Including steps: Providing a circuit board body; forming a connection circuit area on the circuit board body; forming a plurality of pad window areas on the connection circuit area; forming a keep-out area on the pad window area, the keep-out area partially overlapping the pad window area; forming a first connecting pad on the pad window area at a position that does not overlap with the keep-out area to form a complete pad structure; forming a plurality of connection circuits in the connection circuit area; The plurality of pad structures are arranged in an array to form a pad area, the plurality of connection circuits are provided in a one-to-one correspondence with the plurality of pad structures, and the connection circuits are connected to the connection solder balls of the chip at least through the first connection pads.

11. The circuit board according to claim 10, wherein: After the step of forming a first connecting pad at a position on the pad window area that does not overlap with the keep-out area to form a complete pad structure, the method further includes: forming an open window area on the circuit board corresponding to the outer circle of the pad area; The opening window area and the pad area form a chip welding area, and the size of the chip welding area is larger than the size of the chip.

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