Electronic component with simplified interconnection and method of manufacturing same

Abstract

An electronic component with simplified interconnection and a method of manufacturing the same are disclosed. According to an embodiment, an electronic component may include: a substrate having a first active region and a second active region; the first device comprises a first gate electrode, a first side wall on the side wall of the first gate electrode and first source / drain regions on two opposite sides of the first gate electrode on the first active region; the second device comprises a second gate electrode, a second side wall on the side wall of the second gate electrode and second source / drain regions on the two opposite sides of the second gate electrode on the second active region, the first gate electrode extends to the second active region, and the first side wall exposes at least part of the side wall of the first gate electrode on the second active region; therefore, one of the second source / drain regions is in electrical contact with the first gate electrode through at least part of the side wall of the first gate electrode.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuit manufacturing technology, and more particularly to an electronic component with simplified interconnection and a method for manufacturing the same. Background Art

[0002] During integrated circuit manufacturing, various components need to be interconnected. Typically, this interconnection is achieved through metal layers in the back-end of the line (BEOL). This means that testing of certain products, such as static random access memory (SRAM), can only be performed after the higher metal layers have been formed. Summary of the Invention

[0003] An object of the present disclosure is, at least in part, to provide an electronic component with simplified interconnections and a method of manufacturing the same.

[0004] According to one aspect of the present disclosure, an electronic component is provided, comprising: a substrate having a first active region and a second active region; a first device comprising a first gate electrode, a first spacer on a sidewall of the first gate electrode, and first source / drain regions on opposite sides of the first gate electrode on the first active region; and a second device comprising a second gate electrode, a second spacer on a sidewall of the second gate electrode, and second source / drain regions on opposite sides of the second gate electrode on the second active region, wherein the first gate electrode extends onto the second active region, and the first spacer exposes at least a portion of the sidewall of the first gate electrode on the second active region, so that one of the second source / drain regions is electrically contacted with the first gate electrode via the at least portion of the sidewall of the first gate electrode.

[0005] According to another aspect of the present disclosure, a method for manufacturing an electronic component is provided, comprising: defining a first active region and a second active region on a substrate; forming a first gate electrode on the first active region, and forming a second gate electrode on the second active region, wherein the first gate electrode extends onto the second active region; forming a first spacer on the sidewall of the first gate electrode outside at least a portion of the sidewall of the first gate electrode on the second active region, and forming a second spacer on the sidewall of the second gate electrode; and forming a first source / drain region on opposite sides of the first gate electrode on the first active region, and forming a second source / drain region on opposite sides of the second gate electrode on the second active region, wherein one of the second source / drain regions is in electrical contact with the first gate electrode via the at least portion of the sidewall of the first gate electrode.

[0006] According to embodiments of the present disclosure, the electrical connection between the first gate electrode of a first device and the second source / drain region of a second device can be achieved through electrical contact between the two, rather than through a metal layer in the back-end-of-line (BEOL) process. This simplifies the interconnection between the first gate electrode and the second source / drain region (compared to interconnection via metal interconnects and vias), and can therefore be referred to as "simplified interconnection." Furthermore, the electrical connection between the first and second devices can be achieved at a lower level, allowing related testing to be performed at an earlier stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figures 1(a) to 1(d) schematically illustrates an electronic component according to an embodiment of the present disclosure;

[0009] Figure 2 A circuit diagram schematically illustrates a memory cell of a static random access memory (SRAM);

[0010] Figures 3(a) to 3(d) Schematically illustrates an SRAM memory cell according to an embodiment of the present disclosure;

[0011] Figures 4(a) to 5(c) Some stages in the process of manufacturing an SRAM memory cell according to an embodiment of the present disclosure are schematically shown. DETAILED DESCRIPTION

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0013] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and for the purpose of clarity, certain details are magnified and certain details may be omitted. The shapes of the various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0014] Figures 1(a) to 1(d) An electronic component according to an embodiment of the present disclosure is schematically shown.

[0015] In these drawings, FIG1(a) is a top view, FIG1(b) is a cross-sectional view taken along line AA' in FIG1(a), FIG1(c) is a cross-sectional view taken along line BB' in FIG1(a), and FIG1(d) is a cross-sectional view taken along line CC' in FIG1(a). In the top view of FIG1(a), for the sake of clarity, components related to the inventive concept of the present disclosure are shown, and other components that may obscure the inventive concept are not shown.

[0016] like Figures 1(a) to 1(d) As shown, the electronic component according to this embodiment may include a first device 100 and a second device 200 on a substrate SUB.

[0017] The substrate SUB may include various substrate forms, such as a bulk substrate or a semiconductor-on-insulator (SOI) substrate. For example, the substrate SUB may include a silicon wafer. The first device 100 and the second device 200 may have various architectures, such as a planar field-effect transistor (FET), a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAA FET), and the like. The first device 100 and the second device 200 may have the same architecture or different architectures. In this example, the first device 100 and the second device 200 are described as planar FETs, but the present disclosure is not limited thereto.

[0018] Isolation DL, such as shallow trench isolation (STI), may be formed in the substrate SUB to define active regions. The first device 100 and the second device 200 may be formed in their respective active regions ( FIG. 1( b ) shows a cross-section of the active region of the first device 100 , and FIG. 1( d ) shows a cross-section of the active region of the second device 200 ).

[0019] The first device 100 may include a first gate electrode 100_G, a first spacer 100_SP on a sidewall of the first gate electrode 100_G, and first source / drain regions 100_S / D on opposite sides of the first gate electrode 100_G on corresponding active regions.

[0020] The first gate electrode 100_G can have any suitable configuration, such as a polysilicon gate or a metal gate. Although not shown here for convenience, the first gate electrode 100_G can include a gate dielectric layer and a gate conductor layer on the gate dielectric layer. In a metal gate configuration, the gate dielectric layer can include a high-K gate dielectric, and the gate conductor layer can include a work function layer and a conductive layer.

[0021] The first spacer 100_SP can be formed on the sidewall of the first gate electrode 100_G. The first spacer 100_SP can ensure isolation between the first gate electrode 100_G and the first source / drain region 100_S / D. For example, the first spacer 100_SP can be between the first gate electrode 100_G and the first source / drain region 100_S / D and may include a dielectric material such as a nitride. Here, the first spacer 100_SP is shown as a single-layer structure, but may also have a multi-layer structure. In the top view of Figure 1(a), the first gate electrode 100_G is shown as extending along the first direction, and the first spacer 100_SP is formed on the sidewall of the first gate electrode 100_G extending along the first direction. Depending on the manufacturing process, the first spacer 100_SP may also be formed on other sidewalls of the first gate electrode 100_G.

[0022] The first source / drain regions 100_S / D can be formed on opposite sides of the first gate electrode 100_G, for example, on opposite sides in a second direction that intersects (e.g., is perpendicular to) the first direction. The first source / drain regions 100_S / D can include doped regions in the substrate SUB or an epitaxial layer grown separately on the substrate SUB. The first source / drain regions 100_S / D can be doped to a desired conductivity type, such as n-type or p-type. The first source / drain regions 100_S / D can be electrically connected to each other via a channel, which is controlled by the first gate electrode 100_G. The first source / drain regions 100_S / D are shown in FIG1(b) as being elevated relative to the channel, but the present disclosure is not limited thereto.

[0023] The second device 200 may include a second gate electrode 200_G, second spacers 200_SP on sidewalls of the second gate electrode 200_G, and second source / drain regions 200_S / D on opposite sides of the second gate electrode 200_G on the corresponding active regions. The above description of the first device 100 is also applicable to the second device 200 and will not be repeated here.

[0024] In this example, the active regions of the first device 100 and the second device 200 are shown as extending parallel to each other along the second direction, but the disclosure is not limited thereto. In addition, the first gate electrode 100_G and the second gate electrode 200_G are also shown as extending parallel to each other along the first direction, but the disclosure is not limited thereto.

[0025] Depending on the layout design of the electronic components, it may be necessary to form an electrical connection between the first gate electrode 100_G of the first device 100 and the second source / drain region 200_S / D of the second device 200. Instead of implementing this electrical connection through a metal layer in the back-end of line (BEOL) process, the present disclosure proposes a "simplified interconnect" concept.

[0026] The first gate electrode 100_G may extend onto the active region of the second device 200. Figure 1(a) and 1(d) , the first gate electrode 100_G may extend to one end of the active region of the second device 200 (the lower end in the top view of FIG1(a), the left end in the cross-sectional view of FIG1(d)). The first spacer 100_SP may extend outside at least a portion of the sidewall of the first gate electrode 100_G on the active region of the second device 200. In other words, the first spacer 100_SP may not exist on the at least portion of the sidewall. Therefore, the at least portion of the sidewall of the first gate electrode 100_G may be exposed due to the absence of the spacer structure. In this example, as shown in FIG1(a), the first gate electrode 100_G overlaps with the second source and drain regions 200_S / D in the second direction (such as Figure 1(a) and 1(d) In the embodiment shown in the double-dashed line box, the first spacer 100_SP may not exist on the sidewall. The second source / drain region 200_S / D may electrically contact the first gate electrode 100_G via at least a portion of the sidewall of the first gate electrode 100_G. This electrical contact may be achieved through direct physical contact between the first gate electrode 100_G and the second source / drain region 200_S / D, or through silicide formed on at least one of them.

[0027] Referring to Figure 1(d), a first gate electrode 100_G and a second source / drain region 200_S / D are shown facing each other and thus in direct contact. The second source / drain region 200_S / D may contact the gate conductor layer in the first gate electrode 100_G. In other embodiments, a silicide may be formed on the second source / drain region 200_S / D, on the first gate electrode 100_G (particularly on its exposed sidewalls), or on both, through a silicidation process. The second source / drain region 200_S / D and / or the silicide formed thereon may contact the first gate electrode 100_G (e.g., the metal layer therein) and / or the silicide formed thereon (particularly on its exposed sidewalls). The silicide on the second source / drain region 200_S / D and the silicide on the first gate electrode 100_G may extend integrally with each other.

[0028] As shown in FIG1(d), the first gate electrode 100_G may overlap with an end portion (e.g., an end portion in the second direction, i.e., a lower end portion in the top view of FIG1(a)) of the active region of the second device 200. The active region of the second device 200 does not extend across the first gate electrode 100_G to the other side (the lower side in the top view of FIG1(a)) to avoid the formation of a parasitic transistor.

[0029] According to embodiments, electrical connections can be directly formed between the first gate electrode 100_G and the second source / drain regions 200_S / D, without requiring metal layers (e.g., interconnect lines and vias) in the back-end (BEOL) layer (BEOL). This interconnection approach can be referred to as "simplified interconnection." Furthermore, interconnections between components in an electronic component can be (partially) achieved before the back-end (BEOL) layer (BEOL), allowing related operations, such as electrical testing, to be performed at an earlier stage.

[0030] Such an electronic component can be produced, for example, as follows.

[0031] A first active area and a second active area can be defined on a substrate. The first active area can be used for a first device, and the second active area can be used for a second device. A first gate electrode can be formed on the first active area, and a second gate electrode can be formed on the second active area. The first gate electrode can extend onto the second active area. A first sidewall spacer can be formed on the sidewall of the first gate electrode outside at least a portion of the sidewall of the first gate electrode on the second active area, and a second sidewall spacer can be formed on the sidewall of the second gate electrode. A first source / drain region can be formed on opposite sides of the first gate electrode on the first active area, and a second source / drain region can be formed on opposite sides of the second gate electrode on the second active area. One of the second source / drain regions can be in electrical contact with the first gate electrode via at least a portion of the sidewall of the first gate electrode.

[0032] The method according to the embodiments of the present disclosure is compatible with conventional manufacturing processes. When forming the sidewall spacer, the process can be adjusted. For example, the first sidewall spacer can be formed while shielding the area where at least a portion of the sidewall of the first gate electrode is located; or the first sidewall spacer can be formed on the sidewall of the first gate electrode and then removed from the at least a portion of the sidewall of the first gate electrode.

[0033] The electronic components according to the embodiments of the present disclosure may include various electronic components requiring electrical connection between a gate electrode of a first device and a source / drain region of a second device, including but not limited to a memory cell of a static random access memory (SRAM).

[0034] Figure 2 A circuit diagram of an SRAM memory cell is schematically shown.

[0035] like Figure 2As shown, an SRAM memory cell can have a 6T structure, i.e., it includes six component transistors. These six component transistors may include a first pull-up transistor PU1, a first pull-down transistor PD1, a first pass-gate transistor PG1, a second pull-up transistor PU2, a second pull-down transistor PD2, and a second pass-gate transistor PG2. The first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, and the second pull-down transistor PD2 can form two cross-coupled inverters, serving as the storage location for storing a single bit in the SRAM memory cell. The first pass-gate transistor PG1 and the second pass-gate transistor PG2 can, under the control of the word line WL, respectively control the data transmission between the storage location and the bit line BL and the complementary bit line / BL to achieve reading and writing.

[0036] Pull-up transistors PU1 and PU2 may be p-type transistors and may be connected to a power supply voltage VDD. Pull-down transistors PD1 and PD2 may be n-type transistors and may be connected to a ground voltage. Pass-gate transistors PG1 and PG2 may also be n-type transistors.

[0037] like Figure 2 As shown by node Q in FIG, the gate electrode of the first pull-up transistor PU1 (and the first pull-down transistor PD1) can be electrically connected to the source / drain of the second pull-up transistor PU2 (and the second pull-down transistor PD2). Figure 2 As shown at node / Q in FIG, the gate electrodes of the second pull-up transistor PU2 (and the second pull-down transistor PD2 ) may be electrically connected to the source / drain of the first pull-up transistor PU1 (and the first pull-down transistor PD1 ).

[0038] The inventive concepts of this disclosure can be applied to SRAM memory cells. For example, the first device may include a first pull-up transistor PU1 (and a first pull-down transistor PD1), and the second device may include a second pull-up transistor PU2. Alternatively, the first device may include a second pull-up transistor PU2 (and a second pull-down transistor PD2), and the second device may include the first pull-up transistor PU1.

[0039] Figures 3(a) to 3(d) An SRAM memory cell according to an embodiment of the present disclosure is schematically shown.

[0040] In these drawings, FIG3(a) is a top view, FIG3(b) is a cross-sectional view taken along line AA' in FIG3(a), FIG3(c) is a cross-sectional view taken along line BB' in FIG3(a), and FIG3(d) is a cross-sectional view taken along line CC' in FIG3(a). In the top view of FIG3(a), for the sake of clarity, components related to the inventive concept of the present disclosure are shown, and other components that may obscure the inventive concept are not shown.

[0041] like Figures 3(a) to 3(d) As shown, the SRAM cell according to this embodiment may include a first pull-up transistor PU1, a first pull-down transistor PD1, a first pass-gate transistor PG1, a second pull-up transistor PU2, a second pull-down transistor PD2, and a second pass-gate transistor PG2 on a substrate 1000. In FIG3(a), the positions of the transistors in the SRAM memory cell layout are schematically shown in dashed boxes, but do not represent the exact footprint of these transistors. These transistors may form a substantially symmetrical layout.

[0042] In this embodiment, substrate 1000 is shown as an SOI substrate, comprising a base substrate 1001, a buried oxide layer 1003 on base substrate 1001, and an SOI layer 1005 on buried oxide layer 1003. For example, base substrate 1001 may be formed of a suitable semiconductor material such as silicon (Si), buried oxide layer 1003 may include an oxide (e.g., silicon oxide), and SOI layer 1005 may include the same semiconductor material as base substrate 1001, such as Si, or a different semiconductor material, such as silicon germanium (SiGe). Although the SOI substrate is used as an example in this description, the present disclosure is not limited thereto. STI 1015 may be formed in substrate 100 to define an active region.

[0043] In each transistor, a gate electrode 1009 may be disposed on a substrate 1000, and source / drain regions 1007 may be disposed on opposite sides of the gate electrode 1009. Depending on the embodiment, the gate electrode 1009 may extend in a first direction (e.g., the x-direction), and the source / drain regions 1007 may be disposed on opposite sides of the gate electrode 1009 in a second direction (e.g., the y-direction) that intersects (e.g., is perpendicular to) the first direction. The source / drain regions 1007 may be elevated source / drain regions epitaxially grown on the SOI layer 1005.

[0044] like Figure 3(a) and 3(b) As shown, the active regions of the first pull-down transistor PD1 and the first pass-gate transistor PG1 may extend continuously with each other in the second direction (e.g., the y-direction). The first pull-down transistor PD1 and the first pass-gate transistor PG1 may include respective source / drain regions 1007 (particularly, n-type doped source / drain regions 1007n). To allow for electrical connection therebetween, the first pull-down transistor PD1 and the first pass-gate transistor PG1 may have a common source / drain region 1007, such as between the gate electrode 1009 (PD1) of the first pull-down transistor PD1 and the gate electrode 1009 (PG1) of the first pass-gate transistor PG1.

[0045] In Figure 3(a), the active area of ​​the first pull-down transistor PD1 is shown as having a greater width in the first direction (e.g., the x-direction) than the active area of ​​the first pass-gate transistor PG1. This is primarily to visually distinguish the active areas of the two transistors and does not necessarily represent their actual sizes or size ratios. The widths of the active areas of the first pull-down transistor PD1 and the first pass-gate transistor PG1 in the first direction (particularly the gate width) can be designed based on their required driving capabilities.

[0046] On the other hand, the source / drain regions 1007 (particularly the n-type doped source / drain regions 1007 n ) of the second pull-down transistor PD2 and the second pass-gate transistor PG2 may be configured similarly.

[0047] The active area of ​​the second pull-up transistor PU2 can extend in a second direction (e.g., the y-direction). The source / drain region 1007 of the second pull-up transistor PU2 (particularly the p-type doped source / drain region 1007p) can extend in the second direction toward the first pull-down transistor PD1 and the gate electrode 1009 of the first pull-up transistor PU1, thereby forming a simplified interconnection with the gate electrode 1009 as described above. Similarly, the active area of ​​the first pull-up transistor PU1 can extend in the second direction (e.g., the y-direction). The source / drain region 1007 of the first pull-up transistor PU1 (particularly the p-type doped source / drain region 1007p) can extend in the second direction toward the second pull-down transistor PD2 and the gate electrode 1009 of the second pull-up transistor PU2, thereby forming a simplified interconnection with the gate electrode 1009.

[0048] According to the layout of the SRAM memory cell, the gate electrodes 1009 of the first pull-down transistor PD1 and the first pull-up transistor PU1 may extend continuously to each other and may extend to the active area of ​​the second pull-up transistor PU2 (eg, Figure 3(a) and 3(d) (As shown in the double-dashed line box in FIG. 1 ). Furthermore, the gate electrode 1009 of the second pass-gate body transistor PG2 can be aligned with the gate electrodes 1009 of the first pull-down transistor PD1 and the first pull-up transistor PU1 in the first direction. For example, they can be separated from each other from the same gate line. On the other hand, the gate electrodes 1009 of the second pull-down transistor PD2, the second pull-up transistor PU2, and the first pass-gate transistor PG1 can be configured similarly.

[0049] A sidewall spacer 1011 is formed on the sidewall of the gate electrode 1009. In the related art, the sidewall spacer 1011 can extend continuously on the sidewall of the gate electrode 1009. According to an embodiment of the present disclosure, the sidewall spacer 1011 may not exist on at least a portion of the sidewall of the gate electrode 1009. For example, the sidewall spacer 1011 may not exist on at least a portion of the sidewall of the gate electrode 1009 of the first pull-down transistor PD1 and the first pull-up transistor PU1 on the active area of ​​the second pull-up transistor PU2, that is, the sidewall spacer 1011 may extend outside the at least portion of the sidewall. Similarly, the sidewall spacer 1011 may not exist on at least a portion of the sidewall of the gate electrode 1009 of the second pull-down transistor PD2 and the second pull-up transistor PU2 on the active area of ​​the first pull-up transistor PU1, that is, the sidewall spacer 1011 may extend outside the at least portion of the sidewall. Referring to Figure 3(d), the at least portion of the sidewall of the gate electrode 1009 may be in contact with the source / drain region 1007.

[0050] According to other embodiments, a silicidation process may be performed to form a silicide 1013 on at least one of the gate electrode 1009 and the source / drain region 1007. The silicide 1013 formed on the gate electrode 1009 and the source / drain region 1007 may contact each other or even extend integrally. In the top view of FIG3(a), the silicide is not shown to clearly illustrate the layout of the active region and the gate electrode.

[0051] In addition, possible metal interconnects 1017 and vias 1019 are also schematically shown. For example, the electrical connection between the source / drain region of the first pull-up transistor PU1 and the common source / drain region of the first pull-down transistor PD1 and the first pass-gate transistor PG1 can be achieved through metal interconnects 1017 and vias 1019. Similarly, the electrical connection between the source / drain region of the second pull-up transistor PU2 and the common source / drain region of the second pull-down transistor PD2 and the second pass-gate transistor PG2 can be achieved through metal interconnects 1017 and vias 1019.

[0052] In the related art, the electrical connection between the gate electrode 1009 and the source / drain region 1007 can be similarly achieved through metal interconnects and vias. However, according to an embodiment of the present disclosure, the electrical connection between the gate electrode 1009 and the source / drain region 1007 can be implemented by compressing the layer into a single layer (e.g., silicide 1013).

[0053] Figures 4(a) to 5(c) Schematic diagrams show some stages in the process of manufacturing an SRAM memory cell according to an embodiment of the present disclosure. The cross-sectional views in these figures correspond to Figures 3(b) to 3(d) Cross-sectional view in .

[0054] like Figure 4(a) 、 4(b)As shown in FIG4( c ), an SOI substrate 1000 may be provided. On the SOI substrate 1000 , an STI 1015 may be formed to define an active region. For example, the STI 1015 may be formed by forming an isolation trench on the SOI substrate 1000 and filling the isolation trench with oxide.

[0055] Gate electrodes 1009 can be formed on SOI substrate 1000. For example, a gate dielectric layer and a gate conductor layer can be sequentially formed by deposition, such as chemical vapor deposition (CVD), and then patterned into respective gate electrodes. The pattern of gate electrode 1009 can be shown in FIG3(a). As shown in FIG4(c), the gate electrodes 1009 of the first pull-down transistor PD1 and the first pull-up transistor PU1 can extend (in the x-direction) to overlap a portion (end in the y-direction) of the active region of the second pull-up transistor PU2.

[0056] A spacer 1011 may be formed on the sidewall of the gate electrode 1009. For example, a spacer material layer may be formed in a substantially conformal manner by deposition, such as CVD, and the deposited spacer material layer may be anisotropically etched, such as by reactive ion etching (RIE) in the vertical direction, to remove the portion of the spacer material layer extending on the lateral surface of the underlying structure while retaining the portion of the spacer material layer extending on the vertical surface of the underlying structure, thereby obtaining the spacer 1011.

[0057] As described above, the spacer 1011 may be absent from portions of the sidewalls of the gate electrode 1009. For example, the spacer 1011 may not be formed in at least a portion of the region where the gate electrodes 1009 of the first pull-down transistor PD1 and the first pull-up transistor PU1 overlap with the active area of ​​the second pull-up transistor PU2 (as shown in the double-dashed line box in FIG4( c )). In other words, the spacer 1011 may be formed outside of this at least portion of the region. For example, this may be achieved by removing the formed spacer 1011 from this at least portion of the region after forming it. Alternatively, this may be achieved by performing the spacer 1011 formation process while shielding this at least portion of the region.

[0058] like Figure 5(a) 、 5(b) As shown in FIG5( c ), source / drain regions 1007 may be formed on opposite sides of the gate electrode 1009 by, for example, selective epitaxial growth. The source / drain regions 1007 of the n-type transistors (PD1, PG1, PD2, PG2) may be doped to n-type (1007n), and the source / drain regions 1007 of the p-type transistors (PU1, PU2) may be doped to p-type (1007p).

[0059] Return Reference Figures 3(a) to 3(d)A silicide process may be performed to form silicide 1013 on the gate electrode 1009 and the source / drain regions 1007. For example, a metal such as nickel (Ni) or platinum (Pt) may be deposited, and then heat treated to cause the metal to react with a semiconductor material such as Si to form a metal silicide. The remaining metal may then be removed.

[0060] Semiconductor devices according to embodiments of the present disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed from them. Such electronic devices may also include components such as display screens and wireless transceivers that work with the ICs. Examples of such electronic devices include smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and mobile power supplies.

[0061] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0062] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. An electronic component comprising: a substrate having a first active region and a second active region; A first device includes a first gate electrode, a first spacer on a sidewall of the first gate electrode, and first source / drain regions on opposite sides of the first gate electrode on the first active region; as well as The second device includes a second gate electrode, a second spacer on the sidewall of the second gate electrode, and second source / drain regions on opposite sides of the second gate electrode on the second active region. wherein the first gate electrode extends onto the second active region, The first sidewall spacer exposes at least a portion of a sidewall of the first gate electrode on the second active region, so that one of the second source / drain regions is in electrical contact with the first gate electrode via the at least a portion of the sidewall of the first gate electrode.

2. The electronic component according to claim 1, further comprising: A first silicide layer is formed on one of the second source / drain regions, and the first silicide layer is in electrical contact with the first gate electrode via at least a portion of the sidewall.

3. The electronic component according to claim 2, further comprising: A second silicide layer is formed on at least a portion of the sidewall of the first gate electrode, and the second silicide layer is in contact with the first silicide layer.

4. The electronic component according to claim 3, wherein The first silicide layer and the second silicide layer extend integrally.

5. The electronic component according to claim 1, wherein The first gate electrode and the second gate electrode extend in a first direction, The first source / drain regions are located on opposite sides of the first gate electrode in a second direction, and the second direction intersects the first direction. The second source / drain regions are located on opposite sides of the second gate electrode in the second direction. Wherein, the first gate electrode does not have the first spacer on the sidewall of a region where the first gate electrode overlaps with the second source / drain region in the second direction.

6. The electronic component according to any one of claims 1 to 5, wherein The electronic component includes a memory cell of a static random access memory (SRAM), including a first pull-up transistor, a first pull-down transistor, a first pass-gate transistor, a second pull-up transistor, a second pull-down transistor, and a second pass-gate transistor. The first device includes the first pull-up transistor and the first pull-down transistor, and the second device includes the second pull-up transistor.

7. A method of manufacturing an electronic component, comprising: defining a first active region and a second active region on the substrate; forming a first gate electrode on the first active region and forming a second gate electrode on the second active region, wherein the first gate electrode extends onto the second active region; forming a first spacer on the sidewall of the first gate electrode and forming a second spacer on the sidewall of the second gate electrode outside at least a portion of the sidewall of the first gate electrode on the second active region; as well as forming first source / drain regions on opposite sides of the first gate electrode on the first active region, and forming second source / drain regions on opposite sides of the second gate electrode on the second active region, One of the second source / drain regions is in electrical contact with the first gate electrode via at least a portion of the sidewall of the first gate electrode.

8. The method according to claim 7, wherein: Forming the first sidewall includes: forming the first sidewall spacer while shielding the area where at least a portion of the sidewall of the first gate electrode is located; or The first spacer is formed on the sidewall of the first gate electrode, and then the first spacer is removed from at least a portion of the sidewall of the first gate electrode.

9. The method according to claim 7, further comprising: The second source / drain region and the first gate electrode are subjected to silicidation to form silicide, and the electrical contact is achieved through the silicide.

10. The method according to claim 7, wherein: The electronic component includes a memory cell of a static random access memory (SRAM), including a first pull-up transistor, a first pull-down transistor, a first pass-gate transistor, a second pull-up transistor, a second pull-down transistor, and a second pass-gate transistor. The first device includes the first pull-up transistor and the first pull-down transistor, and the second device includes the second pull-up transistor.

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