Preparation method of semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure, which comprises the following steps: forming a gate material layer and an interlayer dielectric layer on the gate material layer on a silicon carbide substrate, patterning the interlayer dielectric layer and the gate material layer, forming a groove exposing the surface of a source region in the interlayer dielectric layer and the gate material layer, and forming a gate structure of an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device; forming a first side wall on the surface of the inner side wall of the groove; forming metal silicide on the surface of the source region between the first side walls; forming a second side wall on the surface of the first side wall and a part of the surface of the metal silicide; and forming a metal plug which fills the remaining groove between the inner side walls of the second side walls. The thickness of the metal silicide formed by the preparation method is uniform, the width (size) of the metal silicide is large, non-ohmic contact between the formed metal silicide and the silicon carbide substrate is avoided, the on-resistance of the MOSFET device is reduced, and the on-resistance is uniform.

Description

Technical Field

[0001] The present application relates to the field of power device preparation, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] Silicon carbide (SiC) is a third-generation semiconductor material with a bandgap three times that of silicon (Si), a critical breakdown field strength 10 times that of Si, an electron saturation drift rate twice that of Si, and a thermal conductivity three times that of Si. This gives SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices significant performance advantages over SiMOSFET devices, including lower on-resistance, higher switching voltage, higher application frequency, and better temperature performance. It holds broad prospects in new energy, rail transit, power electronics, and other fields.

[0003] Metal silicides are used to form ohmic contacts with SiC MOSFET devices (for example, in the source region of a SiC MOSFET device), reducing contact resistivity and lowering the on-resistance of the entire device. Optimizing metal silicide structures and processes is crucial. However, existing metal silicides exhibit non-ohmic contact between the metal silicide and the SiC substrate, which increases the on-resistance of the SiC MOSFET. Summary of the Invention

[0004] Based on this, the present application provides a method for preparing a semiconductor structure to reduce the non-ohmic contact between the metal silicide and the SiC substrate, thereby reducing the on-resistance of the SiC MOSFET.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0006] Providing a silicon carbide substrate, wherein a source region of a MOSFET device is formed in the silicon carbide substrate;

[0007] forming a gate material layer and an interlayer dielectric layer on the gate material layer on the silicon carbide substrate;

[0008] Patterning the interlayer dielectric layer and the gate material layer, forming a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region, and forming a gate structure of the MOSFET device;

[0009] forming a first side wall on the inner side wall surface of the groove;

[0010] forming a metal silicide on the surface of the source region between the first sidewalls;

[0011] forming a second sidewall spacer on a surface of the first sidewall spacer and a portion of a surface of the metal silicide;

[0012] A metal plug is formed to fill the remaining groove between the inner sidewalls of the second spacer.

[0013] In some embodiments of the present application, forming a first sidewall on the inner sidewall surface of the groove includes: forming a first sidewall material layer on the inner sidewall and bottom surface of the groove and the top surface of the interlayer dielectric layer; using a first maskless etching process to remove the first sidewall material layer on the bottom surface of the groove and the top surface of the interlayer dielectric layer, and forming a first sidewall on the inner sidewall surface of the groove.

[0014] In some embodiments of the present application, forming a second sidewall on the surface of the first sidewall and a portion of the surface of the metal silicide includes: forming a second sidewall material layer on the surfaces of the first sidewall and the metal silicide and the top surface of the interlayer dielectric layer; using a second maskless etching process to remove the second sidewall material layer on the surface of the metal silicide and the top surface of the interlayer dielectric layer, and forming a second sidewall on the surface of the groove.

[0015] In some embodiments of the present application, the material of the second spacer is different from the material of the first spacer.

[0016] In some embodiments of the present application, forming a metal silicide on the surface of the source region between the first sidewalls includes: forming a metal layer on the surface of the first sidewalls and the source region and the top surface of the interlayer dielectric layer; performing an annealing process so that the metal layer reacts with the material on the surface of the source region to form a metal silicide layer; and removing the unreacted metal layer.

[0017] In some embodiments of the present application, the annealing temperature is 950 degrees Celsius to 1050 degrees Celsius, and the annealing time is 1 minute to 5 minutes; the material of the metal layer includes one or more of nickel, tungsten, cobalt, and titanium; and a wet etching process is used to remove the unreacted metal layer.

[0018] In some embodiments of the present application, the width of the groove is equal to the width of the source region, or the width of the groove is 80%-100% of the width of the source region, and the aspect ratio of the groove is less than 2:1;

[0019] After the first sidewall spacer is formed, the aspect ratio of the remaining groove is less than 2:1.

[0020] In some embodiments of the present application, the width of the first sidewall is 1 / 8-1 / 10 of the width of the groove, and the width of the first sidewall is smaller than the width of the second sidewall.

[0021] In some embodiments of the present application, the gate material layer includes a gate dielectric material layer and a gate electrode material layer located on the gate dielectric material layer;

[0022] The gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer;

[0023] The source region is located in the silicon carbide substrate on one side of the gate structure, and the MOSFET device also includes a drain region in the silicon carbide substrate on the other side of the gate structure;

[0024] The MOSFET device further includes: a well region located in the silicon carbide substrate, the source region located in the well region, the doping type of the well region being opposite to the doping type of the source region and the drain region;

[0025] The MOSFET device further includes: an inversion doped region located in the source region, the depth of the inversion doped region being the same as the depth of the well region, the doping type of the inversion doped region being opposite to the doping type of the source region and the same as the doping type of the well region;

[0026] The MOSFET device also includes: a drift region located in the silicon carbide substrate, the drift region is located on one side of the well region, the gate structure spans part of the drift region and part of the well region, the drain region is located in the drift region, and the doping type of the drift region is the same as the doping type of the drain region.

[0027] In some embodiments of the present application, patterning the interlayer dielectric layer and the gate material layer to form a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region includes: forming a first photoresist layer on the interlayer dielectric layer; performing a first exposure on the first photoresist layer using a first mask; after the first exposure, performing a first development to form a first opening in the first photoresist layer to expose a portion of the surface of the interlayer dielectric layer, wherein the width of the first opening is equal to the width of the groove; etching the interlayer dielectric layer and the gate material layer along the first opening to form a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region;

[0028] Alternatively, patterning the interlayer dielectric layer and the gate material layer to form a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region includes: forming a second photoresist layer on the interlayer dielectric layer; performing a second exposure on the second photoresist layer using a second mask; after the second exposure, performing a second development to form a second opening in the second photoresist layer to expose a portion of the surface of the interlayer dielectric layer, wherein the width of the second opening is smaller than the width of the groove; widening the second opening so that the width of the second opening is equal to the width of the groove; etching the interlayer dielectric layer and the gate material layer along the widened second opening to form a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region;

[0029] Alternatively, patterning the interlayer dielectric layer and the gate material layer to form a groove exposing the surface of the source region in the interlayer dielectric layer and the gate material layer includes: forming a second photoresist layer on the interlayer dielectric layer; performing a second exposure on the second photoresist layer using a second mask; after the second exposure, performing a second development to form a second opening in the second photoresist layer exposing a portion of the surface of the interlayer dielectric layer, wherein the width of the second opening is smaller than the width of the groove; etching the interlayer dielectric layer and the gate material layer along the second opening to form an initial groove exposing the surface of the source region in the interlayer dielectric layer and the gate material layer; and widening the width of the initial groove to form the groove.

[0030] The embodiments of the present application may or at least have the following advantages:

[0031] In the method for preparing a semiconductor structure in the embodiment of the present application, after forming a gate material layer and an interlayer dielectric layer located on the gate material layer on a silicon carbide substrate, the interlayer dielectric layer and the gate material layer are patterned, a groove exposing the surface of the source region is formed in the interlayer dielectric layer and the gate material layer, and a gate structure of a MOSFET device is formed; a first sidewall is formed on the inner sidewall surface of the groove; a metal silicide is formed on the surface of the source region between the first sidewalls; a second sidewall is formed on the surface of the first sidewall and a portion of the surface of the metal silicide; and a metal plug is formed to fill the remaining groove between the inner sidewalls of the second sidewall. In the present application, since the metal plug is formed after the second sidewall spacer is formed in the groove, the metal plug is isolated from the gate structure by the first sidewall spacer and the second sidewall spacer. When the size of the formed metal plug is small (or the size of the formed MOSFET device is small), the width (or size) of the corresponding formed groove can be larger, and the aspect ratio of the groove can be lower (less than 2:1). After the first sidewall spacer is formed on the inner sidewall surface of the groove, the remaining groove width (or size) can still be larger, and the aspect ratio of the groove can still be lower. Therefore, when a metal layer for forming a metal silicide is formed on the surface of the source region exposed by the remaining groove (the metal layer reacts with the silicon carbide substrate to form the metal silicide), the formed metal layer can be in full contact with the surface of the source region, and the thickness of the formed metal layer is relatively uniform. In addition, the temperature distribution during annealing is relatively uniform, allowing the metal layer to fully react with the silicon carbide substrate, thereby making the thickness of the formed metal silicide uniform and the width (size) of the metal silicide larger. This avoids non-ohmic contact between the formed metal silicide and the silicon carbide substrate, reduces the on-resistance of the MOSFET device, and makes the on-resistance uniform.

[0032] Furthermore, since the remaining groove width (or size) can still be relatively large, the aspect ratio of the groove can still be relatively low. When forming the metal silicide, carbon elements generated during the reaction between the metal layer and the silicon carbide substrate are easily precipitated onto the surface. After the metal silicide is formed, the carbon elements can be removed simultaneously when the unreacted metal layer is removed, thereby reducing the carbon content in the metal silicide and, in turn, the resistance of the formed metal silicide.

[0033] Furthermore, the formation of the groove and the formation of the gate structure adopt the same patterning process, which simplifies the process steps and saves costs.

[0034] Furthermore, the first spacer serves the following purposes: 1. It prevents the metal layer from reacting with the gate electrode to form metal silicide during the subsequent metal silicide formation, and 2. It also prevents short circuits between the metal silicide formed on the source region and the gate electrode. 2. It also regulates the size of the metal plug formed subsequently and the distance between the metal plug and the gate electrode. 3. The second spacer regulates the size of the metal plug formed subsequently and the distance between the metal plug and the gate structure (gate electrode), and also provides electrical isolation between the metal plug and the gate structure, and between the metal silicide and the gate structure.

[0035] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0038] Figure 2 A schematic diagram of a cross-sectional structure after forming a gate material layer and an interlayer dielectric layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0039] Figure 3 A schematic diagram of a cross-sectional structure after a groove is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0040] Figure 4 A schematic diagram of a cross-sectional structure after forming a first sidewall spacer in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0041] Figure 5 A schematic diagram of a cross-sectional structure after metal silicide is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0042] Figure 6 A schematic cross-sectional view of a semiconductor structure fabrication method after forming a second sidewall spacer in some embodiments of the present application;

[0043] Figure 7 This is a schematic diagram of a cross-sectional structure after a metal plug is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application.

[0044] Description of reference numerals:

[0045] Silicon carbide substrate 201; source region 202; well region 203; inversion-doped region 204; gate dielectric material layer 205; gate electrode material layer 206; interlayer dielectric layer 207; hard mask layer 208; recess 209; first sidewall spacer 210; metal silicide 211; second sidewall spacer 212; metal plug 213; gate dielectric layer 215; gate electrode 216. DETAILED DESCRIPTION

[0046] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The drawings provide examples of the present application. However, the present application may be implemented in many different forms and is not limited to the examples described herein. Rather, these examples are provided to make the disclosure of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0048] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0049] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device during use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" can include both the above and below orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0050] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, within this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] The structures of the embodiments of the present application should not be limited to the specific shapes shown in the drawings, but include shape deviations due to, for example, manufacturing technology.

[0052] It can be understood that in the drawings of the present application, some adjacent film layers made of the same processing film material are drawn as being connected to make them close to the actual structure.

[0053] Planar SiC MOSFET devices have been widely studied and applied in new energy, rail transportation, power electronics and other fields due to their excellent high voltage resistance, high frequency, low loss, and high thermal conductivity.

[0054] During the preparation of planar SiC MOSFET devices, it is usually necessary to form a metal silicide on the surface of the source region before forming a metal plug connected to the source region. The preparation process generally includes: providing a SiC substrate; forming a gate structure on the SiC substrate (the gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer); forming sidewalls on the sidewalls of the gate structure; forming a source region and a drain region in the SiC substrate on both sides of the gate structure and the sidewalls, respectively; forming an interlayer dielectric layer covering the gate structure on the SiC substrate; forming a groove in the interlayer dielectric layer to expose the surface of the source region; forming a metal silicide layer on the surface of the source region exposed by the groove; and forming a metal plug in the groove.

[0055] However, with the continuous updating and iteration of planar SiC MOSFET devices, the chip size continues to decrease, and reducing the cell size has become an important direction for the development of planar SiC MOSFET devices. In the process of reducing the cell size, the aforementioned metal silicide formation process encountered problems such as the aspect ratio of the groove being too large (greater than 2:1), the metal silicide formation reaction being insufficient, and the size of the formed metal silicide being too narrow. As a result, non-ohmic contact is shown between the metal silicide and the SiC substrate, resulting in increased on-resistance and uneven on-resistance of the planar SiC MOSFET device. In addition, the aforementioned formation of the gate structure and the groove requires separate graphic processes, which increases the cost of the process.

[0056] To this end, an embodiment of the present application first provides a method for preparing a semiconductor structure. Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present application. The method for preparing a semiconductor structure comprises the following steps:

[0057] Step S101, providing a silicon carbide substrate, wherein a source region of a MOSFET device is formed in the silicon carbide substrate;

[0058] Step S102, forming a gate material layer and an interlayer dielectric layer located on the gate material layer on the silicon carbide substrate;

[0059] Step S103 , patterning the interlayer dielectric layer and the gate material layer, forming a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region, and forming a gate structure of the MOSFET device;

[0060] Step S104, forming a first sidewall on the inner sidewall surface of the groove;

[0061] Step S104, forming metal silicide on the surface of the source region between the first spacers;

[0062] Step S106, forming a second sidewall spacer on the surface of the first sidewall spacer and a portion of the surface of the metal silicide;

[0063] Step S107 , forming a metal plug to fill the remaining groove between the inner sidewalls of the second spacer.

[0064] The specific process of the method for preparing the aforementioned semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0065] First, combined with reference Figure 1 and Figure 2 , perform step S101, provide a silicon carbide substrate 201, and form the silicon carbide substrate 201 with a MOSFET device in the silicon carbide substrate 201; perform step S102, form a gate material layer and an interlayer dielectric layer 207 located on the gate material layer on the silicon carbide substrate 201.

[0066] The silicon carbide substrate 201 can be a P-type silicon carbide substrate or an N-type silicon nitride substrate. The P-type silicon carbide substrate is doped with P-type impurity ions, and the N-type silicon carbide substrate is doped with N-type impurity ions. The N-type impurity ions include one or more of phosphorus ions, arsenic ions or antimony ions, and the P-type impurity ions include one or more of boron ions, gallium ions or indium ions.

[0067] A MOSFET device is formed on a silicon carbide substrate 201. The MOSFET device includes a source region 202 and a drain region (not shown) formed within the silicon carbide substrate 201. The source region 202 has the same doping type as the drain region. Depending on the type of MOSFET device, the doping type of the source region 202 or the type of impurity ions doped in the source region 202 may vary. When the MOSFET device is an N-type device, the source region 202 is N-type or the impurity ions doped in the source region 202 are N-type impurity ions. When the MOSFET device is a P-type device, the source region 202 is N-type or the impurity ions doped in the source region 202 are P-type impurity ions. The source region 202 is formed by implanting N-type impurity ions or P-type impurity ions into the silicon carbide substrate 201 using an ion implantation process.

[0068] The MOSFET device also includes: a well region 203 located in the silicon carbide substrate 201, the source region 202 located in the well region 203, and the doping type of the well region 203 is opposite to the doping type of the source region 202 and the drain region. In one example, when the doping type of the source region 202 is N-type, the doping type of the well region 203 is P-type. In another example, when the doping type of the source region 202 is P-type, the doping type of the well region 203 is N-type.

[0069] The MOSFET device also includes: a drift region (not shown in the figure) located in the silicon carbide substrate 201, the drift region is located on one side of the well region, and the subsequently formed gate structure spans part of the drift region and part of the well region. The drain region is located in the drift region, and the doping type of the drift region is the same as the doping type of the drain region. In one example, when the doping type of the source region 202 is N-type, the doping type of the drift region is N-type. In another example, when the doping type of the drain region is P-type, the doping type of the drift region is P-type.

[0070] The MOSFET device further includes an inversion-doped region 204 located within the source region 202. The depth of the inversion-doped region 204 is the same as the depth of the well region 203. The doping type of the inversion-doped region 204 is opposite to that of the source region 202 and the same as that of the well region 203. In one example, when the doping type of the source region 202 is N-type, the doping type of the inversion-doped region 204 is P-type. In another example, when the doping type of the drain region is P-type, the doping type of the inversion-doped region 204 is N-type. The inversion-doped region 204 is used to apply a certain voltage when the MOSFET device is turned off.

[0071] In some embodiments, the gate material layer includes a gate dielectric material layer 205 located on a silicon carbide substrate 201 and a gate electrode material layer 206 located on the gate dielectric material layer 205. The gate dielectric material layer 205 is subsequently used to form a gate dielectric layer in a gate structure of a MOSFET device, and the gate electrode material layer 206 is subsequently used to form a gate electrode in a gate structure of the MOSFET device. In one example, the gate dielectric material layer 205 includes silicon oxide and is formed by a thermal oxidation process or a deposition process, and the gate electrode material layer 206 includes polysilicon and is formed by a deposition process.

[0072] Interlayer dielectric layer 207 is used to electrically isolate adjacent MOSFET devices and adjacent electrical connection structures within the MOSFET devices. In one example, interlayer dielectric layer 207 comprises a single layer structure formed by one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), BPSG (boron-phosphorus-doped silicon dioxide), or a low-k material (K less than 2.5), or a stacked structure formed by two or more of the foregoing materials. Forming interlayer dielectric layer 207 includes a deposition process.

[0073] In one embodiment, a hard mask layer 208 may be further formed on the interlayer dielectric layer 207. The material of the hard mask layer 208 is different from the material of the interlayer dielectric layer 207 and may be used as a mask for subsequent patterning of the interlayer dielectric layer 207 and the gate material layer. In one example, the material of the hard mask layer 208 is different from the material of the interlayer dielectric layer 207 and includes silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride.

[0074] Combined with reference Figure 1 and Figure 3 , proceed to step S103, pattern the interlayer dielectric layer 207 and the gate material layer, form a groove 209 in the interlayer dielectric layer 207 and the gate material layer to expose the surface of the source region 202, and form a gate structure of the MOSFET device.

[0075] In some embodiments, when patterning the interlayer dielectric layer 207 and the gate material layer, only the interlayer dielectric layer 207 and the gate electrode material layer in the gate material layer may be patterned, and the gate dielectric material layer in the gate material layer may not be patterned. The gate dielectric material layer 205 may serve as a stop layer during patterning and as a protective layer when subsequently forming the first sidewall material layer to prevent damage to the surface of the source region 202 during the process.

[0076] In some embodiments, the patterned interlayer dielectric layer 207 and the gate material layer are etched using an anisotropic dry etching process, which includes an anisotropic plasma etching process, so that the grooves 209 have higher sidewall morphology and position accuracy.

[0077] In some embodiments, the width of the formed groove 209 can be equal to or slightly smaller than the width of the source region 202. In a specific example, the width of the formed groove 209 is equal to the width of the source region 202, or the width of the formed groove 209 is 80%-100% of the width of the source region 202. The specific ratio can be, for example, 80%, 85%, 90%, 95%, or 100%. As a result, the width of the formed groove 209 is larger, and the depth-to-width ratio of the formed groove 209 is lower or reduced (less than 2:1). Subsequently, the first sidewall spacer 210 is formed (see Figure 5 ), the width of the remaining groove 209 can still be relatively large, and the aspect ratio of the remaining groove 209 is still relatively low (less than 2:1). Therefore, after the first sidewall 210 is subsequently formed, when a metal layer for forming a metal silicide 211 is formed on the surface of the source region 202 exposed by the remaining groove 209 (the metal layer is used to react with the silicon carbide substrate to form a metal silicide), the formed metal layer can fully contact the surface of the source region 202, and the thickness of the formed metal layer is relatively uniform. In addition, the temperature distribution during annealing is relatively uniform, so that the metal layer can fully react with the silicon carbide substrate 201, thereby making the thickness of the formed metal silicide 211 uniform and the width (size) relatively large, thereby avoiding non-ohmic contact between the formed metal silicide 211 and the silicon carbide substrate 201, reducing the on-resistance of the MOSFET device, and making the on-resistance uniform.

[0078] In some embodiments, the width of the formed source region 202 is 2.2μm-2.8μm, specifically 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, and 2.8μm; the width of the groove 209 is 1.7μm-2.3μm, specifically 1.7μm, 1.8μm, 1.9μm, 2.0μm, 2.1μm, 2.2μm, and 2.3μm; and the aspect ratio of the groove 209 is less than or equal to 1:1, specifically 1:1, 1:1.2, 1:1.4, 1:1.6, 1:1.8, and 1:2.

[0079] After patterning the interlayer dielectric layer 207 and the gate material layer, the remaining gate material layer outside the groove 209 forms the gate structure of the MOSFET device. Specifically, the gate structure includes a gate dielectric layer 215 and a gate electrode 216 located on the gate dielectric layer 215. In the present application, the formation of the groove 209 and the formation of the gate structure are formed using the same patterning process, which simplifies the process steps and saves costs.

[0080] In some embodiments, continue to refer to Figure 3Patterning the interlayer dielectric layer 207 and the gate material layer to form a recess 209 in the interlayer dielectric layer 207 and the gate material layer, exposing the surface of the source region 202, includes: forming a first photoresist layer (not shown) on the interlayer dielectric layer 207. In one example, the first photoresist layer can be formed on the hard mask layer 208; performing a first exposure on the first photoresist layer using a first photomask; after the first exposure, performing a first development to form a first opening (not shown) in the first photoresist layer that exposes a portion of the surface of the interlayer dielectric layer 207. The width of the first opening is equal to the width of the recess 209; and etching the interlayer dielectric layer 207 and the gate material layer along the first opening to form the recess 209 in the interlayer dielectric layer 207 and the gate material layer, exposing the surface of the source region 202. The first exposure is performed using a first photomask having a larger feature size. After the first development, a first opening having a relatively wide width (size) is formed. After etching, the relatively wide recess 209 is directly formed.

[0081] In other embodiments, patterning the interlayer dielectric layer 207 and the gate material layer to form a groove 209 in the interlayer dielectric layer 207 and the gate material layer to expose the surface of the source region 202 includes: forming a second photoresist layer (not shown in the figure) on the interlayer dielectric layer 207; performing a second exposure on the second photoresist layer using a second mask; after the second exposure, performing a second development to form a second opening in the second photoresist layer to expose a portion of the surface of the interlayer dielectric layer 207, wherein the width of the second opening is smaller than the width of the groove 209; widening the second opening so that the width of the second opening is equal to the width of the groove 209, and the widening of the second opening can be performed by an etching process; etching the interlayer dielectric layer 207 and the gate material layer along the widened second opening to form a groove 209 in the interlayer dielectric layer 207 and the gate material layer to expose the surface of the source region 202. The existing second mask with a smaller characteristic size is still used (the characteristic size of the second mask is smaller than the characteristic size of the first mask), and there is no need to change the existing mask. After the second opening is formed in the second photoresist layer, the second opening can be widened so that the width of the second opening is equal to the width of the groove 209 to be formed, and finally a wider groove 209 can still be formed.

[0082] Alternatively, patterning the interlayer dielectric layer 207 and the gate material layer to form a groove 209 in the interlayer dielectric layer 207 and the gate material layer to expose the surface of the source region 202 includes: forming a second photoresist layer on the interlayer dielectric layer 207; performing a second exposure on the second photoresist layer using a second mask; after the second exposure, performing a second development to form a second opening in the second photoresist layer to expose a portion of the surface of the interlayer dielectric layer 207, wherein the width of the second opening is smaller than the width of the groove 209; etching the interlayer dielectric layer 207 and the gate material layer along the second opening to form an initial groove in the interlayer dielectric layer 207 and the gate material layer to expose the surface of the source region 202; widening the width of the initial groove to form the groove 209, and widening the width of the initial groove uses an etching process. The existing second mask with a smaller feature size is still used (the feature size of the second mask is smaller than the feature size of the first mask), and there is no need to change the existing mask. An initial groove exposing the surface of the source region 202 is formed in the interlayer dielectric layer 207 and the gate material layer. The initial groove can be widened so that the width of the initial groove is equal to the width of the groove 209 to be formed. Finally, a wider groove 209 can still be formed.

[0083] Next, combined with reference Figure 1 and Figure 4 , proceed to step S104 to form a first sidewall 210 on the inner sidewall surface of the groove 209.

[0084] The purpose of forming the first spacer 210 is: on the one hand, to prevent the metal layer from reacting with the gate electrode 216 to form metal silicide when the metal silicide is subsequently formed, and to prevent the metal silicide formed on the source region 202 from short-circuiting with the gate electrode 216; on the other hand, the first spacer 210 is also used to adjust the metal plug 213 to be formed subsequently (refer to Figure 7 ) and the distance between the metal plug 213 and the gate electrode 216.

[0085] In some embodiments, the width of the first sidewall 210 is 1 / 8-1 / 10 of the width of the groove 209, and the width of the first sidewall 210 is smaller than the width of the second sidewall 212 subsequently formed on the surface of the first sidewall 210, so that after the first sidewall 210 is formed, the remaining groove 209 still has a wider width and a smaller aspect ratio, which is conducive to the surface metal silicide of the source region 202 exposed in the remaining groove 209. In a specific embodiment, after the first sidewall 210 is formed, the width of the remaining groove 209 is 3 / 4-4 / 5 of the width of the groove 209 before the first sidewall is formed, and the aspect ratio of the remaining groove 209 is less than 2:1. In one example, the aspect ratio of the remaining groove 209 is 0.8:1-1.8:1, specifically 0.8:1, 0.9:1, 1:1, 1.1:1, 1.2:1, 1.3:1, 1.4:1, 1.5:1, 1.6:1, 1.7:1, 1.8:1.

[0086] In some embodiments, the material of the first spacer 210 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. In a specific example, the material of the first spacer 210 is silicon oxide.

[0087] In some embodiments, forming a first sidewall spacer 210 on the inner sidewall surface of the groove 209 includes: forming a first sidewall spacer material layer (not shown in the figure) on the inner sidewall and bottom surface of the groove 209 and the top surface of the interlayer dielectric layer 207. In one example, the material of the first sidewall spacer material layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide or silicon carbonitride. In a specific example, the material of the first sidewall spacer material layer is silicon oxide. The first sidewall material layer can be formed by low pressure chemical vapor deposition (LPCVD), high pressure chemical vapor deposition (HPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), or atomic layer chemical vapor deposition (ALCVD); using a first maskless etching process to remove the first sidewall material layer from the bottom surface of the groove 209 and the top surface of the interlayer dielectric layer 207, and forming the first sidewall spacer 210 on the inner sidewall surface of the groove 209. In one example, the first maskless etching process can be an anisotropic plasma etching process. The first spacer 210 is formed by a self-alignment process, which does not require an additional photolithography process and improves the accuracy of the position and size of the formed first spacer 210 .

[0088] Next, combined with reference Figure 1 and Figure 5 , proceed to step S104 to form a metal silicide 211 on the surface of the source region 202 between the first spacers 210 .

[0089] In some embodiments, forming a metal silicide 211 on the surface of the source region 202 between the first sidewalls 210 includes: forming a metal layer on the surface of the first sidewalls 210 and the source region 202 and the top surface of the interlayer dielectric layer 207; performing an annealing process so that the metal layer reacts with the material on the surface of the source region 202 to form a metal silicide 211 layer; and removing the unreacted metal layer.

[0090] In some embodiments, the annealing temperature is 950 degrees Celsius to 1050 degrees Celsius, and the annealing time is 1 minute to 5 minutes. In some examples, the annealing may include one or more annealings. The material of the metal layer includes one or more of nickel, tungsten, cobalt, and titanium. A wet etching process is used to remove the unreacted metal layer.

[0091] In the present application, after forming a groove 209 in the interlayer dielectric layer 207 and the gate material layer to expose the surface of the source region 202, a first sidewall 210 is formed on the inner sidewall surface of the groove 209 to form the first sidewall 210 (refer to FIG. Figure 5 ), a metal silicide 211 is formed on the surface of the source region 202 between the first spacers 210; subsequently, a second spacer 212 is formed on the surface of the first spacer 210 and a portion of the surface of the metal silicide 211, and a metal plug 213 is formed to fill the remaining groove between the inner sidewalls of the second spacer 212 (refer to Figure 7 In the present application, since the metal plug 213 is formed after the second sidewall spacer 212 is formed, the metal plug 213 is isolated from the gate structure by the first sidewall spacer 210 and the second sidewall spacer 212. When the size of the formed metal plug 213 is small (or the size of the formed MOSFET device is small), the width (or size) of the corresponding groove 209 can be larger, and the aspect ratio of the groove 209 can be lower (less than 2:1). After the first sidewall spacer 210 is formed on the inner sidewall surface of the groove 209, the remaining width (or size) of the groove 209 can still be larger, and the aspect ratio of the groove 209 can still be lower. Therefore, when a metal layer for forming a metal silicide 211 is formed on the surface of the source region 202 exposed by the remaining groove 209 (the metal layer reacts with the silicon carbide substrate 201 to form the metal silicide 211), the formed metal layer can fully contact the surface of the source region 202 and form The thickness of the metal layer is relatively uniform, and the temperature distribution during annealing is relatively uniform, so that the metal layer can fully react with the silicon carbide substrate 201, thereby making the thickness of the formed metal silicide 211 uniform. The width (size) of the metal silicide 211 is relatively large, thereby avoiding non-ohmic contact between the formed metal silicide 211 and the silicon carbide substrate 201, reducing the on-resistance of the MOSFET device, and making the on-resistance uniform. In addition, because the width (or size) of the remaining groove 209 can still be relatively large, the aspect ratio of the groove 209 can still be relatively low. When the metal silicide 211 is formed, carbon elements in the reaction process between the metal layer and the silicon carbide substrate 201 are easily precipitated to the surface. After the metal silicide 211 is formed, when the unreacted metal layer is removed, the carbon elements can be simultaneously removed, thereby reducing the carbon content in the metal silicide 211 and further reducing the resistance of the formed metal silicide 211.

[0092] Next, combined with reference Figure 1 and Figure 6 , proceed to step S106 to form a second sidewall spacer 212 on the surface of the first sidewall spacer 210 and a portion of the surface of the metal silicide 211 .

[0093] The second sidewall spacer 212 is used to adjust the metal plug 213 formed subsequently (refer to Figure 7 ) and the distance between the metal plug 213 and the gate structure (gate electrode 216), and are also used for electrical isolation between the metal plug 213 and the gate structure, and between the metal silicide 211 and the gate structure.

[0094] In some embodiments, the width of the second spacer 212 is greater than the width of the first spacer 210 .

[0095] In some embodiments, the material of the second sidewall 212 is different from the material of the first sidewall 210. In one example, the material of the second sidewall 212 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide or silicon carbonitride. In a specific example, the material of the second sidewall 212 is silicon nitride.

[0096] Forming a second sidewall spacer 212 on the surface of the first sidewall spacer 210 and a portion of the surface of the metal silicide 211 includes: forming a second sidewall spacer material layer on the surfaces of the first sidewall spacer 210 and the metal silicide 211 and the top surface of the interlayer dielectric layer 207, wherein the material of the second sidewall spacer material layer is different from the material of the first sidewall spacer 210. In one example, the material of the second sidewall material layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide or silicon carbonitride. In a specific example, the material of the second sidewall material layer is silicon oxide, and a second maskless etching process is subsequently used to etch the second sidewall material layer to prevent or reduce etching of the first sidewall spacer 210; and a second maskless etching process is used to remove the second sidewall material layer on the surface of the metal silicide 211 and the top surface of the interlayer dielectric layer 207 to form a second sidewall spacer 212 on the surface of the groove 209. In one example, the second maskless etching process can be an anisotropic plasma etching process. The second sidewall spacer 212 is formed by a self-alignment process, which does not require an additional photolithography process and improves the accuracy of the position and size of the formed second sidewall spacer 212 .

[0097] Finally, combined with reference Figure 1 and Figure 7 , proceed to step S107 to form a metal plug 213 that fills the remaining groove 209 between the inner sidewalls of the second spacer 212 .

[0098] The material of the metal plug 213 includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0099] In some embodiments, the process of forming the metal plug 213 includes: forming a metal plug material layer in the remaining groove 209 between the inner sidewalls of the second sidewall 212 and on the surface of the interlayer dielectric layer 207, wherein the formation of the metal plug material layer includes a sputtering process; and using a chemical mechanical polishing process to planarize and remove a portion of the metal plug material layer to form the metal plug 213 in the remaining groove 209 between the inner sidewalls of the second sidewall 212.

[0100] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. Within this specification, the illustrative descriptions of these terms do not necessarily refer to the same embodiment or example.

[0101] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a silicon carbide substrate, wherein a source region of a MOSFET device is formed in the silicon carbide substrate; forming a gate material layer and an interlayer dielectric layer on the gate material layer on the silicon carbide substrate; Patterning the interlayer dielectric layer and the gate material layer, forming a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region, and forming a gate structure of the MOSFET device; forming a first side wall on the inner side wall surface of the groove; forming a metal silicide on the surface of the source region between the first sidewalls; forming a second sidewall spacer on a surface of the first sidewall spacer and a portion of a surface of the metal silicide; A metal plug is formed to fill the remaining groove between the inner sidewalls of the second sidewall.

2. The method for preparing a semiconductor structure according to claim 1, wherein: Forming a first sidewall on the inner sidewall surface of the groove includes: forming a first sidewall material layer on the inner sidewall and bottom surface of the groove and the top surface of the interlayer dielectric layer; using a first maskless etching process to remove the first sidewall material layer on the bottom surface of the groove and the top surface of the interlayer dielectric layer to form a first sidewall on the inner sidewall surface of the groove.

3. The method for preparing a semiconductor structure according to claim 1, wherein: Forming a second side wall on the surface of the first side wall and a portion of the surface of the metal silicide includes: forming a second side wall material layer on the surfaces of the first side wall and the metal silicide and the top surface of the interlayer dielectric layer; using a second maskless etching process to remove the second side wall material layer on the surface of the metal silicide and the top surface of the interlayer dielectric layer, and forming the second side wall on the surface of the groove.

4. The method for preparing a semiconductor structure according to claim 2 or 3, wherein: The material of the second sidewall is different from that of the first sidewall.

5. The method for preparing a semiconductor structure according to claim 1, wherein: Forming a metal silicide on the surface of the source region between the first side walls includes: forming a metal layer on the surface of the first side walls and the source region and the top surface of the interlayer dielectric layer; performing an annealing process so that the metal layer reacts with the material on the surface of the source region to form a metal silicide layer; and removing the unreacted metal layer.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The annealing temperature is 950 degrees Celsius to 1050 degrees Celsius, and the annealing time is 1 minute to 5 minutes; the material of the metal layer includes one or more of nickel, tungsten, cobalt, and titanium; and a wet etching process is used to remove the unreacted metal layer.

7. The method for preparing a semiconductor structure according to claim 1 or 5, characterized in that: The width of the groove is equal to the width of the source region, or the width of the groove is 80%-100% of the width of the source region, and the aspect ratio of the groove is less than 2:1; After the first sidewall is formed, the aspect ratio of the remaining groove is less than 2:

1.

8. The method for preparing a semiconductor structure according to claim 1 or 5, characterized in that: The width of the first sidewall is 1 / 8-1 / 10 of the width of the groove, and the width of the first sidewall is smaller than the width of the second sidewall.

9. The method for preparing a semiconductor structure according to claim 1, wherein: The gate material layer includes a gate dielectric material layer and a gate electrode material layer located on the gate dielectric material layer; The gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer; The source region is located in the silicon carbide substrate on one side of the gate structure, and the MOSFET device further includes a drain region in the silicon carbide substrate on the other side of the gate structure; The MOSFET device further comprises: a well region located in the silicon carbide substrate, the source region being located in the well region, and the doping type of the well region being opposite to the doping types of the source region and the drain region; The MOSFET device further comprises: an inversion doping region located in the source region, wherein the depth of the inversion doping region is the same as the depth of the well region, and the doping type of the inversion doping region is opposite to the doping type of the source region and the same as the doping type of the well region; The MOSFET device also includes: a drift region located in the silicon carbide substrate, the drift region is located on one side of the well region, the gate structure spans part of the drift region and part of the well region, the drain region is located in the drift region, and the doping type of the drift region is the same as the doping type of the drain region.

10. The method for preparing a semiconductor structure according to claim 1, wherein: Patterning the interlayer dielectric layer and the gate material layer to form a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region includes: forming a first photoresist layer on the interlayer dielectric layer; performing a first exposure on the first photoresist layer using a first mask; after the first exposure, performing a first development to form a first opening in the first photoresist layer to expose a portion of the surface of the interlayer dielectric layer, wherein the width of the first opening is equal to the width of the groove; etching the interlayer dielectric layer and the gate material layer along the first opening to form a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region; Alternatively, patterning the interlayer dielectric layer and the gate material layer to form a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region includes: forming a second photoresist layer on the interlayer dielectric layer; performing a second exposure on the second photoresist layer using a second mask; after the second exposure, performing a second development to form a second opening in the second photoresist layer to expose a portion of the surface of the interlayer dielectric layer, wherein the width of the second opening is smaller than the width of the groove; widening the second opening so that the width of the second opening is equal to the width of the groove; etching the interlayer dielectric layer and the gate material layer along the widened second opening to form a groove in the interlayer dielectric layer and the gate material layer to expose the surface of the source region; Alternatively, patterning the interlayer dielectric layer and the gate material layer to form a groove in the interlayer dielectric layer and the gate material layer that exposes the surface of the source region includes: forming a second photoresist layer on the interlayer dielectric layer; performing a second exposure on the second photoresist layer using a second mask; after the second exposure, performing a second development to form a second opening in the second photoresist layer that exposes a portion of the surface of the interlayer dielectric layer, the width of the second opening being smaller than the width of the groove; etching the interlayer dielectric layer and the gate material layer along the second opening to form an initial groove in the interlayer dielectric layer and the gate material layer that exposes the surface of the source region; and widening the width of the initial groove to form the groove.

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