Silicon carbide MOSFET device with improved follow current capability and manufacturing method thereof

Abstract

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with improved follow current capability, which comprises an MOSFET structure and a plurality of JBS structures integrated in the MOSFET structure, the JBS structure is provided with drain electrode metal, an N-type substrate layer, an N-type epitaxial layer, a source electrode Schottky contact alloy layer and source electrode metal from bottom to top, the top surface of the N-type epitaxial layer is provided with a rectangular ring PP region formed by a vertical PP region and a parallel PP region, and the two ends of the vertical PP region are located in the P-type body region or located on the boundaries of the two sides of the P-type body region. According to the invention, the conduction voltage drop and energy loss of follow current and the turn-on voltage of the silicon carbide diode are obviously reduced, and the follow current capability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a silicon carbide MOSFET device with improved freewheeling capability and a manufacturing method thereof. Background Art

[0002] In the field of power electronics, silicon-based power devices have long been the dominant force due to its significant advantages, including its abundant natural reserves, mature preparation and purification processes, stable single-crystal structure, high reliability, and low price. However, with the continuous advancement of power electronics technology, power devices are moving towards smaller size, higher density, higher frequency, and greater power, placing increasingly stringent demands on semiconductor materials. However, due to the inherent limitations of silicon's material properties, its performance development has reached its limits. Consequently, third-generation wide-bandgap semiconductor materials, represented by silicon carbide, have begun to rapidly develop.

[0003] Due to a series of advantages of silicon carbide materials such as large bandgap width, high critical breakdown field strength, low intrinsic carrier concentration, fast saturation drift rate, and high thermal conductivity, the power devices prepared from it can have smaller chip size and volume than traditional silicon-based power devices while also having high voltage and large current capabilities; especially silicon carbide MOSFET devices, compared with silicon MOSFET and silicon IGBT devices, they have both excellent conduction and switching characteristics, showing great application prospects in high voltage, high temperature, high frequency and other fields; however, silicon carbide MOSFET devices also have obvious disadvantages. Since the parasitic body diodes of silicon carbide MOSFET are all PN junction diodes, their disadvantages are poor forward performance and large freewheeling loss. Therefore, how to reduce the freewheeling loss of the parasitic body diode inside the silicon carbide MOSFET without increasing the chip area too much and improve the performance of the chip is a technical problem that needs to be solved urgently. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a silicon carbide MOSFET device with improved freewheeling capability and a method for manufacturing the same, which significantly reduces the on-state voltage drop during freewheeling, thereby reducing energy loss, can reduce the turn-on voltage of the silicon carbide diode, and improve the freewheeling capability of the device.

[0005] The technical solution adopted in the present invention is: A silicon carbide MOSFET device with improved freewheeling capability, comprising a MOSFET structure and a plurality of JBS structures integrated within the MOSFET structure; The MOSFET structure includes a drain metal, an N-type substrate layer, an N-type epitaxial layer, a source ohmic contact alloy layer and a source metal arranged from bottom to top; An N-type well region is provided on the top surface of the N-type epitaxial layer, and a plurality of P-type body regions are spaced apart from each other on the top surface of the N-type well region. The P-type body regions extend downward from the top surface of the N-type epitaxial layer and are parallel to each other. The JBS structure includes a drain metal, an N-type substrate layer, an N-type epitaxial layer, a source Schottky contact alloy layer and a source metal arranged from bottom to top; A rectangular ring PP region is set on the top surface of the N-type epitaxial layer of the JBS structure. The rectangular ring PP region is a rectangle surrounded by two parallel PP regions and two vertical PP regions. The endpoints of the vertical PP region are located in the P-type body region or on both side boundaries of the P-type body region.

[0006] Preferably, in the silicon carbide MOSFET device with improved freewheeling capability, within the MOSFET structure, a NP region and a first PP region connected to each other are provided downwardly from the top surface of the P-type body region, a gap is provided between the NP region and the bottom surface of the P-type body region, and a gap is provided between the first PP region and the bottom surface of the P-type body region; A gate oxide layer, a polysilicon layer, and an insulating dielectric layer are stacked from bottom to top between the source metal and the N-type epitaxial layer, wherein the bottom surface of the gate oxide layer is connected to the N-type well region, the P-type body region, and the NP region, respectively; and the insulating dielectric layer extends downward from the side of the polysilicon layer and is connected to the NP region. A first through hole is set between adjacent insulating dielectric layers, a source ohmic contact alloy layer is set at the bottom of the first through hole, the source metal is connected to the source ohmic contact alloy layer through the first through hole, and the source ohmic contact alloy layer is connected to the NP region and the first PP region.

[0007] Preferably, in the silicon carbide MOSFET device with improved freewheeling capability, the parallel PP region is parallel to the extension direction of the P-type body region in the horizontal plane, the vertical PP region is perpendicular to the extension direction of the P-type body region in the horizontal plane, and the vertical PP region is connected to the P-type body region.

[0008] Preferably, the silicon carbide MOSFET device with improved freewheeling capability, wherein a second through hole is provided above the N-type epitaxial layer of the JBS structure, a source Schottky contact alloy layer is provided at the bottom of the second through hole, the source metal is connected to the source Schottky contact alloy layer through the second through hole, and the source Schottky contact alloy layer is connected to the rectangular ring PP region and the N-type epitaxial layer.

[0009] Preferably, in the silicon carbide MOSFET device with improved freewheeling capability, a plurality of second PP regions are provided on the top surface of the N-type epitaxial layer of the JBS structure, the second PP regions are provided in the rectangular ring PP region, the two ends of the second PP regions are connected to the rectangular ring PP region, and the interval between adjacent second PP regions is the N-type epitaxial layer of the JBS structure.

[0010] Preferably, in the silicon carbide MOSFET device with improved freewheeling capability, the plurality of second PP regions are distributed in a spaced-apart block or strip shape.

[0011] Preferably, in the silicon carbide MOSFET device with improved freewheeling capability, the first PP region, the rectangular ring PP region and the second PP region are heavily P-type doped.

[0012] A method for manufacturing a silicon carbide MOSFET device with improved freewheeling capability, comprising the following steps: Step S1. epitaxially growing an N-type epitaxial layer on an N-type substrate layer, wherein a side of the N-type epitaxial layer away from the N-type substrate layer is the front side of the chip; Step S2. depositing a first barrier layer on the front surface of the chip, etching a P-type body region injection window on the first barrier layer through a first mask window, and injecting P-type impurities to form a P-type body region; Step S3. Depositing a second barrier layer on the front side of the chip, and etching away a predetermined thickness of the barrier layer material on the second barrier layer through a second mask window to form an injection window for the NP region, and then injecting N-type impurities to form the NP region; Step S4. removing the barrier layer material on the front side of the chip, then depositing a third barrier layer on the front side of the chip, etching an injection window for the N-type well region through a third mask window, and injecting N-type impurities to form an N-type well region; Step S5. Remove the barrier layer material on the front side of the chip, then deposit a fourth barrier layer on the front side of the chip, and etch the injection windows of the first PP region and the rectangular PP region through the fourth mask window, and inject P-type impurities to form the first PP region and the rectangular PP region; Step S6. Remove the barrier layer material on the front side of the chip. Then, grow a gate oxide layer on the front side of the chip and deposit polysilicon to form a polysilicon layer. Etch away the excess gate oxide layer and polysilicon layer through the fifth mask window. In the MOSFET structure area, the surface of the NP region and the first PP region is exposed. In the JBS structure area, the rectangular ring PP region and the N-type epitaxial layer are exposed. Step S7. An insulating dielectric is deposited on the front side of the chip to form an insulating dielectric layer. Then, a first through-hole in the MOSFET structure region and a second through-hole in the JBS structure region are selectively etched through the sixth mask window on the insulating dielectric layer. In the MOSFET structure region, the surfaces of the NP region and the first PP region are exposed. In the JBS structure region, the rectangular ring PP region and the N-type epitaxial layer are exposed. Step S8. Depositing metal on the front side of the chip so that the metal forms a metal silicide with silicon carbide. In the MOSFET structure area, the exposed NP region and the surface of the first PP region form a source ohmic contact alloy layer. In the JBS structure area, the exposed rectangular ring PP region and the surface of the N-type epitaxial layer form a source Schottky contact alloy layer. Step S9. Deposit metal on the front side of the chip and selectively etch the metal through the seventh mask window to form source metal and gate metal, and finally deposit metal on the back side of the chip to form drain metal.

[0013] A method for manufacturing a silicon carbide MOSFET device with improved freewheeling capability, comprising the following steps: Step S1. epitaxially growing an N-type epitaxial layer on an N-type substrate layer, wherein a side of the N-type epitaxial layer away from the N-type substrate layer is the front side of the chip; Step S2. depositing a first barrier layer on the front surface of the chip, etching a P-type body region injection window on the first barrier layer through a first mask window, and injecting P-type impurities to form a P-type body region; Step S3. Depositing a second barrier layer on the front side of the chip, and etching away a predetermined thickness of the barrier layer material on the second barrier layer through a second mask window to form an injection window for the NP region, and then injecting N-type impurities to form the NP region; Step S4. Remove the barrier layer material on the front side of the chip, then deposit a third barrier layer on the front side of the chip, etch an N-type well injection window through a third mask window in the MOSFET structure area, and inject N-type impurities to form an N-type well region; Step S5. Remove the barrier layer material on the front side of the chip, then deposit a fourth barrier layer on the front side of the chip. Etch the injection windows of the first PP region, the rectangular PP region, and the second PP region in the MOSFET structure area through the fourth mask window, and inject P-type impurities to form the first PP region, the rectangular PP region, and the second PP region. Step S6. Remove the barrier layer material on the front side of the chip. Then, grow a gate oxide layer on the front side of the chip and deposit polysilicon to form a polysilicon layer. Etch away the excess gate oxide layer and polysilicon layer through the fifth mask window. In the MOSFET structure area, the surfaces of the NP region and the first PP region are exposed. In the JBS structure area, the rectangular ring PP region, the second PP region, and the N-type epitaxial layer are exposed. Step S7. An insulating dielectric is deposited on the front side of the chip to form an insulating dielectric layer. Then, through the sixth mask window, a through-hole in the MOSFET structure area and a through-hole in the JBS structure area are selectively etched on the insulating dielectric layer. In the MOSFET structure area, the surfaces of the NP region and the first PP region are exposed. In the JBS structure area, the rectangular ring PP region, the second PP region, and the N-type epitaxial layer are exposed. Step S8. Depositing metal on the front side of the chip so that the metal and silicon carbide form a metal silicide. In the MOSFET structure area, the exposed NP region and the surface of the first PP region form a source ohmic contact alloy layer. In the JBS structure area, the exposed rectangular ring PP region, the second PP region, and the surface of the N-type epitaxial layer form a source Schottky contact alloy layer. Step S9. Deposit metal on the front side of the chip and selectively etch the metal through the seventh mask window to form source metal and gate metal, and finally deposit metal on the back side of the chip to form drain metal.

[0014] Advantages of the present invention: (1) The silicon carbide MOSFET device with improved freewheeling capability of the present invention can significantly reduce the on-state voltage drop of freewheeling, thereby reducing energy loss, and can reduce the turn-on voltage of the silicon carbide diode, thereby improving the freewheeling capability of the device; the JBS structure has a high breakdown voltage, a small leakage current, and a high cell density of the JBS structure, which improves the freewheeling capability of the JBS structure.

[0015] (2) The silicon carbide MOSFET device with improved freewheeling capability of the present invention can significantly reduce the freewheeling conduction voltage drop through the electron current when the source metal voltage is less than 3V by implanting the JBS structure in the silicon carbide MOSFET device, thereby reducing energy loss.

[0016] (3) The silicon carbide MOSFET device with improved freewheeling capability of the present invention has multiple JBS structures evenly distributed on the surface of the silicon carbide MOSFET device. There are multiple P-type body regions between each JBS structure. When the source metal 11 is less than 3V, the electron current is freewheeling. The electron current passes through the bottom of the P-type body region, which will cause the potential under the P-type body region to drop, thereby causing the potential of the P-type body region relative to the N-type well region to rise. The more P-type body regions the electron current passes through, the higher the potential difference between the P-type body region and the N-type well region. When the potential difference between the two reaches 3V, even if the source metal is less than 3V, the diode composed of the P-type body region and the N-type well region will turn on normally. The freewheeling capability of the device is enhanced due to the addition of the silicon carbide diode. Therefore, the present invention can reduce the turn-on voltage of the silicon carbide diode and improve the freewheeling capability of the device.

[0017] (4) In the silicon carbide MOSFET device with improved freewheeling capability of the present invention, the rectangular ring PP region is a closed rectangular circle, and each right angle thereof is protected by the P-type body region, thereby ensuring the breakdown voltage of the device; the N-type well region is not provided in the JBS structure, thereby reducing the leakage current of the device and ensuring that the breakdown voltage of the JBS structure is not lower than that of the silicon carbide MOSFET structure; (5) In the manufacturing method of the silicon carbide MOSFET device with improved freewheeling capability of the present invention, the parallel PP region, the vertical PP region and the second PP region in the JBS structure are implanted synchronously with the first PP region, thereby saving a mask window. Moreover, since the parallel PP region, the vertical PP region and the second PP region are heavily P-type doped, the widths of the above three regions can be extremely small, thereby increasing the cell density and improving the freewheeling capability of the JBS structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 1 is a schematic top view of the structure of the P-type body region, the rectangular PP region and the second PP region in Example 1 of the present invention.

[0019] Figure 2 It is along Figure 1 Schematic diagram of the cross-sectional structure taken along the dotted line AB.

[0020] Figure 3 3. It is a schematic top view of the structure of the P-type body region, the rectangular PP region and the second PP region of Example 2 of the present invention.

[0021] Figure 4 It is along Figure 2 Schematic diagram of the cross-sectional structure taken along the dotted line CD.

[0022] Figure 5 3 is a schematic top view of the structure of the P-type body region, the rectangular PP region and the second PP region of Example 3 of the present invention.

[0023] Figure 6 It is along Figure 2 Schematic diagram of the cross-sectional structure taken along the dotted line EF.

[0024] Figure 7 3 is a schematic top view of the structure of the P-type body region, the rectangular PP region and the second PP region in Example 4 of the present invention.

[0025] Figure 8 It is a schematic cross-sectional structural diagram of forming an N-type epitaxial layer in step 1 of embodiment 1 of the present invention.

[0026] Figure 9 It is a schematic cross-sectional structural diagram of forming a P-type body region in step 2 of embodiment 1 of the present invention.

[0027] Figure 10It is a schematic diagram of the cross-sectional structure of forming the NP region in step three of Example 1 of the present invention.

[0028] Figure 11 It is a schematic cross-sectional structural diagram of forming an N-type well region in step four of embodiment 1 of the present invention.

[0029] Figure 12 It is a schematic cross-sectional structural diagram of forming the first PP region, the rectangular circle PP region and the second PP region in step five of Example 1 of the present invention.

[0030] Figure 13 It is a schematic cross-sectional structural diagram of forming a gate oxide layer and a polysilicon layer in step six of embodiment 1 of the present invention.

[0031] Figure 14 It is a schematic cross-sectional structural diagram of etching a through hole after depositing an insulating dielectric layer in step seven of embodiment 1 of the present invention.

[0032] Figure 15 It is a schematic cross-sectional structural diagram of forming a source ohmic contact alloy layer and a source Schottky contact alloy layer in step eight of embodiment 1 of the present invention.

[0033] Figure 16 3. It is a schematic top view of the structure of the P-type body region and the rectangular circle PP region of Example 5 of the present invention.

[0034] Figure 17 It is a schematic top view of the structure of the P-type body region and the rectangular circle PP region of Example 6 of the present invention.

[0035] Figure 18 3. It is a schematic top view of the structure of the P-type body region and the rectangular circle PP region of Example 7 of the present invention. DETAILED DESCRIPTION

[0036] The present invention will be further described below with reference to specific embodiments.

[0037] Example 1 A silicon carbide MOSFET device with improved freewheeling capability includes a JBS structure 16 located in the center of a semiconductor substrate and a MOSFET structure outside the JBS structure 16; Figure 1 FIG. 1 is a top view of the P-type body region 5, the parallel PP region 6b, the perpendicular PP region 6c, and the second PP region 6d of this embodiment. Region 16 is a JBS structure, which is a junction barrier Schottky diode. The area outside region 16 is a MOSFET structure, which is a metal oxide semiconductor field effect transistor. Figure 2 It is along Figure 1 Schematic diagram of the cross-sectional structure taken along the dotted line AB.

[0038] The MOSFET structure includes a drain metal 1, an N-type substrate layer 2, an N-type epitaxial layer 3, a source ohmic contact alloy layer 12 and a source metal 11 stacked from bottom to top; An N-type well region 4 having a lower resistivity than the N-type epitaxial layer 3 is provided on the top surface of the N-type epitaxial layer 3. A plurality of P-type body regions 5 are spaced apart on the top surface of the N-type well region 4. The plurality of P-type body regions 5 extend downward from the top surface of the N-type epitaxial layer 3 and are parallel to each other. An NP region 7 and a first PP region 6a are connected to each other and extend downward from the top surface of the P-type body region 5. A gap is provided between the NP region 7 and the bottom surface of the P-type body region 5. A gap is provided between the first PP region 6a and the bottom surface of the P-type body region 5. A gate oxide layer 8, a polysilicon layer 9, and an insulating dielectric layer 10 are stacked from bottom to top between the source metal 11 and the N-type epitaxial layer 3. The bottom surface of the gate oxide layer 8 is connected to the N-type well region 4, the P-type body region 5, and the NP region 7, respectively. The insulating dielectric layer 10 is connected to the NP region 7. The insulating dielectric layer 10 extends downward from the side of the polysilicon layer 9. A first through hole 14 is set between adjacent insulating dielectric layers 10, and a source ohmic contact alloy layer 12 is set at the bottom of the first through hole 14. The source metal 11 is connected to the source ohmic contact alloy layer 12 through the first through hole 14, and the source ohmic contact alloy layer 12 is connected to the NP region 7 and the first PP region 6a.

[0039] The JBS structure includes a drain metal 1, an N-type substrate layer 2, an N-type epitaxial layer 3, a source Schottky contact alloy layer 13 and a source gold 11 arranged from bottom to top; A rectangular ring PP region is set on the top surface of the N-type epitaxial layer 3 of the JBS structure. The rectangular ring PP region is a rectangle surrounded by two parallel PP regions 6b and two vertical PP regions 6c. The two ends of the vertical PP region 6c are located at the two side boundaries of the P-type body region 5; the parallel PP regions 6b are parallel to the extension direction of the P-type body region 5 on the horizontal plane, and the vertical PP regions 6c are perpendicular to the extension direction of the P-type body region 5 on the horizontal plane. The vertical PP regions 6c are connected to the P-type body region 5.

[0040] When the two ends of the vertical PP region 6c are located at the two side boundaries of the P-type body region 5, the two ends of the vertical PP region 6c are located at the two inner boundaries of different P-type body regions 5, so that the parallel PP region 6b is close to the P-type body region 5, and the P-type body region 5 remains intact.

[0041] A second through hole 15 is provided above the N-type epitaxial layer 3 of the JBS structure, and a source Schottky contact alloy layer 13 is provided at the bottom of the second through hole 15. The source metal 11 is connected to the source Schottky contact alloy layer 13 through the second through hole 15, and the source Schottky contact alloy layer 13 is connected to the rectangular circle PP region and the N-type epitaxial layer 3.

[0042] A plurality of second PP regions 6d are provided on the top surface of the N-type epitaxial layer 3 of the JBS structure. The second PP regions 6d are provided in the rectangular ring PP region. Both ends of the second PP regions 6d are connected to the rectangular ring PP region. The interval between adjacent second PP regions 6d is the N-type epitaxial layer 3 of the JBS structure. The plurality of second PP regions 6d are distributed in the form of spaced strips. The first PP region 6a, the rectangular ring PP region and the second PP region 6d are heavily P-type doped.

[0043] The method for manufacturing a silicon carbide MOSFET device with improved freewheeling capability of this embodiment includes the following steps: Step S1. Figure 8 As shown, an N-type epitaxial layer 3 is epitaxially grown on the N-type substrate layer 2, and the side of the N-type epitaxial layer 3 away from the N-type substrate layer 2 is the front side of the chip; Step S2. Figure 9 As shown, a first barrier layer 17 is deposited on the front side of the chip, and a P-type body region 5 injection window of the MOSFET structure is etched on the first barrier layer 17 through a first mask window, and P-type impurities are injected to form the P-type body region 5, where the P-type impurities are aluminum or boron; Step S3. Figure 10 As shown, a second barrier layer 18 is deposited on the front side of the chip, and a barrier layer material of a set thickness on the second barrier layer 18 is etched away through a second mask window to form an injection window for the NP region 7, and then N-type impurities are injected to form the NP region 7, where the N-type impurities are phosphorus or nitrogen; Step S4. Figure 11 As shown, the barrier layer material of the second barrier layer 18 on the front side of the chip is removed and a third barrier layer 19 is deposited on the front side of the chip. An injection window for the N-type well region 4 is etched in the MOSFET structure area through a third mask window, and N-type impurities are injected to form the N-type well region 4. Step S5. Figure 12 As shown, the barrier layer material of the third barrier layer 19 on the front side of the chip is removed and a fourth barrier layer 20 is deposited on the front side of the chip. In the MOSFET structure area, an injection window for the first PP region 6a and the rectangular PP region is etched through a fourth mask window, and P-type impurities are injected to form the first PP region 6a, the rectangular PP region and the second PP region 6d. Step S6. Figure 13As shown, the barrier layer material of the fourth barrier layer 20 on the front side of the chip is removed and a gate oxide layer 8 is grown on the front side of the chip. Polysilicon is deposited to form a polysilicon layer 9. The excess gate oxide layer 8 and polysilicon layer 9 are etched away through the fifth mask window. In the MOSFET structure area, the surfaces of the NP region 7 and the first PP region 6a are exposed. In the JBS structure area, the rectangular ring PP region and the N-type epitaxial layer 3 are exposed. Step S7. Figure 14 As shown, an insulating dielectric is deposited on the front side of the chip to form an insulating dielectric layer 10. Then, a through hole 14 in the MOSFET structure area and a through hole 15 in the JBS structure area are selectively etched on the insulating dielectric layer 10 through a sixth mask window. In the MOSFET structure area, the surfaces of the NP region 7 and the first PP region 6a are exposed. In the JBS structure area, the rectangular ring PP region and the N-type epitaxial layer 3 are exposed. Step S8. As shown in 15 , metal is deposited on the front surface of the chip, forming a metal silicide with the silicon carbide. In the MOSFET structure area, the exposed NP region 7 and the surface of the first PP region 6 a form a source ohmic contact alloy layer 12. In the JBS structure area, the exposed rectangular ring PP region and the surface of the N-type epitaxial layer 3 form a source Schottky contact alloy layer 13. Step S9. Figure 2 As shown, metal is deposited on the front side of the chip and selectively etched through the seventh mask window to form source metal 11 and gate metal, and then metal is deposited on the back side of the chip to form drain metal 1.

[0044] Example 2 Figure 3 FIG. 1 is a top view of the P-type body region 5, the parallel PP region 6b, the vertical PP region 6c, and the second PP region 6d of this embodiment. Region 16 is a JBS structure, and the region outside region 16 is a MOSFET structure. Figure 4 It is along Figure 3 Schematic diagram of the cross-sectional structure cut by the dotted line CD in FIG; the difference between the MOSFET structure and the JBS structure and Example 1 is that the two ends of the vertical PP region 6c are located in different P-type body regions 5, so that the parallel PP region 6b is embedded in the P-type body region 5, and the P-type body region 5 is in a defective state.

[0045] Example 3 Figure 5 FIG. 1 is a top view of the P-type body region 5, the parallel PP region 6b, the vertical PP region 6c, and the second PP region 6d of this embodiment. Region 16 is a JBS structure, and the region outside region 16 is a MOSFET structure. Figure 6 It is along Figure 5Schematic diagram of the cross-sectional structure cut by the dotted line EF in FIG; the difference between the MOSFET structure and the JBS structure and Example 1 is that the two ends of the vertical PP region 6c are located at the outer boundaries of different P-type body regions 5, and the vertical PP region 6c completely cuts off the P-type body region 5, so that one side of the parallel PP region 6b coincides with the boundary of the P-type body region 5.

[0046] Example 4 Figure 7 FIG1 is a schematic top view of the P-type body region 5, parallel PP region 6b, vertical PP region 6c, and second PP region 6d of this embodiment. Region 16 is a JBS structure, and the area outside region 16 is a MOSFET structure. The MOSFET structure and the JBS structure differ from those in Example 1 in that the two ends of the vertical PP region 6c are located at different inner boundaries of the P-type body region 5, so that the parallel PP region 6b is closely attached to the P-type body region 5, and the P-type body region 5 remains intact; and the second PP region 6d is distributed in a block shape.

[0047] Example 5 Figure 16 1 is a schematic diagram of the top-down structure of the P-type body region 5, the parallel PP region 6b, and the vertical PP region 6c of this embodiment. Region 16 is a JBS structure, and the region outside region 16 is a MOSFET structure. The MOSFET structure is the same as that in Example 1. The difference between the JBS structure and Example 1 is that the two ends of the vertical PP region 6c are located at the inner boundaries of the two adjacent P-type body regions 5, so that the parallel PP region 6b is in close contact with the P-type body region 5, and the second PP region 6d is not provided.

[0048] The method for manufacturing a silicon carbide MOSFET device with improved freewheeling capability of this embodiment includes the following steps: Step S1. epitaxially growing an N-type epitaxial layer 3 on the N-type substrate layer 2, wherein the side of the N-type epitaxial layer 3 away from the N-type substrate layer 2 is the front side of the chip; Step S2. Depositing a first barrier layer 17 on the front side of the chip, etching a P-type body region 5 injection window of the MOSFET structure on the first barrier layer 17 through a first mask window, and injecting P-type impurities to form a P-type body region 5; Step S3. Depositing a second barrier layer 18 on the front side of the chip, and etching away a set thickness of the barrier layer material on the second barrier layer 18 through a second mask window to form an injection window for the NP region 7, and then injecting N-type impurities to form the NP region 7; Step S4. Remove the barrier layer material of the second barrier layer 18 on the front side of the chip and deposit a third barrier layer 19 on the front side of the chip. Etch an injection window for the N-type well region 4 through a third mask window in the MOSFET structure area, and inject N-type impurities to form the N-type well region 4. Step S5. The barrier layer material of the third barrier layer 19 on the front side of the chip is removed and a fourth barrier layer 20 is deposited on the front side of the chip. In the MOSFET structure area, an injection window for the first PP region 6a and the rectangular PP region is etched through a fourth mask window, and P-type impurities are injected to form the first PP region 6a and the rectangular PP region. Step S6. Remove the barrier layer material of the fourth barrier layer 20 on the front side of the chip and grow a gate oxide layer 8 on the front side of the chip. Deposit polysilicon to form a polysilicon layer 9. Etch away the excess gate oxide layer 8 and polysilicon layer 9 through the fifth mask window. In the MOSFET structure area, the surfaces of the NP region 7 and the first PP region 6a are exposed. In the JBS structure area, the rectangular ring PP region and the N-type epitaxial layer 3 are exposed. Step S7. An insulating dielectric is deposited on the front surface of the chip to form an insulating dielectric layer 10. Then, a through hole 14 in the MOSFET structure region and a through hole 15 in the JBS structure region are selectively etched through the sixth mask window in the insulating dielectric layer 10. In the MOSFET structure region, the surfaces of the NP region 7 and the first PP region 6a are exposed. In the JBS structure region, the rectangular ring PP region and the N-type epitaxial layer 3 are exposed. Step S8. Depositing metal on the front side of the chip so that the metal forms a metal silicide with silicon carbide. In the MOSFET structure area, the exposed NP region 7 and the surface of the first PP region 6a form a source ohmic contact alloy layer 12. In the JBS structure area, the exposed rectangular ring PP region and the surface of the N-type epitaxial layer 3 form a source Schottky contact alloy layer 13. Step S9. Deposit metal on the front side of the chip and selectively etch the metal through the seventh mask window to form source metal 11 and gate metal, and then deposit metal on the back side of the chip to form drain metal 1.

[0049] Example 6 Figure 17 3 is a schematic diagram of the top-down structure of the P-type body region 5, the parallel PP region 6b, and the vertical PP region 6c of this embodiment. Region 16 is a JBS structure, and the area outside region 16 is a MOSFET structure. The MOSFET structure is the same as that of Example 1. The difference between the JBS structure and Example 1 is that the rectangular circle PP region is a closed rectangular circle, and the rectangular circle PP region replaces a section of the P-type body region 5. The endpoints of the vertical PP region 6c are located at the boundary of the same P-type body region 5, and the vertical PP region 6c completely cuts off the P-type body region 5, so that one side of the parallel PP region 6b coincides with the boundary of the P-type body region 5. The interior of the rectangular circle PP region is the N-type epitaxial layer 3; and the second PP region 6d is not provided.

[0050] The manufacturing method of this embodiment is the same as that of embodiment 5.

[0051] Example 7 Figure 18 1 is a schematic diagram of the top-down structure of the P-type body region 5, the parallel PP region 6b, and the vertical PP region 6c of this embodiment. Region 16 is a JBS structure, and the region outside region 16 is a MOSFET structure. The MOSFET structure is the same as that of Example 1. The difference between the JBS structure and Example 1 is that the two ends of the vertical PP region 6c are located within two adjacent P-type body regions 5, so that the parallel PP region 6b is embedded in the P-type body region 5, and the P-type body region 5 is in a defective state; the interior of the rectangular circle PP region is the N-type epitaxial layer 3, and the second PP region 6d is not provided.

[0052] The manufacturing method of this embodiment is the same as that of embodiment 5.

[0053] When a traditional silicon carbide MOSFET chip enters the freewheeling state, the source metal 11 needs to reach above 3V, because 3V is the turn-on voltage of the silicon carbide PN diode. The present invention implants a JBS structure in the silicon carbide MOSFET chip, which can significantly reduce the freewheeling conduction voltage drop through the electron current when the source metal 11 is less than 3V, thereby reducing energy loss.

[0054] In addition, if Figure 2 As shown, since multiple JBS structures are evenly distributed on the surface of the silicon carbide MOSFET chip, there are multiple P-type body regions 5 between each JBS structure. When the source metal 11 is less than 3V, the electron current continues to flow. The electron current passes under the P-type body region 5, which will cause the potential under the P-type body region 5 to drop, thereby causing the potential of the P-type body region 5 relative to the N-type well region 4 to rise. The more P-type body regions 5 the electron current passes through, the higher the potential difference between the P-type body region 5 and the N-type well region 4. When the potential difference between the two reaches 3V, even if the source metal 11 is less than 3V, the body diode composed of the P-type body region 5 and the N-type well region 4 will turn on normally. The JBS structure of the present invention helps to turn on the body diode of the silicon carbide MOSFET. The freewheeling capability of the device is enhanced due to the addition of the body diode of the silicon carbide MOSFET. Therefore, the present invention can reduce the turn-on voltage of the silicon carbide diode and improve the freewheeling capability of the device.

[0055] The rectangular ring PP region of the present invention is a closed rectangular circle, and each right angle thereof is protected by the P-type body region 5, thereby ensuring the breakdown voltage of the device. The N-type well region 4 is not provided in the JBS structure, thereby reducing the leakage current of the device and ensuring that the breakdown voltage of the JBS structure is not lower than that of the silicon carbide MOSFET structure. Since the parallel PP region 6b, the vertical PP region 6c and the second PP region 6d in the JBS structure of the present invention are injected synchronously with the first PP region 6a, a mask window is saved. Moreover, since the parallel PP region 6b, the vertical PP region 6c and the second PP region 6d are heavily P-type doped, the widths of the above three regions can be extremely small, thereby increasing the cell density and improving the freewheeling capability of the JBS structure.

[0056] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A silicon carbide MOSFET device with improved freewheeling capability, characterized in that: It includes a MOSFET structure and a plurality of JBS structures integrated in the MOSFET structure; The MOSFET structure comprises a drain metal (1), an N-type substrate layer (2), an N-type epitaxial layer (3), a source ohmic contact alloy layer (12), and a source metal (11) arranged from bottom to top; An N-type well region (4) is provided on the top surface of the N-type epitaxial layer (3), a plurality of P-type body regions (5) are provided on the top surface of the N-type well region (4) at intervals, and the P-type body regions (5) extend downward from the top surface of the N-type epitaxial layer (3) and are parallel to each other; The JBS structure comprises a drain metal (1), an N-type substrate layer (2), an N-type epitaxial layer (3), a source Schottky contact alloy layer (13), and a source metal (11) arranged from bottom to top; A rectangular ring PP region is provided on the top surface of the N-type epitaxial layer (3) of the JBS structure. The rectangular ring PP region is a rectangle formed by two parallel PP regions (6b) and two vertical PP regions (6c). The endpoints of the vertical PP regions (6c) are located within the P-type body region (5) or on both side boundaries of the P-type body region (5).

2. The silicon carbide MOSFET device with improved freewheeling capability according to claim 1, characterized in that: In the MOSFET structure, a NP region (7) and a first PP region (6a) are provided downwardly from the top surface of the P-type body region (5), and are connected to each other. A distance is provided between the NP region (7) and the bottom surface of the P-type body region (5), and a distance is provided between the first PP region (6a) and the bottom surface of the P-type body region (5). A gate oxide layer (8), a polysilicon layer (9) and an insulating dielectric layer (10) are stacked from bottom to top between the source metal (11) and the N-type epitaxial layer (3); the bottom surface of the gate oxide layer (8) is connected to the N-type well region (4), the P-type body region (5) and the NP region (7), respectively; and the insulating dielectric layer (10) is extended downward from the side of the polysilicon layer (9) and is connected to the NP region (7); A first through hole (14) is provided between adjacent insulating dielectric layers (10); a source ohmic contact alloy layer (12) is provided at the bottom of the first through hole (14); the source metal (11) is connected to the source ohmic contact alloy layer (12) through the first through hole (14); and the source ohmic contact alloy layer (12) is connected to the NP region (7) and the first PP region (6a).

3. The silicon carbide MOSFET device with improved freewheeling capability according to claim 1, wherein: The parallel PP region (6b) is parallel to the extension direction of the P-type body region (5) on the horizontal plane, the vertical PP region (6c) is perpendicular to the extension direction of the P-type body region (5) on the horizontal plane, and the vertical PP region (6c) is connected to the P-type body region (5).

4. The silicon carbide MOSFET device with improved freewheeling capability according to claim 1, wherein: A second through hole (15) is provided above the N-type epitaxial layer (3) of the JBS structure, a source Schottky contact alloy layer (13) is provided at the bottom of the second through hole (15), the source metal (11) is connected to the source Schottky contact alloy layer (13) through the second through hole (15), and the source Schottky contact alloy layer (13) is connected to the rectangular ring PP region and the N-type epitaxial layer (3).

5. The silicon carbide MOSFET device with improved freewheeling capability according to claim 1, wherein: A plurality of second PP regions (6d) are provided on the top surface of the N-type epitaxial layer (3) of the JBS structure. The second PP regions (6d) are provided in the rectangular ring PP region. Both ends of the second PP regions (6d) are connected to the rectangular ring PP region. The interval between adjacent second PP regions (6d) is the N-type epitaxial layer (3) of the JBS structure.

6. The silicon carbide MOSFET device with improved freewheeling capability according to claim 5, characterized in that: The plurality of second PP regions (6d) are distributed in a spaced block or strip shape.

7. The silicon carbide MOSFET device with improved freewheeling capability according to claim 5, characterized in that: The first PP region (6a), the rectangular ring PP region and the second PP region (6d) are heavily P-type doped.

8. A method for manufacturing a silicon carbide MOSFET device with improved freewheeling capability according to any one of claims 1 to 4, characterized in that: The following steps are involved: Step S1. epitaxially growing an N-type epitaxial layer (3) on the N-type substrate layer (2), wherein the side of the N-type epitaxial layer (3) away from the N-type substrate layer (2) is the front side of the chip; Step S2. depositing a first barrier layer (17) on the front surface of the chip, etching a P-type body region (5) injection window on the first barrier layer (17) through a first mask window, and injecting P-type impurities to form a P-type body region (5); Step S3. depositing a second barrier layer (18) on the front surface of the chip, and etching away a predetermined thickness of barrier layer material on the second barrier layer (18) through a second mask window to form an injection window for the NP region (7), and then injecting N-type impurities to form the NP region (7); Step S4. removing the barrier layer material on the front side of the chip, then depositing a third barrier layer (19) on the front side of the chip, etching an injection window for the N-type well region (4) through a third mask window, and injecting N-type impurities to form the N-type well region (4); Step S5. removing the barrier layer material on the front side of the chip, then depositing a fourth barrier layer (20) on the front side of the chip, and etching the first PP region (6a) and the rectangular ring PP region injection window through the fourth mask window, and injecting P-type impurities to form the first PP region (6a) and the rectangular ring PP region; Step S6. Remove the barrier layer material on the front side of the chip, then grow a gate oxide layer (8) on the front side of the chip, and deposit polysilicon to form a polysilicon layer (9), and etch away the excess gate oxide layer (8) and polysilicon layer (9) through the fifth mask window, exposing the surfaces of the NP region (7) and the first PP region (6a) in the MOSFET structure region, and exposing the rectangular ring PP region and the N-type epitaxial layer (3) in the JBS structure region; Step S7. Depositing an insulating dielectric on the front side of the chip to form an insulating dielectric layer (10), and then selectively etching a first through hole (14) in the MOSFET structure region and a second through hole (15) in the JBS structure region on the insulating dielectric layer (10) through a sixth mask window, exposing the surfaces of the NP region (7) and the first PP region (6a) in the MOSFET structure region, and exposing the rectangular ring PP region and the N-type epitaxial layer (3) in the JBS structure region; Step S8. Depositing metal on the front side of the chip, and forming a metal silicide with the metal and silicon carbide. In the MOSFET structure area, the exposed NP area (7) and the surface of the first PP area (6a) form a source ohmic contact alloy layer (12). In the JBS structure area, the exposed rectangular ring PP area and the surface of the N-type epitaxial layer (3) form a source Schottky contact alloy layer (13). Step S9: Deposit metal on the front side of the chip and selectively etch the metal through the seventh mask window to form source metal (11) and gate metal, and finally deposit metal on the back side of the chip to form drain metal (1).

9. A method for manufacturing a silicon carbide MOSFET device with improved freewheeling capability according to any one of claims 5 to 7, characterized in that: The following steps are involved: Step S1. epitaxially growing an N-type epitaxial layer (3) on the N-type substrate layer (2), wherein the side of the N-type epitaxial layer (3) away from the N-type substrate layer (2) is the front side of the chip; Step S2. depositing a first barrier layer (17) on the front surface of the chip, etching a P-type body region (5) injection window on the first barrier layer (17) through a first mask window, and injecting P-type impurities to form a P-type body region (5); Step S3. depositing a second barrier layer (18) on the front surface of the chip, and etching away a predetermined thickness of barrier layer material on the second barrier layer (18) through a second mask window to form an injection window for the NP region (7), and then injecting N-type impurities to form the NP region (7); Step S4. removing the barrier layer material on the front side of the chip, then depositing a third barrier layer (19) on the front side of the chip, etching an injection window for the N-type well region (4) in the MOSFET structure region through a third mask window, and injecting N-type impurities to form the N-type well region (4); Step S5. removing the barrier layer material on the front side of the chip, then depositing a fourth barrier layer (20) on the front side of the chip, etching the first PP region (6a), the rectangular PP region, and the second PP region (6d) injection windows in the MOSFET structure region through the fourth mask window, and injecting P-type impurities to form the first PP region (6a), the rectangular PP region, and the second PP region (6d); Step S6. Remove the barrier layer material on the front side of the chip, then grow a gate oxide layer (8) on the front side of the chip, and deposit polysilicon to form a polysilicon layer (9), and etch away the excess gate oxide layer (8) and polysilicon layer (9) through the fifth mask window, exposing the surfaces of the NP region (7) and the first PP region (6a) in the MOSFET structure region, and exposing the rectangular ring PP region, the second PP region (6d) and the N-type epitaxial layer (3) in the JBS structure region; Step S7. Depositing an insulating dielectric on the front side of the chip to form an insulating dielectric layer (10), and then selectively etching a through hole (14) in the MOSFET structure region and a through hole (15) in the JBS structure region on the insulating dielectric layer (10) through a sixth mask window, exposing the surfaces of the NP region (7) and the first PP region (6a) in the MOSFET structure region, and exposing the rectangular ring PP region, the second PP region (6d) and the N-type epitaxial layer (3) in the JBS structure region; Step S8. Depositing metal on the front side of the chip, and forming a metal silicide with the metal and silicon carbide; in the MOSFET structure region, the exposed NP region (7) and the surface of the first PP region (6a) form a source ohmic contact alloy layer (12); in the JBS structure region, the exposed rectangular ring PP region, the second PP region (6d) and the surface of the N-type epitaxial layer (3) form a source Schottky contact alloy layer (13); Step S9: Deposit metal on the front side of the chip and selectively etch the metal through the seventh mask window to form source metal (11) and gate metal, and finally deposit metal on the back side of the chip to form drain metal (1).

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