Transistor device and manufacturing method thereof

Abstract

The invention provides a transistor device and a manufacturing method thereof. The transistor device includes a first semiconductor fin and a second semiconductor fin; the isolation structure is located between the first semiconductor fin and the second semiconductor fin, and the isolation structure comprises an internal shallow trench isolation region; a first liner layer along a sidewall and a bottom surface of the internal shallow trench isolation region; and a shallow trench isolation hard mask on a top surface of the internal shallow trench isolation region. The shallow trench isolation hard mask and the first liner layer each include a higher concentration of nitrogen than the internal shallow trench isolation region.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a transistor device and a method of manufacturing the transistor device. Background Art

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit elements and components thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed. Summary of the Invention

[0004] In some embodiments, a transistor device includes a first semiconductor fin, a second semiconductor fin, an isolation structure, a hard mask structure, a plurality of nanostructures, and a gate structure. The isolation structure is located between the first semiconductor fin and the second semiconductor fin. The hard mask structure is located above the isolation structure, wherein the hard mask structure includes a semiconductor hard mask covering the isolation structure. The nanostructure is located above the first semiconductor fin. The gate structure is located above the hard mask structure and the first semiconductor fin, wherein the gate structure surrounds each of the plurality of nanostructures.

[0005] In some embodiments, a transistor device includes a semiconductor fin, a plurality of nanostructures, a first source / drain region, a second source / drain region, a shallow trench isolation region, a first hard mask, a second hard mask, and a gate structure. The nanostructure is located above the semiconductor fin. The first source / drain region and the second source / drain region are located in the semiconductor fin, and the nanostructure extends between the first source / drain region and the second source / drain region. A shallow trench isolation region is located along a sidewall of the semiconductor fin. A first hard mask is located above the shallow trench isolation region, wherein the first hard mask comprises an insulating material. A second hard mask is located above the first hard mask, wherein the second hard mask comprises a semiconductor material. A gate structure surrounds the nanostructure, and the gate structure overlaps a first portion of the second hard mask.

[0006] In some embodiments, a method for fabricating a transistor device includes the following steps: etching a trench in a substrate to define a first semiconductor fin and a second semiconductor fin, the trench being disposed between the first semiconductor fin and the second semiconductor fin; forming a shallow trench isolation region in the trench; forming a first hard mask over the shallow trench isolation region; forming a second hard mask over the first hard mask, the second hard mask comprising a semiconductor material; and forming a gate structure over and along sidewalls of the first semiconductor fin, wherein the gate structure covers at least a portion of the second hard mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of some embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In practice, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a nanostructure field-effect transistor (nano-FET) according to some embodiments is illustrated in a three-dimensional view;

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 18A 、 Figure 18B 、 Figure 18C 、 Figure 18D 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 22A 、 Figure 22B 、 Figure 23A 、 Figure 23B 、 Figure 23C 、 Figure 24A 、 Figure 24B 、 Figure 24C 、 Figure 25A 、 Figure 25B and Figure 25C various views illustrating intermediate steps in fabricating a nano-FET transistor according to some embodiments;

[0010] Figure 26A 、 Figure 26B and Figure 26C A cross-sectional view illustrating a nano-FET transistor according to some embodiments is shown.

[0011]

Explanation of symbols

[0012] 20: Divider

[0013] 50:Substrate

[0014] 50N: n-type region

[0015] 50P: p-type region

[0016] 51, 51A-C: first semiconductor layer

[0017] 52, 52A-52C: first nanostructure

[0018] 53, 53A-C: second semiconductor layer

[0019] 54, 55: Nanostructure

[0020] 54A-54C: Second nanostructure

[0021] 56:Hard Mask

[0022] 58: Groove

[0023] 60: Protective pad

[0024] 62: Mask layer

[0025] 64: Multi-layer stacking

[0026] 66: Fin

[0027] 67: Arrow

[0028] 68: Isolation Structure

[0029] 69A: First liner material

[0030] 69A-B, 69B-B: bottom part

[0031] 69A-U, 69B-U: Upper part

[0032] 69A-S, 69B-S: Side wall

[0033] 69B: Secondary liner material

[0034] 70:Hard mask structure

[0035] 70A: First hard mask

[0036] 70B: Second hard mask

[0037] 71: dummy gate dielectric layer

[0038] 72: Sacrificial Materials

[0039] 76: dummy gate

[0040] 78:Mask

[0041] 81: Gate spacer

[0042] 83: Fin spacer

[0043] 86: Groove

[0044] 90: Internal spacer

[0045] 92: epitaxial source / drain region

[0046] 92A: first semiconductor material layer

[0047] 92B: second semiconductor material layer

[0048] 92C: third semiconductor material layer

[0049] 94: Contact etch stop layer

[0050] 96: first interlayer dielectric layer

[0051] 98: Second groove

[0052] 100: gate dielectric layer

[0053] 102: Gate electrode

[0054] 104: Gate mask

[0055] 106: Second interlayer dielectric layer

[0056] 108: The third groove

[0057] 110: Silicide region

[0058] 112, 114: Contact

[0059] A-A', B-B', C-C': cross section

[0060] T1, T2, T3, T4, T5, T6, T7, T8, T9, T10: thickness DETAILED DESCRIPTION

[0061] The following disclosure provides many different embodiments or examples for implementing the different features of some embodiments of the present disclosure. Specific examples of components and configurations are described below to simplify some embodiments of the present disclosure. Of course, these specific examples are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, some embodiments of the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0062] Additionally, for ease of description, some embodiments of the present disclosure may use spatially relative terms (such as "below," "beneath," "bottom," "above," "upper," and the like) to describe the relationship of one component or feature to another component or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in some embodiments of the present disclosure should be interpreted accordingly.

[0063] In various embodiments, isolation regions (e.g., shallow trench isolation (STI) regions) are formed between and around the fins of transistors to provide isolation between the various active regions of the transistors and to isolate the transistors from other transistors in the integrated circuit die. A hard mask layer can be formed on the top surface of the isolation regions to reduce loss of the isolation regions during subsequent cleaning and / or etching processes performed to fabricate the transistors. The hard mask layer can include a nitride hard mask and a silicon hard mask over the nitride hard mask. Due to the high etch selectivity of the silicon hard mask compared to even a nitride hard mask, the silicon hard mask can provide additional protection during subsequent processing steps (e.g., etching steps). Thus, the combined thickness of the hard mask layers can be kept relatively low while still providing adequate protection for the underlying isolation regions and reducing parasitic capacitance caused by an overly thick hard mask layer. A thinner hard mask layer further reduces the risk of inadvertently covering the transistor's nanostructures and hindering transistor performance. As a result, manufacturing defects can be reduced, and the electrical performance of the resulting device can be improved.

[0064] Embodiments are described below in the specific context of dies including nano-FETs. However, various embodiments may be applied to dies including other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) in place of or in combination with nano-FETs.

[0065] Figure 1 An example of a nano-FET (e.g., a nanowire FET, a nanosheet FET (Nano-FET), or the like) according to some embodiments is illustrated in a three-dimensional view. For ease of illustration, Figure 1 Some features are simplified and / or omitted. The nano-FET includes a nanostructure 54 (e.g., a nanosheet, a nanowire, or the like) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 54 serves as a channel region of the nano-FET. The nanostructure 54 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation structure 68 (also referred to as an STI structure or an STI region) is disposed between adjacent fins 66, and the fins 66 may protrude above or between adjacent isolation structures 68. A hard mask structure 70 is formed on the top surface of the isolation structure 68. Figure 1 , the hard mask structure 70 is illustrated as a single layer. However, as will be described in subsequent paragraphs, in various embodiments, the hard mask structure 70 is a multi-layer structure including, for example, a nitride hard mask and a silicon hard mask over the nitride hard mask. Although the isolation structure 68 and the hard mask structure 70 are described / illustrated as separate from the substrate 50, as used in some embodiments of the present disclosure, the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate with the isolation region and / or the hard mask structure 70. Furthermore, although the bottom portion of the fin 66 is described as being a single, continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In some embodiments of the present disclosure, the fin 66 refers to the portion extending between adjacent isolation structures 68.

[0066] A gate dielectric layer 100 is located over the top surface of the fin 66 and along the top surface, sidewalls, and bottom surface of the nanostructure 54. A gate electrode 102 is located over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. The epitaxial source / drain regions 92 may be referred to as a source or a drain, individually or collectively, depending on the context.

[0067] Figure 1The reference cross sections used in the following figures are further described. Cross section AA' is along the longitudinal axis of the gate electrode 102 and in a direction perpendicular to, for example, the direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of the fin 66 of the nano-FET and in a direction of current flow between, for example, the epitaxial source / drain regions 92 of the nano-FET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nano-FET. For clarity, the subsequent figures refer to these reference cross sections.

[0068] Some embodiments of the present disclosure are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects for use in planar devices such as planar FETs or fin field-effect transistors (FinFETs).

[0069] Figures 2 to 25C is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some embodiments. Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 21A 、 Figure 22A 、 Figure 23A 、 Figure 24A and Figure 25A illustrate Figure 1 Reference section AA' is illustrated. Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B 、 Figure 20B 、 Figure 21B 、 Figure 22B 、 Figure 23B 、 Figure 24B and Figure 25B illustrate Figure 1Reference section BB' is illustrated. Figure 15C 、 Figure 17C 、 Figure 18C 、 Figure 18D 、 Figure 21C 、 Figure 23C 、 Figure 24C and Figure 25C illustrate Figure 1 Reference section CC' is illustrated.

[0070] exist Figure 2 In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide; or a combination thereof.

[0071] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nano-FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nano-FET. The n-type region 50N can be physically separated from the p-type region 50P (as illustrated by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P can be provided. Unless otherwise noted, subsequent figures describe processing steps that can be performed in either the n-type region 50N or the p-type region 50P.

[0072] In addition, Figure 2In the embodiment of the present invention, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustration purposes, and as discussed in more detail below, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form the channel region of the nano-FET in both the n-type region 50N and the p-type region 50P. However, in some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form the channel region of the nano-FET in both the n-type region 50N and the p-type region 50P. For example, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously.

[0073] In other embodiments, the first semiconductor layer 51 can be removed, and the second semiconductor layer 53 can be patterned to form a channel region of the nano-FET in the p-type region 50P, and the second semiconductor layer 53 can be removed, and the first semiconductor layer 51 can be patterned to form a channel region of the nano-FET in the n-type region 50N. In still other embodiments, the first semiconductor layer 51 can be removed, and the second semiconductor layer 53 can be patterned to form a channel region of the nano-FET in the n-type region 50N, and the second semiconductor layer 53 can be removed, and the first semiconductor layer 51 can be patterned to form a channel region of the nano-FET in the p-type region 50P. In such embodiments, the channel region of the n-type region 50N can have a different material composition than the channel region of the p-type region 50P. The first semiconductor layer 51 and the second semiconductor layer 53 can be selectively removed from each of the n-type region 50N and the p-type region 50P by additional masking and etching steps. For example, the channel region of the n-type region 50N may be a silicon channel region, and the channel region of the p-type region 50P may be a silicon germanium channel region.

[0074] For illustrative purposes, the multilayer stack 64 is illustrated as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the layers of the multilayer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.

[0075] In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material such as silicon germanium or the like, and the second semiconductor layer 53 may be formed of a second semiconductor material such as silicon, silicon carbon or the like. The first semiconductor material and the second semiconductor material may be materials having high etching selectivity to each other. As such, the first semiconductor layer 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nano-FET.

[0076] Now refer to Figure 3 According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches 58 in multilayer stack 64 and substrate 50. The etching process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching process can be anisotropic. During the etching process, a hard mask 56 can be used to define the pattern of fins 66 and nanostructures 55. Hard mask 56 can include any suitable insulating material, such as oxide, nitride, oxynitride, oxycarbonitride, or the like. In some embodiments (not separately illustrated), hard mask 56 can be a multilayer structure. Hard mask 56 can be formed over nanostructures 55 using an acceptable process, such as thermal oxidation, physical vapor deposition (PVD), CVD, ALD, a combination thereof, or the like.

[0077] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more lithography processes including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography with self-alignment processes, allowing the creation of patterns having a pitch smaller than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66 and nanostructures 55.

[0078] By etching the multilayer stack 64 to form the nanostructure 55, first nanostructures 52A-52C (collectively referred to as first nanostructures 52) can be further defined based on the first semiconductor layer 51, and second nanostructures 54A-54C (collectively referred to as second nanostructures 54) can be defined based on the second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can be further collectively referred to as nanostructure 55.

[0079] For illustrative purposes, Figure 3 The fins 66 are shown to have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N can be greater or less than the width of the fins 66 in the p-type region 50P. Figure 3 Each of the fins 66 and nanostructures 55 is described as having a uniform width throughout some embodiments of the present disclosure. However, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or nanostructures 55 continuously increases in a direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal. Furthermore, the bottom surface of the trenches 58 between the fins 66 may be rounded and include concave and / or convex portions.

[0080] exist Figure 4 , an isolation structure 68 is formed in the trench 58 and adjacent to the fin 66. The isolation structure 68 can be formed by depositing a layer of insulating material over the substrate 50, the fin 66, the nanostructure 55, and the hard mask 56 and then patterning the insulating material layer under the nanostructure 55. Forming the isolation structure 68 can include depositing an insulating material over the substrate 50 and between the semiconductor fin 66 and the nanostructure 55. The insulating material can be an oxide, such as silicon oxide, nitride, the like, or a combination thereof, and can be formed using high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. Other insulating materials formed using any acceptable process can be used. The insulating material can be formed of a carbon-free dielectric material. In some embodiments, the insulating material includes silicon oxide formed using an FCVD process. Once the insulating material is formed, an annealing process can be performed. Although in Figure 3 While the insulating material is illustrated as a single layer in FIG. 5 , some embodiments may utilize multiple layers. For example, in some embodiments, one or more liners (not separately illustrated) may first be formed along the surfaces of substrate 50, semiconductor fins 66, and nanostructures 55. Thereafter, a filler material, such as one of the aforementioned insulating materials, may be formed over the liners.

[0081] An insulating material may be deposited over semiconductor fins 66 and nanostructures 55 such that excess insulating material covers nanostructures 55 and, optionally, hard mask 56. A removal process is then applied to the insulating material to remove excess insulating material over nanostructures 55. In some embodiments, a planarization process such as chemical mechanical polish (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes nanostructures 55 such that, after the planarization process is complete, the top surfaces of nanostructures 55 and the insulating material are substantially coplanar (within process variation). The planarization process may also remove hard mask 56. Alternatively, hard mask 56 may be removed in a separate etching process prior to depositing the insulating material.

[0082] After the planarization process, the insulating material is recessed to form isolation structures 68 (also known as isolation regions or shallow trench isolation (STI) regions). Isolation structures 68 are adjacent to semiconductor fins 66. Isolation structures 68 are recessed so that upper portions of semiconductor fins 66 and nanostructures 55 protrude from between adjacent isolation structures 68. Upper portions of semiconductor fins 66 and nanostructures 55 are located above isolation structures 68. Furthermore, the top surface of isolation structures 68 can have a flat surface as illustrated, a convex surface, a concave surface (such as a dished surface), or a combination thereof. The top surface of isolation structures 68 can be formed to be flat, convex, and / or concave using a suitable etch. Isolation structures 68 can be recessed using any acceptable etch process, such as an etch process that is selective to the material of the insulating material (e.g., selectively etches the isolation material of isolation structures 68 at a faster rate than the material of semiconductor fins 66 and nanostructures 55). For example, an oxide removal process using, for example, dilute hydrofluoric acid (dHF) can be used. In some embodiments, the etch is anisotropic.

[0083] exist Figure 5In the embodiment of the present invention, an optional protective liner 60 is deposited above and along the sidewalls of the nanostructures 55 and on the exposed upper sidewalls of the fins 66. In some embodiments, the protective liner 60 is formed by growing a silicon layer using an epitaxial process, such as CVD, ALD, VPE, MBE, or the like. In some embodiments, the protective liner 60 is selectively deposited on the semiconductor material of the nanostructures 55 and fins 66, while not depositing on the exposed surfaces of the isolation structures 68. The deposition process used to form the protective liner 60 can allow for the formation of a relatively high-quality material. For example, when the protective liner 60 is a silicon layer deposited using an ALD process, the protective liner 60 can have improved coverage and a higher crystallinity than the second nanostructure 54. The higher-quality material of the protective liner 60 can be more resistant to etching and reduce undesirable thinning of the second nanostructure 54 during subsequent processing steps. As a result, the protective liner 60 can allow for the formation of a higher-quality channel region in the resulting device. In some embodiments, the protective liner 60 can be omitted.

[0084] exist Figure 6 In the embodiment of the present invention, a first liner material 69A is deposited over and along the sidewalls of the nanostructures 55, on the upper sidewalls of the fins 66, and on the upper surface of the isolation structure 68. In embodiments where a protective liner 60 is present, the first liner material 69A can be deposited over the protective liner 60. The first liner material 69A can be a nitride layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbonitride layer, or the like. The nitrogen concentration of the first liner material 69A can be greater than the nitrogen concentration of the isolation structure 68. In some embodiments, the first liner material 69A has a nitrogen-to-silicon ratio in the range of 0.7 to 1.5. It has been observed that when the nitrogen-to-silicon ratio of the first liner material 69A is within the above range, it can provide sufficient protection for the underlying isolation structure 68 to prevent excessive isolation structure loss during subsequent process steps (e.g., subsequent etching steps). In some embodiments, the first liner material 69A has a carbon-to-silicon ratio of less than 0.1, and the first liner material 69A has an oxygen-to-silicon ratio of less than 0.1.

[0085] In some embodiments, the first liner material 69A is deposited using a non-conformal deposition process, such as a plasma enhanced chemical vapor deposition (PECVD) process or the like. The non-conformal deposition process can form the sidewall portion of the first liner material 69A to have a thickness T1 that is less than the thickness T2 of the lateral portion of the first liner material 69A. The non-conformal deposition process can facilitate patterning and selective removal of the sidewall portion of the first liner material 69A, as will be discussed in more detail later.

[0086] In some embodiments, the non-conformal deposition process is a PECVD process. The PECVD process can be performed at a temperature in the range of 400° C. to 500° C. During the PECVD process, a silicon-based precursor and H2 gas can be flowed into the chamber to form a silicon-based material layer (e.g., a silicon layer) above and along the sidewalls of the fins 66 and nanostructures 55. After or simultaneously with the deposition of the silicon-based material layer, a plasma treatment can be applied to treat the silicon-based material layer with nitrogen-containing radicals to form the first liner material 69A. As indicated by arrow 67, the plasma treatment can be applied in a direction substantially perpendicular to the top surface of the substrate 50. The directionality of the plasma treatment results in differences in thickness T1 and thickness T2, respectively, between the sidewall portion and the lateral portion of the first liner material 69A. Furthermore, the directionality of the plasma treatment can result in improved film quality (e.g., increased nitrogen uniformity) in the lateral portion of the first liner material 69A compared to the sidewall portion of the first liner material 69A.

[0087] exist Figure 7 and Figure 8 , removing the upper portion 69A-U of the first liner material 69A. The upper portion 69A-U of the first liner material 69A may include a lateral portion of the first liner material 69A disposed above the nanostructures 55. Removing the upper portion 69A-U of the first liner material 69A may include depositing a mask layer 62 over the first liner material 69A, such as Figure 7 As shown. Mask layer 62 may extend over nanostructures 55. In some embodiments, mask layer 62 is a backside anti-reflective coating (BARC) deposited using PVD or the like. In other embodiments, other materials and / or deposition processes are possible.

[0088] Later, in Figure 8 In the embodiment of the present invention, one or more etching processes may be performed to remove the upper portion 69A-U of the first liner material 69A. For example, an etch-back process may be applied to the mask layer 62 to expose the upper portion 69A-U of the first liner material 69A. The upper portion 69A-U of the first liner material 69A may then be etched away, for example, using an anisotropic etching process. The remaining portion of the mask layer 62 protects the sidewalls and bottom portion of the first liner material 69A while removing the upper portion 69A-U of the first liner material 69A. After removing the upper portion 69A-U, the remaining mask layer 62 may also be removed using a suitable etching and / or cleaning process. The resulting structure is Figure 9 Instructions.

[0089] exist Figure 10 In the side wall portion 69A-S (see Figure 9) are then removed from the sidewalls of the nanostructures 55 and fins 66, while bottom portions 69A-B remain on the top surface of the isolation structure 68. Removing sidewall portions 69A-S may include an etching process, such as an isotropic etching process. In some embodiments, the isotropic etching process is a wet etch using HPO3 or the like as an etchant. As described above, as a result of the non-conformal deposition process (e.g., PECVD) used to deposit the first liner material 69A, sidewall portions 69A-S are formed to be thinner than bottom portions 69A-B. The relatively thin sidewall portions 69A-S compared to bottom portions 69A-B allow sidewall portions 69A-S to be completely removed before bottom portions 69A-B are completely removed when the isotropic etching process is applied. As a result, the non-conformal deposition process described above allows first liner material 69A to be selectively etched away from the sidewalls of the nanostructures 55 and fins 66, while still leaving a bottom, lateral portion of first liner material 69A covering the isolation structure 68.

[0090] After removing the sidewall portions 69A-S, the remaining first liner material 69A may be referred to as a first hard mask 70A (also referred to as an isolation hard mask or STI hard mask). The first hard mask 70A is formed on the side surfaces of the trench 58 at the bottom above the protective liner 60 (if present) and the isolation structure 68. The first hard mask 70A may be formed to have a thickness T3 ranging from 1 nanometer (nm) to 10 nm to adequately protect the isolation structure 68 during subsequent fabrication processes. In addition, the top surface of the first hard mask 70A may be located below the top surface of the fin 66 and the bottommost nanostructure 55 (e.g., the first nanostructure 52A) so as not to interfere with the removal of the first nanostructure 52 in subsequent process steps.

[0091] exist Figure 11 In the embodiment of the present invention, second liner material 69B is deposited in trench 58 and above first hard mask 70A. Second liner material 69B may be deposited above the top surface of nanostructure 55, along the sidewalls of nanostructure 55, and above the upper surface of isolation structure 68. Relative to the same etching process, second liner material 69B may be formed from a material having a higher etch selectivity for isolation structure 68 than first hard mask 70A. In some embodiments, second liner material 69B is a semiconductor material. For example, when first hard mask 70A is made of a nitride material and isolation structure 68 is made of an oxide material, second liner material 69B may be made of silicon or the like.

[0092] The second liner material 69B can be formed by a non-conformal deposition process, such as an FCVD process. Once the second liner material 69B is formed, an annealing process can be performed. As a result of the FCVD process, the second liner material 69B may tend to accumulate on the side surfaces at the bottom of the trench 58, compared to the sidewalls or top surfaces of the nanostructures 55. For example, the thickness T4 of the second liner material 69B along the bottom surface of the trench 58 may be greater than the thickness T5 of the sidewall portion of the second liner material 69B and the thickness T6 of the second liner material 69B on the top surface of the nanostructures 55. In some embodiments, the thickness T6 of the second liner material 69B on the top surface of the nanostructures 55 may also be greater than the thickness T5 of the sidewall portion of the second liner material 69B. Furthermore, a non-conformal deposition process may deposit a material of lower quality than the material of the protective liner 60. For example, the second liner material 69B may have poorer coverage, particularly on the sidewalls and top surface of the nanostructures 55, and may have a lower degree of crystallinity than the protective liner 60. As a result, the second liner material 69B is more easily etched away in subsequent processes than the protection liner 60. In other embodiments, other non-conformal deposition processes, such as a PECVD process, may be used to deposit the second liner material 69B.

[0093] exist Figure 12 , the sidewall portion 69B-S and the upper portion 69B-U of the second liner material 69B are removed, while the bottom portion 69B-B of the second liner material 69B remains (see Figure 11). Similar to the first liner material 69A, the non-conformal deposition process allows for the selective removal of the sidewall portions 69B-S and upper portion 69B-U of the second liner material 69B without completely removing the bottom portion 69B-B of the second liner material 69B. Removing the sidewall portions 69B-S and upper portion 69B-U of the second liner material 69B may include an etching process, such as an isotropic etching process. In some embodiments, the isotropic etching process is a multi-stage process that includes exposing the second liner material 69B to a solution of hydrofluoric acid (HF) and ozonated deionized water (DIW), which may begin etching the second liner material 69B and further oxidize the second liner material 69B. The isotropic etching process may then continue by applying a standard clean 1 (SC1) process to remove the oxidized second liner material 69B. In other embodiments, other etchants or etching processes may be used. As described above, as a result of the non-conformal deposition process (e.g., FCVD) used to deposit the second liner material 69B, the sidewall portion 69B-S and upper portion 69B-U of the second liner material 69B are formed to be thinner than the bottom portion 69B-B of the second liner material 69B. The relatively thin sidewall portion 69B-S and upper portion 69B-U compared to the bottom portion 69B-B allow the sidewall portion 69B-S to be completely removed before the bottom portion 69B-B is completely removed when an isotropic etching process is applied. As a result, the non-conformal deposition process described above allows the second liner material 69B to be selectively etched away from the sidewalls and top surfaces of the nanostructures 55 and fins 66, while still leaving the bottom and lateral portions of the second liner material 69B to cover the isolation structures 68 and the first hard mask 70A.

[0094] Due to the improved film quality of the protective liner 60 compared to the second liner material 69B, the protective liner 60 is more etch-resistant than the second liner material 69B, even when the protective liner 60 and the second liner material 69B are made of similar materials (e.g., silicon). The difference in film quality can be attributed to the difference in the deposition processes used to form the protective liner 60 (e.g., ALD) and the second liner material 69B (e.g., FCVD). Various embodiments can remove the sidewall portion 69B-S of the second liner material 69B without removing the protective liner 60.

[0095] In some embodiments, etching the second liner material 69B may thin the bottom portion 69B-B of the second liner material 69B (e.g., reduce its thickness). For example, after etching, the bottom portion 69B-B of the second liner material 69B may have a thickness T6 that is less than the bottom portion 69B-B of the second liner material 69B before etching (see FIG. Figure 11 ) has a thickness T7. In some embodiments, the thickness T7 may be in a range of 1 nm to 10 nm.

[0096] After patterning the second liner material 69B, the remaining second liner material 69B can also be referred to as a second hard mask 70B (also referred to as an isolation hard mask or STI hard mask). The second hard mask 70B is formed on the side surfaces at the bottom of the trench 58 above the first hard mask 70A, the protective liner 60 (if present), and the isolation structure 68. The second liner material 69B can be thinned so that the top surface of the resulting second hard mask 70B is located below the bottommost surface of the nanostructure 55 (e.g., below the bottommost first nanostructure 52A). As a result, the nanostructure 55 is fully exposed to subsequent processing steps, allowing various isolation hard masks (e.g., the first hard mask 70A and the second hard mask 70B) to be smoothly integrated into the transistor fabrication process. The second hard mask 70B has a thickness of 1 nm to 10 nm. Forming the second hard mask 70B with a thickness within this range has advantages. For example, when the thickness of the second hard mask 70B is less than 1 nm, it may not adequately protect the underlying first hard mask 70A and isolation structure 68 during subsequent processing. Furthermore, when the thickness of the second hard mask 70B is greater than 10 nm, it may interfere with subsequent processing steps (e.g., by covering one or more of the nanostructures 55). Furthermore, when the thickness of the second hard mask 70B is greater than 10 nm, the parasitic capacitance in the resulting transistor device due to the semiconductor material of the second hard mask 70B may be unacceptably high.

[0097] Thus, a hard mask structure 70 is formed. The isolation hard mask structure 70 has a multi-layer structure including a first hard mask 70A (e.g., nitride) and a second hard mask 70B (e.g., a silicon hard mask). In some embodiments, upon exposure of the second hard mask 70B to ambient oxygen, a native oxide may form in an upper region of the second hard mask 70B. Various embodiments contemplate that the second hard mask 70B comprises this native oxide layer. The hard mask structure 70 protects the underlying isolation structure 68 during subsequent processing steps (e.g., subsequent etching and / or cleaning processes). In some embodiments, the isolation hard mask structure 70 has a thickness T8, which is the combined thickness of the first hard mask 70A's thickness T3 and the second hard mask 70B's thickness T7. In various embodiments, by including the second hard mask 70B above the first hard mask 70A, the overall thickness of the hard mask structure 70 can be maintained at an acceptably low value, thereby not hindering subsequent fabrication steps by, for example, covering the sidewalls of the bottom nanostructures 55. Furthermore, by including a combination of materials in the first hard mask 70A and the second hard mask 70B, parasitic capacitance in the resulting device can be reduced.

[0098] The materials of the first hard mask 70A and the second hard mask 70B can be selected to have a high etch selectivity to the material of the isolation structure 68 relative to the same etching process. For example, the materials of the first hard mask 70A and the second hard mask 70B can be selected to be resistant to an etchant that etches the material of the isolation structure 68, and one or more etchants can etch the materials of the first hard mask 70A and the second hard mask 70B at a slower rate than the etchant etches the isolation structure 68. In some embodiments, the second hard mask 70B can have a greater etch selectivity to the isolation structure 68 than the first hard mask 70A relative to the same etching process. In some embodiments, the isolation structure 68 is an oxide layer, the first hard mask 70A includes a nitride material, and the second hard mask 70B is a semiconductor material (e.g., silicon). As a result, excessive loss of the isolation structure 68 can be avoided, manufacturing defects can be reduced, and device performance can be improved.

[0099] In addition, Figure 12 In the embodiment having different well types, appropriate wells (not separately described) may be formed in the fins 66 and / or nanostructures 55. In the embodiment having different well types, a photoresist or other mask (not separately described) may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the fins 66 and nanostructures 55 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, or the like implanted in the region, with the concentration of the n-type impurity being between about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0100] After or before implanting the p-type region 50P, a photoresist or other mask (not separately illustrated) is formed over the fins 66 and nanostructures 55 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, or the like implanted in the region, with the concentration of the p-type impurity being between about 10 13 atoms / cm 3 to about 10 14atoms / cm 3 After implantation, the photoresist may be removed, such as by an acceptable ashing process.

[0101] After implantation of n-type region 50N and p-type region 50P, an annealing step may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, although in-situ and implantation doping can be used together, the growth material of the epitaxial fin can be doped in-situ during growth, which can avoid implantation.

[0102] exist Figure 13A and Figure 13B In the embodiment of the present invention, a dummy gate is formed over and along the sidewalls of the nanostructure 55 and the fin 66. To form the dummy gate, first, a dummy dielectric layer is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed over the dummy dielectric layer, and a mask layer is formed over the dummy gate layer. The dummy gate layer can be deposited over the dummy dielectric layer and then planarized using, for example, CMP. A mask layer can be deposited over the dummy gate layer. The dummy gate layer can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer can be deposited using physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing a selected material. The dummy gate layer can be made of other materials that have high etch selectivity for etching the isolation region. The mask layer can include, for example, silicon nitride, silicon oxynitride, or the like.

[0103] Subsequently, the mask layer can be patterned using acceptable photolithography and etching techniques to form mask 78. The pattern of mask 78 can then be transferred to the dummy gate layer and the dummy dielectric layer to form dummy gate 76 and dummy gate dielectric layer 71, respectively. Dummy gate 76 covers the channel region of fin 66. The pattern of mask 78 can be used to physically separate each of dummy gates 76 from adjacent dummy gates 76. Dummy gates 76 can also have a length direction that is substantially perpendicular to the length direction of the corresponding fin 66. It should be noted that for illustrative purposes only, dummy gate dielectric layer 71 is shown as covering only fin 66 and nanostructure 55. In some embodiments, dummy gate dielectric layer 71 can be deposited such that dummy gate dielectric layer 71 covers isolation structure 68 and hard mask structure 70, such that dummy gate dielectric layer 71 extends between dummy gate 76 and isolation structure 68.

[0104] exist Figure 14A and Figure 14B In the embodiment of the present invention, gate spacers 81 are formed over nanostructures 55 and isolation structures 68 (e.g., over hard mask structure 70), over the exposed sidewalls of mask 78 (if present), dummy gate 76, and dummy gate dielectric layer 71. Gate spacers 81 can be formed by conformally forming one or more dielectric materials and then etching the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed using deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other insulating materials formed using any acceptable process can be used. Any acceptable etching process, such as dry etching, wet etching, the like, or a combination thereof, can be performed to pattern the dielectric material. The etching can be anisotropic. When etched, the dielectric material has portions remaining on the sidewalls of dummy gate 76 (thus forming gate spacers 81). As described in more detail subsequently, the dielectric material, when etched, may also have portions remaining on the sidewalls of the semiconductor fins 66 and / or nanostructures 55 (thus forming fin spacers 83, see Figure 15C After etching, the fin spacers 83 and / or the gate spacers 81 may have straight sidewalls (as illustrated) or may have curved sidewalls (not separately illustrated).

[0105] In addition, implantation for lightly doped source / drain (LDD) regions (not separately described) may be performed. The LDD implantation may be performed before forming the gate spacer 81. In embodiments having different device types, similar to the implantation for the aforementioned wells, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of an appropriate type (e.g., p-type) may be implanted into the semiconductor fins 66 and nanostructures 55 exposed in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of an appropriate type (e.g., n-type) may be implanted into the semiconductor fins 66 and nanostructures 55 exposed in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. The lightly doped source / drain regions may have a thickness between 10 15 atoms / cm 3 to 10 19 atoms / cm 3 Annealing can be used to repair implantation damage and activate implanted impurities.

[0106] It should be noted that the foregoing disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used, additional spacers may be formed and removed, and / or the like. Furthermore, different structures and steps may be used to form n-type devices and p-type devices.

[0107] According to some embodiments, Figures 15A to 15C In the embodiment, a first recess 86 is formed in the fin 66, the nanostructure 55 and the substrate 50. The epitaxial source / drain region will be subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and extend into the substrate 50. Figure 15CAs illustrated, the top surface of the hard mask structure 70 (e.g., the top surface of the second hard mask 70B) can be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 can be etched such that the bottom surface of the first recess 86 is disposed below the top surface of the hard mask structure 70, or the like. The first recess 86 can be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, or the like. During the etching process used to form the first recess 86, the gate spacers 81, the fin spacers 83, and the mask 78 mask portions of the fin 66, the nanostructure 55, and the substrate 50. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single etching process or multiple etching processes. After the first recess 86 reaches the desired depth, a timed etching process can be used to terminate the etching of the first recess 86.

[0108] exist Figure 16A and Figure 16B , the first nanostructure 52 is replaced with the sacrificial material 72. Replacing the first nanostructure 52 may include etching away the first nanostructure 52 using a suitable etching process, such as an isotropic etching process performed through the first recess 86. The etching process may be selective to the material of the first nanostructure 52 and remove the first nanostructure 52 without significantly removing the second nanostructure 54 or the semiconductor fin 66. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, the first nanostructure 52 may be removed using a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0109] Subsequently, a layer of sacrificial material is deposited in the recess 86 and the space where the first nanostructure 52 was removed. The layer of sacrificial material can be deposited using a conformal deposition process such as CVD, ALD, or the like. The layer of sacrificial material can include an insulating material such as silicon oxide (e.g., SiO2) or the like. The layer of sacrificial material can then be etched to form the sacrificial material 72. The etching can be isotropic or anisotropic. For example, the layer of sacrificial material can be etched using a wet etching process using diluted HF or the like as an etchant. In some embodiments, the etching is performed until the sidewalls of the sacrificial material 72 are recessed beyond the sidewalls of the nanostructure 54. Although the sidewalls of the sacrificial material 72 are Figure 16B The sidewalls are described as straight, but may be concave or convex (see, for example, Figure 17CDuring the etching of the sacrificial material layer, the hard mask structure 70 protects the isolation structure 68. In some embodiments, during the patterning of the sacrificial material layer, the material of the second hard mask 70B (e.g., silicon) is more etch-resistant (e.g., has a higher etch selectivity) than the material of the first hard mask 70A (e.g., nitride). As a result, by including the second hard mask 70B, improved protection of the underlying isolation structure 68 can be achieved without significantly increasing the overall thickness of the hard mask structure 70.

[0110] Replacing first nanostructure 52 can provide advantages. For example, during subsequent source / drain formation steps, one or more high-temperature processes can be performed, for example, to activate dopants in the source / drain regions. When the material of first nanostructure 52 (e.g., SiGe) is exposed to high temperatures, this can result in increased germanium intermixing and roughness at the interface between first nanostructure 52 and nanostructure 54. Such manufacturing defects can reduce the performance of the resulting transistor device. By replacing first nanostructure 52 with an insulating material before a high-temperature process (e.g., source / drain annealing), manufacturing defects can be reduced and device performance can be improved.

[0111] exist Figure 17A and Figure 17B In the embodiment, an inner spacer 90 is formed in the groove 86 on the sidewall of the sacrificial material 72. The inner spacer 90 can be formed by Figure 16A and Figure 16B An internal spacer layer (not separately illustrated) is deposited over the illustrated structure to form the structure. Internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in recess 86, and sacrificial material 72 will be replaced with the corresponding gate structure. Internal spacer 90 can also be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as the etching process used to form the gate structure.

[0112] The inner spacer layer can be deposited using a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer can include a material such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer can then be anisotropically etched to form the inner spacer 90. Although the outer sidewalls of the inner spacer 90 are illustrated as being flush with the sidewalls of the second nanostructure 54, the outer sidewalls of the inner spacer 90 can extend beyond the sidewalls of the second nanostructure 54 or be recessed from the sidewalls of the second nanostructure 54 (see, e.g., FIG. 1 ). Figure 17C ).

[0113] Furthermore, although the outer sidewalls of the inner partition 90 are Figure 17BAs shown in FIG as straight, the outer sidewalls of the inner spacer 90 can be concave or convex. As an example, Figure 17C The following embodiment is described: the sidewalls of the sacrificial material 72 are concave, the outer sidewalls of the inner spacer 90 are concave, and the inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. The inner spacer layer can be etched using an anisotropic etching process such as RIE, NBE, or the like.

[0114] exist 18A to 18D In the embodiment, the epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54 in the n-type region 50N and / or the first nanostructure 52 in the p-type region 50P, thereby improving performance. Figure 18B As illustrated in FIG, epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, gate spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the sacrificial material 72 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short to a subsequently formed gate of the resulting nano-FET.

[0115] Epitaxial source / drain regions 92 in n-type regions 50N, such as NMOS regions, can be formed by masking p-type regions 50P, such as PMOS regions. Epitaxial source / drain regions 92 are then epitaxially grown in first recesses 86 in n-type regions 50N. Epitaxial source / drain regions 92 can comprise any acceptable material suitable for n-type nano-FETs. For example, if second nanostructure 54 is silicon, epitaxial source / drain regions 92 in n-type regions 50N can comprise a material that imparts tensile strain on second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0116] Epitaxial source / drain regions 92 in p-type regions 50P, such as PMOS regions, can be formed by masking n-type regions 50N, such as NMOS regions. Epitaxial source / drain regions 92 are then epitaxially grown in first recesses 86 in p-type regions 50P. Epitaxial source / drain regions 92 can comprise any acceptable material suitable for use in p-type nano-FETs. For example, if second nanostructure 54 is silicon, epitaxial source / drain regions 92 in p-type regions 50P can comprise a material that imposes compressive strain on second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like.

[0117] The epitaxial source / drain regions 92, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a density of about 1x10 19 atoms / cm 3 With about 1x10 21 atoms / cm 3 The n-type and / or p-type impurities for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0118] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructure 55. In some embodiments, these facets result in the merging of adjacent epitaxial source / drain regions 92 of the same nano-FET, such as Figure 18C In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as shown in FIG. Figure 18D As described. Figure 18C and Figure 18D In the illustrated embodiment, the fin spacers 83 can be formed to the top surface of the hard mask structure 70, thereby blocking epitaxial growth. In some other embodiments, the fin spacers 83 can cover portions of the sidewalls of the nanostructures 55, further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the fin spacers 83 can be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the shallow trench isolation structure 68.

[0119] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0120] exist Figure 19A and Figure 19B In the embodiment, a first interlayer dielectric layer 96 is deposited on Figure 18A and Figure 18B . The first interlayer dielectric layer 96 may be formed of a dielectric material and may be deposited using any suitable method such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed using any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric layer 96 and the epitaxial source / drain regions 92, the mask 78, and the gate spacer 81. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD layer 96 .

[0121] After depositing the first interlayer dielectric layer 96, a planarization process, such as CMP, may be performed to make the top surface of the first interlayer dielectric layer 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the gate spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the gate spacer 81, and the first interlayer dielectric layer 96 are flush within a range of process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first interlayer dielectric layer 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first interlayer dielectric layer 96 flush with the top surfaces of the mask 78 and the gate spacer 81.

[0122] exist Figure 20A and Figure 20BIn one or more etching steps, dummy gate 76 and mask 78 (if present) are removed, forming second recesses 98. Portions of dummy gate dielectric layer 71 and portions of protective liner 60 within second recesses 98 may also be removed. In some embodiments, dummy gate 76 and dummy gate dielectric layer 71 are removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches dummy gate 76 at a faster rate than first interlayer dielectric layer 96 or gate spacers 81. Each second recess 98 exposes and / or overlies portions of nanostructure 55 that serve as channel regions in the subsequently completed nano-FET. The portions of nanostructure 55 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, dummy gate dielectric layer 71 may serve as an etch stop when etching dummy gate 76. The dummy gate dielectric layer 71 may then be removed after the dummy gate 76 is removed.

[0123] The portion of the protective liner 60 in the second recess 98 can then be removed. Removing the protective liner 60 can include any suitable etching process. The etching can be isotropic. In some embodiments, due to the similarity of the materials of the protective liner 60 and the second hard mask 70B, removing the protective liner 60 can include thinning the second hard mask 70B. However, because the protective liner 60 is formed thinner than the second hard mask 70B, the timing can be controlled so that the protective liner 60 is removed without completely removing the second hard mask 70B. In some embodiments, portions of the protective liner 60 remain on the sidewalls of the fin 66, such as portions of the protective liner 60 that are covered by the hard mask structure 70. In other embodiments, the protective liner 60 is completely removed, or even removed from the fin 66 (see, for example, FIG. 2 ). Figures 26A to 26C ).

[0124] exist Figures 21A to 21C , the sacrificial material 72 is removed, extending the second recess 98. Removing the sacrificial material 72 may include performing an isotropic etching process, such as a wet etch or the like, using an etchant that is selective to the material of the sacrificial material 72, while the second nanostructure 54, the substrate 50, and the hard mask structure 70 remain relatively unetched compared to the sacrificial material 72.

[0125] In various embodiments, due to the increased etch resistivity provided by the hard mask structure 70, and particularly the second hard mask 70B, the isolation structure 68 in both the n-type region 50N and the p-type region 50P remains relatively unetched, particularly during patterning and removal of the sacrificial material 72. For example, during the aforementioned process steps, the hard mask structure 70 may be exposed to one or more etchants that etch the isolation structure 68 at a greater rate than each of the first hard mask 70A and the second hard mask 70B. While the etchant may still reduce the overall thickness of the hard mask structure 70 (e.g., reduce the overall thickness of the second hard mask 70B), STI loss is maintained at an acceptably low level. For example, the thickness of the second hard mask 70B may be reduced from an original thickness T8 to a thickness T9 in the second recess 98. Due to the high etch selectivity provided by the material of the second hard mask 70B, loss of the hard mask structure 70 may be relatively minimal, thereby leaving sufficient isolation in the resulting transistor device and improving device performance. In some embodiments, for example, the original thickness T9 of the second hard mask 70B may be in the range of 1 nm to 10 nm, and the thickness T9 of the second hard mask 70B after additional processing may be less than 5 nm. Figure 21C As illustrated, during some of the above-described processes (e.g., during removal of the dummy gate 76, the dummy gate dielectric layer 71, and selection of the nanostructures 55), portions of the hard mask structure 70 may be covered by the contact etch stop layer 94 and the first interlayer dielectric layer 96. As such, these covered portions of the hard mask structure 70 directly underlying the first interlayer dielectric layer 96 may be etched less than the exposed portions of the hard mask structure 70 (see FIG. Figure 21A For example, the covered portion of the second hard mask 70B may have a thickness T9 that is different from (eg, greater than) the exposed portion of the second hard mask 70B (see Figure 21A ) thickness T10 (see Figure 21C In some embodiments, the thickness T10 may also be smaller than the original thickness T8.

[0126] exist Figure 22A and Figure 22B In the embodiment of the present invention, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first interlayer dielectric layer 96, the contact etch stop layer 94, the gate spacer 81, and the hard mask structure 70.

[0127] According to some embodiments, gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, gate dielectric layer 100 may include a silicon oxide layer and a metal oxide layer overlying the silicon oxide layer. In some embodiments, gate dielectric layer 100 includes a high-k dielectric material. In these embodiments, gate dielectric layer 100 may have a k value greater than approximately 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of gate dielectric layer 100 may be the same or different in n-type region 50N and p-type region 50P. Methods for forming gate dielectric layer 100 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

[0128] The gate electrodes 102 are deposited over the gate dielectric layer 100 and fill the remaining portion of the second recess 98. The gate electrodes 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although in Figure 22A and Figure 22B Although a single-layer gate electrode 102 is described in detail, the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers comprising the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructures 54 and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0129] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material. The formation of the gate electrode 102 can also occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed using different processes, such that the gate dielectric layer 100 can be made of different materials and / or have a different number of layers. Furthermore, the gate electrode 102 in each region can be formed using different processes, such that the gate dielectric layer 100 can be made of different materials and / or have a different number of layers. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0130] After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 102 material that are located above the top surface of the first interlayer dielectric layer 96. The remaining portions of the gate electrode 102 and the gate dielectric layer 100 material thus form a replacement gate structure for the resulting nano-FET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure."

[0131] exist Figures 23A to 23C In the embodiment of the present invention, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed so that a groove is formed directly above the gate structure and between the opposing portions of the gate spacer 81. A gate mask 104 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like) is filled in the groove, followed by a planarization process to remove excess portions of the dielectric material extending above the first interlayer dielectric layer 96. The gate contact (such as that described below with reference to FIG. 1 ) is subsequently formed. Figures 25A to 25C The gate contact 114 , discussed herein, penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102 .

[0132] like Figures 23A to 23C As further illustrated, a second interlayer dielectric layer 106 is deposited over the first interlayer dielectric layer 96 and the gate mask 104. In some embodiments, the second interlayer dielectric layer 106 is a flowable film formed using FCVD. In some embodiments, the second interlayer dielectric layer 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited using any suitable method such as CVD, PECVD, or the like.

[0133] exist Figures 24A to 24CIn the embodiment of the present invention, the second interlayer dielectric layer 106, the first interlayer dielectric layer 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a third recess 108 that exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process such as RIE, NBE, or the like. In some embodiments, the third recess 108 can be etched through the second interlayer dielectric layer 106 and the first interlayer dielectric layer 96 using a first etching process; etched through the gate mask 104 using a second etching process; and then etched through the contact etch stop layer 94 using a third etching process. A mask, such as a photoresist, can be formed and patterned over the second interlayer dielectric layer 106 to mask portions of the second interlayer dielectric layer 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the third recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with the epitaxial source / drain region 92 and / or the gate structure (e.g., at the same level, or at the same distance from the substrate), or lower than the epitaxial source / drain region 92 and / or the gate structure (e.g., closer to the substrate). Figure 24B The third recess 108 is illustrated as exposing the epitaxial source / drain regions 92 and the gate structure in the same cross-section, but in various embodiments, the epitaxial source / drain regions 92 and the gate structure may be exposed in different cross-sections to reduce the risk of subsequently formed contact shorts.

[0134] After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) that reacts with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof) over the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 110. Subsequently, unreacted portions of the deposited metal are removed, for example, using an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region or a silicon germanium region (e.g., a region including both silicide and germanide). In one embodiment, the silicide region 110 comprises TiSi and has a thickness ranging from approximately 2 nm to approximately 10 nm.

[0135] Next, in Figures 25A to 25CIn the third recess 108, contacts 112 and 114 (also referred to as contact plugs) are formed. Contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material and are electrically coupled to underlying conductive features (e.g., the gate electrode 102 and / or the silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate electrode 102 and may be referred to as a gate contact, and contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second interlayer dielectric layer 106.

[0136] Figures 26A to 26B Cross-sectional views illustrating devices according to some alternative embodiments. Figure 26A illustrate Figure 1 Reference section AA' is illustrated. Figure 26B illustrate Figure 1 Reference section BB' is illustrated. Figure 26C illustrate Figure 1 The reference section C-C' is shown. Figures 26A to 26C In the Figures 25A to 25C The same components are formed by the same process. For example, Figures 26A to 26C The structure includes a double-layer hard mask structure 70, which includes the first hard mask 70A and the second hard mask 70B as described above. Figures 26A to 26C In the embodiment shown in FIG5 , the protective liner 60 does not remain on the sidewalls of the fin 66, and the hard mask structure 70 may be in direct physical contact with the fin 66. For example, the protective liner 60 may not be formed, or the protective liner 60 may be completely removed during one or more of the removal steps described above (e.g., dummy gate removal).

[0137] In various embodiments, isolation regions are formed between and around the fins of the transistor to provide isolation between the various active regions of the transistor. A protective liner can be formed to cover the sidewalls, bottom surface, and top surface of the isolation region to reduce isolation loss during subsequent cleaning and / or etching processes in manufacturing the transistor. When the inner isolation region is made of oxide, the outer protective liner can be a nitride layer. In this way, the protective liner can provide etch selectivity for the encapsulated isolation region and reduce isolation loss (e.g., shallow trench isolation loss) during subsequently applied cleaning / etching processes. As a result, manufacturing defects can be reduced and the electrical performance of the resulting device can be improved.

[0138] In various embodiments, a hard mask layer can be formed on the top surface of the isolation region to reduce the loss of the isolation region during subsequent cleaning and / or etching processes performed to fabricate the transistor. The hard mask layer can include a nitride hard mask and a silicon hard mask over the nitride hard mask. Due to the high etch selectivity of the silicon hard mask compared to even the nitride hard mask, the silicon hard mask can provide additional protection during subsequent processing steps (e.g., etching steps). Thus, the combined thickness of the hard mask layers can be kept relatively low while still providing adequate protection for the underlying isolation region and reducing parasitic capacitance caused by an overly thick hard mask layer. A thinner hard mask layer further reduces the risk of inadvertently covering nanostructures in the transistor and hindering transistor performance. As a result, manufacturing defects can be reduced and the electrical performance of the resulting device can be improved.

[0139] In various embodiments, a transistor device includes a first semiconductor fin, a second semiconductor fin, an isolation structure, a hard mask structure, a plurality of nanostructures, and a gate structure. The isolation structure is located between the first semiconductor fin and the second semiconductor fin. The hard mask structure is located above the isolation structure, wherein the hard mask structure includes a semiconductor hard mask covering the isolation structure. The nanostructure is located above the first semiconductor fin. The gate structure is located above the hard mask structure and the first semiconductor fin, wherein the gate structure surrounds each of the plurality of nanostructures. Optionally, in some embodiments, the hard mask structure further includes a nitride hard mask located between the semiconductor hard mask and the isolation structure. Optionally, in some embodiments, the nitride hard mask has a nitrogen to silicon ratio in a range of 0.7 to 1.5. Optionally, in some embodiments, the semiconductor hard mask includes silicon. Optionally, in some embodiments, a top surface of the hard mask structure is lower than a bottom surface of the nanostructure. Optionally, in some embodiments, the semiconductor hard mask extends from the first semiconductor fin to the second semiconductor fin. Optionally, in some embodiments, the semiconductor hard mask includes a native oxide region at the top surface of the semiconductor hard mask.

[0140] In one embodiment, a transistor device includes a semiconductor fin, a plurality of nanostructures, a first source / drain region, a second source / drain region, a shallow trench isolation region, a first hard mask, a second hard mask, and a gate structure. The nanostructure is located above the semiconductor fin. The first source / drain region and the second source / drain region are located in the semiconductor fin, with the nanostructure extending between the first source / drain region and the second source / drain region. A shallow trench isolation region is located along the sidewalls of the semiconductor fin. A first hard mask is located above the shallow trench isolation region, wherein the first hard mask comprises an insulating material. A second hard mask is located above the first hard mask, wherein the second hard mask comprises a semiconductor material. A gate structure surrounds the nanostructure, with the gate structure overlapping a first portion of the second hard mask. Optionally, in some embodiments, the first hard mask comprises nitride, and the second hard mask comprises silicon. Optionally, in some embodiments, the nitrogen to silicon ratio of the first hard mask is in a range of 0.7 to 1.5. Optionally, in some embodiments, the transistor device further includes a dielectric layer surrounding the gate structure, the dielectric layer overlapping the second portion of the second hard mask. Optionally, in some embodiments, the first portion of the second hard mask has a first thickness, wherein the second portion of the second hard mask has a second thickness, and wherein the first thickness is less than the second thickness. Optionally, in some embodiments, the transistor device further includes a protective liner located between the first hard mask and the shallow trench isolation region, wherein the protective liner comprises a semiconductor material.

[0141] In one embodiment, a method for fabricating a transistor device includes the following steps: etching a trench in a substrate to define a first semiconductor fin and a second semiconductor fin, the trench being disposed between the first semiconductor fin and the second semiconductor fin; forming a shallow trench isolation region in the trench; forming a first hard mask over the shallow trench isolation region; forming a second hard mask over the first hard mask, the second hard mask comprising a semiconductor material; forming a gate structure over and along sidewalls of the first semiconductor fin, wherein the gate structure covers at least a portion of the second hard mask. Optionally, in some embodiments, the first hard mask comprises nitride and the second hard mask comprises silicon. Optionally, in some embodiments, the method further includes forming a protective liner over and along the sidewalls of the first semiconductor fin and the second semiconductor fin after forming the shallow trench isolation region and before forming the first hard mask. Optionally, in some embodiments, forming the second hard mask includes the following steps: depositing a second liner material over a top surface of the first semiconductor fin, over the sidewalls of the first semiconductor fin, and over a top surface of the first hard mask. and removing a first portion of a second liner material, the first portion of the second liner layer being disposed above a top surface of the first semiconductor fin. Removing a second portion of the second liner layer, the second portion of the second liner layer being disposed on a sidewall of the first semiconductor fin, wherein after removing the second portion of the second liner layer, a third portion of the second liner layer defines a second hard mask, the third portion of the second liner layer being disposed on a bottom surface of the trench. Optionally, in some embodiments, depositing the second liner material comprises a non-conformal deposition process, the non-conformal deposition process depositing the third portion of the second liner material to have a greater thickness than the first portion of the second liner material and the second portion of the second liner material, and wherein removing the first portion of the second liner material and removing the second portion of the second liner material comprise an isotropic etching process. Optionally, in some embodiments, depositing the second liner material comprises a flowable chemical vapor deposition process. Optionally, in some embodiments, the second hard mask has a thickness in a range from 1 nm to 10 nm.

[0142] The foregoing overview of the features of several embodiments is provided so that those skilled in the art can better understand the aspects of some embodiments of the present disclosure. Those skilled in the art should understand that they can easily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments introduced in some embodiments of the present disclosure. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of some embodiments of the present disclosure, and that those skilled in the art can make various changes, substitutions, and modifications without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A transistor device, characterized in that Include: a first semiconductor fin and a second semiconductor fin; an isolation structure located between the first semiconductor fin and the second semiconductor fin; a hard mask structure located above the isolation structure, wherein the hard mask structure comprises a semiconductor hard mask covering the isolation structure; a plurality of nanostructures located above the first semiconductor fin; and A gate structure is located above the hard mask structure and the first semiconductor fin, wherein the gate structure surrounds each of the plurality of nanostructures.

2. The transistor device according to claim 1, wherein The hard mask structure further includes a nitride hard mask located between the semiconductor hard mask and the isolation structure.

3. The transistor device according to claim 1, wherein A top surface of the hard mask structure is lower than a bottom surface of the plurality of nanostructures.

4. The transistor device according to claim 1, wherein The semiconductor hard mask extends from the first semiconductor fin to the second semiconductor fin.

5. The transistor device according to claim 1, wherein The semiconductor hard mask includes a native oxide region at a top surface of the semiconductor hard mask.

6. A transistor device, characterized in that Include: a semiconductor fin; a plurality of nanostructures located above the semiconductor fin; A first source / drain region and a second source / drain region are located in the semiconductor fin, and the plurality of nanostructures extend between the first source / drain region and the second source / drain region; a shallow trench isolation region along a sidewall of the semiconductor fin; a first hard mask located above the shallow trench isolation region, wherein the first hard mask comprises an insulating material; a second hard mask located above the first hard mask, wherein the second hard mask comprises a semiconductor material; and A gate structure surrounds the plurality of nanostructures, and the gate structure overlaps a first portion of the second hard mask.

7. The transistor device according to claim 6, wherein Further including: A dielectric layer surrounds the gate structure, the dielectric layer overlapping a second portion of the second hard mask.

8. The transistor device according to claim 7, wherein The first portion of the second hard mask has a first thickness, the second portion of the second hard mask has a second thickness, and the first thickness is less than the second thickness.

9. The transistor device according to claim 6, wherein Further including: A protection liner is located between the first hard mask and the shallow trench isolation region, wherein the protection liner comprises a semiconductor material.

10. A method for manufacturing a transistor device, characterized in that Include: Etching a trench in a substrate to define a first semiconductor fin and a second semiconductor fin, wherein the trench is disposed between the first semiconductor fin and the second semiconductor fin; forming a shallow trench isolation region in the trench; forming a first hard mask above the shallow trench isolation region; forming a second hard mask over the first hard mask, the second hard mask comprising a semiconductor material; and A gate structure is formed over and along the sidewalls of the first semiconductor fin, wherein the gate structure covers at least a portion of the second hard mask.

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