Grid-control multi-mode ferroelectric transistor device and preparation method thereof

Abstract

The invention discloses a grid-control multi-mode ferroelectric transistor device and a preparation method thereof, and belongs to the technical field of microelectronic materials and devices. The structure of the grid-control multi-mode ferroelectric transistor device comprises a grid electrode, a CuInP2S6 ferroelectric insulating layer, a hexagonal boron nitride dielectric layer, a stannous sulfide channel layer, a source electrode and a drain electrode on the stannous sulfide channel layer, and a substrate on the source electrode and the drain electrode which are arranged in sequence, the grid electrode, the source electrode and the drain electrode are all made of inert metal. The grid-control multi-mode ferroelectric transistor device provided by the invention can show different response behaviors to light with the same wavelength by changing the magnitude of the grid voltage, so that the simulation of controllable biological sensitivity and the simulation of adjustable biological accuracy are realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic materials and devices, and particularly relates to a gate-controlled multi-mode ferroelectric transistor device and a preparation method thereof. Background Art

[0002] Over the past few decades, ferroelectric materials with switchable macroscopic polarization have been developed for a wide range of technological applications, including non-volatile memory, logic, sensors, and actuators. Field-effect transistors (FeFETs) with ferroelectric gate dielectrics are considered an attractive architecture for existing semiconductor memory technologies due to their lossless and low-voltage operation, small cell size, and non-volatility. Traditional ferroelectric materials (such as PZT and BTO) are limited by their three-dimensional lattice structure and experience significant degradation of ferroelectricity when their thickness is reduced to the nanometer scale. However, the emerging two-dimensional van der Waals ferroelectric materials have thicknesses that can be easily controlled at the atomic level. Due to their unique ability to maintain ferroelectricity at atomic-level thicknesses, when combined with other two-dimensional thin layers such as metals, semiconductors, and insulators, they offer the possibility of application in ferroelectric transistor memories for long-term storage. The absence of dangling bonds on the surface of van der Waals ferroelectric materials and the ability of single-crystal van der Waals ferroelectric layers to maintain square ferroelectromagnetic hysteresis loops help eliminate retention losses caused by the depolarization field. The flexibility of the stacking process also helps design the desired device structure without mutual diffusion and constraint of lattice parameters, ensuring the feasibility of van der Waals heterojunction preparation. Summary of the Invention

[0003] The present invention aims to utilize the advantages of van der Waals ferroelectric semiconductors to solve the phenomenon that the ferroelectricity of traditional ferroelectrics is significantly degraded at nanometer scale, and proposes a gate-controlled multimodal ferroelectric transistor device and a preparation method thereof.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] One of the technical solutions of the present invention is to provide a gate-controlled multimodal ferroelectric transistor device, the structure of which includes: a gate, a CuInP2S6 (CIPS) ferroelectric insulating layer, a hexagonal boron nitride (h-BN) dielectric layer, a tin sulfide (SNS) channel layer, a source and a drain on the tin sulfide channel layer, and a substrate on the source and the drain; the materials of the gate, the source and the drain are all inert metals.

[0006] Optionally, the inert metal is gold.

[0007] Optionally, the substrate is made of silicon oxide.

[0008] Preferably, the thickness of the gate electrode is 20-30 nm; the thickness of the source electrode is 20-30 nm; and the thickness of the drain electrode is 20-30 nm.

[0009] Preferably, the thickness of the CuInP2S6 ferroelectric insulating layer is 70-80 nm.

[0010] Preferably, the thickness of the hexagonal boron nitride dielectric layer is 5-15 nm.

[0011] Preferably, the thickness of the tin sulfide channel layer is 20-30 nm.

[0012] A second technical solution of the present invention provides a method for preparing the above-mentioned gate-controlled multimodal ferroelectric transistor device, comprising the following steps:

[0013] First, a source and a drain are generated on the substrate, and then a tin sulfide channel layer is generated on the source and the drain. Then, a hexagonal boron nitride dielectric layer and a CuInP2S6 ferroelectric insulating layer are sequentially generated to form a van der Waals heterojunction, and finally a gate is generated; thus, the preparation of a gate-controlled multimodal ferroelectric transistor device is completed.

[0014] Preferably, the substrate is subjected to surface pretreatment before the source and drain are formed.

[0015] Preferably, the source electrode, the drain electrode and the gate electrode are formed by thermal evaporation.

[0016] Preferably, the step of generating the tin sulfide channel layer includes: mechanically exfoliating the two-dimensional tin sulfide, and transferring the two-dimensional tin sulfide to the source electrode and the drain electrode to obtain the tin sulfide channel layer.

[0017] Preferably, the step of generating the hexagonal boron nitride dielectric layer comprises: mechanically peeling off the two-dimensional hexagonal boron nitride, and transferring the two-dimensional hexagonal boron nitride onto the tin sulfide channel layer to obtain the hexagonal boron nitride dielectric layer.

[0018] Preferably, the step of generating the CuInP2S6 ferroelectric insulating layer comprises: mechanically peeling off the two-dimensional CuInP2S6 and transferring it onto the hexagonal boron nitride dielectric layer to obtain the CuInP2S6 ferroelectric insulating layer.

[0019] The two-dimensional tin sulfide, two-dimensional hexagonal boron nitride or two-dimensional CuInP2S6 obtained by mechanical exfoliation in the present invention is observed in color through an optical microscope. Combining the previously measured AFM data with the color correspondence, the two-dimensional nanosheets of corresponding thickness can be found.

[0020] The beneficial technical effects of the present invention are as follows:

[0021] The gate-controlled multimodal ferroelectric transistor device provided by this invention utilizes a novel two-dimensional ferroelectric material. This novel material allows for a simple device structure. During the fabrication of the two-dimensional van der Waals heterojunction, each layer maintains its lattice structure, avoiding the lattice mismatch problem encountered during epitaxial growth of traditional ferroelectrics. Each layer of the two-dimensional material has a clean surface and few dangling bonds, which limits defects and reduces the risk of breakdown in the heterostructured transistor. A tin sulfide channel layer, placed between the source and drain electrodes, is used for synaptic simulation.

[0022] The gate-controlled multimodal ferroelectric transistor device of the present invention can exhibit different responses to light of the same wavelength by varying the gate voltage, enabling simulation of controllable biological sensitivity and adjustable biological accuracy. This response to varying gate voltages not only improves the device's adaptability to complex environmental changes but also enables the system to possess dynamic balancing functions similar to biological vision, reducing energy consumption and computational redundancy, and optimizing power management and information processing capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of the structure of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 of the present invention; wherein 1 is a silicon oxide substrate, 2 is an inert metal source and an inert metal drain, 3 is an SNS channel layer, 4 is an h-BN dielectric layer, 5 is a CIPS ferroelectric insulating layer, and 6 is an inert metal gate.

[0024] Figure 2 Schematic diagram of the structure of the Au / CuInP2S6 / Au vertical structure memristor prepared in Example 2; wherein 1 is the gold bottom electrode, 2 is the ferroelectric functional layer CuInP2S6, and 3 is the gold top electrode.

[0025] Figure 3 This is the hysteresis loop of the CIPS ferroelectric insulating layer.

[0026] Figure 4 This is the transfer characteristic curve of the gate-controlled multi-mode ferroelectric transistor device prepared in Example 1.

[0027] Figure 5 This is the output characteristic curve of the gate-controlled multi-mode ferroelectric transistor device prepared in Example 1.

[0028] Figure 6 This is the current-time curve of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 after continuous ultraviolet light irradiation at a gate voltage of 0V.

[0029] Figure 7 The current-time curve of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 when two ultraviolet light pulses are applied at a gate voltage of 0 V.

[0030] Figure 8This is a simulated curve of the calculated value of the PPD behavior of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 and the interval time when two ultraviolet light pulses are applied at different intervals at a gate voltage of 0V.

[0031] Figure 9 This is a current-time curve of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 after continuous ultraviolet light irradiation at a gate voltage of -5V.

[0032] Figure 10 The current-time curve of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 under a gate voltage of -5 V and two ultraviolet light pulses applied thereto.

[0033] Figure 11 This is a simulated curve of the calculated value of the PPD behavior of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 and the interval time when two ultraviolet light pulses are applied at different intervals at a gate voltage of -5V. DETAILED DESCRIPTION

[0034] Various exemplary embodiments of the present invention are now described in detail. This detailed description should not be considered as a limitation of the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention. It should be understood that the terms used in the present invention are only for describing specific embodiments and are not intended to limit the present invention.

[0035] It should be pointed out that the matters not described in detail in the present invention are conventional operating means in this field and are not the focus of the present invention.

[0036] In addition, for numerical ranges in the present invention, it is understood that each intervening value between the upper and lower limits of the range is also specifically disclosed. Each smaller range between any stated value or stated range, and any other stated value or intervening value in the stated range, is also included in the present invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains. Although preferred methods and materials have been described herein, any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the present invention.

[0038] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0039] The schematic diagram of the structure of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 is shown in FIG. Figure 1; Among them, 1 is a silicon oxide substrate, 2 is an inert metal source and an inert metal drain, 3 is an SNS channel layer, 4 is an h-BN dielectric layer, 5 is a CIPS ferroelectric insulating layer, and 6 is an inert metal gate.

[0040] Example 1

[0041] Preparation of gate-controlled multimodal ferroelectric transistor devices:

[0042] Step 1: Use the purchased silicon oxide wafer as the substrate for pre-processing:

[0043] After laser collection and cutting, the silicon oxide substrates were ultrasonically cleaned in trichloroethylene, acetone, anhydrous ethanol, and deionized water for 10 minutes at 70W to remove oil and other impurities from the substrate surface. After cleaning, an air compressor was used to dry the surface of the silicon oxide substrate to facilitate subsequent processing.

[0044] Step 2: Use thermal evaporation process to grow inert metal source and drain electrodes:

[0045] First, a photoresist is spin-coated on a pre-treated silicon oxide substrate using a coating machine. The thickness of the photoresist is about 1.5 μm. Then, the electrode positions are marked on the wafer with the photoresist spin-coated using a direct write lithography machine. The wavelength of the ultraviolet light used for lithography is 390 nm and the power is 390 mW / cm 2 After the photolithography is completed, the substrate is placed in developer and deionized water in turn to reveal the photolithography pattern. Finally, the inert metal electrode is prepared by thermal evaporation coating machine. The thermal evaporation conditions are as follows: the chamber vacuum is greater than 3.0×10 -4 Pa; 0.1 g of gold wire (purity of 99.99%); heating current of 130 A; the remaining photoresist was washed away by acetone.

[0046] Step 3: Prepare the two-dimensional functional sheet:

[0047] After the SnS, h-BN, and CIPS bulk materials are transferred to the film in turn, they are folded in half several times to make the bulk materials evenly distributed on the blue film tape. Subsequently, transparent polydimethylsiloxane (PDMS) is pasted on the blue film tape several times, and the two-dimensional thin film to be transferred is found with the help of an optical microscope.

[0048] Step 3: Transferring the 2D functional sheet:

[0049] First, an optical microscope was used to locate the SnS layer on the PDMS and find the appropriate transfer location. The transfer stage was heated to 80°C, and a micromanipulator was used to press the PDMS film with the SnS flakes onto the appropriate click location. After peeling off the PDMS film, the SnS flakes were released and transferred to the source and drain electrodes. Next, h-BN and CIPS 2D flakes were transferred to the SnS using the same method.

[0050] Step 4: Prepare the inert gate electrode:

[0051] First, a photoresist is spin-coated on a clean silicon oxide substrate using a spin coater. The thickness of the photoresist is about 1.5 μm and the coating is placed on a hot plate at 95°C. Then, a direct write lithography machine is used to find the device position on the spun-coated substrate and mark it with the lithography machine. The wavelength of the ultraviolet light used in the lithography is 390 nm and the power is 390 mW / cm 2 After the photolithography is completed, the substrate is placed in the developer and deionized water in turn to make the photolithography pattern appear. Finally, the inert metal electrode is prepared by the thermal evaporation coating machine. The thermal evaporation conditions are as follows: the chamber vacuum is greater than 3.0×10 -4 Pa; 0.1 g of gold wire (purity 99.99%); a heating current of 130 A, and the remaining photoresist was washed away with acetone to produce a gate-controlled multimodal ferroelectric transistor device, wherein the thickness of the source electrode was 24 nm, the thickness of the drain electrode was 24 nm, the thickness of SnS was 26 nm, the thickness of h-BN was 14.5 nm, the thickness of CuInP2S6 was 72 nm, and the thickness of the gate was 26 nm.

[0052] Example 2

[0053] Preparation of Au / CuInP2S6 / Au vertical structure memristor:

[0054] Step 1: Grow the gold bottom electrode using thermal evaporation process:

[0055] First, a photoresist is spin-coated on a pre-treated silicon oxide substrate using a coating machine. The thickness of the photoresist is about 1.5 μm. Then, a direct write lithography machine is used to mark the position of the electrode on the silicon wafer with the photoresist spun on. The wavelength of the ultraviolet light used for lithography is 390 nm and the power is 390 mw / cm 2 After the photolithography is completed, the film is placed in AZ300 developer and deionized water in turn for 1 minute to make the photolithography pattern appear. Finally, the inert metal electrode is prepared by thermal evaporation coating machine. The thermal evaporation conditions are as follows: the chamber vacuum is greater than 3.0×10 -4 Pa; 0.1 g of gold wire (purity 99.99%); heating current 130 A. After metal plating, the remaining photoresist was promptly washed away with acetone.

[0056] Step 2: Prepare two-dimensional functional sheets

[0057] After the CIPS bulk material is transferred to the film in sequence, it is folded in half several times to make the bulk material evenly distributed on the blue film tape. Then, transparent polydimethylsiloxane (PDMS) is pasted on the blue film tape several times, and the CIPS two-dimensional thin film to be transferred is found with the help of an optical microscope.

[0058] Step 3: Transferring the 2D functional sheet

[0059] First, use an optical microscope to find the position of CIPS on PDMS and find a suitable transfer position. Heat the transfer table to 80°C and use a micromanipulator to imprint the PDMS film with the CIPS sheet to the marked electrode position. Wait for 10 minutes. After the sample falls, slowly lift the PDMS glue to prevent the sample sheet from being lifted up along with the PDMS.

[0060] Step 4: Prepare the gold top electrode:

[0061] First, a photoresist is spin-coated on a clean silicon oxide substrate using a spin coater. The thickness of the photoresist is about 1.5 μm and the coating is placed on a hot plate at 95°C. Then, a direct write lithography machine is used to find the device position on the spun-coated substrate and mark it with the lithography machine. The wavelength of the ultraviolet light used in the lithography is 390 nm and the power is 390 mW / cm 2 After the photolithography is completed, the substrate is placed in the developer and deionized water in turn to make the photolithography pattern appear. Finally, the inert metal electrode is prepared by the thermal evaporation coating machine. The thermal evaporation conditions are as follows: the chamber vacuum is greater than 3.0×10 -4 Pa; 0.1g gold wire (99.99% purity); heating current of 130A; remaining photoresist removed with acetone to produce an Au / CuInP2S6 / Au vertical memristor. The thickness of the gold bottom electrode is 24nm, the thickness of the CuInP2S6 is 76nm, and the thickness of the gold bottom electrode is 24nm.

[0062] The schematic diagram of the structure of the Au / CuInP2S6 / Au vertical structure memristor prepared in Example 2 is shown in FIG. Figure 2 ; Among them, 1 is the gold bottom electrode, 2 is the ferroelectric functional layer CuInP2S6, and 3 is the gold top electrode.

[0063] The prepared Au / CuInP2S6 / Au vertical structure memristor is used to characterize the ferroelectricity of the material. The hysteresis loop of the CIPS ferroelectric functional layer is shown in Figure 3 During the test, the bottom electrode is connected to the negative pole of the power supply, the top electrode is connected to the positive pole of the power supply, the electrical signal is applied to the top electrode, and the voltage scanning mode is -8v~+8v~-8v.

[0064] Figure 3 It was shown that CIPS exhibited significant electrical hysteresis with a threshold voltage of 4V.

[0065] The transfer characteristic is the most basic performance of the transistor, which is reflected in the fact that a small voltage is applied between the source and drain to act as a reading voltage, and the control of the gate on the channel current is observed by changing the gate voltage. ds ) is the reading voltage, which is set to a smaller value of 0.5V. The gate voltage is scanned in the range of +10V to -10V to +10V. The transfer characteristics of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 are tested. The test results are shown in FIG. Figure 4 .

[0066] Figure 4 It shows that the device exhibits counterclockwise hysteresis characteristics, indicating that the hysteresis characteristics are caused by the switching of the CIPS polarization direction. At a small read voltage, the switching ratio of the device reaches 5 orders of magnitude.

[0067] Under the condition that the source-drain voltage scanning range remains unchanged, the output characteristics of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 are tested at different gate voltages. The test results are shown in Figure 5 .

[0068] Figure 5 It shows that the device channel current exhibits good linear behavior when no gate voltage is applied and when a certain gate voltage is applied, reflecting the good ohmic contact behavior between the SnS channel layer and the source and drain electrodes.

[0069] When the gate voltage is 0V, the source-drain voltage is 0.1V, the wavelength of the continuous ultraviolet light is 320nm, and the power density is 0.22W / cm 2 The relationship between the current and time of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 was tested under the conditions of Figure 6 .

[0070] Figure 6 It shows that under the stimulation of continuous ultraviolet light pulses, the carrier concentration in the channel of the device decreases, the resistance continues to increase, and the conductance continues to decrease, exhibiting a multi-level inhibition phenomenon, which is highly similar to the closure of postsynaptic membrane channels and reduced neuronal excitability after multiple inhibitory stimuli at the synapse.

[0071] When the gate voltage is 0V, the source-drain voltage is 0.1V, the wavelength of the ultraviolet light pulse is 320nm, and the power density is 0.22W / cm 2 The relationship between current and time when two ultraviolet light pulses are applied to the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 is tested under the conditions of 1s and an interval time of 1s. The results are shown in FIG. Figure 7 .

[0072] Figure 7 It shows that the conductance value under the second pulse stimulation is significantly lower than that under the first pulse, and the device response behavior can simulate the synaptic paired pulse depression (PPD) behavior.

[0073] When the gate voltage is 0V, the source-drain voltage is 0.1V, the wavelength of the ultraviolet light pulse is 320nm, and the power density is 0.22W / cm 2 Under the conditions of , the relationship between current and time when two ultraviolet light pulses were applied to the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 at different intervals was tested, and the calculated value of PPD behavior was calculated: PPD = A2 / A1×100%, where A2 is the current response amplitude of the second pulse light pulse, in nA; A1 is the current response amplitude of the first pulse light pulse, in nA. The simulated curve of the calculated value of PPD behavior and the interval time is shown in Figure . Figure 8 .

[0074] Figure 8 It shows that as the time interval between the two pulses increases, the calculated value of PPD will decrease accordingly. This is basically similar to the situation where the response behavior of a synapse becomes smaller after the first stimulation and the same stimulation is applied for the second time after a long time.

[0075] When the gate voltage is -5V, the source-drain voltage is 0.1V, the wavelength of the continuous ultraviolet light is 320nm, and the power density is 0.22W / cm 2 The relationship between the current and time of the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 was tested under the conditions of Figure 9 .

[0076] Figure 9 It shows that under the influence of the gate, after continuous ultraviolet light pulse stimulation, the carrier concentration in the channel increases, the resistance continues to decrease, and the conductance continues to increase, showing a multi-level promotion phenomenon, which is highly similar to the opening of postsynaptic membrane channels and increased neuronal excitability after multiple facilitatory stimulations of the synapse.

[0077] When the gate voltage is -5V, the source-drain voltage is 0.1V, the wavelength of the ultraviolet light pulse is 320nm, and the power density is 0.22W / cm 2 The relationship between current and time when two ultraviolet light pulses are applied to the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 is tested under the conditions of 1s and an interval time of 1s. The results are shown in FIG. Figure 10 .

[0078] Figure 10 It shows that the conductance value under the second pulse stimulation is significantly higher than that after the first pulse, successfully simulating the PPF behavior.

[0079] When the gate voltage is -5V, the source-drain voltage is 0.1V, the wavelength of the ultraviolet light pulse is 320nm, and the power density is 0.22W / cm 2 The relationship between current and time when two ultraviolet light pulses were applied at different intervals to the gate-controlled multimodal ferroelectric transistor device prepared in Example 1 was tested under the conditions of , and the calculated value of PPD behavior was calculated. The simulated curve of the calculated value of PPD behavior and the interval time is shown in Figure 11 .

[0080] Figure 11 It shows that as the time interval between the two pulses increases, the calculated value of PPF will decrease accordingly, which is basically similar to the situation where the response behavior of a synapse becomes smaller after a long time after the first stimulation when the same stimulation is applied for the second time.

[0081] The embodiments described above are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by persons skilled in the art should fall within the scope of protection defined by the claims of the present invention.

Claims

1. A gate-controlled multimodal ferroelectric transistor device, characterized in that: The structure includes: a gate, a CuInP2S6 ferroelectric insulating layer, a hexagonal boron nitride dielectric layer, a tin sulfide channel layer, a source and a drain on the tin sulfide channel layer, and a substrate on the source and the drain, which are arranged in sequence; the materials of the gate, the source and the drain are all inert metals.

2. The gate-controlled multimodal ferroelectric transistor device according to claim 1, characterized in that: The thickness of the gate electrode is 20-30 nm; the thickness of the source electrode is 20-30 nm; and the thickness of the drain electrode is 20-30 nm.

3. The gate-controlled multi-mode ferroelectric transistor device according to claim 1, characterized in that: The thickness of the CuInP2S6 ferroelectric insulating layer is 70-80 nm.

4. The gate-controlled multi-mode ferroelectric transistor device according to claim 1, wherein: The thickness of the hexagonal boron nitride dielectric layer is 5-15 nm.

5. The gate-controlled multi-mode ferroelectric transistor device according to claim 1, characterized in that: The thickness of the tin sulfide channel layer is 20-30 nm.

6. A method for preparing the gate-controlled multimodal ferroelectric transistor device according to any one of claims 1 to 5, characterized in that: The following steps are involved: First, a source and a drain are generated on the substrate, and then a tin sulfide channel layer is generated on the source and the drain. Then, a hexagonal boron nitride dielectric layer and a CuInP2S6 ferroelectric insulating layer are sequentially generated to form a van der Waals heterojunction, and finally a gate is generated; thus, the preparation of a gate-controlled multimodal ferroelectric transistor device is completed.

7. The method for preparing a gate-controlled multimodal ferroelectric transistor device according to claim 6, wherein: The source electrode, the drain electrode and the gate electrode are formed by thermal evaporation.

8. The method for preparing a gate-controlled multimodal ferroelectric transistor device according to claim 6, wherein: The step of generating the tin sulfide channel layer includes: mechanically stripping off the two-dimensional tin sulfide, transferring the two-dimensional tin sulfide to the source electrode and the drain electrode, and obtaining the tin sulfide channel layer.

9. The method for preparing a gate-controlled multimodal ferroelectric transistor device according to claim 6, wherein: The step of generating the hexagonal boron nitride dielectric layer includes: mechanically peeling off the two-dimensional hexagonal boron nitride, transferring it onto the tin sulfide channel layer, and obtaining the hexagonal boron nitride dielectric layer.

10. The method for preparing a gate-controlled multi-mode ferroelectric transistor device according to claim 6, characterized in that: The steps of generating the CuInP2S6 ferroelectric insulating layer include: mechanically peeling off the two-dimensional CuInP2S6 and transferring it onto the hexagonal boron nitride dielectric layer to obtain the CuInP2S6 ferroelectric insulating layer.

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