Vertical LED chip and preparation method thereof

Abstract

The invention discloses a vertical LED chip and a preparation method thereof, and the preparation method comprises the following steps: providing a first substrate, and forming an epitaxial layer on the first substrate; etching and forming an N-type conductive step; sequentially forming a reflecting layer and a metal connecting layer on the P-type semiconductor layer; forming a first insulating layer on the metal connecting layer, the P-type semiconductor layer and the N-type conductive step; etching the first insulating layer on the N-type conductive step to form a first hole; the side wall of the first hole is arc-shaped; forming a conductive alloy layer in the first hole as an N-type bonding pad; providing a transfer substrate, and stripping the first substrate after bonding; and forming a P-type bonding pad to obtain the vertical LED chip. By implementing the invention, the heat-conducting property of the vertical LED chip can be obviously improved, and the working voltage is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a vertical LED chip and a preparation method thereof. Background Art

[0002] LED chips are widely used in lighting and display fields due to their advantages such as energy saving and high efficiency. When it comes to high-power applications such as outdoor lighting and automotive lighting, vertically structured LED chips are usually used.

[0003] During the preparation process of vertical LED chips, the epitaxial structure needs to be transferred to other highly thermally and electrically conductive substrates such as silicon, copper, or metal substrates, and the epitaxial growth substrate needs to be removed. This can effectively improve technical issues such as light absorption, current crowding, and poor heat dissipation caused by the epitaxial growth substrate. Bonding is mainly achieved by forming a metal bonding layer between one side of the epitaxial structure and the transfer substrate and performing hot pressing. However, due to the height difference on the surface of the epitaxial structure, bonding voids are easily generated, especially at the steps of the N-type semiconductor. This leads to high thermal resistance of the chip, poor heat dissipation, and high junction temperature, which seriously affects the reliability of the vertical LED chip. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a vertical LED chip and a preparation method thereof, which can significantly improve the thermal conductivity of the vertical LED chip and reduce the operating voltage.

[0005] In order to solve the above problems, the present invention discloses a method for preparing a vertical LED chip, comprising the following steps:

[0006] Providing a first substrate, and forming an epitaxial layer on the first substrate; the epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially stacked on the first substrate;

[0007] Etching and exposing the N-type semiconductor layer to form an N-type conductive step;

[0008] forming a reflective layer and a metal connection layer in sequence on the P-type semiconductor layer; wherein the metal connection layer completely covers the reflective layer;

[0009] forming a first insulating layer on the metal connection layer, the P-type semiconductor layer and the N-type conductive step;

[0010] Etching the first insulating layer on the N-type conductive step to form a first hole exposing the N-type conductive step; the sidewall of the first hole is arc-shaped;

[0011] forming a conductive alloy layer in the first hole to serve as an N-type pad connected to the N-type semiconductor layer;

[0012] Providing a transfer substrate, bonding the transfer substrate to the epitaxial layer through a bonding process, and peeling off the first substrate;

[0013] A P-type pad connected to the P-type semiconductor layer is formed to obtain the vertical LED chip.

[0014] As an improvement to the above technical solution, the steps of forming the first hole are as follows:

[0015] Applying photoresist on the surface of the first insulating layer, exposing and developing the photoresist using a photomask to form a first opening;

[0016] Etching the first opening using an inductively coupled plasma etching process to remove excess photoresist and form the first hole;

[0017] Wherein, along the first direction, the photoresist plate includes an etching area and a protection area, the etching area includes a plurality of light-transmitting areas and a first light-shielding area, and the plurality of light-transmitting areas and the first light-shielding area are arranged at intervals, the protection area includes a second light-shielding area, and the protection area is arranged at both ends of the etching area;

[0018] The widths of the plurality of light-transmitting areas decrease from the center to the edge of the photoresist; and the widths of the plurality of first light-shielding areas are the same.

[0019] As an improvement of the above technical solution, the width of each light-transmitting area is 2 μm to 6 μm, the width difference between two adjacent light-transmitting areas is 0.5 μm to 1 μm, and the width of each first light-shielding area is 2 μm to 3 μm.

[0020] As an improvement to the above technical solution, the projection of the etched area of ​​the photoresist in the vertical direction completely covers the N-type conductive step.

[0021] As an improvement of the above technical solution, the conductive alloy layer includes a first reflective layer and a second alloy layer stacked in sequence; the first reflective layer is an Al layer, and the thickness of the Al layer is The second alloy layer includes 3 to 5 alloy sub-layers stacked in sequence, each of the alloy sub-layers includes a Ti layer, a Ni layer, an Au layer and a Sn layer stacked in sequence, and the thickness of the Ti layer is The thickness of the Ni layer is The thickness of the Au layer is The thickness of the Sn layer is

[0022] As an improvement to the above technical solution, the top of the conductive alloy layer is higher than the top of the first insulating layer, and the distance between the top of the conductive alloy layer and the top of the first insulating layer is

[0023]

[0024] As an improvement to the above technical solution, the step of bonding the transfer substrate to the epitaxial layer is as follows:

[0025] Depositing a metal bonding layer on the surfaces of the transfer substrate, the first insulating layer and the conductive alloy layer by using an electron beam evaporation process;

[0026] The transfer substrate is bonded to the epitaxial layer through the metal bonding layer using a thermal compression bonding process.

[0027] As an improvement of the above technical solution, the transfer substrate is a Si substrate or a Cu substrate;

[0028] The metal bonding layer includes a first sublayer and a second sublayer, wherein the first sublayer is a Ti layer with a thickness of The second sub-layer is a stack of Sn and Ni layers, with overlapping periods of 2 to 5. In each period, the thickness of the Sn layer is The thickness of the Ni layer is

[0029] As an improvement to the above technical solution, the steps of forming the P-type pad are as follows:

[0030] Etching and exposing the metal connection layer to form an isolation trench;

[0031] forming a second insulating layer on the N-type semiconductor layer and the isolation trench;

[0032] Etching the second insulating layer on the isolation trench to form a second hole exposing the metal connection layer;

[0033] A P-type pad is formed in the second hole.

[0034] Correspondingly, the present invention also discloses a vertical LED chip, which is manufactured using the above-mentioned manufacturing method.

[0035] The implementation of the present invention has the following beneficial effects:

[0036] The present invention provides a method for fabricating a vertical LED chip. By creating an arc-shaped sidewall on a first hole positioned on an N-type conductive step and disposing a conductive alloy layer within the first hole, bonding voids on the N-type conductive step during subsequent substrate transfer are avoided. The arc-shaped sidewall is more conducive to metal deposition than the stepped sidewall. The conductive alloy layer completely covers the sidewall of the first hole, significantly reducing the gap between the N-type conductive step and the conductive alloy layer, thereby significantly improving the optoelectronic performance and reliability of the vertical LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 11 is a schematic structural diagram after step S1 of the method for preparing a vertical LED chip provided by an embodiment of the present invention;

[0038] Figure 2 1 is a schematic structural diagram after step S2 of the method for preparing a vertical LED chip provided by an embodiment of the present invention;

[0039] Figure 3 1 is a schematic structural diagram after step S3 of the method for preparing a vertical LED chip provided by an embodiment of the present invention;

[0040] Figure 4 1 is a schematic structural diagram after step S4 of the method for preparing a vertical LED chip provided by an embodiment of the present invention;

[0041] Figure 5 1 is a schematic structural diagram after step S5 of the method for preparing a vertical LED chip provided by an embodiment of the present invention;

[0042] Figure 6 1 is a schematic structural diagram after step S51 of the method for preparing a vertical LED chip provided by an embodiment of the present invention;

[0043] Figure 7 is a schematic structural diagram of a photoresist provided by an embodiment of the present invention;

[0044] Figure 8 1 is a schematic structural diagram of the method for preparing a vertical LED chip after step S52 according to an embodiment of the present invention;

[0045] Figure 9 1 is a schematic structural diagram after step S6 of the method for preparing a vertical LED chip provided by an embodiment of the present invention;

[0046] Figure 10 is a schematic structural diagram of a conductive alloy layer provided by an embodiment of the present invention;

[0047] Figure 11 yes Figure 9 A magnified view of part A;

[0048] Figure 12 1 is a schematic structural diagram after step S7 of the method for preparing a vertical LED chip provided by an embodiment of the present invention;

[0049] Figure 13 1 is a schematic structural diagram after step S8 of the method for preparing a vertical LED chip provided by an embodiment of the present invention;

[0050] Figure 14 3 is a structural diagram after step S8 of the method for preparing a vertical LED chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0052] The present invention provides a method for preparing a vertical LED chip, comprising the following steps:

[0053] S1, such as Figure 1 As shown, a first substrate 10 is provided, and an epitaxial layer 11 is formed on the first substrate 10. The epitaxial layer 11 includes an N-type semiconductor layer 111, an active light emitting layer 112, and a P-type semiconductor layer 113 sequentially stacked on the first substrate 10.

[0054] Specifically, an epitaxial layer 11 is formed on the first substrate 10 using methods such as MOCVD, MBE, and PVD. The first substrate 10 may be a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto. The N-type semiconductor layer 111 may be an N-type GaN layer, an N-type AlGaInP layer, or an N-type AlGaN layer, but is not limited thereto, and has a thickness of 1 μm to 5 μm. The active light-emitting layer 112 may be an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, an AlGaN / AlGaN multi-quantum well layer, or an AlGaInP / AlGaInP multi-quantum well layer, but is not limited thereto, and has a thickness of 20 nm to 200 nm. The P-type semiconductor layer 113 may be a P-type GaN layer, a P-type AlGaInP layer, or a P-type AlGaN layer, but is not limited thereto, and has a thickness of 200 nm to 500 nm.

[0055] S2, such as Figure 2 As shown, the N-type semiconductor layer 111 is etched and exposed to form an N-type conductive step 114 .

[0056] In one embodiment, a photoresist is coated on the surface of the P-type semiconductor layer 113, and a portion of the photoresist is removed by exposure and development to expose the P-type semiconductor layer 113 below the portion of the photoresist. Then, an inductively coupled plasma etching process is used to remove a portion of the P-type semiconductor layer 113 and the active light-emitting layer 112 below the P-type semiconductor layer 113 until the N-type semiconductor layer 111 is exposed. Finally, the photoresist is removed to form an N-type conductive step 114.

[0057] S3, such as Figure 3 As shown, a reflective layer 12 and a metal connection layer 13 are sequentially formed on the P-type semiconductor layer 113 , wherein the metal connection layer 13 completely covers the reflective layer 12 .

[0058] In one embodiment, a negative photoresist is coated on the surface of the P-type semiconductor layer 113 and the N-type conductive step 114. A portion of the photoresist is then removed by exposure and development. A metal is deposited as the reflective layer 12 using an electron beam evaporation process. The metal above the photoresist is stripped using a blue film stripping process, and the photoresist is then removed. In one embodiment, the reflective layer 12 includes a Ni layer, an Ag layer, a Ti layer, a Ni layer, and a Ti layer stacked in sequence. The thickness of the reflective layer 12 is 100 nm to 400 nm.

[0059] Next, a negative photoresist is applied to the reflective layer 12, the N-type conductive step 114, and the portion of the P-type semiconductor layer 113 not covered by the reflective layer 12. A portion of the photoresist is removed by exposure and development. Then, metal is deposited using an electron beam evaporation process to form the metal connection layer 13. The metal above the photoresist is stripped using a blue film stripping process, and the photoresist is then removed. In one embodiment, the metal connection layer 13 includes a Ti layer, a Ni layer, a Pt layer, and a Ti layer stacked in sequence. The thickness of the metal connection layer 13 is 20 nm to 100 nm.

[0060] It can be understood that the metal connection layer 13 completely covers the reflective layer 12 , and the area of ​​the metal connection layer 13 is larger than the area of ​​the reflective layer 12 .

[0061] S4, such as Figure 4 As shown, a first insulating layer 14 is formed on the metal connection layer 13 , the P-type semiconductor layer 113 and the N-type conductive step 114 .

[0062] In one embodiment, a first insulating layer 14 is formed on the metal connection layer 13, the N-type conductive step 114, and the P-type semiconductor layer 113 not covered by the metal connection layer 13. In one embodiment, a SiO2 thin film is deposited by PECVD as the first insulating layer 14.

[0063] S5, such as Figure 5 As shown, the first insulating layer 14 on the N-type conductive step 114 is etched to form a first hole exposing the N-type conductive step 114 ; the sidewall of the first hole is arc-shaped.

[0064] In one embodiment, photoresist is coated on the surface of the first insulating layer 14 and exposed using a photomask 16. The exposed area is the area where the first hole will be subsequently formed. The present invention provides an arc-shaped sidewall for the first hole, rather than the stepped shape used in the prior art. This prevents the formation of voids at the stepped portion during the subsequent preparation of the filler layer for the first hole. This void, which can then become larger after high-temperature bonding and affect the heat dissipation capability of the vertical LED chip, can be curved, elliptical, or otherwise, as long as it is concave or convex toward the P-type semiconductor layer 113.

[0065] In one embodiment, the steps of forming the first hole are as follows:

[0066] S51, such as Figure 6 As shown, photoresist is coated on the surface of the first insulating layer 14 , and the photoresist is exposed and developed using a photoresist plate 16 to form a first opening.

[0067] Among them, such as Figure 7 As shown, along a first direction, the photoresist plate 16 includes an etched area 162 and a protection area 161. It can be understood that the first direction is a horizontal direction and is parallel to the direction in which the N-type conductive steps 114 are spaced apart. The etched area 162 includes a plurality of light-transmitting areas 162a and a first light-shielding area 162b, and the plurality of light-transmitting areas 162a and the first light-shielding areas 162b are spaced apart. The protection area 161 includes a second light-shielding area 161a, and the protection area 161 is provided at both ends of the etched area 162.

[0068] The widths of the plurality of light-transmitting regions 162 a decrease from the center to the edge of the photoresist 16 ; the widths of the plurality of first light-shielding regions 162 b are the same.

[0069] Preferably, the width of each light-transmitting region 162 a is 2 μm to 6 μm, the width difference between two adjacent light-transmitting regions 162 a is 0.5 μm to 1 μm, and the width of each first light-shielding region 162 b is 2 μm to 3 μm.

[0070] During exposure, light is diffracted between the alternating light-transmitting regions 162a and the first light-shielding regions 162b, resulting in an arc-shaped sidewall of the first hole 115 after development. The radius of the arc of the sidewall depends on the width of the light-transmitting regions 162a, the decreasing width of adjacent light-transmitting regions 162a, and the width of the first light-shielding regions 162b. The smaller the width of the first light-shielding regions 162b, the smaller the arc radius; the larger the width of the first light-shielding regions 162b, the larger the arc radius. The greater the decreasing width of adjacent light-transmitting regions 162a, the smaller the arc radius; the smaller the decreasing width of adjacent light-transmitting regions 162a, the larger the arc radius.

[0071] S52, such as Figure 8 As shown, the first opening is etched using an inductively coupled plasma etching process to remove excess photoresist and form the first hole 115 .

[0072] Specifically, the projection of the etched area 162 of the photoresist 16 in the vertical direction completely covers the N-type conductive step 114 to form the first hole 115 with an arc-shaped sidewall.

[0073] S6, such as Figure 9 As shown, a conductive alloy layer 17 is formed in the first hole to serve as an N-type pad connected to the N-type semiconductor layer 111 .

[0074] In one embodiment, a negative photoresist is coated on the first insulating layer 14 and the first hole, and the photoresist in the first hole is removed by exposure and development. Then, a metal is evaporated using an electron beam evaporation process to form a conductive alloy layer 17. The metal on the photoresist is removed using a blue film stripping process, and then the photoresist is removed.

[0075] In one embodiment, Figure 10 As shown, the conductive alloy layer 17 includes a first reflective layer 171 and a second alloy layer 172 stacked in sequence; the first reflective layer 171 is an Al layer, and the thickness of the Al layer is The second alloy layer 172 includes 3 to 5 alloy sub-layers stacked in sequence, each of which includes a Ti layer 172a, a Ni layer 172b, an Au layer 172c, and a Sn layer 172d stacked in sequence. The thickness of the Ti layer 172a is The thickness of the Ni layer 172b is The thickness of the Au layer 172c is The thickness of Sn layer 172d is

[0076] The second alloy layer 172 of the present invention comprises a sequential stack of Ti, Ni, Au, and Sn metals. The Ni, Au, and Sn metals are alloyed at high temperatures during the subsequent bonding process to form a ternary alloy. The Ti metal does not participate in the alloying process, acting as an alloy divider. This reduces the number of individual alloy sublayers, minimizes deformation of the second alloy layer 172 after alloying, and thus reduces voids in subsequent bonding layers. This stacked arrangement of multiple sublayers avoids the problem of concentrated current injection at the N-type conductive step 114 during operation, which can reduce the operating voltage of the vertical LED chip.

[0077] It is understood that the top of the conductive alloy layer 17 is higher than the top of the first insulating layer 14, so as to avoid the bonding material being unable to cover the surface of the N-type conductive step 114 and causing bonding voids. Figure 11 As shown, the distance L between the top of the conductive alloy layer 17 and the top of the first insulating layer 14 is

[0078] S7, such as Figure 12 As shown, a transfer substrate 19 is provided, the transfer substrate 19 is bonded to the epitaxial layer 11 through a bonding process, and the first substrate 10 is peeled off.

[0079] In one embodiment, the steps of bonding the transfer substrate 19 to the epitaxial layer 11 are as follows:

[0080] S71 , using an electron beam evaporation process to evaporate a metal bonding layer 18 on the surfaces of the transfer substrate 19 , the first insulating layer 14 and the conductive alloy layer 17 .

[0081] S72 , using a thermocompression bonding process to bond the transfer substrate 19 to the epitaxial layer 11 through the metal bonding layer 18 .

[0082] Optionally, the transfer substrate 19 is a Si substrate or a Cu substrate, but is not limited thereto. Selecting a substrate with high thermal conductivity and high electrical conductivity as the transfer substrate 19 can significantly reduce series resistance and improve current spreading uniformity.

[0083] In one embodiment, the metal bonding layer 18 includes a first sublayer and a second sublayer, wherein the first sublayer is a Ti layer with a thickness of The second sub-layer is a stack of Sn and Ni layers, with overlapping periods of 2 to 5. In each period, the thickness of the Sn layer is The thickness of the Ni layer is The temperature of the hot pressing bonding is 150° C. to 400° C., the pressure is 1 MPa to 50 MPa, and the time is 10 s to 600 s.

[0084] After bonding is completed, the first substrate 10 is peeled off using a laser lift-off process. The laser lift-off process uses a 266nm ultraviolet laser to irradiate and remove the first substrate 10 from the first substrate 10. Taking the sapphire substrate and the N-type GaN layer as an example, the energy of the laser can decompose the GaN at the interface between the sapphire and the N-type GaN layer, generating metallic gallium and nitrogen, thereby decomposing and removing the sapphire substrate. In one embodiment, the laser spot radius of the laser lift-off process is 12μm to 16μm, the moving speed of the laser spot is 2500mm / s to 3000mm / s, and the laser power is 80W to 100W.

[0085] S8, such as Figure 13 and Figure 14 As shown, a P-type pad 22 connected to the P-type semiconductor layer 113 is formed to obtain the vertical LED chip.

[0086] In one embodiment, the steps of forming the P-type pad 22 are as follows:

[0087] S81 , etching and exposing the metal connection layer 13 to form an isolation trench 20 .

[0088] In one embodiment, after the first substrate 10 is stripped and removed, a photoresist is coated on the surface of the N-type semiconductor layer 111, and a portion of the photoresist is removed by exposure and development to expose the portion of the N-type semiconductor layer 111 from which the photoresist has been removed. The exposed portion of the N-type semiconductor layer 111 is removed through an inductively coupled plasma etching process up to the metal connection layer 13 to form an isolation trench 20.

[0089] S82 , forming a second insulating layer 21 on the N-type semiconductor layer 111 and the isolation trench 20 .

[0090] In one embodiment, an Al 2 O 3 thin film is deposited on the surface of the N-type semiconductor layer 111 and the isolation trench 20 by atomic layer deposition as the second insulating layer 21 .

[0091] S83 , etching the second insulating layer 21 on the isolation trench 20 to form a second hole exposing the metal connection layer 13 .

[0092] In one embodiment, a negative photoresist is coated on the surface of the second insulating layer 21, and a portion of the photoresist is removed by exposure and development to expose a portion of the second insulating layer 21. The exposed portion of the second insulating layer 21 is removed by an inductively coupled plasma etching process up to the metal connection layer 13 to form a second hole.

[0093] S84 , forming a P-type pad 22 in the second hole.

[0094] In one embodiment, a metal is deposited in the second hole by electron beam evaporation to form a P-type pad 22, and the metal on the photoresist is removed by lift-off process, and then the photoresist is removed. Specifically, the P-type pad 22 includes a Ti layer, a Pt layer, an Au layer, a Ni layer and an Au layer stacked in sequence, and the thickness of the Ti layer is The thickness of the Pt layer is The thickness of the Au layer is The thickness of the Ni layer is The thickness of the Au layer is

[0095] Correspondingly, the present invention also provides a vertical LED chip, which is manufactured using the above-mentioned manufacturing method.

[0096] The present invention will be further described below with specific embodiments:

[0097] Example 1

[0098] This embodiment provides a method for preparing a vertical LED chip, comprising the following steps:

[0099] S1. Provide a first substrate and form an epitaxial layer on the first substrate; the epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer stacked in sequence on the first substrate.

[0100] S2. Etching and exposing the N-type semiconductor layer to form an N-type conductive step.

[0101] S3. Forming a reflective layer and a metal connection layer in sequence on the P-type semiconductor layer; the metal connection layer completely covers the reflective layer.

[0102] S4. Form a first insulating layer on the metal connection layer, the P-type semiconductor layer and the N-type conductive step.

[0103] S5. Etching the first insulating layer on the N-type conductive step to form a first hole exposing the N-type conductive step; the sidewall of the first hole is arc-shaped.

[0104] S6, forming a conductive alloy layer in the first hole as an N-type pad connected to the N-type semiconductor layer. The conductive alloy layer includes a first reflective layer and a second alloy layer stacked in sequence, the first reflective layer is an Al layer, and the thickness of the Al layer is The second alloy layer includes three alloy sub-layers stacked in sequence, each alloy sub-layer includes a Ti layer, a Ni layer, an Au layer and a Sn layer stacked in sequence, and the thickness of the Ti layer is The thickness of the Ni layer is The thickness of the Au layer is The thickness of the Sn layer is

[0105] S7. Provide a transfer substrate, bond the transfer substrate to the epitaxial layer through a bonding process, and peel off the first substrate.

[0106] S8. Form a P-type pad connected to the P-type semiconductor layer to obtain a vertical LED chip.

[0107] Example 2

[0108] This embodiment provides a method for preparing a vertical LED chip, comprising the following steps:

[0109] S1. Provide a first substrate and form an epitaxial layer on the first substrate; the epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer stacked in sequence on the first substrate.

[0110] S2. Etching and exposing the N-type semiconductor layer to form an N-type conductive step.

[0111] S3. Forming a reflective layer and a metal connection layer in sequence on the P-type semiconductor layer; the metal connection layer completely covers the reflective layer.

[0112] S4. Form a first insulating layer on the metal connection layer, the P-type semiconductor layer and the N-type conductive step.

[0113] S5. Etching the first insulating layer on the N-type conductive step to form a first hole exposing the N-type conductive step; the sidewall of the first hole is arc-shaped.

[0114] S6, forming a conductive alloy layer in the first hole as an N-type pad connected to the N-type semiconductor layer. The conductive alloy layer includes a first reflective layer and a second alloy layer stacked in sequence, the first reflective layer is an Al layer, and the thickness of the Al layer is The second alloy layer includes four alloy sub-layers stacked in sequence, each alloy sub-layer includes a Ti layer, a Ni layer, an Au layer and a Sn layer stacked in sequence, and the thickness of the Ti layer is The thickness of the Ni layer is The thickness of the Au layer is The thickness of the Sn layer is

[0115] S7. Provide a transfer substrate, bond the transfer substrate to the epitaxial layer through a bonding process, and peel off the first substrate.

[0116] S8. Form a P-type pad connected to the P-type semiconductor layer to obtain a vertical LED chip.

[0117] Example 3

[0118] This embodiment provides a method for preparing a vertical LED chip, comprising the following steps:

[0119] S1. Provide a first substrate and form an epitaxial layer on the first substrate; the epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer stacked in sequence on the first substrate.

[0120] S2. Etching and exposing the N-type semiconductor layer to form an N-type conductive step.

[0121] S3. Forming a reflective layer and a metal connection layer in sequence on the P-type semiconductor layer; the metal connection layer completely covers the reflective layer.

[0122] S4. Form a first insulating layer on the metal connection layer, the P-type semiconductor layer and the N-type conductive step.

[0123] S5. Etching the first insulating layer on the N-type conductive step to form a first hole exposing the N-type conductive step; the sidewall of the first hole is arc-shaped.

[0124] S6, forming a conductive alloy layer in the first hole as an N-type pad connected to the N-type semiconductor layer. The conductive alloy layer includes a first reflective layer and a second alloy layer stacked in sequence, the first reflective layer is an Al layer, and the thickness of the Al layer is The second alloy layer includes five alloy sub-layers stacked in sequence, each alloy sub-layer includes a Ti layer, a Ni layer, an Au layer and a Sn layer stacked in sequence, and the thickness of the Ti layer is The thickness of the Ni layer is The thickness of the Au layer is The thickness of the Sn layer is

[0125] S7. Provide a transfer substrate, bond the transfer substrate to the epitaxial layer through a bonding process, and peel off the first substrate.

[0126] S8. Form a P-type pad connected to the P-type semiconductor layer to obtain a vertical LED chip.

[0127] The vertical LED chips prepared in Examples 1 to 3 and Comparative Example 1 were processed into 1050 μm × 1250 μm dimensions and tested for operating voltage and thermal conductivity at a current of 700 mA. The thermal conductivity test method was to first test the luminous brightness at 700 mA and record it as the initial brightness. The vertical LED chip was then placed in an oven at a constant temperature of 105°C for aging. The luminous brightness was tested at 700 mA every 72 hours and recorded as the current brightness. If the ratio of the current brightness to the initial brightness was less than 90%, the vertical LED chip had failed due to high-temperature aging. The specific performance test results are as follows:

[0128]

[0129] The above is a preferred embodiment of the invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a vertical LED chip, characterized in that: The following steps are involved: Providing a first substrate, and forming an epitaxial layer on the first substrate; the epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially stacked on the first substrate; Etching and exposing the N-type semiconductor layer to form an N-type conductive step; forming a reflective layer and a metal connection layer in sequence on the P-type semiconductor layer; wherein the metal connection layer completely covers the reflective layer; forming a first insulating layer on the metal connection layer, the P-type semiconductor layer and the N-type conductive step; Etching the first insulating layer on the N-type conductive step to form a first hole exposing the N-type conductive step; the sidewall of the first hole is arc-shaped; forming a conductive alloy layer in the first hole to serve as an N-type pad connected to the N-type semiconductor layer; Providing a transfer substrate, bonding the transfer substrate to the epitaxial layer through a bonding process, and peeling off the first substrate; A P-type pad connected to the P-type semiconductor layer is formed to obtain the vertical LED chip.

2. The method for preparing a vertical LED chip according to claim 1, wherein: The steps of forming the first hole are as follows: Applying photoresist on the surface of the first insulating layer, exposing and developing the photoresist using a photomask to form a first opening; Etching the first opening using an inductively coupled plasma etching process to remove excess photoresist and form the first hole; Wherein, along the first direction, the photoresist plate includes an etching area and a protection area, the etching area includes a plurality of light-transmitting areas and a first light-shielding area, and the plurality of light-transmitting areas and the first light-shielding area are arranged at intervals, the protection area includes a second light-shielding area, and the protection area is arranged at both ends of the etching area; The widths of the plurality of light-transmitting areas decrease from the center to the edge of the photoresist; and the widths of the plurality of first light-shielding areas are the same.

3. The method for preparing a vertical LED chip according to claim 2, wherein: The width of each light-transmitting area is 2 μm to 6 μm, the width difference between two adjacent light-transmitting areas is 0.5 μm to 1 μm, and the width of each first light-shielding area is 2 μm to 3 μm.

4. The method for preparing a vertical LED chip according to claim 1, wherein: The projection of the etched area of ​​the photoresist in the vertical direction completely covers the N-type conductive step.

5. The method for preparing a vertical LED chip according to claim 1, wherein: The conductive alloy layer includes a first reflective layer and a second alloy layer stacked in sequence; the first reflective layer is an Al layer, and the thickness of the Al layer is The second alloy layer includes 3 to 5 alloy sub-layers stacked in sequence, each of which includes a Ti layer, a Ni layer, an Au layer and a Sn layer stacked in sequence, and the thickness of the Ti layer is The thickness of the Ni layer is The thickness of the Au layer is The thickness of the Sn layer is 6. The method for preparing a vertical LED chip according to claim 5, wherein: The top of the conductive alloy layer is higher than the top of the first insulating layer, and the distance between the top of the conductive alloy layer and the top of the first insulating layer is 7. The method for preparing a vertical LED chip according to claim 1, wherein: The steps of bonding the transfer substrate to the epitaxial layer are as follows: Depositing a metal bonding layer on the surfaces of the transfer substrate, the first insulating layer and the conductive alloy layer by using an electron beam evaporation process; The transfer substrate is bonded to the epitaxial layer through the metal bonding layer using a thermal compression bonding process.

8. The method for preparing a vertical LED chip according to claim 7, wherein: The transfer substrate is a Si substrate or a Cu substrate; The metal bonding layer includes a first sublayer and a second sublayer, wherein the first sublayer is a Ti layer with a thickness of The second sub-layer is a stack of Sn and Ni layers, with an overlapping period of 2 to 5. In each period, the thickness of the Sn layer is The thickness of the Ni layer is 9. The method for preparing a vertical LED chip according to claim 1, wherein: The steps of forming the P-type pad are as follows: Etching and exposing the metal connection layer to form an isolation trench; forming a second insulating layer on the N-type semiconductor layer and the isolation trench; Etching the second insulating layer on the isolation trench to form a second hole exposing the metal connection layer; A P-type pad is formed in the second hole.

10. A vertical LED chip, characterized in that: The vertical LED chip is manufactured using the manufacturing method according to any one of claims 1 to 9.

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