Chip array and light-emitting module

Abstract

The invention discloses a chip array and a light-emitting module, the chip array comprises a substrate and a plurality of chip structures, and the chip structures are arranged on the substrate in an array; the substrate is provided with electrode bonding pads which are arranged in an array, and the electrode bonding pads comprise P electrode bonding pads and N electrode bonding pads; any chip structure comprises a P electrode, a semiconductor layer and an N electrode, the P electrode is arranged on the substrate and pressed on the corresponding P electrode bonding pad, the semiconductor layer is arranged on the top surface of the P electrode, the N electrode is arranged on the top surface of the semiconductor layer, the N electrode is arranged on the side walls of the semiconductor layer and the P electrode, the N electrode extends on the substrate, and the P electrode bonding pad is arranged on the substrate. And the N electrode pads are pressed on the corresponding N electrode pads. According to the invention, the positions of the P electrode, the semiconductor layer and the N electrode in the chip structure are arranged, the N electrode extension connection structure based on the adjacent chip structures is matched with the chip array formed by the electrode bonding pads on the substrate, the structural design is simplified, and the light emitting efficiency and the light emitting efficiency of the chip structure of the light emitting module are effectively optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of display devices, and in particular to a chip array and a light-emitting module. Background Art

[0002] With the continuous development of digitalization and intelligence, the function of vehicle lights is gradually changing from traditional lighting to digital and personalized lighting, becoming an information exchange window for human-vehicle interaction, vehicle-to-vehicle interaction, and vehicle-road interaction, and accelerating the evolution towards the mainstream trend of smart headlights that integrate lighting + display functions. DLP (Digital Light Processing) technology based on DMD (Digital Micromirror Device) is currently the mainstream solution for realizing digital headlight projection functions. The DLP pixel level can reach millions, which can realize fine lighting zoning and ultra-high-definition imaging projection functions. However, DLP technology currently has the problem of relatively complex optical design. The chip array and device module it carries are large in size, complex in structure, and high in cost. The backlight light source module required is high in power and power consumption. In addition, the manufacturing process also has problems such as poor high-precision alignment and low manufacturing efficiency. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides a chip array and a light-emitting module, sets the positions of the P electrode, semiconductor layer and N electrode in the chip structure, and forms a chip array based on the N electrode extension connection structure of the adjacent chip structure and the electrode pad on the substrate, thereby simplifying the structural design and effectively optimizing the light output effect and light output efficiency of the light-emitting module chip structure.

[0004] The present invention provides a chip array, comprising a substrate and a plurality of chip structures, wherein the plurality of chip structures are arranged in an array on the substrate;

[0005] The substrate is provided with a plurality of electrode pads, the plurality of electrode pads are arranged in an array, and the plurality of electrode pads include a plurality of P-electrode pads and a plurality of N-electrode pads;

[0006] Any one of the chip structures includes: a P electrode, a semiconductor layer and an N electrode, the P electrode is arranged on the substrate and pressed onto the corresponding P electrode pad, the semiconductor layer is arranged on the top surface of the P electrode, the N electrode is arranged on the top surface of the semiconductor layer, and the N electrode is arranged on the side walls of the semiconductor layer and the P electrode, and the N electrode extends on the substrate and is pressed onto the corresponding N electrode pad.

[0007] Furthermore, the P electrodes of the plurality of chip structures are independently arranged;

[0008] The N electrodes of the plurality of chip structures extend on the substrate and are electrically connected to each other.

[0009] Furthermore, the chip structure further includes a first insulating layer, which is arranged on the top surface and sidewalls of the semiconductor layer, and the first insulating layer is arranged on the sidewalls of the P electrode;

[0010] The first insulating layer is disposed between the P-electrode and the N-electrode, and the first insulating layer is disposed between the semiconductor layer and the N-electrode.

[0011] Furthermore, the chip structure further includes an ITO conductive layer, which is disposed on the top surface of the semiconductor layer and between the N electrode and the semiconductor layer.

[0012] Furthermore, the chip structure further includes a second insulating layer, and the second insulating layer covers the surface of the N electrode.

[0013] Furthermore, the plurality of N-electrode pads are arranged on at least one side of the plurality of P-electrode pads.

[0014] Furthermore, the substrate is a CMOS substrate.

[0015] The present invention also provides a light-emitting module, which includes the above-mentioned chip array, transition carrier, dam, packaging layer, phosphor film, and flat layer;

[0016] The chip array is arranged on the transition carrier, the dam covers the four sides of the chip array, the phosphor film and the flat layer are arranged above the chip array, and the packaging layer covers the four sides of the dam.

[0017] Furthermore, the material of the transition carrier is aluminum nitride.

[0018] Furthermore, the dam is made of transparent silicone and the flat layer is made of transparent silicone.

[0019] Furthermore, the phosphor film is a YAG film or a nitride yellow phosphor film.

[0020] Furthermore, the encapsulation layer is black silica gel doped with carbon powder.

[0021] The present invention provides a chip array and a light-emitting module. By providing a chip structure in which a plurality of P electrodes, semiconductor layers, and N electrodes are stacked in sequence, and based on the design of an N-electrode extension connection structure of adjacent chip structures, and a chip array consisting of electrode pads opened on a substrate, the structural design of the existing chip array and light-emitting module is simplified, and the light output effect and light output efficiency of the light-emitting module chip structure are effectively optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 is a cross-sectional structural diagram of a chip array in Embodiment 1 of the present invention;

[0024] Figure 2 is a flow chart of a method for manufacturing a chip array in the second embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the semi-finished product structure after completing step S201 in the second embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the semi-finished product structure after completing step S202 in the second embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of the semi-finished product structure after completing step S203 in the second embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of the finished chip array structure in the second embodiment of the present invention;

[0029] Figure 7 It is a cross-sectional structural diagram of the light-emitting module in the third embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] In the present invention, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts or their combinations disclosed in this specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts or their combinations exist or are added.

[0032] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] Example 1

[0034] Embodiment 1 of the present invention provides a chip array, which includes a substrate and several chip structures, and the several chip structures are arranged in an array on the substrate; a plurality of electrode pads are opened on the substrate, and the several electrode pads are arranged in an array, and the several electrode pads include several P-electrode pads and several N-electrode pads; any one of the chip structures includes: a P-electrode, a semiconductor layer and an N-electrode, the P-electrode is arranged on the substrate and pressed onto the corresponding P-electrode pad, the semiconductor layer is arranged on the top surface of the P-electrode, the N-electrode is arranged on the top surface of the semiconductor layer, and the N-electrode is arranged on the side walls of the semiconductor layer and the P-electrode, and the N-electrode extends on the substrate and is pressed onto the corresponding N-electrode pad.

[0035] In an optional implementation of this embodiment, as Figure 1 As shown, Figure 1 The cross-sectional structure diagram of the chip array in the first embodiment of the present invention is shown. The chip array includes a substrate 1 and a plurality of chip structures 2. The plurality of chip structures 2 are arranged in an array on the substrate 1.

[0036] In an optional implementation of this embodiment, a plurality of electrode pads are provided on the substrate 1 , and the plurality of electrode pads are arranged in an array. The plurality of electrode pads include a plurality of P-electrode pads 32 and a plurality of N-electrode pads 31 .

[0037] Specifically, the plurality of N-electrode pads are arranged on at least one side of the plurality of P-electrode pads, including one side, two adjacent sides, three adjacent sides, two opposite sides or four sides.

[0038] In an optional implementation of this embodiment, any one of the chip structures 2 includes: a P electrode 21, a semiconductor layer 22 and an N electrode 23, the P electrode 21 is arranged on the substrate 1 and pressed onto the corresponding P electrode pad 32, the semiconductor layer 22 is arranged on the top surface of the P electrode 21, the N electrode 23 is arranged on the top surface of the semiconductor layer 22, and the N electrode 23 is arranged on the side walls of the semiconductor layer 22 and the P electrode 21, and the N electrode 23 extends on the substrate 1 and is pressed onto the corresponding N electrode pad 31.

[0039] Specifically, the P electrode 21 is arranged at the bottom of the chip structure 2, that is, it contacts the surface of the substrate 1, and is also in contact with the P electrode pad 32 provided on the substrate 1. The semiconductor layer 22 is pressed on the top surface of the P electrode 21. The N electrode 23 is arranged on the outer edge area of ​​the top surface of the semiconductor layer 22, and extends along the side walls of the semiconductor layer 22 and the P electrode 21, and extends on the substrate 1. Its extended structure is in contact with the N electrode pad 31 provided on the substrate 1.

[0040] In an optional implementation of this embodiment, the P electrodes of the plurality of chip structures are independently arranged.

[0041] Specifically, in any chip structure 2 , the P electrodes 21 are independently arranged at the bottom of the chip structure 2 , and the P electrodes 21 of any two chip structures 2 are not in direct contact with each other and are independently arranged.

[0042] Here, the P electrodes of all chip structures are set to be independent of each other, which can realize independent control of the P electrodes and improve the control accuracy of a single chip structure.

[0043] In an optional implementation of this embodiment, the N electrodes of the plurality of chip structures extend on the substrate and are electrically connected to each other.

[0044] Specifically, such as Figure 1 As shown, Figure 1 The N electrodes 23 of two adjacent chip structures 2 are extended on the substrate and then contact each other to achieve electrical connection.

[0045] In an optional implementation of this embodiment, the chip structure also includes a first insulating layer, which is arranged on the top surface and side wall of the semiconductor layer, and the first insulating layer is on the side wall of the P electrode; the first insulating layer is arranged between the P electrode and the N electrode, and the first insulating layer is arranged between the semiconductor layer and the N electrode.

[0046] Specifically, the chip structure 2 also includes a first insulating layer 25, which covers the outer edge area on the surface of the semiconductor layer 22, and is arranged on the side walls of the semiconductor layer 22 and the side walls of the P electrode 21, that is, between the P electrode 21 and the N electrode 23, and between the semiconductor layer 22 and the N electrode 23.

[0047] Furthermore, the first insulating layer 25 is used to isolate the direct contact between the P electrode 21 and the N electrode 23, and the direct contact between the semiconductor layer 22 and the N electrode 23 on the single chip structure 2, so that the conductive connection between the semiconductor layer 22 and the N electrode 23 is only realized through the ITO conductive layer 24.

[0048] More preferably, the first insulating layer 25 is made of silicon dioxide or silicon nitride.

[0049] In an optional implementation of this embodiment, the chip structure further includes an ITO conductive layer, which is disposed on the top surface of the semiconductor layer and between the N electrode and the semiconductor layer.

[0050] Specifically, such as Figure 1 As shown, the chip structure 2 further includes an ITO conductive layer 24 . The ITO conductive layer 24 covers the top surface of the semiconductor layer 22 and is disposed between the N electrode 23 and the semiconductor layer 22 .

[0051] Furthermore, the ITO conductive layer 24 is a wide-band thin film material made of ITO (Indium Tin Oxide), which is mainly used to achieve conductivity and has good conductivity and high permeability. In this embodiment, the ITO conductive layer 24 is set as a medium to achieve a conductive connection between the semiconductor layer 22 and the N electrode 23.

[0052] In an optional implementation of this embodiment, the chip structure further includes a second insulating layer, and the second insulating layer covers the surface of the N electrode.

[0053] Specifically, such as Figure 1 As shown, the chip structure 2 further includes a second insulating layer 26 , and the second insulating layer 26 covers the surface of the N electrode 23 .

[0054] Furthermore, the second insulating layer 26 is used to insulate and protect the N-electrode 23. More preferably, the second insulating layer 26 is made of silicon dioxide or silicon nitride.

[0055] In an optional implementation of this embodiment, the substrate 1 is a CMOS substrate.

[0056] In an optional implementation of this embodiment, the semiconductor layer 22 is a combination of n-type GaN (gallium nitride) + MQW (Multiple Quantum Well) + p-type GaN.

[0057] Key advantages:

[0058] 1. The chip structure is a GaN-based vertical structure chip, with the P electrode set at the bottom and eutectic interconnected with the P electrode pad on the substrate. The N electrode is equivalent to being set at the top and eutectic interconnected with the N electrode pad on the substrate after extending on the sidewall of the chip structure and the substrate. A semiconductor layer is set between the P electrode and the N electrode, wherein the semiconductor layer is directly connected to the P electrode and indirectly connected to the N electrode through an ITO conductive layer. The P electrode is set separately and the N electrodes are interconnected, realizing conductive connection of the chip structure, simplifying the structural design, and effectively optimizing the light output effect and efficiency of the chip structure.

[0059] 2. The N-electrode is not completely set on the top of the chip structure, but is formed on the side wall and extends on the substrate, which has three advantages: First, the formed N-electrode has a reflective effect. Forming it on the side wall can effectively separate the adjacent chip structures and avoid the problem of cross-light between adjacent pixels; second, the N-electrode is formed on the side wall, which is equivalent to wrapping the other structures of the semiconductor layer of the chip structure except the top surface, which can improve the light reflection efficiency and the light output intensity; finally, the N-electrode extends on the substrate and covers the periphery of all chip structures. The N-electrodes of adjacent chip structures extend and connect on the substrate to form an interconnected network, which improves the uniformity of current transmission in the chip array and realizes the effect of current homogenization.

[0060] 3. The substrate using a silicon-based circuit substrate can independently drive the LED pixel unit composed of a single chip structure, that is, the number of chip structures in the chip array is not fixed, which can adapt to more production requirements.

[0061] 4. In addition, the first insulating layer and the second insulating layer are provided to isolate and protect the chip structure of the chip array, thereby improving the safety and reliability of the chip array.

[0062] In summary, embodiment 1 of the present invention provides a chip array, which simplifies the structural design of the existing chip array and the light-emitting module by setting a chip structure composed of several P electrodes, semiconductor layers and N electrodes stacked in sequence, and designs an N-electrode extension connection structure of adjacent chip structures, and a chip array composed of electrode pads opened on a substrate, thereby effectively optimizing the light output effect and light output efficiency of the light-emitting module chip structure.

[0063] Example 2

[0064] Embodiment 2 of the present invention provides a method for manufacturing a chip array, which is used to manufacture the chip array in embodiment 1, and the method includes: preparing a first bonding metal layer on a substrate, and preparing a second bonding metal layer on an LED epitaxial wafer; performing hot-press bonding on the substrate and the LED epitaxial wafer to form a first semi-finished product consisting of a metal eutectic layer formed by bonding the LED epitaxial wafers stacked in sequence, the first bonding metal layer and the second bonding metal layer, and a substrate; etching the LED epitaxial wafer and the metal eutectic layer to form a plurality of independent semiconductor layers and P electrodes; forming a first insulating layer on the semiconductor layer and the P electrode; forming an ITO conductive layer on the top surface of the semiconductor layer; forming an N electrode on the top surface and side walls of the semiconductor layer, on the side walls of the P electrode, and on the CMOS substrate; and forming a second insulating layer on the surface of the N electrode.

[0065] In an optional implementation of this embodiment, as Figure 2 As shown, Figure 2 The flowchart of the method for manufacturing a chip array in the second embodiment of the present invention is shown, which includes the following steps:

[0066] S201, preparing a first bonding metal layer on a substrate, and preparing a second bonding metal layer on an LED epitaxial wafer;

[0067] In an optional implementation of this embodiment, a CMOS substrate is prepared, and a first bonding metal layer is formed on the CMOS substrate by a preparation method including magnetron sputtering or electron beam evaporation.

[0068] Furthermore, the first bonding metal layer is a multi-layer metal structure, such as Cr / Ti-Ni-Au-Sn-Au.

[0069] In an optional implementation of this embodiment, an LED epitaxial wafer is prepared, and a second bonding metal layer is formed on the LED epitaxial wafer by a preparation method including magnetron sputtering or electron beam evaporation.

[0070] Furthermore, the second bonding metal layer is also a multi-layer metal structure, such as Cr / Ti-Ni-Au.

[0071] In an optional implementation of this embodiment, before preparing the first bonding metal layer on the substrate, the method further includes: opening a plurality of electrode pads arranged in an array on the substrate, including a plurality of P-electrode pads and a plurality of N-electrode pads.

[0072] Specifically, a groove is etched on the substrate, and metal is filled in the groove to form an electrode pad.

[0073] Furthermore, the plurality of N-electrode pads are arranged on at least one side of the plurality of P-electrode pads, including one side, two adjacent sides, three adjacent sides, two opposite sides or four sides.

[0074] In an optional implementation of this embodiment, as Figure 3 As shown, Figure 3 A schematic diagram of the semi-finished product structure after completing step S201 in the second embodiment of the present invention is shown, including a substrate 1 and an LED epitaxial wafer 4, wherein a P-electrode pad 32 and an N-electrode pad 31 are provided on the substrate 1, a first bonding metal layer 51 is formed on the substrate 1, the LED epitaxial wafer 4 is bonded to a substrate 41, and a second bonding metal layer 52 is formed. The substrate 41 is a sapphire substrate or a silicon substrate.

[0075] S202, performing thermal compression bonding on the substrate and the LED epitaxial wafer to form a first semi-finished product consisting of the sequentially stacked LED epitaxial wafer, the metal eutectic layer formed by bonding the first bonding metal layer and the second bonding metal layer, and the substrate;

[0076] In an optional implementation of this embodiment, in a vacuum or inert gas environment, the bonding metal layers of the substrate and the LED epitaxial wafer are hot-pressed and bonded on one side, so that the first bonding metal layer and the second bonding metal layer are bonded to form a metal eutectic layer, and finally a first semi-finished product is formed consisting of the LED epitaxial wafers stacked in sequence, the metal eutectic layer formed by bonding the first bonding metal layer and the second bonding metal layer, and the substrate.

[0077] In an optional implementation of this embodiment, after the base plate and the LED epitaxial wafer are thermally pressed to form a first semi-finished product, the substrate on the LED epitaxial wafer is removed.

[0078] Specifically, the substrate on the LED epitaxial wafer is removed by using a laser lift-off or wet etching process.

[0079] In an optional implementation of this embodiment, as Figure 4 As shown, Figure 4 The schematic diagram of the semi-finished product structure after completing step S202 in the second embodiment of the present invention is shown. The substrate 1 and the LED epitaxial wafer 4 are bonded together to form a metal eutectic layer 53 therebetween, and the substrate 41 of the LED epitaxial wafer 4 is removed.

[0080] S203, etching the LED epitaxial wafer and the metal eutectic layer to form a plurality of independent semiconductor layers and P electrodes;

[0081] In an optional implementation of this embodiment, ICP etching (Inductively Coupled Plasmaetching) is used to etch the LED epitaxial wafer to form several independent semiconductor layers, and IBE equipment (Ion Beam Etching) is used to etch the metal eutectic layer to form several independent P electrodes.

[0082] In an optional implementation of this embodiment, before etching the LED epitaxial wafer and the metal eutectic layer, a barrier layer is etched on the LED epitaxial wafer, and after etching to form the semiconductor layer and the P electrode, the barrier layer is removed.

[0083] Specifically, a barrier layer is formed on the LED epitaxial wafer using photoresist or silicon dioxide.

[0084] In an optional implementation of this embodiment, as Figure 5 As shown, Figure 5 The schematic diagram of the semi-finished product structure after completing step S203 in the second embodiment of the present invention is shown, where a plurality of P electrodes 21 and semiconductor layers 22 independently arranged from each other are formed on the substrate 1 .

[0085] Furthermore, a semiconductor layer and a P-electrode are formed at corresponding positions on the P-electrode pad 32 .

[0086] Specifically, when forming the barrier layer, it is selected to be formed directly above the P-electrode pad, and then the LED epitaxial wafer and the metal eutectic layer are etched so that the P-electrode and the semiconductor layer formed by etching are located directly above the P-electrode pad, so that the P-electrode is in contact with the P-electrode pad.

[0087] S204, forming a first insulating layer on the semiconductor layer and the P electrode;

[0088] In an optional implementation of this embodiment, an ALD (Atomic Layer Deposition) preparation method is used to form a first insulating layer on the outer edge area and sidewalls of the top surface of the semiconductor layer and on the sidewalls of the P electrode.

[0089] Specifically, the first insulating layer is made of silicon dioxide or silicon oxide.

[0090] S205, forming an ITO conductive layer on the top surface of the semiconductor layer;

[0091] In an optional implementation of this embodiment, an ITO conductive layer is prepared on the top surface of the semiconductor layer, that is, on the surface of the light-emitting surface.

[0092] S206, forming an N electrode on the top surface and sidewalls of the semiconductor layer, on the sidewalls of the P electrode, and on the substrate;

[0093] In an optional implementation of this embodiment, a metal electrode is prepared as an N electrode on the surface of the ITO conductive layer on the top surface of the semiconductor layer, on the side wall of the semiconductor layer and on the surface of the first insulating layer on the side wall of the P electrode, and on the substrate by a preparation method of magnetron sputtering or electron beam evaporation. The material of the N electrode adopts a multi-layer metal structure, such as Cr-Ti / Al / Ti / Al / Ti / Al / Pt.

[0094] The N electrode is formed here, which has three main functions: 1. The N electrode is coated on the side wall of the semiconductor layer. As a metal electrode layer, it has a reflective effect and can be used as a light blocking layer to block the side light, thereby avoiding the problem of cross-light between adjacent pixels. 2. The N electrode is coated on the semiconductor layer as the light-emitting layer of the chip, which can increase the light reflection efficiency and improve the light extraction efficiency. 3. The N electrode extends and connects to the substrate, forming a metal grid on it, which can reduce the electrode resistivity, increase the conductivity of the N electrode, improve the uniformity of current transmission in the chip array, and achieve the effect of current homogenization.

[0095] S207 , forming a second insulating layer on the surface of the N electrode.

[0096] In an optional implementation of this embodiment, an ALD preparation method is used to form a second insulating layer on the surface of the N-electrode, and the second insulating layer covers the N-electrode.

[0097] Specifically, the first and second insulation layers are made of silicon dioxide or silicon oxide.

[0098] In an optional implementation of this embodiment, as Figure 6 As shown, Figure 6 A schematic diagram of the finished structure of the chip array in Example 2 of the present invention is shown, in which a first insulating layer 25, an ITO conductive layer 24, an N electrode 23 and a second insulating layer 26 are formed on the several P electrodes 21 and the semiconductor layer 22 on the substrate 1, forming a chip array consisting of several chip structures 2, the substrate 1 and the P electrode pads 32 and the N electrode pads 31 on the substrate 1.

[0099] In summary, embodiment 2 of the present invention provides a method for manufacturing a chip array, which forms a chip array by bonding a substrate and an LED epitaxial wafer and then performing a series of preparation processes, thereby avoiding the high-precision alignment problem of directly bonding the chip array to the substrate, and effectively improving the manufacturing efficiency and manufacturing accuracy of the chip array; the manufactured chip array simplifies the structural design of the existing chip array and the light-emitting module by setting a chip structure composed of a plurality of P electrodes, semiconductor layers and N electrodes stacked in sequence, based on the design of the N-electrode extension connection structure of adjacent chip structures, and the chip array composed of electrode pads opened on the substrate, and effectively optimizes the light output effect and light output efficiency of the light-emitting module chip structure.

[0100] Example 3

[0101] Embodiment 3 of the present invention provides a light-emitting module, which includes the chip array, transition carrier, dam, packaging layer, phosphor film, and flat layer described in embodiment 1; the chip array is arranged on the transition carrier, the dam is covered around the chip array, the phosphor film and flat layer are arranged above the chip array, and the packaging layer is covered around the dam.

[0102] In an optional implementation of this embodiment, as Figure 7 As shown, Figure 7 A cross-sectional structural diagram of the light-emitting module in embodiment 3 of the present invention is shown, wherein the light-emitting module includes a chip array 6, a transition carrier 71, a dam 72, an encapsulation layer 73, a phosphor film 74, and a flat layer 75; the chip array 6 is arranged on the transition carrier 71, the dam 72 is covered around the chip array 6, the phosphor film 74 and the flat layer 75 are arranged above the chip array 6, and the encapsulation layer 73 is covered around the dam 72.

[0103] In an optional implementation of this embodiment, the material of the transition carrier 71 is AlN aluminum nitride.

[0104] Furthermore, the thermal expansion coefficient of the transition carrier 71 is between that of the upper CMOS substrate and the lower PCB board.

[0105] The material of the transition carrier is aluminum nitride. Due to its thermal expansion coefficient, it can solve the problem of thermal expansion coefficient mismatch between the CMOS silicon substrate located on the upper layer and the PCB board located on the lower layer. It also serves as a transfer carrier to realize the conversion of wire bonding mode to BGA solder point connection mode, which facilitates the integrated design with the lower PCB board and optimizes the structure of the entire device.

[0106] In an optional implementation of this embodiment, the dam 72 is made of transparent silicone, and the flat layer 75 is made of transparent silicone.

[0107] Specifically, the dam 72 is used to cover and protect the chip structure in the chip array 6 , and the flat layer 75 is used to flatten the surface of the chip array 6 , making it easier to attach the phosphor film 74 to the surface of the chip array 6 .

[0108] In an optional implementation of this embodiment, the phosphor film 74 is a YAG film or a nitride yellow phosphor film.

[0109] Specifically, the phosphor film 74 is used to convert the blue light emitted by the chip into white light, and at the same time can converge the light to avoid the problem of cross-light.

[0110] In an optional implementation of this embodiment, the encapsulation layer 73 is black silica gel doped with carbon powder.

[0111] Specifically, the encapsulation layer 73 is used to protect the reliability of the light-emitting module.

[0112] In summary, the third embodiment of the present invention provides a light-emitting module, including the chip array in the first embodiment, which simplifies the electrical connection structure of the light-emitting module and effectively optimizes the light-emitting effect and efficiency of the chip structure of the light-emitting module.

[0113] The above is a detailed introduction to a chip array and a light-emitting module provided by the present invention. A person skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the relevant hardware through a program. The program can be stored in a computer-readable storage medium, and the storage medium may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0114] In addition, the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A chip array, characterized in that: The chip array includes a substrate and a plurality of chip structures, wherein the plurality of chip structures are arranged in an array on the substrate; The substrate is provided with a plurality of electrode pads, the plurality of electrode pads are arranged in an array, and the plurality of electrode pads include a plurality of P-electrode pads and a plurality of N-electrode pads; Any one of the chip structures includes: a P electrode, a semiconductor layer and an N electrode, the P electrode is arranged on the substrate and pressed onto the corresponding P electrode pad, the semiconductor layer is arranged on the top surface of the P electrode, the N electrode is arranged on the top surface of the semiconductor layer, and the N electrode is arranged on the side walls of the semiconductor layer and the P electrode, and the N electrode extends on the substrate and is pressed onto the corresponding N electrode pad.

2. The chip array according to claim 1, wherein: The P electrodes of the plurality of chip structures are independently arranged; The N electrodes of the plurality of chip structures extend on the substrate and are electrically connected to each other.

3. The chip array according to claim 1, wherein: The chip structure further includes a first insulating layer, which is arranged on the top surface and sidewalls of the semiconductor layer, and the first insulating layer is arranged on the sidewalls of the P electrode; The first insulating layer is disposed between the P-electrode and the N-electrode, and the first insulating layer is disposed between the semiconductor layer and the N-electrode.

4. The chip array according to claim 1, wherein: The chip structure further includes an ITO conductive layer, which is arranged on the top surface of the semiconductor layer and between the N electrode and the semiconductor layer.

5. The chip array according to claim 1, wherein: The chip structure further includes a second insulating layer, which covers the surface of the N-electrode.

6. The chip array according to claim 1, wherein: The plurality of N-electrode pads are arranged on at least one side of the plurality of P-electrode pads.

7. The chip array according to claim 1, wherein: The substrate is a CMOS substrate.

8. A light emitting module, characterized in that: The light-emitting module comprises the chip array according to any one of claims 1 to 7, a transition carrier, a dam, an encapsulation layer, a phosphor film, and a flat layer; The chip array is arranged on the transition carrier, the dam covers the four sides of the chip array, the phosphor film and the flat layer are arranged above the chip array, and the packaging layer covers the four sides of the dam.

9. The light emitting module according to claim 8, wherein: The material of the transition carrier is aluminum nitride.

10. The light emitting module according to claim 8, wherein: The dam is made of transparent silicone and the flat layer is made of transparent silicone.

11. The light emitting module according to claim 8, wherein: The phosphor film is a YAG film or a nitride yellow phosphor film.

12. The light emitting module according to claim 8, wherein: The packaging layer is black silica gel mixed with carbon powder.

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