Circuit board and semiconductor package including same

Abstract

An embodiment includes: a first insulating layer having a via; the insulating component is arranged in the through hole; a first through electrode disposed within the through hole, and surrounding at least a portion of the insulating member; and a first wiring electrode that is provided on the first insulating layer. Here, the first insulating layer is a core layer having a thickness of 150 [mu] m to 600 [mu] m, and the first wiring electrode includes: a pad electrode overlapping the first through electrode and the insulating member in a vertical direction; and a connection electrode that is connected to the pad electrode and does not overlap the first through electrode and the insulating member in the vertical direction.

Description

Technical Field

[0001] One embodiment relates to a circuit board, and more particularly, to a circuit board including a fine circuit pattern formed through a via capping process and a semiconductor package including the circuit board. Background Art

[0002] Semiconductor packages have a structure in which at least one chip is mounted on a circuit board. The increasing demand for high functionality and integration of electronic devices necessitates high density circuit boards used in semiconductor packages. Furthermore, these circuit boards often have a multilayer structure.

[0003] Product groups to which a circuit board having a multilayer structure is applied include FCBGA (Flip Chip Ball Grid Array) and FCCSP (Flip Chip - Chip Scale Package). A circuit board applied to FCBGA or FCCSP may include a core layer.

[0004] The core layer has a thickness of 150 μm or more to achieve multi-layer stacking.

[0005] Furthermore, the core layer includes through electrodes for electrical connection between wiring electrodes located on different layers.

[0006] The wiring electrodes disposed on the upper and / or lower surfaces of the core layer are formed using a semi-additive process (SAP), a modified semi-additive process (MSAP), or a capping process.

[0007] When the wiring electrodes are formed using the SAP and / or MSAP process, the product price increases due to the need for a relatively expensive copper layer. In addition, when the wiring electrodes are formed using the SAP and / or MSAP process, a seed layer etching process must be included as a final step, which complicates the manufacturing process.

[0008] Furthermore, when forming wiring electrodes using the capping process, the circuit line width is lost during the metal layer etching step, making it difficult to pulverize the winding electrodes. This loss in circuit line width means a large difference in width between the upper and lower surfaces of the wiring electrodes.

[0009] Therefore, when wiring electrodes are formed on the upper and / or lower surfaces of the core layer using the capping process, the wiring electrodes only include pads connected to the through electrodes and the dummy electrodes. In other words, due to the difficulty in miniaturization, the wiring electrodes formed on the upper and / or lower surfaces of the core layer may not include circuit wiring, such as traces.

[0010] (Patent Document 1) KR 10-2014-0046225 A Summary of the Invention

[0011] [Technical Issues]

[0012] One embodiment provides a circuit board having a novel structure and a semiconductor package including the same.

[0013] Furthermore, the present embodiment provides: a circuit board including wiring electrodes manufactured using a capping process; and a semiconductor package including the circuit board.

[0014] Furthermore, the present embodiment provides: a circuit board including wiring electrodes having traces provided on an upper surface and / or a lower surface of a core layer; and a semiconductor package including the circuit board.

[0015] Furthermore, the present embodiment provides a circuit board with improved circuit integration and a semiconductor package including the circuit board.

[0016] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the proposed embodiments pertain from the following description.

[0017] [Technical solution]

[0018] According to one embodiment, a circuit board includes: a core layer; a first wiring electrode, which is arranged on the core layer; a stacked insulating layer, which is arranged on the first wiring electrode; and a second wiring electrode, which is arranged on the stacked insulating layer, wherein the second wiring electrode has an inclination angle that reduces its width in the horizontal direction along the vertical direction from the upper surface of the second wiring electrode toward the lower surface of the second wiring electrode.

[0019] Furthermore, the first wiring electrode has an inclination angle different from an inclination angle of the second wiring electrode.

[0020] Furthermore, the inclination angle of the first wiring electrode is inclined in a direction different from the inclination angle of the second wiring electrode.

[0021] Furthermore, the first wiring electrode has an inclination angle such that the width increases in the horizontal direction along the vertical direction.

[0022] In addition, the core layer has a thickness of 150μm to 600μm, and wherein the first wiring electrode includes: a pad electrode, which overlaps with the first through electrode and the insulating member in the vertical direction; and a connecting electrode, which is connected to the pad electrode and does not overlap with the first through electrode and the insulating member in the vertical direction.

[0023] In addition, the width of the upper surface of the connection electrode satisfies the range of 90% to 99% of the width of the lower surface of the connection electrode.

[0024] In addition, a first inner angle between the upper surface of the connecting electrode and the side surface of the connecting electrode satisfies the range of 91° to 100°, and wherein a second inner angle between the lower surface of the connecting electrode and the side surface of the connecting electrode satisfies the range of 80° to 89°.

[0025] Furthermore, the connection electrode includes a plurality of connection electrode patterns spaced apart from each other in the horizontal direction, and wherein a pitch between two adjacent connection electrode patterns among the plurality of connection electrode patterns satisfies a range of 5 μm to 30 μm.

[0026] Furthermore, an internal angle between an upper surface of the second wiring electrode and a side surface of the second wiring electrode is an acute angle, and wherein an internal angle between a lower surface of the second wiring electrode and a side surface of the second wiring electrode is an obtuse angle.

[0027] Furthermore, the core layer includes a through hole, and wherein a width of the through hole in the horizontal direction satisfies a range of 80 μm to 500 μm.

[0028] Furthermore, the circuit board further includes an insulating member disposed in the through hole; and a first through electrode surrounding at least a portion of the insulating member.

[0029] At the same time, according to one embodiment, a circuit board includes: a first insulating layer, the first insulating layer having a through hole; an insulating member, the insulating member being arranged in the through hole; a first through electrode, the first through electrode being arranged in the through hole and surrounding at least a portion of the insulating member; and a first wiring electrode, the first wiring electrode being arranged on the first insulating layer, wherein the first insulating layer is a core layer having a thickness of 150μm to 600μm, and the first wiring electrode includes a pad electrode, the pad electrode overlaps with the first through electrode and the insulating member in a vertical direction; and a connecting electrode, the connecting electrode is connected to the pad electrode and does not overlap with the first through electrode and the insulating member in the vertical direction.

[0030] In addition, the width of the upper surface of the connecting electrode is smaller than the width of the lower surface of the connecting electrode.

[0031] In addition, the width of the lower surface of the connection electrode satisfies the range of 5 μm to 30 μm.

[0032] In addition, the width of the upper surface of the connection electrode satisfies the range of 90% to 99% of the width of the lower surface of the connection electrode.

[0033] In addition, a first inner angle between an upper surface of the connection electrode and a side surface of the connection electrode ranges from 91° to 100°, and a second inner angle between a lower surface of the connection electrode and a side surface of the connection electrode ranges from 80° to 89°.

[0034] In addition, the connection electrode includes a plurality of connection electrode patterns spaced apart from each other in a horizontal direction, and a pitch between two adjacent connection electrode patterns among the plurality of connection electrode patterns satisfies a range of 5 μm to 30 μm.

[0035] In addition, the connection electrode has a thickness of 15 μm to 30 μm.

[0036] In addition, the etching factor of the connection electrode satisfies the range of 10 to 60, and the etching factor is calculated as "thickness of the connection electrode / ((width of the lower surface of the connection electrode-width of the upper surface of the connection electrode) / 2)".

[0037] In addition, the circuit board includes: a second insulating layer, which is arranged on the first insulating layer; and a second wiring electrode, which is arranged on the second insulating layer, wherein the inclination angle of the side surface of the second wiring electrode is inclined in a direction different from the inclination angle of the side surface of the connecting electrode.

[0038] Furthermore, the width of the upper surface of the second wiring electrode is larger than the width of the lower surface of the second wiring electrode.

[0039] In addition, an internal angle between an upper surface of the second wiring electrode and a side surface of the second wiring electrode is an acute angle, and an internal angle between a lower surface of the second wiring electrode and a side surface of the second wiring electrode is an obtuse angle.

[0040] Furthermore, the width of the through hole in the horizontal direction satisfies the range of 80 μm to 500 μm.

[0041] Meanwhile, a semiconductor package according to an embodiment includes: a first insulating layer having a through hole; an insulating member disposed in the through hole; a first through electrode disposed in the through hole and surrounding at least a portion of the insulating member; a first wiring electrode disposed on the first insulating layer; at least one second insulating layer disposed on the first insulating layer; a second wiring electrode disposed on the at least one second insulating layer; a conductive bonding portion disposed on the second wiring electrode; a connecting portion disposed on the conductive bonding portion; and a semiconductor device disposed on the connecting portion, wherein the first insulating layer is a core layer and the core The layer has a thickness of 150μm to 600μm, the first wiring electrode includes a pad electrode, the pad electrode overlaps with the first through electrode and the insulating member in the vertical direction; and a connecting electrode, the connecting electrode is connected to the pad electrode and does not overlap with the first through electrode and the insulating member in the vertical direction, wherein the width of the upper surface of the connecting electrode is smaller than the width of the lower surface of the connecting electrode, the width of the lower surface of the connecting electrode satisfies the range of 5μm to 30μm, the width of the upper surface of the connecting electrode satisfies the range of 90% to 99% of the width of the lower surface of the connecting electrode, and the connecting electrode includes a plurality of connecting electrode patterns spaced apart from each other in the horizontal direction, and the spacing between two adjacent connecting electrode patterns in the plurality of connecting electrode patterns satisfies the range of 5μm to 30μm.

[0042] In addition, the inclination angle of the side surface of the second wiring electrode is inclined in a direction different from the inclination angle of the side surface of the connecting electrode, the width of the upper surface of the second wiring electrode is greater than the width of the lower surface of the second wiring electrode, the internal angle between the upper surface of the second wiring electrode and the side surface of the second wiring electrode is an acute angle, and the internal angle between the lower surface of the second wiring electrode and the side surface of the second wiring electrode is an obtuse angle.

[0043] Furthermore, the semiconductor device includes a plurality of semiconductor devices spaced apart in a horizontal direction, and the semiconductor package further includes a connection member embedded in the first insulating layer and electrically connecting the plurality of semiconductor devices horizontally.

[0044] [Beneficial Effects]

[0045] One embodiment includes: a first insulating layer having a through-hole; an insulating member disposed in the through-hole; a first through-electrode disposed in the through-hole and surrounding at least a portion of the insulating member; and a first wiring electrode disposed on the first insulating layer. The first insulating layer is a core layer having a thickness of 150 μm to 600 μm, and the first wiring electrode includes: a pad electrode vertically overlapping the first through-electrode and the insulating member; and a connecting electrode connected to the pad electrode and not vertically overlapping the first through-electrode and the insulating member.

[0046] In addition, the width of the upper surface of the connecting electrode is smaller than the width of the lower surface of the connecting electrode, the width of the lower surface of the connecting electrode satisfies the range of 5μm to 30μm, and the width of the upper surface of the connecting electrode satisfies the range of 90% to 99% of the width of the lower surface of the connecting electrode.

[0047] That is, the first wiring electrode of the present embodiment is manufactured using the capping process and includes a connection electrode in addition to the pad electrode.

[0048] That is, since the first wiring electrodes are manufactured using the capping process, this embodiment can simplify the process compared to wiring electrodes manufactured using the MSAP and / or SAP process, thereby significantly reducing the unit cost of the circuit board.

[0049] Furthermore, since the first wiring electrode is manufactured using the capping process and includes the connection electrode, this embodiment can improve circuit integration of the circuit board, thereby miniaturizing the circuit board and the semiconductor package.

[0050] Specifically, in the comparative example compared to the present embodiment, when the first wiring electrode was manufactured using the capping process, a difference occurred between the width of the upper surface and the width of the lower surface of the electrode pattern during the etching process of the first wiring electrode. Therefore, due to this difference, the width of the electrode pattern and the spacing between adjacent electrode patterns increased.

[0051] For example, when the electrode pattern is manufactured using the capping process of the comparative example, the width of the electrode pattern exceeds at least 35 μm, and the spacing between adjacent electrode patterns exceeds at least 35 μm. This is because the difference between the width of the upper surface and the width of the lower surface of the electrode pattern must be considered.

[0052] In contrast, this embodiment uses an etchant with an anisotropic etching structure to manufacture the first wiring electrode. This minimizes the difference between the width of the upper surface and the width of the lower surface of the connection electrode of the first wiring electrode. Therefore, this embodiment can improve circuit integration by including connection electrodes such as traces in the first wiring electrode, thereby enabling miniaturization of circuit boards and semiconductor packages.

[0053] Furthermore, the present embodiment can improve the degree of freedom in wiring design of the circuit board by including the connection electrode in the first wiring electrode, thereby improving user satisfaction.

[0054] Furthermore, by including connection electrodes in the first wiring electrodes, the present embodiment can easily control the wiring density of the first wiring electrodes 121. Thus, the present embodiment can adjust the wiring density of the first wiring electrodes by taking into account the warping direction of the circuit board, thereby resolving the reliability issue of the circuit board and semiconductor package significantly warping in a specific direction.

[0055] Furthermore, this embodiment can utilize the connection electrode of the first wiring electrode as a heat transfer path serving as a heat dissipation path, thereby improving the heat dissipation characteristics of the circuit board and the semiconductor package.

[0056] Therefore, this embodiment can allow the semiconductor device attached to the circuit board to operate stably, thereby allowing electronic products such as servers to which the semiconductor package is applied to operate stably. Thus, this embodiment can improve product satisfaction and product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a cross-sectional view showing a circuit board according to an embodiment.

[0058] Figure 2 yes Figure 1 Magnified view of the inner region.

[0059] Figure 3 It shows Figure 2 Floor plan of the inner area.

[0060] Figure 4 It shows Figure 2 An enlarged view of the connection pattern of the first wiring electrode.

[0061] Figure 5 1 is a cross-sectional view showing a connection pattern of first wiring electrodes compared with the embodiment.

[0062] Figure 6 It shows Figure 1 An enlarged view of the connection pattern of the second wiring electrode.

[0063] Figure 7is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0064] Figure 8 is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0065] Figures 9 to 19 It is shown in the order of the process Figure 1 sectional view of the method for manufacturing a circuit board shown in . DETAILED DESCRIPTION

[0066] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0067] However, the spirit and scope of the present invention are not limited to part of the described embodiments and may be implemented in various other forms, and one or more elements of the embodiments may be selectively combined and replaced within the spirit and scope of the present invention.

[0068] In addition, unless otherwise clearly defined and described, the terms (including technical and scientific terms) used in the embodiments of the present invention can be understood to have the same meaning as that commonly understood by ordinary technicians in the field to which the present invention belongs, and terms (such as those defined in commonly used dictionaries) can be interpreted as having a meaning consistent with their meaning in the context of the relevant field. In addition, the terms used in the embodiments of the present invention are used to describe the embodiments and are not intended to limit the present invention.

[0069] In this specification, a singular form may also include a plural form unless otherwise stated in a phrase, and may include at least one of all combinations that can be combined in A, B, and C when described in “at least one (or more) of A and / or B, C.” In addition, when describing elements of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used.

[0070] These terms are only used to distinguish these elements from other elements, and the terms are not limited to the nature, order or sequence of the elements. In addition, when an element is described as being "connected," "coupled" or "connected" to another element, it can include not only when the element is directly "connected," "coupled" or "connected" to the other element, but also when the element is "connected," "coupled" or "connected" through another element between the element and the other element.

[0071] In addition, when it is described as being formed or disposed “on (above)” or “under (below)” each element, “on (above)” or “under (below)” may include not only when two elements are directly connected to each other but also when one or more other elements are formed or disposed between the two elements. In addition, when expressed as “on (above)” or “under (below)”, it may include not only an upper direction but also a lower direction based on one element.

[0072] -Electronic devices-

[0073] Before describing the embodiments, we will briefly describe an electronic device to which the semiconductor package of the embodiments is applied. The electronic device includes a motherboard (not shown). The motherboard can be physically and / or electrically connected to various components. For example, the motherboard can be connected to the semiconductor package of the embodiments. Various semiconductor devices can be mounted on the semiconductor package.

[0074] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs), in which hundreds to millions of devices are integrated into a single semiconductor device. Semiconductor devices may include logic chips, memory chips, and the like. Logic chips may include central processing units (CPUs), graphics processing units (GPUs), and the like. For example, a logic chip may include an application processor (AP) chip that includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, an analog-to-digital converter, an application-specific integrated circuit (ASIC), and the like, or a chipset that includes a specific combination of those listed thus far.

[0075] The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, etc.

[0076] On the other hand, the product group to which the semiconductor package of this embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip - chip scale package), FC-BGA (flip chip ball grid array), POP (package on package) and SIP (system in package), but is not limited thereto.

[0077] In addition, the electronic device may be a smartphone, a personal digital assistant, a digital camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game, a smart watch, a car, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0078] -Circuit Board-

[0079] Figure 1 is a sectional view showing a circuit board according to an embodiment, Figure 2 yes Figure 1 A magnified view of the inner region of Figure 3 It shows Figure 2 The floor plan of the inner area, Figure 4 It shows Figure 2 An enlarged view of the connection pattern of the first wiring electrode, Figure 5 is a cross-sectional view showing a connection pattern of a first wiring electrode compared with the embodiment, and Figure 6 It shows Figure 1 An enlarged view of the connection pattern of the second wiring electrode.

[0080] In the following, reference will be made to Figures 1 to 6 A circuit board according to an embodiment is described in detail.

[0081] refer to Figure 1 The circuit board allows for attachment of at least one semiconductor device. Furthermore, the circuit board can be coupled to an external substrate. For example, the external substrate can be a mainboard of an electronic device, such as a motherboard. Furthermore, the external substrate can be a separate memory package including a memory device, or it can be an interposer connecting a memory package of an embodiment to the circuit board.

[0082] The circuit board includes an insulating layer 110. The insulating layer 110 may be formed of a plurality of layers.

[0083] In one embodiment, Figure 1 As shown in FIG, the insulating layer 110 may have a five-layer structure, but the embodiment is not limited thereto. For example, in other embodiments, the insulating layer 110 may have a layer structure of four or fewer layers or six or more layers.

[0084] The circuit board of this embodiment may be a core board, and thus, at least one of the plurality of layers of the insulating layer 110 may be provided as a core layer.

[0085] For example, the insulating layer 110 may include a first insulating layer 111. The first insulating layer 111 may be a core layer. The first insulating layer 111 may be a rigid insulating member. Preferably, the first insulating layer 111 may be a copper clad laminate (CCL).

[0086] In particular, a CCL is a substrate typically used to manufacture circuit boards. It is a laminate composed of copper foil laminated onto an insulating layer. Depending on the intended use, CCLs can include glass / epoxy CCLs, heat-resistant resin CCLs, paper / phenol CCLs, high-frequency CCLs, flexible CCLs (e.g., polyimide film), and composite CCLs. The first insulating layer 111 of this embodiment may be a glass / epoxy copper-clad laminate used in the production of double-sided and multilayer circuit boards, but is not limited thereto.

[0087] This glass / epoxy copper-clad laminate includes a reinforcing substrate made by impregnating glass fiber or organic fiber with epoxy resin and copper foil. Glass / epoxy copper-clad laminates are classified according to the reinforcing substrate. For example, glass / epoxy copper-clad laminates are classified into grades (such as FR-1 to FR-5) according to standards set by the National Electrical Manufacturers Association (NEMA) based on the reinforcing substrate and heat resistance. Generally, FR-4 is the most commonly used among the FR-1 to FR-5 grades, but recently, demand for FR-5 with improved glass transition temperature (Tg) characteristics has also been increasing.

[0088] The first insulating layer 111 may have a certain thickness (T1, see Figure 2 At this time, the thickness T1 of the first insulating layer 111 may be greater than 150 μm, or greater than 200 μm, or greater than 300 μm, or greater than 400 μm.

[0089] For example, the thickness T1 of the first insulating layer 111 may be within a range of 150 μm to 600 μm. For example, the thickness T1 of the first insulating layer 111 may be within a range of 200 μm to 580 μm. For example, the thickness T1 of the first insulating layer 111 may be within a range of 250 μm to 550 μm.

[0090] If the thickness T1 of the first insulating layer 111 is less than 150 μm, the rigidity and warpage characteristics of the circuit board may deteriorate. In addition, if the thickness of the first insulating layer 111 exceeds 600 μm, the thickness of the circuit board increases, making it difficult to miniaturize the semiconductor package.

[0091] The stacking insulating layer may be disposed above and below the first insulating layer 111. In this case, the upper stacking insulating layer disposed on the first insulating layer 111 and the lower stacking insulating layer disposed below the first insulating layer 111 may have a symmetrical structure with respect to the first insulating layer 111, but is not limited thereto.

[0092] In one embodiment, the number of upper buildup insulating layers disposed on the first insulating layer 111 may be the same as the number of lower buildup insulating layers disposed under the first insulating layer 111 .

[0093] In another embodiment, the number of layers of the upper stacked insulating layer disposed on the first insulating layer 111 and the number of layers of the lower stacked insulating layer disposed under the first insulating layer 111 may be different.

[0094] The second insulating layer 112 and the third insulating layer 113 may be disposed on the first insulating layer 111. In addition, the fourth insulating layer 114 and the fifth insulating layer 115 may be disposed under the first insulating layer 111.

[0095] The second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115 may include an insulating material different from the insulating material of the first insulating layer 111. For example, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115 may not include a reinforcing member such as glass fiber that is present in the first insulating layer 111.

[0096] For example, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115 may be formed of a material including an inorganic filler and an insulating resin. For example, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115 may include a structure in which an inorganic filler (such as silicon dioxide or aluminum oxide) is dispersed in a thermosetting resin (such as epoxy resin) or a thermoplastic resin (such as polyimide). For example, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115 may include ABF (Ajinomoto Build-up Film), BT (Bismaleimide Triazine), and PID (Photo Imageable Dielectric Resin).

[0097] The circuit board includes an electrode portion, which includes a wiring electrode 120 and a through electrode 130 .

[0098] The wiring electrode 120 may refer to an electrode pattern, such as a pad and / or a trace, provided on the upper surface and / or lower surface of each of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115. In addition, the through electrode 130 may refer to a via electrode that penetrates at least one of the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, and the fifth insulating layer 115.

[0099] The wiring electrode 120 may include a first wiring electrode 121 , a second wiring electrode 122 , a third wiring electrode 123 , a fourth wiring electrode 124 , a fifth wiring electrode 125 , and a sixth wiring electrode 126 .

[0100] The first wiring electrode 121 may be provided on the upper surface of the first insulating layer 111. The second wiring electrode 122 may be provided on the upper surface of the second insulating layer 122. The third wiring electrode 123 may be provided on the upper surface of the third insulating layer 113. The fourth wiring electrode 124 may be provided on the lower surface of the first insulating layer 111. The fifth wiring electrode 125 may be provided on the lower surface of the fourth insulating layer 114. The sixth wiring electrode 126 may be provided on the lower surface of the fifth insulating layer 115.

[0101] At least one of the first wiring electrode 121 , the second wiring electrode 122 , the third wiring electrode 123 , the fourth wiring electrode 124 , the fifth wiring electrode 125 , and the sixth wiring electrode 126 may be manufactured using a method different from that of at least one of the other wiring electrodes.

[0102] For example, the first and fourth wiring electrodes 121 and 124 provided on the surface of the first insulating layer 111 may be manufactured using a manufacturing method different from the manufacturing method of the second, third, fifth, and sixth wiring electrodes 122 , 123 , 125 , and 126 .

[0103] Specifically, the first wiring electrode 121 and the fourth wiring electrode 124 may be manufactured using a capping process. For example, the first wiring electrode 121 and the fourth wiring electrode 124 may be formed by forming a metal layer on a copper foil layer and then removing the copper foil layer and the metal layer by etching.

[0104] Second wiring electrode 122, third wiring electrode 123, fifth wiring electrode 125, and sixth wiring electrode 126 can be manufactured using a modified semi-additive process (MSAP) and / or a semi-additive process (SAP). For example, second wiring electrode 122, third wiring electrode 123, fifth wiring electrode 125, and sixth wiring electrode 126 can be formed by forming a circuit pattern corresponding to the wiring electrodes on a seed layer and then removing the seed layer by etching. In this case, the seed layer may optionally include a copper foil layer, depending on the manufacturing method.

[0105] In this embodiment, the first and fourth wiring electrodes 121 and 124 each include pad electrodes 121P and 124P connected to the through-electrode 130. Furthermore, each of the first and fourth wiring electrodes 121 and 124 includes connecting electrodes 121T and 124T connected to the pad electrodes 121P and 124P. That is, this embodiment manufactures the first and fourth wiring electrodes 121 and 124 using a capping process, providing the first and fourth wiring electrodes 121 and 124 with the connecting electrodes 121T and 124T and the pad electrodes 121P and 124P. In this embodiment, the pad electrodes 121P and 124P may vertically overlap with the first through-electrode 131 and the insulating member 140, while the connecting electrodes 121T and 124T may vertically not overlap with the first through-electrode 131 and the insulating member 140.

[0106] That is, in this embodiment, since the first wiring electrode 121 and the fourth wiring electrode 124 are manufactured using the capping process, the process can be simplified compared to wiring electrodes manufactured using the MSAP and / or SAP method, thereby greatly reducing the unit cost of the circuit board.

[0107] Furthermore, in this embodiment, since the first and fourth wiring electrodes 121 and 124 are manufactured using the capping process and include the connection electrodes 121T and 124T, circuit integration of the circuit board can be improved, thereby miniaturizing the circuit board and the semiconductor package.

[0108] Specifically, in the comparative example compared to the embodiment, when the first and fourth wiring electrodes were manufactured using the capping process, a difference in the upper and lower surface widths of the electrode patterns occurred during the etching process of each of the first and fourth wiring electrodes. Consequently, due to this difference, the width of the electrode patterns and the spacing between adjacent electrode patterns increased.

[0109] For example, when the electrode pattern is manufactured using the capping process of the comparative example, the width of the electrode pattern exceeds at least 35 μm, and the spacing between adjacent electrode patterns exceeds at least 35 μm. This is because the difference between the upper and lower widths of the electrode pattern must be considered.

[0110] In contrast, this embodiment uses an etchant with an anisotropic etching structure to manufacture the first wiring electrode 121 and the fourth wiring electrode 124. Thus, this embodiment can minimize the difference between the upper and lower widths of the connection electrodes 121T and 124T of the first wiring electrode 121 and the fourth wiring electrode 124. Therefore, the widths of the connection electrodes 121T and 124T of this embodiment can be 30 μm or less, 25 μm or less, 20 μm or less, 15 μm or less, or 10 μm or less, and the spacing between adjacent connection electrodes can be 30 μm or less, 25 μm or less, 20 μm or less, 15 μm or less, or 10 μm or less.

[0111] Therefore, this embodiment can improve circuit integration by providing the first wiring electrode 121 and the fourth wiring electrode 124 with the trace-shaped connection electrodes 121T and 124T, thereby enabling miniaturization of a circuit board and a semiconductor package.

[0112] Furthermore, the present embodiment can improve the degree of freedom of circuit board wiring design by providing the first wiring electrode 121 and the fourth wiring electrode 124 with the connection electrodes 121T and 124T, thereby improving user satisfaction.

[0113] Furthermore, since this embodiment includes connection electrodes 121T and 124T for first and fourth wiring electrodes 121 and 124, the wiring density of each of first and fourth wiring electrodes 121 and 124 (e.g., the planar area of ​​first and fourth wiring electrodes 121 and 124) can be easily adjusted. Therefore, this embodiment can adjust the wiring density of first and fourth wiring electrodes 121 and 124 by taking into account the warping direction of the circuit board, thereby resolving reliability issues associated with circuit boards and semiconductor packages that significantly bend in a particular direction.

[0114] Furthermore, the present embodiment can utilize the connection electrodes 121T and 124T of the first wiring electrode 121 and the fourth wiring electrode 124 as heat transfer paths for heat dissipation, thereby improving heat dissipation characteristics of the circuit board and the semiconductor package.

[0115] Thus, the present embodiment can ensure that the semiconductor device attached to the circuit board operates stably, and therefore, electronic products such as servers to which the semiconductor package is applied can operate stably. Thus, the present embodiment can improve product satisfaction and product reliability.

[0116] Each of the first wiring electrode 121 and the fourth wiring electrode 124 may have a thickness (T2, see Figure 2For example, each of the first wiring electrode 121 and the fourth wiring electrode 124 may have a thickness T2 in the range of 17 μm to 28 μm. For example, each of the first wiring electrode 121 and the fourth wiring electrode 124 may have a thickness T2 in the range of 18 μm to 25 μm.

[0117] If the thickness T2 of each of the first and fourth wiring electrodes 121 and 124 is less than 15 μm, it may be difficult to manufacture the first and fourth wiring electrodes 121 and 124 using a capping process. If the thickness T2 of each of the first and fourth wiring electrodes 121 and 124 is less than 15 μm, it may be difficult to form an electrode pattern having a uniform thickness on the surface of the first insulating layer 111 corresponding to the core layer, and thus the electrical characteristics of the circuit board and the semiconductor package may be degraded. If the thickness T2 of each of the first and fourth wiring electrodes 121 and 124 exceeds 30 μm, it may be difficult to provide the first and fourth wiring electrodes 121T and 124T with the connection electrodes 121T and 124T.

[0118] Meanwhile, the thicknesses of second wiring electrode 122, third wiring electrode 123, fifth wiring electrode 125, and sixth wiring electrode 126 may correspond to the corresponding thickness T2 of first wiring electrode 121 and fourth wiring electrode 124, but are not limited thereto. For example, the thicknesses of second wiring electrode 122, third wiring electrode 123, fifth wiring electrode 125, and sixth wiring electrode 126 may be less than the corresponding thickness T2 of first wiring electrode 121 and fourth wiring electrode 124.

[0119] In addition, the through electrode 130 may be provided to penetrate each insulating layer.

[0120] For example, the first through electrode 131 may penetrate the first insulating layer 111. The first through electrode 131 can electrically connect the first wiring electrode 121 and the fourth wiring electrode 124.

[0121] The second through electrode 132 can penetrate the second insulating layer 112 . The second through electrode 132 can electrically connect the first wiring electrode 121 and the second wiring electrode 122 .

[0122] The third through electrode 133 can penetrate the third insulating layer 113. The third through electrode 133 can electrically connect the second wiring electrode 122 and the third wiring electrode 123.

[0123] The fourth through electrode 134 can penetrate the fourth insulating layer 114 . The fourth through electrode 134 can electrically connect the fourth wiring electrode 124 and the fifth wiring electrode 125 .

[0124] The fifth through electrode 135 can penetrate the fifth insulating layer 115 . The fifth through electrode 135 can electrically connect the fifth wiring electrode 125 and the third wiring electrode 126 .

[0125] At this time, the inclination angle of the side surface of the first through electrode 131 may be different from the inclination angle of the side surfaces of the second to fifth through electrodes 132, 133, 134, and 135. For example, the inclination angle of the side surface of the first through electrode 131 may be perpendicular to the upper surface or the lower surface of the first insulating layer 111. For example, the width of the first through electrode 131 may not change from the upper surface to the lower surface.

[0126] In contrast, the inclination angle of each side surface of the second to fifth through electrodes 132, 133, 134, and 135 may be inclined at a predetermined inclination angle relative to the upper surface or the lower surface of the first wiring electrode 121. For example, the width of each of the second to fifth through electrodes 132, 133, 134, and 135 may vary from the upper surface to the lower surface.

[0127] However, the present embodiment is not limited thereto. For example, the first through electrode 131 may be formed using a laser method, and in this case, the side surface of the first through electrode 131 may include a plurality of protruding surfaces spaced apart from each other in the vertical direction and protruding in the horizontal direction.

[0128] Furthermore, the wiring electrodes 120 and the through-electrodes 130 may be formed of at least one metal selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Furthermore, the wiring electrodes 120 and the through-electrodes 130 may be formed of a paste or solder paste having excellent bonding strength, the paste or solder paste containing at least one metal selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the wiring electrodes 120 and the through-electrodes 130 may be formed of relatively inexpensive copper (Cu).

[0129] In this embodiment, the first wiring electrode 121 and the fourth wiring electrode 124 are manufactured using a capping process. Therefore, it may be difficult to form a through-electrode that completely fills the through-hole TH of the first insulating layer 111 using an electroplating method. Therefore, the first through-electrode 131 may be formed by partially filling the through-hole TH of the first insulating layer 111.

[0130] Furthermore, the insulating member 140 may be formed in the through hole TH of the first insulating layer 111. The insulating member 140 may be formed in the through hole TH of the first insulating layer 111, and thus the first through electrode 131 may be formed to surround a side of the insulating member 140 filled in the through hole TH.

[0131] The insulating member 140 may include an insulating material. For example, the insulating member 140 may include an insulating ink material. For example, the insulating member 140 may also be referred to as a plugging member.

[0132] Furthermore, the circuit board includes a protective layer.

[0133] A first protective layer 150 is provided on the third insulating layer 113. The first protective layer 150 can protect the upper surface of the third insulating layer 113. In addition, the first protective layer 150 can protect the upper surface of the third wiring electrode 123. The first protective layer 150 may include at least one opening that vertically overlaps with a pad connected to a terminal of a semiconductor device in the third wiring electrode 123.

[0134] Second protective layer 160 is provided below fifth insulating layer 115. Second protective layer 160 can protect the lower surface of fifth insulating layer 115. Furthermore, second protective layer 160 can protect the lower surface of sixth wiring electrode 126. Second protective layer 160 may include at least one opening vertically overlapping a pad of an electrode connected to an external substrate (e.g., a motherboard) in sixth wiring electrode 126.

[0135] The first protective layer 150 and the second protective layer 160 may include an insulating material. The first protective layer 150 and the second protective layer 160 may include various materials that can be applied and then cured by heating to protect the surfaces of the insulating layer and the circuit layer.

[0136] The first protective layer 150 and the second protective layer 160 may be solder resist layers containing an organic polymer material. For example, the first protective layer 150 and the second protective layer 160 may include an epoxy acrylate-based resin. Specifically, the first protective layer 150 and the second protective layer 160 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the present embodiment is not limited thereto, and the first protective layer 150 and the second protective layer 160 may be any one of a photo solder resist layer, a cover layer, and a polymer material.

[0137] The specific structure of first wiring electrode 121 according to this embodiment will be described below. Furthermore, the first wiring electrode 121 of this embodiment and a wiring electrode formed using the capping process of a comparative example will be described below. Furthermore, the difference in shape between first wiring electrode 121 and second wiring electrode 122 will be described below.

[0138] refer to Figures 2 to 4 , the first wiring electrode 121 is located on the upper surface of the first insulating layer 111 , and the fourth wiring electrode 124 is located on the lower surface of the first insulating layer 111 .

[0139] The first wiring electrode 121 includes a pad electrode 121P vertically overlapping the first through electrode 131. In addition, the first wiring electrode 121 includes a connection electrode 121T that electrically connects the plurality of pad electrodes 121P of the first wiring electrode 121. The connection electrode 121T of the first wiring electrode 121 may refer to a trace connected to the pad electrode 121P.

[0140] In addition, the fourth wiring electrode 124 includes a pad electrode 124P that overlaps the first through electrode 131 in the vertical direction and a connection electrode 124T connected to the pad electrode 124P of the fourth wiring electrode 124. At this time, the fourth wiring electrode 124 may have a structure substantially corresponding to that of the first wiring electrode 121, and the following description will be based on the first wiring electrode 121.

[0141] At this time, as described above, the thickness T1 of the first insulating layer 111 may satisfy the range of 150 μm to 600 μm, or 200 μm to 580 μm, or 250 μm to 550 μm.

[0142] In addition, the thickness T2 of the first wiring electrode 120 can satisfy the range of 15 μm to 30 μm, or 17 μm to 28 μm, or 18 μm to 25 μm.

[0143] Here, a through hole TH is provided in the first insulating layer 111. The width W1 of the through hole TH in the horizontal direction can be within a range of 80 μm to 500 μm. For example, the width W1 of the through hole TH in the first insulating layer 111 in the horizontal direction can be within a range of 90 μm to 480 μm. In addition, the width W1 of the through hole TH in the first insulating layer 111 in the horizontal direction can be within a range of 95 μm to 450 μm.

[0144] If the width W1 of the through hole TH of the first insulating layer 111 is less than 80 μm, a reliability problem may occur in that the through hole TH does not penetrate the first insulating layer 111 having the predetermined thickness T1. If the width W1 of the through hole TH of the first insulating layer 111 exceeds 500 μm, the area of ​​the circuit board may increase, making it difficult to miniaturize the circuit board and the semiconductor package, or it may be difficult to provide the connection electrode 121T to the first wiring electrode 120.

[0145] The width W2 of the pad electrode 121P of the first wiring electrode 121 can be determined based on the width W1 of the through hole TH. For example, the width W2 of the pad electrode 121P of the first wiring electrode 121 can be in the range of 1.1 times to 2 times the width W1 of the through hole TH. For example, the width W2 of the pad electrode 121P of the first wiring electrode 121 can be in the range of 1.2 times to 1.8 times the width W1 of the through hole TH. For example, the width W2 of the pad electrode 121P of the first wiring electrode 121 can be in the range of 1.2 times to 1.6 times the width W1 of the through hole TH.

[0146] If the width W2 of the pad electrode 121P of the first wiring electrode 121 is less than 1.1 times the width W1 of the through hole TH, a reliability problem may occur in which the pad electrode 121P is not electrically connected to the first through electrode 131 provided in the through hole TH. If the width W2 of the pad electrode 121P of the first wiring electrode 121 exceeds twice the width W1 of the through hole TH, the area of ​​the circuit board increases, making it difficult to miniaturize the circuit board and the semiconductor package, or it may be difficult to provide the connection electrode 121T to the first wiring electrode 120.

[0147] At this time, the pad electrode 121P of the first wiring electrode 121 may have different widths on the upper and lower surfaces. Preferably, the width of the upper surface of the pad electrode 121P of the first wiring electrode 121 may be smaller than the width of the lower surface of the pad electrode 121P. This may occur because the pad electrode 121P of the first wiring electrode 121 is manufactured using a capping process.

[0148] Here, the pad electrode 121P of the first wiring electrode 121 has a relatively large width W2 compared to the connection electrode 121T. Therefore, the difference between the width of the upper surface of the pad electrode 121P and the width of the lower surface of the pad electrode 121P may not significantly affect the circuit density of the first wiring electrode 121. However, the circuit density of the first wiring electrode 121 is affected by the difference between the width of the upper surface of the connection electrode 121T of the first wiring electrode 121 and the width of the lower surface of the connection electrode 121T. In addition, the difference between the width of the upper surface of the pad electrode 121P of the first wiring electrode 121 and the width of the lower surface of the pad electrode 121P may correspond to the difference between the width of the upper surface of the connection electrode 121T of the first wiring electrode 121 and the width of the lower surface of the connection electrode 121T. Therefore, the difference between the width of the upper surface of the pad electrode 121P of the first wiring electrode 121 and the width of the lower surface of the pad electrode 121P can correspond to the difference between the width W3 of the upper surface of the connection electrode 121T and the width W4 of the lower surface of the connection electrode 121T, which will be described below.

[0149] The first wiring electrode 121 includes a connection electrode 121T.

[0150] At this time, the connection electrode 121T may include a first connection electrode pattern 121T1 and a second connection electrode pattern 121T2 spaced apart from each other in a horizontal direction on the first insulating layer 111 .

[0151] The first and second connection electrode patterns 121T1 and 121T2 may each have different upper and lower surface widths W3 and W4. Preferably, the upper surface width W3 of each of the first and second connection electrode patterns 121T1 and 121T2 may be smaller than the lower surface width W4. This may be a structural characteristic resulting from the use of a capping process to manufacture the first and second connection electrode patterns 121T1 and 121T2.

[0152] However, this embodiment uses an etchant having an anisotropic etching structure to form the first and second connection electrode patterns 121T1 and 121T2. Here, the anisotropic etching structure may also be referred to as a vertical etching structure. For example, the anisotropic etching structure may refer to a structure in which etching is selectively performed only in the vertical direction without horizontal expansion during the etching process.

[0153] For example, this embodiment forms the first wiring electrode 121 by etching the metal layer using an etchant containing copper chloride and / or ferric chloride. Thus, this embodiment can minimize the difference between the width of the upper surface and the width of the lower surface of each of the pad electrode 121P and the connecting electrode 121T of the first wiring electrode 121. Consequently, this embodiment can minimize the width of each of the pad electrode 121P and the connecting electrode 121T, as well as the spacing between adjacent electrodes.

[0154] To briefly describe the etching process of the metal layer by the etchant of this embodiment, the etchant may include an organic material used as a barrier layer. Therefore, when etching the metal layer, the organic material may adhere to the surface of the metal layer. At this time, the attached organic material can be removed when in direct contact with the etchant. Therefore, when etching the metal layer, the area vertically overlapping with the open area of ​​the dry film may directly contact the etchant, thereby removing the organic material used as a barrier layer, and thus performing etching in the vertical direction. In contrast, the area that does not vertically overlap with the open area of ​​the dry film may not directly contact the etchant, and therefore the organic material used as a barrier layer may not be removed, and therefore etching in the horizontal direction that does not overlap with the open area may not occur. Therefore, this embodiment can form wiring electrodes with substantially the same upper surface width and lower surface width.

[0155] The width W4 of the lower surface of each of the first connection electrode pattern 121T1 and the second connection electrode pattern 121T2 can be within a range of 5 μm to 30 μm. For example, the width W4 of the lower surface of each of the first connection electrode pattern 121T1 and the second connection electrode pattern 121T2 can be within a range of 5 μm to 25 μm. For example, the width W4 of the lower surface of each of the first connection electrode pattern 121T1 and the second connection electrode pattern 121T2 can be within a range of 5 μm to 20 μm.

[0156] At this time, if the width W4 of the lower surface of each of first and second connection electrode patterns 121T1 and 121T2 is less than 5 μm, the width of the upper surface of each of first and second connection electrode patterns 121T1 and 121T2 may become too narrow due to manufacturing errors. Therefore, the vertical cross-sectional shape of first and second connection electrode patterns 121T1 and 121T2 may be close to a triangle, which can prevent first and second connection electrode patterns 121T1 and 121T2 from functioning as traces. If the width W4 of the lower surface of each of first and second connection electrode patterns 121T1 and 121T2 exceeds 30 μm, it may be difficult to arrange connection electrode 121T of first wiring electrode 121 within a limited space, which may result in reduced circuit integration.

[0157] The width W3 of the upper surface of each of the first and second connection electrode patterns 121T1 and 121T2 may correspond to the width W4 of the lower surface. Here, "corresponding" may mean that the width W3 of the upper surface is smaller than the width W4 of the lower surface, and the difference therebetween is 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0158] For example, the width W3 of the upper surface of each of the first connection electrode pattern 121T1 and the second connection electrode pattern 121T2 may be within a range of 90% to 99% of the width W4 of the lower surface. For example, the width W3 of the upper surface of each of the first connection electrode pattern 121T1 and the second connection electrode pattern 121T2 may be within a range of 92% to 99% of the width W4 of the lower surface. For example, the width W3 of the upper surface of each of the first connection electrode pattern 121T1 and the second connection electrode pattern 121T2 may be within a range of 95% to 99% of the width W4 of the lower surface.

[0159] If the width W3 of the upper surface of each of the first and second connection electrode patterns 121T1 and 121T2 is less than 90% of the width W4 of the lower surface, the width of each of the first and second connection electrode patterns 121T1 and 121T2 or the spacing therebetween may increase, and thus, it may be difficult for the first wiring electrode 121 to have a connection electrode 121T. If the width W3 of the upper surface of each of the first and second connection electrode patterns 121T1 and 121T2 exceeds 99% of the width W4 of the lower surface, this means that the etchant of the embodiment does not smoothly etch in the vertical direction, and accordingly, the electrical characteristics of the first wiring electrode 121 may be degraded. For example, using the capping process, it may be impossible to form the first and second connection electrode patterns 121T1 and 121T2 so that the width W3 of their upper surfaces exceeds 99% of the width W4 of their lower surfaces.

[0160] Thus, the present embodiment can provide the first wiring electrode 121 and the fourth wiring electrode 124 provided on the upper surface and the lower surface of the first insulating layer 111 with the pad electrodes 121P and 124P and the connection electrodes 121T and 124T, respectively.

[0161] Furthermore, this embodiment can minimize the interval W5 between the plurality of adjacent connection electrode patterns by forming the connection electrode 121T of the first wiring electrode 121 using an etchant having an anisotropic etching structure.

[0162] For example, the interval W5 between adjacent first connection electrode patterns 121T1 and second connection electrode patterns 121T2 can be within a range of 5 μm to 30 μm. For example, the interval W5 between adjacent first connection electrode patterns 121T1 and second connection electrode patterns 121T2 can be within a range of 5 μm to 25 μm. For example, the interval W5 between adjacent first connection electrode patterns 121T1 and second connection electrode patterns 121T2 can be within a range of 5 μm to 20 μm.

[0163] At this time, if the spacing W5 between adjacent first connection electrode patterns 121T1 and second connection electrode patterns 121T2 is less than 5 μm, first connection electrode patterns 121T1 and second connection electrode patterns 121T2 may contact each other due to manufacturing errors, which may cause electrical reliability issues such as electrical short circuits. In addition, if the spacing W5 between adjacent first connection electrode patterns 121T1 and second connection electrode patterns 121T2 exceeds 30 μm, it may be difficult to place connection electrodes 121T of first wiring electrodes 121 within a limited space, which may result in reduced circuit integration.

[0164] Furthermore, the side surface 121S of the connection electrode 121T of the first wiring electrode 121 may have an inclination angle that increases in width from the upper surface 121U toward the lower surface 121L of the connection electrode 121T. In this case, the inclination angle of the side surface 121S of the connection electrode 121T may be close to 90 degrees.

[0165] The inclination angle of the side surface 121S of the connection electrode 121T of the first wiring electrode 121 may mean a first inner angle θ between the upper surface 121U and the side surface 121S, and may mean a second inner angle θ between the lower surface 121L and the side surface 121S.

[0166] The first inner angle θ may satisfy the range of 91° to 100°. Preferably, the first inner angle θ may satisfy the range of 91° to 98°. More preferably, the first inner angle θ may satisfy the range of 91° to 95°. Correspondingly, the second inner angle θ may satisfy the range of 80° to 89°. Preferably, the second inner angle θ may satisfy the range of 82° to 89°. More preferably, the second inner angle θ may satisfy the range of 85° to 89°. At this time, when the side surface 121S of the connection electrode 121T has a curved surface, the first inner angle θ and the second inner angle θ may each mean the inner angle between an imaginary straight line connecting the innermost point and the outermost point on the side surface 121S and the upper surface 121U or the lower surface 121L of the connection electrode 121T.

[0167] If the first internal angle θ is less than 91° or the second internal angle θ exceeds 89°, this means that the etchant of this embodiment does not smoothly etch in the vertical direction, and thus the electrical characteristics of the first wiring electrode 121 may be degraded. For example, it may be difficult to form the connection electrode 121T having a first internal angle θ less than 91° or a second internal angle θ exceeding 89° through the capping process. In addition, if the first internal angle θ exceeds 100° or the second internal angle θ is less than 80°, the width of each of the first connection electrode pattern 121T1 and the second connection electrode pattern 121T2 or the spacing therebetween may increase, making it difficult to form the connection electrode 121T on the first wiring electrode 121.

[0168] At this time, when manufacturing the first wiring electrode 121, the metal layer used may have the following etching factor: Preferably, the etching factor of the first wiring electrode 121 may be as follows.

[0169] Here, the etching factor may be defined by the following Equation 1.

[0170] [Equation 1]

[0171] Etching factor = thickness of connecting electrode / (width of lower surface of connecting electrode - width of upper surface of connecting electrode) / 2)

[0172] The etching factor of the first wiring electrode 121 of this embodiment may be 10 to 60. Preferably, the etching factor of the first wiring electrode 121 of this embodiment may be 12 to 58. More preferably, the etching factor of the first wiring electrode 121 of this embodiment may be 15 to 55.

[0173] In addition, when the etching factor of the first wiring electrode 121 of the present embodiment is outside the range of 10 to 60, the width of the upper surface, the width of the lower surface of the connecting electrode 121T, the width difference between the width of the upper surface and the width of the lower surface, the spacing between the multiple connecting electrode patterns, and the inclination angle of the side surface of the connecting electrode may not satisfy the above range.

[0174] At the same time, reference Figure 5 When the width W3 of the upper surface of the connection electrode 21 of the comparative example manufactured by the capping process compared to the present embodiment is the same as the width W3 of the upper surface of the connection electrode 121T of the present invention, the width W5 of the lower surface of the connection electrode 21 of the comparative example exceeds 110% of the width W3 of the upper surface of the connection electrode 21. This is because the connection electrode 21 of the comparative example is manufactured using an etchant having an isotropic etching structure, rather than an etchant having an anisotropic etching structure as in the present embodiment, and therefore the metal layer is etched while expanding in the horizontal direction.

[0175] Furthermore, the internal angle θ between the upper surface 21U and the side surface 21S of the connection electrode 21 of the comparative example is 110°, and further, the internal angle θ between the lower surface 21L and the side surface 21S of the connection electrode 21 is smaller than 75°.

[0176] Therefore, in the comparative example, it is difficult to place the connection electrodes on the upper surface and / or lower surface of the core layer, so only dummy patterns are provided in the corresponding areas. In contrast, in this embodiment, the first wiring electrode 121 and the fourth wiring electrode 124, which include the connection electrodes, can be placed on the upper surface and the lower surface of the first insulating layer 111, which serves as the core layer, respectively.

[0177] At the same time, reference Figure 6 , the second wiring electrode 122 is provided on the second insulating layer 112. At this time, the vertical cross-sectional shape of the second wiring electrode 122 may be different from the vertical cross-sectional shape of the first wiring electrode 121.

[0178] For example, the second wiring electrode 122 is manufactured using the MSAP method or the SAP method, unlike the first wiring electrode 121. Therefore, the manufacturing of the second wiring electrode 122 includes a process of finally etching the seed layer from the metal layer including the seed layer.

[0179] Therefore, the width W7 of the upper surface 122U of the second wiring electrode 122 may be greater than the width W8 of the lower surface 122L of the second wiring electrode 122. For example, the side surface 122S of the second wiring electrode 122 may have an inclination angle in which the width decreases from the upper surface 122U of the second wiring electrode 122 toward the lower surface 122L of the second wiring electrode 122.

[0180] That is, the inclination angle of the side surface 122S of the second wiring electrode 122 may be inclined in a direction different from the inclination angle of the side surface 121S of the first wiring electrode 121 .

[0181] Therefore, unlike the first internal angle θ of the first wiring electrode 121, the internal angle θ between the side surface 122S and the upper surface 122U of the second wiring electrode 122 may be an acute angle. In addition, unlike the second internal angle θ of the first wiring electrode 121, the internal angle θ between the side surface 122S and the lower surface 122L of the second wiring electrode 122 may be an obtuse angle.

[0182] One embodiment includes: a first insulating layer having a through-hole; an insulating member disposed in the through-hole; a first through-electrode disposed in the through-hole and surrounding at least a portion of the insulating member; and a first wiring electrode disposed on the first insulating layer. The first insulating layer is a core layer having a thickness of 150 μm to 600 μm, and the first wiring electrode includes: a pad electrode vertically overlapping the first through-electrode and the insulating member; and a connecting electrode connected to the pad electrode and not vertically overlapping the first through-electrode and the insulating member.

[0183] In addition, the width of the upper surface of the connecting electrode is smaller than the width of the lower surface of the connecting electrode, the width of the lower surface of the connecting electrode satisfies the range of 5μm to 30μm, and the width of the upper surface of the connecting electrode satisfies the range of 90% to 99% of the width of the lower surface of the connecting electrode.

[0184] That is, the first wiring electrode of the present embodiment is manufactured using the capping process and includes a connection electrode in addition to the pad electrode.

[0185] That is, since the first wiring electrodes are manufactured using the capping process, this embodiment can simplify the process compared to wiring electrodes manufactured using the MSAP and / or SAP process, thereby significantly reducing the unit cost of the circuit board.

[0186] Furthermore, since the first wiring electrode is manufactured using the capping process and includes the connection electrode, this embodiment can improve circuit integration of the circuit board, thereby miniaturizing the circuit board and the semiconductor package.

[0187] Specifically, in the comparative example compared to the present embodiment, when the first wiring electrode was manufactured using the capping process, a difference occurred between the width of the upper surface and the width of the lower surface of the electrode pattern during the etching process of the first wiring electrode. Therefore, due to this difference, the width of the electrode pattern and the spacing between adjacent electrode patterns increased.

[0188] For example, when the electrode pattern is manufactured using the capping process of the comparative example, the width of the electrode pattern exceeds at least 35 μm, and the spacing between adjacent electrode patterns exceeds at least 35 μm. This is because the difference between the width of the upper surface and the width of the lower surface of the electrode pattern must be considered.

[0189] In contrast, this embodiment uses an etchant with an anisotropic etching structure to manufacture the first wiring electrode. This minimizes the difference between the width of the upper surface and the width of the lower surface of the connection electrode of the first wiring electrode. Therefore, this embodiment can improve circuit integration by including connection electrodes such as traces in the first wiring electrode, thereby enabling miniaturization of circuit boards and semiconductor packages.

[0190] Furthermore, the present embodiment can improve the degree of freedom in wiring design of the circuit board by including the connection electrode in the first wiring electrode, thereby improving user satisfaction.

[0191] Furthermore, by including connection electrodes in the first wiring electrodes, the present embodiment can easily control the wiring density of the first wiring electrodes 121. Thus, the present embodiment can adjust the wiring density of the first wiring electrodes by taking into account the warping direction of the circuit board, thereby resolving the reliability issue of the circuit board and semiconductor package significantly warping in a specific direction.

[0192] Furthermore, this embodiment can utilize the connection electrode of the first wiring electrode as a heat transfer path serving as a heat dissipation path, thereby improving the heat dissipation characteristics of the circuit board and the semiconductor package.

[0193] Therefore, this embodiment can allow the semiconductor device attached to the circuit board to operate stably, thereby allowing electronic products such as servers to which the semiconductor package is applied to operate stably. Thus, this embodiment can improve product satisfaction and product reliability.

[0194] -Semiconductor packaging-

[0195] Figure 7 is a cross-sectional view showing a semiconductor package according to a first embodiment, and Figure 8is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0196] refer to Figure 7 , semiconductor packages may include Figure 1 circuit board.

[0197] In addition, the circuit board may further include a conductive bonding portion 170 .

[0198] The conductive bonding portion 170 is positioned on the uppermost wiring electrode among the wiring electrodes located on each layer of the insulating layer 110. For example, the conductive bonding portion 170 may be located on the third wiring electrode 123. The conductive bonding portion 170 protrudes above the first protective layer 150. The conductive bonding portion 170 may be referred to as a bump.

[0199] The conductive bonding portion 170 protrudes above the first protective layer 150 of the circuit board to stably connect to the terminal 225 of the semiconductor device 220 and the terminal 235 of the semiconductor device 230 using the connecting portion 210. This allows the conductive bonding portion 170 to maintain a certain distance between the connecting portion 210 and the circuit board, thereby improving the positional alignment between the conductive bonding portion 170 and the terminals of the semiconductor devices 220 and 230.

[0200] There are provided a plurality of conductive bonding portions 170. On the third wiring electrode 123, these conductive bonding portions 170 are arranged in a horizontal direction.

[0201] The connection portion 210 is provided on the conductive bonding portion 170 .

[0202] The connection portion 210 can be connected to a terminal 225 of the first semiconductor device 220 and a terminal 235 of the second semiconductor device 230 , respectively.

[0203] The first semiconductor device 220 and the second semiconductor device 230 are connected to the connection portion 210. In this case, Figure 7 The first semiconductor device 220 and the second semiconductor device 230 are shown to be horizontally connected and spaced apart from each other on the connection portion 210 , but the embodiment is not limited thereto. For example, one semiconductor device may be connected to the connection portion 210 , or three or more semiconductor devices may be connected to the connection portion 210 .

[0204] Meanwhile, although not shown in the figure, the connection portion may also be located under the lowest wiring electrode of the circuit board. In addition, an external substrate may be connected to the connection portion located under the lowest wiring electrode. For example, the external substrate may be a mainboard of an electronic device.

[0205] At the same time, reference Figure 8The semiconductor package may further include a connection member 300 located within the circuit board. The connection member 300 may be embedded within the insulating layer 110 of the circuit board.

[0206] The connection member 300 partially overlaps the semiconductor devices 320 and 330 in the vertical direction.

[0207] The connection member 300 electrically connects a portion of the terminal 325 of the first semiconductor device 320 and a portion of the terminal 335 of the second semiconductor device 330 .

[0208] For example, functionally separated semiconductor devices such as chiplets or multiple semiconductor devices having different functions such as a CPU and a GPU or a GPU and an HBM may be mounted on a circuit board, and the connection member 300 may be used to electrically connect them horizontally.

[0209] In one embodiment, the connection member 300 is an inorganic bridge. For example, the inorganic bridge can be a silicon bridge. For example, the connection member 300 can include a silicon substrate and a redistribution layer.

[0210] In another embodiment, the connecting member 300 is an organic bridge. For example, the connecting member 300 may include an organic material. For example, the connecting member 300 may include an organic substrate, wherein the silicon substrate of the inorganic bridge is replaced with an organic material.

[0211] The connection member 300 includes a pad portion 310. The pad portion 310 of the connection member 300 is electrically connected to an electrode portion (eg, a through electrode and a wiring electrode) of a circuit board.

[0212] -Circuit board manufacturing method-

[0213] Figures 9 to 19 It is shown in the order of the process Figure 1 sectional view of the method for manufacturing a circuit board shown in .

[0214] First, refer to Figure 9 This embodiment prepares a component used as a basis for manufacturing a circuit board. For example, this embodiment prepares a copper-clad laminate (CCL) used as a basis for manufacturing a core board. The copper-clad laminate includes a first insulating layer 111. In addition, the copper-clad laminate includes copper foil layers respectively provided on the upper and lower surfaces of the first insulating layer 111.

[0215] For example, the member includes a first insulating layer 111, a first copper foil layer 121-1 disposed on the first insulating layer 111, and a second copper foil layer 124-1 disposed under the first insulating layer 111. In this case, the first copper foil layer 121-1 may constitute a portion of the multiple metal layers of the first wiring electrode 121. In addition, the second copper foil layer 124-1 may constitute a portion of the multiple metal layers of the fourth wiring electrode 124.

[0216] Next, refer to Figure 10 In this embodiment, a through hole TH is formed through the first copper foil layer 121-1, the first insulating layer 111, and the second copper foil layer 124-1. The through hole TH may be formed using a CNC drill or, alternatively, may be formed using a laser process.

[0217] Next, refer to Figure 11 , this embodiment can perform a process of forming a metal layer on the upper surface of the first copper foil layer 121-1, the lower surface of the second copper foil layer 124-1, and the inner wall of the through hole TH. That is, this embodiment can form the first metal layer 121-2 constituting the first wiring electrode 121 on the upper surface of the first copper foil layer 121-1. In addition, this embodiment can form the second metal layer 124-2 constituting the fourth wiring electrode 124 on the lower surface of the second copper layer 124-1. In addition, this embodiment can form the third metal layer 131 constituting the first through electrode 131 on the inner wall of the through hole TH. In this case, the first metal layer 121-2, the second metal layer 124-2, and the third metal layer 131 can be substantially a single metal layer and can be distinguished based on their placement.

[0218] In addition, although the embodiment describes forming the first metal layer 121-2, the second metal layer 124-2, and the third metal layer 131 through a single electroplating process, this is not limited thereto. For example, the first metal layer 121-2, the second metal layer 124-2, and the third metal layer 131 can be formed through multiple electroplating processes to achieve uniform thickness.

[0219] Next, refer to Figure 12 For example, the present embodiment may perform a process of forming the insulating member 140 in the through hole TH of the first insulating layer 111 .

[0220] Next, refer to Figure 13 , this embodiment may perform a process of forming a fourth metal layer 121 - 3 on the first metal layer 121 - 2 of the first wiring electrode 121 and the insulating member 140 . The fourth metal layer 121 - 3 constitutes a portion of the plurality of metal layers of the first wiring electrode 121 .

[0221] In addition, the present embodiment may perform a process of forming a fifth metal layer 124-3 under the second metal layer 124-2 and the insulating member 140 of the fourth wiring electrode 124. The fifth metal layer 124-3 constitutes a portion of the plurality of metal layers of the fourth wiring electrode 124.

[0222] Next, refer to Figure 14 In this embodiment, a process of forming a first dry film DF1 on the fourth metal layer 121-3 of the first wiring electrode 121 may be performed. In this case, the first dry film DF1 may have a first open area OR1. The first open area OR1 may vertically overlap with an area of ​​the upper surface of the fourth metal layer 121-3 where the first wiring electrode 121 is not formed.

[0223] In addition, the present embodiment may also form a second dry film DF2 under the fifth metal layer 124-3 of the fourth wiring electrode 124. In this case, the second dry film DF2 may have a second open region OR2. The second open region OR2 may vertically overlap with a region of the lower surface of the fifth metal layer 124-3 where the fourth wiring electrode 124 is not formed.

[0224] Next, refer to Figure 15 In this embodiment, the metal layer exposed through the open regions of each of the first dry film DF1 and the second dry film DF2 can be removed by etching using an etchant having an anisotropic etching structure. Thus, in this embodiment, the pad electrode 121P and the connecting electrode 121T of the first wiring electrode 121 can be formed. Furthermore, in this embodiment, the pad electrode 124P and the connecting electrode 124T of the fourth wiring electrode 124 can be formed.

[0225] Next, refer to Figure 16 In this embodiment, the process of removing the first dry film DF1 and the second dry film DF2 can be performed.

[0226] Next, refer to Figure 17 In this embodiment, the second insulating layer 112 may be stacked on the first insulating layer 111. In addition, the second through electrode 132 penetrating the second insulating layer 112 and the second wiring electrode 122 on the second insulating layer 112 may be formed.

[0227] In addition, this embodiment may stack the fourth insulating layer 114 under the first insulating layer 111. In addition, this embodiment may form the fourth through electrode 134 penetrating the fourth insulating layer 114 and the fifth wiring electrode 125 under the fourth insulating layer 114.

[0228] Next, refer to Figure 18In this embodiment, the third insulating layer 113 may be stacked over the second insulating layer 112. In addition, the third through electrode 133 penetrating the third insulating layer 113 and the third wiring electrode 123 on the third insulating layer 113 may be formed.

[0229] In addition, the present embodiment may stack the fifth insulating layer 115 under the fourth insulating layer 114. In addition, the present embodiment may form the fifth through electrode 135 penetrating the fifth insulating layer 115 and the sixth wiring electrode 126 under the fifth insulating layer 115.

[0230] Next, refer to Figure 19 In this embodiment, the first protective layer 150 may be formed on the third insulating layer 113. In addition, the second protective layer 160 may be formed under the fifth insulating layer 115.

[0231] On the other hand, when the circuit board of the present invention having the above-mentioned characteristics is used in an IT device or a household appliance (such as a smart phone, a server computer, a television set, etc.), it can stably perform functions such as signal transmission or power supply. For example, when the circuit board having the characteristics of the present invention performs a semiconductor packaging function, the circuit board can be used to safely protect the semiconductor chip from external moisture or pollutants, or alternatively, it can solve the problems of leakage current, electrical short circuit between terminals, and electrical disconnection of terminals supplied to the semiconductor chip. In addition, when responsible for the function of signal transmission, the noise problem can be solved. Thus, the circuit board having the above-mentioned characteristics of the present invention can maintain the stable function of the IT device or household appliance, so that the entire product and circuit board to which the present invention is applied can achieve functional unification or technical interlocking with each other.

[0232] When a circuit board having the characteristics of the above invention is used in a transport device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transport device. Alternatively, it can further improve the safety of the transport device by safely protecting the semiconductor chip that controls the transport device from external influences and resolving issues such as leakage current, electrical short circuits between terminals, or electrical disconnection of terminals supplied to the semiconductor chip. Therefore, the transport device and the circuit board to which the present invention is applied can achieve functional integrity or technical interlocking with each other.

[0233] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, the characteristics, structures, and effects shown in each embodiment can be combined or modified with respect to other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, it should be understood that the contents related to such combinations and such modifications are included in the scope of the embodiment.

[0234] The above description has focused on the embodiments, but the above description is merely illustrative and does not limit the embodiments. Those skilled in the art will appreciate that various modifications and applications not shown above are possible without departing from the essential features of the embodiments. For example, each component specifically shown in the embodiments may be modified and implemented. Furthermore, it should be understood that differences related to such modifications and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: core layer; a first wiring electrode provided on the core layer; a buildup insulating layer disposed on the first wiring electrode; as well as a second wiring electrode provided on the buildup insulating layer; The second wiring electrode has an inclination angle such that its width in the horizontal direction decreases along a vertical direction from an upper surface of the second wiring electrode toward a lower surface of the second wiring electrode.

2. The circuit board according to claim 1, wherein The first wiring electrode has an inclination angle different from an inclination angle of the second wiring electrode.

3. The circuit board according to claim 2, wherein: The inclination angle of the first wiring electrode is inclined in a direction different from the inclination angle of the second wiring electrode.

4. The circuit board according to claim 2, wherein: The first wiring electrode has an inclination angle such that the width increases in the horizontal direction along the vertical direction.

5. The circuit board according to claim 1, wherein The core layer has a thickness of 150 μm to 600 μm, and Wherein, the first wiring electrode includes: a pad electrode, the pad electrode overlapping the first through-electrode and the insulating member in the vertical direction; and A connection electrode is connected to the pad electrode and does not overlap with the first through electrode and the insulating member in the vertical direction. The circuit board according to claim 5 , wherein: The width of the upper surface of the connection electrode satisfies a range of 90% to 99% of the width of the lower surface of the connection electrode.

7. The circuit board according to claim 5, wherein A first inner angle between the upper surface of the connection electrode and the side surface of the connection electrode satisfies a range of 91° to 100°, and Wherein, a second inner angle between the lower surface of the connecting electrode and the side surface of the connecting electrode satisfies the range of 80° to 89°.

8. The circuit board according to claim 5, wherein The connection electrode includes a plurality of connection electrode patterns spaced apart from each other in the horizontal direction, and Wherein, the interval between two adjacent connection electrode patterns among the plurality of connection electrode patterns satisfies the range of 5 μm to 30 μm.

9. The circuit board according to claim 1, wherein An inner angle between an upper surface of the second wiring electrode and a side surface of the second wiring electrode is an acute angle, and The inner angle between the lower surface of the second wiring electrode and the side surface of the second wiring electrode is an obtuse angle.

10. The circuit board according to claim 1, wherein The core layer includes through holes, and The width of the through hole in the horizontal direction is within a range of 80 μm to 500 μm.

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