Device and method for stress testing

Abstract

A first voltage source is coupled to the first terminal of the test transistor. A first terminal of the detection circuit is coupled to a first terminal of the test transistor. A second terminal of the detection circuit is coupled to a second terminal of the test transistor. A third terminal of the detection circuit is coupled to a control terminal of the test transistor. A first terminal of the first resistor is coupled to a second terminal of the test transistor. A second terminal of the first resistor is coupled to a second voltage source. A first input terminal of the amplifier is coupled to a third voltage source. The second input terminal of the amplifier is coupled to the first terminal of the first resistor. An output terminal of the amplifier is coupled to a control terminal of the test transistor. The embodiment of the invention also relates to a device and a method for stress testing.

Description

Technical Field

[0001] Embodiments of the present application relate to apparatus and methods for stress testing. Background Art

[0002] Modern integrated chips consist of millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Silicon-based semiconductor devices (e.g., transistors and photodiodes) have been the standard in the semiconductor industry for the past four decades. However, semiconductor devices based on alternative materials are gaining increasing attention. For example, semiconductor devices based on III-N semiconductors (e.g., gallium nitride (GaN)) have been widely used in high-power, optoelectronic, and high-temperature applications. Summary of the Invention

[0003] According to one aspect of an embodiment of the present application, a device for stress testing is provided, including: a first voltage source, a second voltage source and a third voltage source, the first voltage source being coupled to the first terminal of a test transistor; a detection circuit having a first terminal, a second terminal and a third terminal, the first terminal of the detection circuit being coupled to the first terminal of the test transistor, the second terminal of the detection circuit being coupled to the second terminal of the test transistor, and the third terminal of the detection circuit being coupled to the control terminal of the test transistor; a first resistor having a first terminal and a second terminal, the first terminal of the first resistor being coupled to the second terminal of the test transistor, and the second terminal of the first resistor being coupled to the second voltage source; and an amplifier having a first input terminal, a second input terminal and an output terminal, the first input terminal of the amplifier being coupled to the third voltage source, the second input terminal of the amplifier being coupled to the first terminal of the first resistor, and the output terminal of the amplifier being coupled to the control terminal of the test transistor.

[0004] According to another aspect of an embodiment of the present application, a device for stress testing is provided, including: a first voltage source, a second voltage source, and a third voltage source, the first voltage source being coupled to a first terminal of a test transistor and being configured to provide a stress voltage to the first terminal of the test transistor; a detection circuit being coupled to the first terminal of the test transistor, the second terminal of the test transistor, and a control terminal of the test transistor, the detection circuit being configured to measure a voltage on the test transistor and a current flowing through the test transistor; a first resistor being coupled between the second terminal of the test transistor and the second voltage source; and an amplifier being coupled to the test transistor and the first resistor, the amplifier being configured to receive a control voltage from the third voltage source, and providing an amplifier voltage to the control terminal of the test transistor based on the voltage on the first resistor and the control voltage so that a current having a test current level flows through the test transistor, the amplifier being configured to adjust the amplifier voltage to maintain the test current level flowing through the test transistor.

[0005] According to another aspect of an embodiment of the present application, a method for stress testing is provided, comprising: measuring an initial performance of a test transistor before a first time period; after measuring the initial performance of the test transistor, applying a first voltage to a control terminal of the test transistor so that a first current flows through the test transistor during the first time period; increasing the temperature of the test transistor from the first temperature to a second temperature, and maintaining the temperature of the test transistor at the second temperature during the first time period; adjusting the first voltage during the first time period in response to the increase in the temperature of the test transistor to maintain the first current through the test transistor during the first time period; measuring a final performance of the test transistor after the first time period; and determining a difference between the initial performance of the test transistor and the final performance of the test transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. Indeed, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Circuit diagram illustrating some embodiments of an apparatus for stress testing a test transistor.

[0008] Figure 2 Show Figure 1 Graphs of some embodiments of the performance of an apparatus.

[0009] Figure 3 A flow chart illustrating some embodiments of a method of stress testing a test transistor.

[0010] Figure 4 Show Figure 1 Circuit diagrams of some other embodiments of the device.

[0011] Figure 5 Show Figure 4 Cross-sectional views of some embodiments of the device.

[0012] Figure 6 Flowchart illustrating some embodiments of a process flow for producing a test transistor.

[0013] Figure 7 Show Figure 4 Circuit diagrams of some other embodiments of the device.

[0014] Figure 8 Show Figure 7 Circuit diagrams of some other embodiments of the device.

[0015] Figure 9 A cross-sectional view of some embodiments of a test transistor is shown. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Furthermore, the present invention may refer to repeated numbers and / or letters in various examples. This repetition is for simplicity and clarity, but does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," and "upper," may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] During the integrated chip manufacturing process, defects may form within the various layers of the chip or along its surface. For example, when manufacturing gallium nitride (GaN) high electron mobility transistors (HEMTs), crystal defects (e.g., vacancies, grain boundaries, edge dislocations, screw dislocations, mixed dislocations, etc.) may appear within the various layers of the transistor or along its surface. These defects can affect the performance and reliability of the transistor. For example, over time, these defects can affect linear drain current decay, current leakage, on-resistance, threshold voltage, etc. Therefore, many integrated chips are subjected to stress testing after manufacturing to ensure that the chip's reliability and performance meet certain requirements before the chip is considered qualified.

[0019] Some stress tests involve applying electrical and thermal stress to a test transistor over a period of time and determining how the device performance changes as a result of the stress test. First, the initial performance of the test transistor is measured before the stress is applied. Next, the stress test is performed. For example, a high temperature reverse bias (HTRB) stress test involves heating the test transistor to a high temperature (e.g., greater than 100 degrees Celsius) and simultaneously applying a large voltage (e.g., greater than 100 volts) to the test transistor. The test transistor is turned on (e.g., a voltage is applied to the control terminal of the test transistor) to allow current to flow through the test transistor. The high voltage and high temperature are maintained for a period of time to maintain the stress on the test transistor. The stress test is ended by removing the high voltage and high temperature from the transistor. Next, the final performance of the test transistor is measured after the stress test. Finally, the difference between the initial performance and the final performance of the test transistor is determined.

[0020] A challenge with this type of stress test is that the on-resistance of the test transistor may increase as the temperature of the test transistor increases, so the current flowing through the test transistor during the stress test may decrease. Therefore, the duration of the stress test may need to be increased. Increasing the duration of the stress test can increase testing costs and potentially slow chip production.

[0021] In various embodiments of the present disclosure, the voltage at the control terminal of the transistor is adjusted throughout the stress test process so that the current flowing through the transistor remains approximately constant throughout the stress test process (although the on-resistance may change during the stress test). By maintaining a constant current flowing through the test transistor throughout the stress test process, the duration of the stress test can be reduced. Therefore, testing costs can be reduced and chip yield can be increased.

[0022] Figure 1 A circuit diagram 100 illustrates some embodiments of an apparatus for stress testing a test transistor 102 . Figure 2 Show Figure 1 Graphs of some embodiments of the performance of an apparatus.

[0023] refer to Figure 1 The apparatus includes a first voltage source 104, a second voltage source 106, a third voltage source 108, a detection circuit 110, a first resistor 112, an amplifier 114, a heater 118, and a heater power supply 120. In some embodiments, the second voltage source 106 is grounded or coupled to ground 122.

[0024] Test transistor 102 has a first terminal 102a, a second terminal 102b, and a control terminal 102c. First voltage source 104 has an output terminal 104a coupled to first terminal 102a of test transistor 102. First resistor 112 has a first terminal 112a coupled to second terminal 102b of test transistor 102. Second voltage source 106 has an output terminal 106a coupled to second terminal 112b of first resistor 112. Amplifier 114 has a first input terminal 114a (e.g., a reference terminal), a second input terminal 114b (e.g., a feedback terminal), and an output terminal 114c. Third voltage source 108 has an output terminal 108a coupled to first input terminal 114a of amplifier 114. Second input terminal 114b of amplifier 114 is coupled to first terminal 112a of first resistor 112 (and second terminal 102b of test transistor 102). The detection circuit 110 has a first terminal 110a coupled to the first terminal 102a of the test transistor 102, a second terminal 110b coupled to the second terminal 102b of the test transistor 102, and a third terminal 110c coupled to the control terminal 102c of the test transistor 102. In some embodiments, the detection circuit 110 has a fourth terminal (not shown) coupled to a bulk terminal (not shown) of the test transistor 102. A heater 118 is located proximate to the test transistor 102. The heater 118 is coupled to a heater power supply 120.

[0025] To perform stress testing on the test transistor 102 under thermal stress and electrical stress (eg, HTRB testing), the heater 118 heats the test transistor 102 and the first voltage source 104 provides a stress voltage V to the first terminal 102a of the test transistor 102. stress , the second voltage source 106 provides a reference voltage V to the second terminal 112b of the first resistor 112 ref The third voltage source 108 provides a control voltage V to the first input terminal 114a of the amplifier 114. ctrl The amplifier 114 receives the feedback voltage V at the second input terminal 114b. fb (eg, the voltage across the first resistor 112). The amplifier 114 increases the amplifier voltage V amp The magnitude of the stress current I stress is passed from the first terminal 102a to the second terminal 102b, and the amplifier 114 adjusts the amplifier voltage V amp The amplitude of the feedback voltage V fb (at the second input terminal 114b) is approximately equal to the control voltage V ctrl (at the first input terminal 114a), as Figure 2For example, the amplifier 114 adjusts the amplifier voltage V amp This increases the magnitude of the current through the test transistor 102 and the first resistor 112, which increases the voltage across the first resistor 112 (the feedback voltage V fb ), at least until the voltage on the first resistor 112 (the feedback voltage V fb ) is equal to the control voltage V ctrl ,like Figure 2 shown.

[0026] In some cases, under thermal stress and electrical stress, the characteristics of the test transistor 102 may change as the temperature TEMP of the test transistor 102 increases (for example, the on-resistance R on increase), such as Figure 2 However, due to the control voltage V from the third voltage source 108 to the first input terminal 114a ctrl is constant, and since the amplifier 114 adjusts the amplifier voltage V amp So that the feedback voltage V fb = equal to the control voltage V at the first input terminal 114a ctrl , so the feedback voltage V at the second input terminal 114b fb (e.g., the voltage across the first resistor 112) is substantially constant, such as Figure 2 Therefore, the current through the first resistor 112 is substantially constant, and thus the stress current I stress is substantially constant, even if the characteristics of the test transistor 102 change under stress (e.g., the on-resistance increases), as Figure 2 shown.

[0027] Since the current through the test transistor 102 remains substantially constant during the entire stress test process, the stress test T test The duration of the stress test can be reduced (e.g., from about 500 hours to about 10 minutes). For example, by maintaining a constant current throughout the stress test process, charge carrier injection defects (e.g., hot carrier injection) can be induced more quickly into the test transistor 102, and degradation of the test transistor 102 performance (e.g., on-resistance, linear drain current, threshold voltage, leakage, etc.) can be induced more quickly. Therefore, the reliability and performance of the device can be tested in a shorter time. By reducing the duration of the stress test, test costs can be reduced and chip yields can be improved.

[0028] Figure 3 Flowchart 300 shows some embodiments of a method for stress testing a test transistor 102. Figure 3Although the method of the present invention is shown and described as a series of steps or events, it should be understood that the order of these steps or events shown should not be interpreted as limiting. For example, some steps can occur in different orders and / or occur simultaneously with other steps or events other than those shown and / or described herein. In addition, it is not required that all shown operations are used to implement one or more aspects or embodiments described herein. In addition, one or more steps described herein can be performed in one or more separate steps and / or stages.

[0029] At block 302, initial performance of the test transistor is measured. For example, while the test transistor 102 is maintained at room temperature, a normal operating voltage is applied to the first terminal 102a and the control terminal 102c of the test transistor 102, and the performance of the test transistor (e.g., linear drain current, on-resistance, gate-source leakage, drain-source leakage, gate-bulk leakage, etc.) is measured by the probing circuit 110. For example, the probing circuit measures the voltages at the first terminal 102a, the second terminal 102b, and the control terminal 102c of the test transistor 102, and measures the current through the test transistor 102 (e.g., from terminal 102a to terminal 102b, from terminal 102c to terminal 102b, from terminal 102c to terminal 102a, from terminal 102c to bulk, etc.).

[0030] At block 304, a stress voltage is applied to a first terminal of the test transistor and an amplifier voltage is applied to a control terminal of the test transistor to cause a stress current to flow through the test transistor. test The first terminal 102a of the internal test transistor 102 is provided with a stress voltage V stress (For example, ranging from 300 to 800 volts, from 400 to 700 volts, or some other suitable range), the stress voltage is significantly higher than the normal operating voltage. In addition, the third voltage source 108 is in the first time period T test A control voltage V is supplied to the first input terminal 114a of the amplifier 114. ctrl (For example, a range from 0.1 to 20 volts, from 1 to 15 volts, from 5 to 10 volts, or some other suitable range.) In turn, amplifier 114 operates during a first time period T test The control terminal 102c of the internal test transistor 102 is supplied with the amplifier voltage V amp As a result, the stress current I stress In the first time period T test The current flows through the test transistor 102 between the first terminal 102a and the second terminal 102b.

[0031] At block 306, the temperature of the test transistor is increased and maintained at the increased temperature. For example, heater 118 heats test transistor 102 from a first temperature (e.g., room temperature) to a test temperature (e.g., in a range from 100 to 175 degrees Celsius, from 100 to 150 degrees Celsius, from 125 to 150 degrees Celsius, or some other suitable range) and maintains test transistor 102 at the test temperature for a first time period T. test .

[0032] At block 308 , the amplifier voltage at the control terminal of the test transistor is adjusted to maintain the stress current through the test transistor. For example, in some cases, increasing the temperature TEMP of the test transistor 102 may increase the on-resistance R of the test transistor 102 . on In turn, amplifier 114 responds to the on-resistance R of test transistor 102. on The increase of the amplifier voltage V provided to the control terminal 102c of the test transistor 102 increases. amp , to maintain the stress current I through the test transistor 102 stress The current level, despite the on-resistance R on Increase.

[0033] At block 310, the final performance of the test transistor is measured. For example, after removing electrical and thermal stresses from the test transistor 102, a normal operating voltage is applied to the first terminal 102a and the control terminal 102c of the test transistor 102 while the test transistor 102 is maintained at room temperature, and the performance of the test transistor (e.g., linear drain current, on-resistance, gate-source leakage, drain-source leakage, gate-bulk leakage, etc.) is measured by the probing circuit 110. For example, the probing circuit measures the voltages at the first terminal 102a, the second terminal 102b, and the control terminal 102c of the test transistor 102, and measures the current through the test transistor 102 (e.g., from terminal 102a to terminal 102b, from terminal 102c to terminal 102b, from terminal 102c to terminal 102a, from terminal 102c to bulk, etc.).

[0034] At block 312 , a difference between the initial performance and the final performance of the test transistor is determined. For example, the difference between the initial linear drain current of the test transistor 102 and the final linear drain current of the test transistor 102 is determined to determine linear drain current degradation caused by the stress test. Additionally, the difference between the initial on-resistance and the final on-resistance is determined, the difference between the initial leakage and the final leakage is determined, the difference between the initial threshold voltage and the final threshold voltage is determined, and so on. In some embodiments, in addition to the initial and final measurements, the performance of the test transistor 102 is measured and monitored during the stress test.

[0035] Figure 4 Show Figure 1 FIG4 is a circuit diagram 400 of some embodiments of an apparatus, wherein the detection circuit 110 , the first resistor 112 , and the amplifier 114 are integrated on an integrated chip 402 .

[0036] A first terminal 110a of the detection circuit 110 is coupled to a first terminal 402a of the integrated chip 402. The first terminal 402a is coupled to the output terminal 104a of the first voltage source 104 and the first terminal 102a of the test transistor 102. A second terminal 110b of the detection circuit 110, a first terminal 112a of the first resistor 112, and a second input terminal 114b of the amplifier 114 are coupled to the second terminal 402b of the integrated chip 402. The second terminal 402b is coupled to the second terminal 102b of the test transistor 102. A third terminal 110c of the detection circuit 110 and an output terminal 114c of the amplifier 114 are coupled to a third terminal 402c of the integrated chip 402. The third terminal 402c is coupled to the control terminal 102c of the test transistor 102. The second terminal 112b of the first resistor 112 is coupled to a fourth terminal 402d of the integrated chip 402. The fourth terminal 402d is coupled to the output terminal 106a of the second voltage source 106 (e.g., ground 122). The first input terminal 114 a of the amplifier 114 is coupled to a fifth terminal 402 e of the integrated chip. The fifth terminal 402 e is coupled to the output terminal 108 a of the third voltage source 108 .

[0037] In some embodiments, the apparatus further includes a control circuit 406. The control circuit 406 is coupled to the first voltage source 104 and the third voltage source 108 and controls the voltage levels output by the first voltage source 104 and the third voltage source 108. For example, a first terminal 406a of the control circuit 406 is coupled to the control terminal 104b of the first voltage source 104. The stress voltage V provided by the first voltage source 104 to the first terminal 102a of the test transistor 102 is V stress The control circuit 406 can be adjusted to adjust the electrical stress between the first terminal 102a and the second terminal 102b of the test transistor 102. For example, in some embodiments, the control circuit 406 controls the first voltage source 104 to provide 500 volts to the first terminal 102a of the test transistor 102. In some other embodiments, the control circuit 406 controls the first voltage source 104 to provide 520 volts to the first terminal 102a of the test transistor 102. In some other embodiments, the control circuit 406 controls the first voltage source 104 to provide 650 volts or some other suitable voltage to the first terminal 102a of the test transistor 102.

[0038] Furthermore, the second terminal 406b of the control circuit 406 is coupled to the control terminal 108b of the third voltage source 108. The third voltage source 108 provides a control voltage V to the first input terminal 114a of the amplifier 114. ctrl can be adjusted by the control circuit 406 to adjust the stress current I stress (Thereby adjusting the stress test duration.) For example, in some embodiments, the control circuit 406 controls the third voltage source 108 to provide a voltage of 5 volts to the first input terminal 114 a of the amplifier 114. In some such embodiments, the resistance of the first resistor is 1000 ohms, so the stress current through the test transistor 102 is approximately 5 milliamperes. In some such embodiments, the stress time (e.g., the amount of time the stress current flows through the test transistor 102 while the test transistor 102 is at the test temperature) is 10 minutes.

[0039] In some other embodiments, the control circuit 406 controls the third voltage source 108 to provide a voltage of 7.5 volts to the first input terminal 114a of the amplifier 114. In some such embodiments, the resistance of the first resistor is 1000 ohms, so the stress current through the test transistor 102 is approximately 7.5 milliamperes. In some such embodiments, the stress time is 7.5 minutes.

[0040] In some other embodiments, the control circuit 406 controls the third voltage source 108 to provide 10 volts or another suitable voltage to the first input terminal 114a of the amplifier 114. In some such embodiments, the resistance of the first resistor is 1000 ohms, so the stress current through the test transistor 102 is approximately 10 milliamperes. In some such embodiments, the stress time is 5 minutes.

[0041] In some embodiments, the control circuit 406 is coupled to the heater 118 (e.g., the third terminal 406 c of the control circuit 406 is coupled to the control terminal 118 a of the heater 118) and controls the heater 118 to maintain the temperature of the test transistor 102. The control circuit 406 can adjust the temperature of the test transistor 102 to adjust the thermal stress applied to the test transistor 102. For example, in some embodiments, the control circuit 406 controls the heater 118 to heat the test transistor 102 to 100 degrees Celsius. In some other embodiments, the control circuit 406 controls the heater 118 to heat the test transistor 102 to 125 degrees Celsius. In some other embodiments, the control circuit 406 controls the heater 118 to heat the test transistor 102 to 150 degrees Celsius or some other suitable temperature.

[0042] In some systems, stress testing is accelerated (reducing the duration of the stress test) by increasing the thermal stress on the test transistor 102 (e.g., increasing the temperature of the test transistor 102). However, increasing the thermal stress may increase the power consumption of the test. By using a constant current to accelerate the stress test (rather than increasing the temperature during the test to accelerate the stress test) as described in various embodiments of the present disclosure, the temperature of the test transistor can be reduced. Therefore, the power consumption of the stress test can be reduced.

[0043] In some embodiments, the apparatus further includes a calculation circuit 408 coupled to the detection circuit 110. For example, the detection circuit 110 has an output terminal 110d, which is coupled to an input terminal 408a of the calculation circuit 408 via a sixth terminal 402f of the integrated chip 402. The calculation circuit 408 receives the measurement values ​​(e.g., current measurement values, voltage measurement values, etc.) of the detection circuit and calculates the performance (e.g., on-resistance, leakage current, threshold voltage, linear drain current, etc.) of the test transistor 102 based on the measurement values ​​from the detection circuit 110. In addition, the calculation circuit 408 determines the difference between the measurement values ​​before the stress test and the measurement values ​​after the stress test. Thus, the calculation circuit 408 can determine the performance and reliability degradation of the test transistor 102.

[0044] In some embodiments, the first resistor 112 is a variable resistor having a control terminal 112c. The control terminal 112c is coupled to a terminal 406d of the control circuit 406 via a terminal 402g of the integrated chip 402. The resistance of the first resistor 112 can be adjusted to further adjust the stress current I stress (Thereby further adjusting the stress time.) For example, in some embodiments, the control circuit 406 controls the first resistor 112 to have a resistance of 500 ohms. In some such embodiments, the voltage at the first input terminal 114a of the amplifier 114 is 5 volts, so the stress current through the test transistor 102 is approximately 10 milliamperes. In some such embodiments, the stress time is 5 minutes.

[0045] In some other embodiments, the control circuit 406 controls the first resistor 112 to have a resistance of 1000 ohms. In some such embodiments, the voltage at the first input terminal 114a of the amplifier 114 is 5 volts, so the stress current through the test transistor 102 is approximately 5 milliamperes. In some such embodiments, the stress time is 10 minutes.

[0046] In some other embodiments, the control circuit 406 controls the first resistor 112 to have a resistance of 2000 ohms. In some such embodiments, the voltage at the first input terminal 114a of the amplifier 114 is 5 volts, so the stress current through the test transistor 102 is approximately 2.5 milliamperes. In some such embodiments, the stress time is 20 minutes.

[0047] Figure 5 Show Figure 4 Cross-sectional view 500 of some embodiments of the device.

[0048] In some embodiments, the test transistor 102 is located on a test wafer 502. Other transistors 506 and 508 are located on the test wafer 502 and are spaced apart from the test transistor 102. In some embodiments, the integrated chip 402 is referred to as a probe card chip and is disposed on a probe card 518. The test wafer 502 is disposed on a wafer support 504 within a test chamber 520. The heater 118 is located in the test chamber 520 and heats the test chamber 520. In some embodiments, the probe card 518 including the integrated chip 402 is located in the test chamber 520.

[0049] In some embodiments, a first probe 510 extends from the probe card 518 to the test transistor 102 and electrically couples the terminal 402a of the integrated chip 402 to the first terminal 102a of the test transistor 102. For example, the first probe 510 extends from a first connection (not shown) on the probe card 518 (which is coupled to the terminal 402a of the integrated chip 402) to a first conductive pad 526 on the test wafer 502 (which is coupled to the first terminal 102a of the test transistor 102). A second probe 512 extends from the probe card 518 to the test transistor 102 and electrically couples the terminal 402b of the integrated chip 402 to the second terminal 102b of the test transistor 102. For example, the second probe 512 extends from a second connection (not shown) on the probe card 518 (which is coupled to the terminal 402b of the integrated chip 402) to a second conductive pad 528 on the test wafer 502 (which is coupled to the second terminal 102b of the test transistor 102). The third probe 514 extends from the probe card 518 to the test transistor 102 and electrically couples the terminal 402 c of the integrated chip 402 to the control terminal 102 c of the test transistor. For example, the third probe 514 extends from a third connection (not shown) on the probe card 518 (which is coupled to the terminal 402 c of the integrated chip 402) to a third conductive pad 530 on the test wafer 502 (which is coupled to the control terminal 102 c of the test transistor 102).

[0050] In some embodiments, the first voltage source 104, the second voltage source 106, the third voltage source 108, the heater power supply 120, the control circuit 406, and the calculation circuit 408 are disposed within a test device 516. The test device 516 is coupled to a probe card 518 via external wiring 522. For example, the external wiring 522 couples the first terminal 402a of the integrated chip 402 to the first voltage source 104, the fourth terminal 402d of the integrated chip 402 to the second voltage source 106 (e.g., ground 122), the fifth terminal 402e of the integrated chip 402 to the third voltage source 108, and the sixth terminal 402f of the integrated chip 402 to the calculation circuit 408. The test device 516 is coupled to the heater 118 via external wiring 524. For example, the external wiring 524 couples the heater power supply 120 to the heater 118 and couples the terminal 406c of the control circuit 406 to the terminal 118a of the heater 118.

[0051] By integrating the first resistor 112 and the amplifier 114 into the probe card 518, a stress test can be performed on the test transistor 102 on the test wafer 502. As a result, parasitic resistance, parasitic inductance, and parasitic capacitance generated by packaging the test transistor 102 during the test process can be avoided. Therefore, the test results can have improved precision and accuracy. In addition, stress testing the test transistor 102 on the test wafer 502 can increase the speed of the chip manufacturing process, thereby increasing the yield of the chip. In addition, the number of sacrificial wafers can be reduced, thereby further increasing the yield of the chip.

[0052] In some embodiments, the first resistor 112 and the amplifier 114 are integrated into the test wafer 502. For example, the first resistor 112 and the amplifier 114 are formed on the test wafer 502 and coupled to the test transistor 102 through on-wafer interconnects.

[0053] In some embodiments, test wafer 502 is diced, test transistors 102 are packaged, the test transistor packages are placed on an evaluation board, and stress testing is performed on the packaged test transistors 102 on the evaluation board. In some embodiments, this package-level testing is performed in addition to wafer-level testing. In some embodiments, package-level testing and wafer-level testing are performed alternately.

[0054] Figure 6 Flowchart 600 illustrates some embodiments of a process flow for producing a test transistor.

[0055] In block 602, a wafer is fabricated. For example, a plurality of transistors are formed on the wafer.

[0056] At block 604, the wafer is probed to test the transistors on the wafer to ensure they are functioning properly. Additionally, stress testing is performed on the transistors on the wafer. In some embodiments, probing and wafer-level stress testing can take approximately one week. For example, in some embodiments, probing can take approximately one week, and stress testing can take approximately 10 minutes.

[0057] The wafer is diced and the chips are packaged at block 606. In some embodiments, dicing and packaging may take approximately three weeks.

[0058] Figure 6 Flowchart 650 further illustrates some other embodiments of a process flow for testing transistors.

[0059] At block 652 , a wafer is fabricated.

[0060] At block 654 , the wafer is probed to test the transistors on the wafer to ensure that they are functioning properly.

[0061] At block 656 , the wafer is diced and the chips are packaged.

[0062] At block 658, the transistor is subjected to stress testing. For example, the package containing the transistor is subjected to stress testing on an evaluation board. In some embodiments, the package-level stress test takes approximately 10 minutes.

[0063] Figure 7 Show Figure 4 700 of some embodiments of an apparatus, wherein a first function generator circuit 702 is coupled between the third voltage source 108 and the amplifier 114.

[0064] First function generator circuit 702 has a first input terminal 702a coupled to output terminal 108a of third voltage source 108, a second input terminal 702b coupled to terminal 406e of control circuit 406, and an output terminal 702c coupled to first input terminal 114a of amplifier 114 (via terminal 402e of integrated chip 402).

[0065] The first function generator circuit 702 receives a control voltage from the third voltage source 108 and an input signal from the control circuit 406. Based on the voltage from the third voltage source 108 and the input signal from the control circuit 406, the first function generator circuit 702 outputs a control signal to the first input terminal 114a of the amplifier 114. In some embodiments, the control signal is a square wave whose maximum voltage is set by the third voltage source 108 and whose frequency and duty cycle are set by the control circuit 406. For example, in some embodiments, the control signal is a square wave signal with a peak voltage ranging from 1 to 15 volts or other suitable voltages, a frequency ranging from 1000 Hz to 100 million Hz or other suitable frequencies, and a duty cycle ranging from 1% to 50% or other suitable duty cycle. In some other embodiments, the control signal is a step signal that steps from a first voltage to a second voltage, then to a third voltage, and so on. In still other embodiments, the control signal is a ramp signal or some other suitable signal.

[0066] In some embodiments, the apparatus further includes a second function generator circuit 704. The second function generator circuit 704 has a first input terminal 704a coupled to the output terminal 104a of the first voltage source 104, a second input terminal 704b coupled to the terminal 406f of the control circuit 406, and an output terminal 704c coupled to the first terminal 102a of the test transistor 102.

[0067] The second function generator circuit 704 receives the voltage from the first voltage source 104 and the input signal from the control circuit 406. Based on the voltage from the first voltage source 104 and the input signal from the control circuit 406, the second function generator circuit 704 outputs a stress signal to the first terminal 102a of the test transistor 102. In some embodiments, the stress signal is a square wave whose maximum voltage is set by the first voltage source 104 and whose frequency and duty cycle are set by the control circuit 406. In some other embodiments, the stress signal is a step signal. For example, in some embodiments, the stress signal steps from 0 volts to 400 volts in 25 volt steps. In some other embodiments, the stress signal steps from 0 volts to 600 volts or other suitable voltages in 50 volt steps or other suitable steps. In some embodiments, the stress signal is a square wave signal with a peak voltage in the range of 400 to 600 volts or other suitable voltages, a frequency in the range of 1000 Hz to 100 million Hz or other suitable frequencies, and a duty cycle in the range of 1% to 50% or other suitable duty cycles. In some embodiments, the stress signal is a ramp signal or other suitable signal.

[0068] In some embodiments, in addition to or as an alternative to the HTRB stress test, the test transistor 102 is subjected to a high temperature operating life (HTOL) test, wherein the temperature of the test transistor 102 is raised to a test temperature ranging from 125 degrees Celsius to 175 degrees Celsius or other suitable temperature, the frequency of the control signal ranges from 1000 Hz to 100 million Hz or other suitable frequency, the duty cycle of the control signal ranges from 1% to 50% duty cycle, the stress voltage output at the first voltage source 104 ranges from 40 volts to 1200 volts, and leakage of the test transistor 102 is measured. For example, the leakage is measured before and after applying the HTOL stress, and the difference between the initial leakage and the final leakage is determined.

[0069] In some embodiments, in addition to or as an alternative to the HTRB stress test and / or the HTOL test, the test transistor 102 is subjected to a high temperature current collapse (HTCC) test, wherein the temperature of the test transistor is raised to a test temperature in the range of 125 degrees Celsius to 175 degrees Celsius or other suitable temperature, the control signal is a pulse signal having a pulse duration of 1 microsecond to 1 second or other suitable pulse duration, the control signal is periodic having a period of 1 millisecond to 1 second or other suitable time period, and the on-resistance of the test transistor 102 is measured before and after the HTCC test.

[0070] In some embodiments, in addition to or as an alternative to the stress test, the HTOL test, and / or the HTCC test, the test transistor is further subjected to a room temperature current collapse (RTCC) test, wherein the temperature of the test transistor 102 is set to room temperature (e.g., 25 degrees Celsius), the control signal is a pulse signal with a pulse duration ranging from 1 microsecond to 1 second or other suitable pulse durations, the control signal is periodic with a period ranging from 1 millisecond to 1 second or other suitable time periods, and the on-resistance of the test transistor 102 is measured before and after the RTCC test.

[0071] Figure 8 Show Figure 7 800 of some embodiments of a device, wherein the device further includes a second resistor 802, a third resistor 804, and a fourth resistor 806.

[0072] The second resistor 802 has a first terminal 802a coupled to the second terminal 102b of the test transistor 102 via the terminal 402b of the integrated chip 402. The second resistor 802 has a second terminal 802b coupled to the first terminal 112a of the first resistor 112 and the second input terminal 114b of the amplifier 114. The third resistor 804 has a first terminal 804a coupled to the output terminal 702c of the first function generator circuit 702 and / or to the output terminal 108a of the third voltage source 108 via the terminal 402e of the integrated chip 402. The third resistor 804 has a second terminal 804b coupled to the first input terminal 114a of the amplifier 114. The fourth resistor 806 has a first terminal 806a coupled to the second terminal 804b of the third resistor 804 and the first input terminal 114a of the amplifier 114. The fourth resistor 806 has a second terminal 806b that is coupled to the second voltage source 106 (eg, ground 122) via the terminal 402d of the integrated chip 402. In some embodiments, the resistors 112, 802, 804, 806, and the amplifier 114 are integrated into a test wafer (eg, Figure 5 502) and coupled via on-wafer interconnects.

[0073] The first resistor 112 and the second resistor 802 form a first voltage divider that provides a portion of the voltage at the second terminal 102 b of the test transistor 102 to the second input terminal 114 b of the amplifier 114. The third resistor 804 and the fourth resistor 806 form a second voltage divider that provides a portion of the voltage from the third voltage source 108 to the first input terminal 114 a of the amplifier 114.

[0074] The second resistor 802 and the third resistor 804 have a first temperature coefficient. The first resistor 112 and the fourth resistor 806 have a second temperature coefficient that is less than the first temperature coefficient. The second temperature coefficient is relatively low in magnitude, such that the resistance of the first resistor 112 and the resistance of the fourth resistor 806 are substantially stable over a certain temperature range. The first temperature coefficient is relatively high in magnitude, such that the resistance of the second resistor 802 and the resistance of the third resistor 804 vary with temperature. For example, when the temperature of the resistors 112, 802, 804, 806 increases from a first temperature to a second temperature during a stress test, the resistance of the first resistor 112 and the resistance of the fourth resistor 806 remain substantially constant, while the resistance of the second resistor 802 and the resistance of the third resistor 804 change from the first resistance to the second resistance.

[0075] Since the resistance of the second resistor 802 and the resistance change of the third resistor 804 are substantially the same, the amplifier voltage V outputted from the output terminal 114c of the amplifier 114 is ampTherefore, the influence of temperature on the output of the amplifier 114 can be reduced, and the dependence of the performance of the entire device on temperature can be reduced.

[0076] In some embodiments, the first resistor 112 and the fourth resistor 806 are silicon chromium (SiCr) thin film resistors (TFRs), and the second resistor 802 and the third resistor 804 are gallium nitride (GaN) two-dimensional electron gas (2DEG) resistors.

[0077] Figure 9 A cross-sectional view 900 of some embodiments of testing transistor 102 is shown.

[0078] In some embodiments, the test transistor 102 is a gallium nitride (GaN) high electron mobility transistor (HEMT). The test transistor 102 is formed along a semiconductor substrate 902. A nucleation layer 904 is located above the semiconductor substrate 902. A buffer layer 906 is located above the nucleation layer 904. A superlattice layer 908 is located above the buffer layer 906. A channel layer 910 is located above the superlattice layer 908. A barrier layer 912 is located above the channel layer 910. In some embodiments, a two-dimensional electrode gas layer 930 is located within the channel layer 910 and along the interface between the channel layer 910 and the barrier layer 912.

[0079] A first source / drain structure 914 and a second source / drain structure 916 are laterally spaced apart above barrier layer 912. A gate structure 918 is located above barrier layer 912 and between source / drain structures 914, 916. In some embodiments, a capping layer 920 is located between gate structure 918 and barrier layer 912. The source / drain structures may be referred to individually or collectively as sources or drains, depending on the context.

[0080] A dielectric structure 922 is located over source / drain structures 914, 916 and gate structure 918. In some embodiments, a field plate 924 extends from over first source / drain structure 914 to over gate structure 918. An interconnect 926 extends from field plate 924 to first source / drain structure 914.

[0081] In some embodiments, during the fabrication of the test transistor 102, defects 928 (e.g., crystal defects such as vacancies, grain boundaries, edge dislocations, screw dislocations, mixed dislocations, grooves, pits, etc.) are formed along the buffer layer 906. Furthermore, in some embodiments, during the fabrication of the test transistor 102, defects 932 are formed along the surface of the barrier layer 912.

[0082] In some embodiments, the semiconductor substrate 902 comprises silicon or other suitable materials. In some embodiments, the nucleation layer 904 comprises aluminum nitride or other suitable materials. In some embodiments, the buffer layer 906 comprises aluminum gallium nitride or other suitable materials with graded aluminum and gallium concentrations. In some embodiments, the superlattice layer 908 comprises gallium nitride or other suitable materials. In some embodiments, the channel layer 910 comprises gallium nitride or other suitable materials. In some embodiments, the barrier layer 912 comprises aluminum gallium nitride or other suitable materials. In some embodiments, the capping layer 920 comprises gallium nitride or other suitable materials. In some embodiments, the source / drain structures 914, 916, the gate structure 918, the field plate 924, and / or the interconnect 926 comprise copper, tungsten, titanium, aluminum, nickel, gold, or other suitable materials. In some embodiments, the dielectric structure 922 comprises silicon dioxide, silicon nitride, or some other suitable material.

[0083] Therefore, in some embodiments, the present disclosure relates to an apparatus for stress testing, comprising a first voltage source, a second voltage source, and a third voltage source, a detection circuit, a first resistor, and an amplifier. The first voltage source is coupled to a first terminal of a test transistor. The detection circuit has a first terminal, a second terminal, and a third terminal. The first terminal of the detection circuit is coupled to the first terminal of the test transistor. The second terminal of the detection circuit is coupled to the second terminal of the test transistor. The third terminal of the detection circuit is coupled to a control terminal of the test transistor. The first resistor has a first terminal and a second terminal. The first terminal of the first resistor is coupled to the second terminal of the test transistor. The second terminal of the first resistor is coupled to the second voltage source. The amplifier has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the third voltage source. The second input terminal is coupled to the first terminal of the first resistor. The output terminal is coupled to the control terminal of the test transistor. In some embodiments, the first resistor has a control terminal, and the apparatus further includes a control circuit having a first output terminal coupled to the control terminal of the first resistor. In some embodiments, the first voltage source has a control terminal coupled to the second output terminal of the control circuit; and the third voltage source has a control terminal coupled to the third output terminal of the control circuit. In some embodiments, the apparatus includes a first signal generator circuit coupled between a third voltage source and a first input terminal of the amplifier. In some embodiments, the apparatus includes a second signal generator circuit coupled between the first voltage source and a first terminal of the test transistor. In some embodiments, the apparatus includes a voltage divider circuit coupled between the third voltage source and the first input terminal of the amplifier, wherein the voltage divider circuit has a first terminal coupled to the third voltage source, a second terminal coupled to the first input terminal of the amplifier, and a third terminal coupled to the second voltage source. In some embodiments, the apparatus includes a second resistor having a first terminal and a second terminal; the first terminal of the second resistor is coupled to the second terminal of the test transistor; and the second terminal of the second resistor is coupled to the second input terminal of the amplifier and the first terminal of the first resistor. In some embodiments, the voltage divider circuit includes a third resistor and a fourth resistor; the first terminal of the third resistor is coupled to the third voltage source; the second terminal of the third resistor and the first terminal of the fourth resistor are coupled to the first input terminal of the amplifier; and the second terminal of the fourth resistor is coupled to the second voltage source. In some embodiments, the first and third resistors have a first temperature coefficient, and the second and fourth resistors have a second temperature coefficient different from the first temperature coefficient. In some embodiments, the first resistor and the third resistor have a first resistance, and the second resistor and the fourth resistor have a second resistance different from the first resistance.In some embodiments, the first resistor is located on the integrated chip, the amplifier is located on the integrated chip, and the test transistor is located on a test wafer separate from the integrated chip, and the apparatus includes: a first wafer probe extending from the integrated chip to the test wafer and coupling a first voltage source and a first terminal of a detection circuit to a first terminal of the test transistor; a second wafer probe extending from the integrated chip to the test wafer and coupling a first terminal of the first resistor, a second input terminal of the amplifier, and a second terminal of the detection circuit to a second terminal of the test transistor; and a third wafer probe extending from the integrated chip to the test wafer and coupling an output terminal of the amplifier and a third terminal of the detection circuit to a control terminal of the test transistor. In some embodiments, the apparatus includes a test chamber in which the integrated chip and the test wafer are arranged, and a heater in the test chamber. In some embodiments, the first resistor is located on the integrated chip, the amplifier is located on the integrated chip, and the test transistor is located on the integrated chip.

[0084] In other embodiments, the present disclosure relates to an apparatus for stress testing, comprising a first voltage source, a second voltage source, a third voltage source, a detection circuit, a first resistor, and an amplifier. The first voltage source is coupled to a first terminal of a test transistor and configured to provide a stress voltage to the first terminal of the test transistor. The detection circuit is coupled to the first terminal of the test transistor, the second terminal of the test transistor, and a control terminal of the test transistor. The detection circuit is configured to measure a voltage across the test transistor and a current through the test transistor. A first resistor is coupled between the second terminal of the test transistor and the second voltage source. An amplifier is coupled to the test transistor and the first resistor. The amplifier is configured to receive a control voltage from the third voltage source and provide an amplifier voltage to the control terminal of the test transistor based on a voltage across the first resistor and the control voltage, thereby causing a current having a test current level to flow through the test transistor. The amplifier is configured to adjust the amplifier voltage to maintain the test current level through the test transistor. In some embodiments, the apparatus includes a signal generator configured to generate a control signal based on the control voltage, a frequency, and a duty cycle, and configured to provide the control signal to the amplifier; the amplifier is configured to provide the amplifier voltage to the control terminal of the test transistor based on the control signal. In some embodiments, the apparatus includes a control circuit configured to adjust the resistance of the first resistor, adjust the control voltage, and adjust the stress voltage. In some embodiments, the apparatus includes: a first voltage divider circuit coupled to a third voltage source and an amplifier and configured to adjust the control voltage based on a temperature of the first voltage divider circuit; and a second voltage divider circuit including the first resistor, coupled to a test transistor and the amplifier and configured to adjust the voltage across the first resistor based on the temperature of the second voltage divider circuit.

[0085] In yet other embodiments, the present disclosure relates to a method for stress testing, comprising measuring an initial performance of a test transistor before a first time period. The method comprises, after measuring the initial performance of the test transistor, applying a first voltage to a control terminal of the test transistor to cause a first current to flow through the test transistor during the first time period. The method comprises increasing the temperature of the test transistor from a first temperature to a second temperature, and maintaining the temperature of the test transistor at the second temperature during the first time period. The method comprises adjusting the first voltage during the first time period in response to the increase in the temperature of the test transistor to maintain the first current through the test transistor during the first time period. The method comprises measuring a final performance of the test transistor after the first time period. The method comprises determining a difference between the initial performance of the test transistor and the final performance of the test transistor. In some embodiments, the method comprises adjusting a resistance between a second terminal of the test transistor and ground to adjust the magnitude of the first current. In some embodiments, the method comprises adjusting the first voltage to adjust the magnitude of the first current. In some embodiments, the method comprises oscillating the first voltage based on a frequency and a duty cycle.

[0086] The components of several embodiments have been discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It will be appreciated by those skilled in the art that the present invention can be easily used as a basis to design or modify other processes and structures to achieve the same purpose and / or advantages as the embodiments described herein. It will also be appreciated by those skilled in the art that these equivalent structures do not depart from the spirit and scope of the present invention, and that various variations, replacements, and changes may be made without departing from the spirit and scope of the present invention.

Claims

1. A device for stress testing, comprising: a first voltage source, a second voltage source, and a third voltage source, the first voltage source being coupled to a first terminal of a test transistor; a detection circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the detection circuit is coupled to the first terminal of the test transistor, the second terminal of the detection circuit is coupled to the second terminal of the test transistor, and the third terminal of the detection circuit is coupled to the control terminal of the test transistor; a first resistor having a first terminal and a second terminal, the first terminal of the first resistor being coupled to the second terminal of the test transistor, the second terminal of the first resistor being coupled to the second voltage source; as well as An amplifier has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the amplifier is coupled to the third voltage source, the second input terminal of the amplifier is coupled to the first terminal of the first resistor, and the output terminal of the amplifier is coupled to the control terminal of the test transistor.

2. The device for stress testing according to claim 1, wherein: The first resistor has a control terminal, the apparatus further comprising: A control circuit has a first output terminal coupled to a control terminal of the first resistor.

3. The device for stress testing according to claim 2, wherein: The first voltage source has a control terminal coupled to the second output terminal of the control circuit, and wherein the third voltage source has a control terminal coupled to the third output terminal of the control circuit.

4. The apparatus for stress testing according to claim 1 , further comprising: A first signal generator circuit is coupled between the third voltage source and the first input terminal of the amplifier.

5. The apparatus for stress testing according to claim 4, further comprising: A second signal generator circuit is coupled between the first voltage source and the first terminal of the test transistor.

6. The apparatus for stress testing according to claim 1 , further comprising: A voltage divider circuit is coupled between the third voltage source and the first input terminal of the amplifier, the voltage divider circuit having a first terminal coupled to the third voltage source, a second terminal coupled to the first input terminal of the amplifier, and a third terminal coupled to the second voltage source.

7. The apparatus for stress testing according to claim 6, further comprising: a second resistor having a first terminal and a second terminal, the first terminal of the second resistor being coupled to the second terminal of the test transistor, the second terminal of the second resistor being coupled to the second input terminal of the amplifier and the first terminal of the first resistor, The voltage divider circuit includes a third resistor and a fourth resistor, a first terminal of the third resistor is coupled to the third voltage source, a second terminal of the third resistor and a first terminal of the fourth resistor are coupled to the first input terminal of the amplifier, and a second terminal of the fourth resistor is coupled to the second voltage source.

8. The device for stress testing according to claim 1, wherein: The first resistor is located on an integrated chip, and the amplifier is located on the integrated chip, and wherein the test transistor is located on a test wafer separate from the integrated chip, the apparatus further comprising: a first wafer probe extending from the integrated chip to the test wafer and coupling the first voltage source and the first terminal of the detection circuit to the first terminal of the test transistor; a second wafer probe extending from the integrated chip to the test wafer and coupling the first terminal of the first resistor, the second input terminal of the amplifier, and the second terminal of the detection circuit to the second terminal of the test transistor; and A third wafer probe extends from the integrated chip to the test wafer and couples the output terminal of the amplifier and the third terminal of the detection circuit to the control terminal of the test transistor.

9. A device for stress testing, comprising: a first voltage source, a second voltage source, and a third voltage source, the first voltage source being coupled to a first terminal of a test transistor and configured to provide a stress voltage to the first terminal of the test transistor; a detection circuit coupled to the first terminal of the test transistor, the second terminal of the test transistor, and the control terminal of the test transistor, the detection circuit configured to measure a voltage across the test transistor and a current flowing through the test transistor; a first resistor coupled between the second terminal of the test transistor and the second voltage source; as well as an amplifier coupled to the test transistor and the first resistor, the amplifier configured to receive a control voltage from the third voltage source, provide an amplifier voltage to a control terminal of the test transistor based on a voltage across the first resistor and the control voltage to cause a current having a test current level to flow through the test transistor, and the amplifier configured to adjust the amplifier voltage to maintain the test current level flowing through the test transistor.

10. A method for stress testing, comprising: measuring initial performance of the test transistor before a first time period; After measuring initial performance of the test transistor, applying a first voltage to a control terminal of the test transistor to cause a first current to flow through the test transistor during the first time period; increasing the temperature of the test transistor from a first temperature to a second temperature, and maintaining the temperature of the test transistor at the second temperature during the first time period; In response to an increase in temperature of the test transistor, adjusting the first voltage during the first time period to maintain a first current through the test transistor during the first time period; measuring a final performance of the test transistor after the first period of time; and determining a difference between the initial performance of the test transistor and the final performance of the test transistor.

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