Data storage device by erasing memory block packets and method of operating same

Abstract

The invention provides a data storage device and an operating method thereof. The data storage device may include: a storage medium including a plurality of storage blocks; and a memory controller configured to combine memory blocks that are simultaneously accessed among the plurality of memory blocks to manage the combined memory block as a super block. The memory controller erases a preliminary super block for a subsequent write operation during a write time corresponding to a write operation mode of a selected super block that performs the write operation. The memory controller divides the memory blocks of the preliminary super block into a plurality of erase units, each including a set number of memory blocks, the plurality of erase units being sequentially erased with a uniform erase interval between erase operations of the plurality of erase units.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean application No. 10-2024-0039907, filed on March 22, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a data storage device, and more particularly, to a data storage device that erases memory blocks in groups and a method of operating the data storage device. Background Art

[0004] A semiconductor memory device may include a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines.

[0005] Flash memory devices, typically non-volatile memory devices, can define a group of memory cells sharing a common word line as a page. Furthermore, a flash memory device can include multiple memory blocks. Each memory block can include multiple pages. Programming and reading operations on the memory cells of a flash memory device can be performed page by page. Erasing operations on a flash memory device can be performed block by block. Furthermore, a flash memory device can group some memory blocks that are accessed simultaneously and manage some of the memory blocks as super blocks to increase access speed.

[0006] However, when erasing a super block, the peak power required to erase the super block may increase. Currently, the memory blocks included in the super block can be divided into multiple memory groups, each memory group including at least one of the memory blocks from the super block. The erase operation can be performed on a memory group by memory group basis. Summary of the Invention

[0007] According to an embodiment of the present disclosure, a data storage device may be provided. The data storage device may include a storage medium and a storage controller. The storage medium may include multiple storage blocks. The storage controller combines storage blocks that are accessed simultaneously among the multiple storage blocks to manage the combined storage blocks as a super block. The storage controller erases a preliminary super block for subsequent write operations during a write time set according to a write operation mode of a selected super block for performing a write operation. The storage controller divides the storage blocks of the preliminary super block into multiple erase units, each erase unit including a set number of storage blocks, and the multiple erase units are sequentially erased using uniform erase intervals between erase operations of the multiple erase units.

[0008] According to an embodiment of the present disclosure, a data storage device may be provided. The data storage device may include a storage controller. The storage controller may combine storage blocks that are accessed simultaneously among a plurality of storage blocks included in a storage medium to manage the combined storage blocks as a super block. The storage controller may erase a preliminary super block for a subsequent write operation during a write time set according to a write operation mode of a super block selected for performing a write operation. In addition, the storage controller may group the storage blocks of the preliminary super block into a plurality of erase units and determine whether to complete the erase operation of the plurality of erase units of the preliminary super block within the write time based on the erase time of each erase unit, the number of storage blocks in each erase unit, and the erase interval between the erase operations of the plurality of erase units.

[0009] According to an embodiment of the present disclosure, a method for operating a data storage device may be provided. The method may include: combining simultaneously accessed storage blocks from a plurality of storage blocks to manage the combined storage blocks as a super block; determining a write time set according to a write operation mode of a selected super block for performing a write operation; dividing a plurality of storage blocks of a preliminary super block for a subsequent write operation into a plurality of erase units; and erasing the plurality of erase units using a uniform erase interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the embodiments of the present disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a data processing system according to an embodiment of the present disclosure;

[0012] Figure 2 is a view illustrating a concept for managing a storage medium including a nonvolatile memory device according to an embodiment of the present disclosure;

[0013] Figure 3 is a block diagram illustrating an erase management circuit according to an embodiment of the present disclosure;

[0014] Figure 4 is a diagram illustrating a concept of grouping memory blocks based on the type of write operation and determining an erase interval according to an embodiment of the present disclosure;

[0015] Figure 5A and Figure 5B is a graph illustrating peak power of an erase operation based on a preliminary super block according to an embodiment of the present disclosure;

[0016] Figure 6 is a diagram illustrating a concept of grouping memory blocks based on the type of write operation and determining an erase interval according to an embodiment of the present disclosure;

[0017] Figure 7A and Figure 7B is a graph illustrating peak power of an erase operation based on a preliminary super block according to an embodiment of the present disclosure;

[0018] Figure 8 is a diagram illustrating a concept of grouping memory blocks based on the type of write operation and determining an erase interval according to an embodiment of the present disclosure;

[0019] Figure 9A and Figure 9B is a graph illustrating peak power of an erase operation based on a preliminary super block according to an embodiment of the present disclosure; and

[0020] Figure 10 is a flowchart illustrating a method of operating a data storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Various embodiments of the present disclosure will be described in greater detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments and intermediate structures. Therefore, variations from the illustrated configurations and shapes are to be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the described embodiments should not be construed as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes without departing from the spirit and scope of the embodiments as defined by the appended claims.

[0022] Embodiments of the present disclosure are described herein with reference to cross-sections and / or plan views of the embodiments of the present disclosure. However, the embodiments of the present disclosure should not be construed as limiting the inventive concept. Although some embodiments of the present disclosure will be shown and described, it will be understood by those skilled in the art that these embodiments may be modified without departing from the principles and spirit of the embodiments.

[0023] As used herein, the term "configuration" refers to the size, shape, material composition, orientation, connection structure between components, and arrangement of one or more of at least one structure and at least one device to facilitate operation of one or more of the structure and device in a predetermined manner.

[0024] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0025] As used herein, the phrases "interfacing with," "coupled to," and "connected to" refer to structures being operatively connected to each other, such as by direct contact or electrically connected through an indirect connection medium (eg, through another structure).

[0026] Figure 1 is a block diagram illustrating a data processing system 10 according to an embodiment of the present disclosure.

[0027] Reference Figure 1 , the data processing system 10 may include an external device 100 and a data storage device 200 .

[0028] The external device 100 may include at least one processor. The external device 100 may be the processor itself, or the external device 100 may be an electronic device or system including a processor. The external device 100 may be referred to as a host.

[0029] The data storage device 200 may include a storage controller 210, a buffer memory device 220, and a storage medium 260. The storage medium 260 may include a plurality of nonvolatile memory devices 230, 240, and 250.

[0030] The external device 100 may transmit a write request including a write command WT, an address ADD, and write data DATA to the data storage device 200 to write data. When the data storage device 200 receives the write request, the data storage device 200 may control the storage medium 260 to program the write data.

[0031] The external device 100 may transmit a read request including a read command RD and an address ADD to the data storage device 200 to read data. The data storage device 200 may read the requested data from the storage medium 260 and transmit the requested data to the external device 100 as data DATA.

[0032] The data storage device 200 can not only perform read operations and write operations in response to external requests such as read requests and write requests, but can also read data from / write data to the storage medium 260 in order to perform internal operations of the data storage device 200. The internal operations of the data storage device 200 may include housekeeping operations that are performed independently of external requests from the external device 100. For example, the housekeeping operations may include garbage collection operations, wear leveling operations, or read reclaim operations. The data storage device 200 can use the storage space of the storage medium 260 and / or ensure the reliability of the data stored in the storage medium 260 through the housekeeping operations.

[0033] The buffer memory device 220 may temporarily store data transferred between the external device 100 and the data storage device 200 during a write operation or a read operation.

[0034] The memory controller 210 may interface between the external device 100 and the data storage device 200. The memory controller 210 may include an erase management circuit 30.

[0035] The data storage device 200 may include at least one Super Block. For example, the operation of the data storage device 200 may be performed Super Block by Super Block. For example, the Super Block to be written to in a subsequent step should be erased based on the write operation mode or the type of Super Block in the write operation.

[0036] The time required for a write operation may vary depending on the write operation mode. Therefore, during a write operation of a super block, an erase operation of the super block for a subsequent write operation should be completed.

[0037] The write operation mode can be divided into a sequential write operation and a random write operation.

[0038] For example, the sequential write operation may be performed by at least one of a write request of the external device 100 and an internal operation of the data storage device 200 .

[0039] For example, the random write operation may be performed by a write request of the external device 100. Alternatively, the random write operation may be performed by an internal operation of the data storage device 200.

[0040] As shown in Table 1, the write time may vary based on the write operation mode. In addition, the write time may vary based on the write operation mode and the state of the data storage device 200.

[0041] [Table 1]

[0042] Type of write operation Write time Sequential write operations based on requests from external devices or internal operations of data storage devices a Random write operations according to requests from external devices b Random write operations based on internal operations c

[0043] Data storage device 200 can be managed using Super Blocks of different sizes. In one embodiment, data storage device 200 can be managed using a first Super Block having a first number of memory blocks and a second Super Block having a second number of memory blocks that is different from the first number. For the same type of write operation, the first Super Block and the second Super Block can have different write times. Furthermore, during an erase operation, the first Super Block and the second Super Block can have different power consumption.

[0044] The erase management circuit 30 may determine the number of memory blocks included in an erase unit and an erase interval between erase units.

[0045] For example, the erase management circuit 30 may set an erase unit based on the write time of the Super Block for performing a current write operation (hereinafter referred to as the first write operation) to ensure the write time of the preliminary Super Block for performing a subsequent write operation (hereinafter referred to as the second write operation). The erase unit may be obtained by grouping a set number of memory blocks constituting the preliminary Super Block.

[0046] In various embodiments, the erase management circuit 30 may group the memory blocks based on the number of memory blocks in the preliminary super block and the erase time of each memory block, thereby making the erase interval between erase units uniform.

[0047] The detailed description of the erase management circuit 30 will be referred to later. Figure 3 Provide a description.

[0048] Figure 2 is a view illustrating a concept for managing a storage medium including a nonvolatile memory device according to an embodiment of the present disclosure.

[0049] The nonvolatile memory device included in storage medium 260 may include at least one die. For example, the die may include multiple dies DIE 0 and DIE 1. Each of dies DIE 0 and DIE 1 may include at least one plane. For example, die DIE 0 may include multiple planes PLANE00 / PLANE01, and die DIE 1 may include multiple planes PLANE10 / PLANE11. The multiple planes PLANE00 / PLANE01 and PLANE10 / PLANE11 may include multiple memory blocks BLOCK000-BLOCK00N, BLOCK010-BLOCK01N, BLOCK100-BLOCK10N, and BLOCK110-BLOCK11N, respectively. Each of the memory blocks BLOCK000 - BLOCK00N, BLOCK010 - BLOCK01N, BLOCK100 - BLOCK10N, and BLOCK110 - BLOCK11N may include a plurality of pages PAGE 0 - PAGE M.

[0050] The storage medium 260 can input / output data through channels CHa and CHb. Each channel CHa and CHb can input / output data in an interleaved manner. Each channel CHa and CHb can be connected to its respective planes PLANE00 / PLANE01 and PLANE10 / PLANE11, for example, via a plurality of paths WAY0, WAY1, WAY2, and WAY3 that branch into the common channels CHa and CHb.

[0051] Reference Figure 2 , each of the dies DIE0 and DIE1 can be connected to independent channels CHa and CHb, respectively, and each of the planes PLANE00 / PLANE01 and PLANE10 / PLANE11 can be connected to paths WAY0, WAY1, WAY2, and WAY3 branching from each channel CHa and CHb, respectively. However, the configuration of the nonvolatile memory device is not limited to this embodiment.

[0052] The memory controller 210 may include at least one super block by grouping simultaneously accessible memory blocks among a plurality of memory blocks.

[0053] For example, a super block may include A1 group memory blocks BLOCK000 and BLOCK010 or A2 group memory blocks BLOCK100 and BLOCK110 in different planes PLANE00 / PLANE01 or PLANE10 / PLANE11 within the same die DIE 0 or DIE 1. Alternatively, a super block may include B group memory blocks BLOCK001, BLOCK011, BLOCK101, and BLOCK111 in different planes PLANE00 to PLANE11 and different dies DIE 0 and DIE 1.

[0054] Figure 3 is a block diagram illustrating an erase management circuit according to an embodiment of the present disclosure.

[0055] Reference Figure 3 The erase management circuit 30 may include a write mode determination circuit 310 , a grouping circuit 320 , an erase interval determination circuit 330 , and an erase control circuit 340 .

[0056] When data is written to the selected Super Block, the preliminary Super Block for the subsequent write operation may be erased in preparation for the subsequent write operation in the preliminary Super Block.

[0057] Since the write time varies based on the write operation pattern of the Super Block, it is advantageous for the erase time of the preliminary Super Block to be shorter than or equal to the write time of the selected Super Block for the current write operation.

[0058] In addition, since the power consumption of the data storage device 200 may increase in proportion to the number of memory blocks being erased simultaneously, the erase units of the preliminary super block may be grouped to include a minimum number of memory blocks being erased simultaneously. A uniform erase interval may be set between the erase units to obtain stable performance of the data storage device 200.

[0059] The write mode determination circuit 310 may determine a write time based on a write operation mode of the selected super block. For example, the write operation mode may be divided into a sequential write operation by a request of the external device 100 or an internal operation of the data storage device 200, a random write operation by a request of the external device 100, and a random write operation by an internal operation of the data storage device 200.

[0060] The grouping circuit 320 may group the simultaneously erased memory blocks of the preliminary super block to define an erase unit. An erase unit may include a minimum number of simultaneously erased memory blocks.

[0061] For example, the write time may be determined by Equation 1 below.

[0062] Equation 1

[0063] T>E × (B / X) (where X is the smallest natural number that satisfies Equation 1)

[0064] In Equation 1, T is a write time, E is an erase time per memory block, B is the number of memory blocks in a preliminary super block, and X is the number of simultaneously erased memory blocks of an erase unit.

[0065] Therefore, the number of erase units in the preliminary super block can be determined as (B / X).

[0066] The erase interval determination circuit 330 may determine the erase interval IG between erase units based on Equation 3 so that the idle time I satisfying Equation 2 is evenly distributed between the erase units.

[0067] Equation 2

[0068] T = I + E × (B / X)

[0069] Equation 3

[0070] IG = I / (B / X) or IG = I / ((B / X)-1)

[0071] The erase control circuit 340 may control the storage medium 260 to erase the preliminary super block based on the erase interval IG determined by the erase interval determination circuit 330 and the erase unit determined by the grouping circuit 320 .

[0072] Figure 4 2 is a diagram illustrating a concept of grouping memory blocks and determining an erase interval based on a write operation mode according to an embodiment of the present disclosure. In this embodiment, the write operation mode is a sequential write operation.

[0073] Reference Figure 4 , for example, the write time T of the sequential write operation WT is 5 seconds, the number B of memory blocks in the preliminary super block is 4, and the erase time E of the memory block is 1 second, the number X of memory blocks of the erase unit can be determined to be 1 based on Equation 1.

[0074] Since the idle time I is 1 second based on Equation 2, the erasure interval IG can be determined to be, for example, 0.25 seconds.

[0075] For example, since the preliminary Super Block includes four erase units, the erase process of the preliminary Super Block can repeat four basic erase operations, where the basic erase operation includes erasing an erase unit of one memory block for 1 second and stopping the erase operation for 0.25 seconds (TE11->TI11->TE12->TI12->TE13->TI13->TE14->TI4). Therefore, the erase operation ER of the preliminary Super Block is performed within a 5-second sequential write operation WT.

[0076] If the erasure interval IG is determined to be I / ((B / X)-1), the last erasure interval TI14 may be omitted.

[0077] Figure 5A and Figure 5B is a graph illustrating peak power of an erase operation based on a preliminary super block according to an embodiment of the present disclosure.

[0078] Figure 5A Shows simultaneous erasure Figure 4 The peak power of all 4 memory blocks of the initial super block. Figure 5B The preliminary super block is grouped into multiple erase units and Figure 4 Peak power when erasing at uniform intervals.

[0079] like Figure 5A As shown, when the erase power of a memory block is 10 mW and four memory blocks included in a preliminary super block are erased at the same time, the peak power of each erase operation of the preliminary super block is 40 mW.

[0080] like Figure 5B As shown, when the erase power of the memory block is 10 mW and four erase units each including one memory block are sequentially erased with an erase interval (e.g., 0.25 seconds) between erase operations of the erase units in the preliminary super block, the peak power of each erase operation of the preliminary super block is reduced to 10 mW, which can reduce instantaneous power consumption.

[0081] Figure 6 1 is a diagram illustrating the concept of grouping memory blocks and determining erase intervals based on a write operation mode according to an embodiment of the present disclosure. In this embodiment, the write operation mode is a random write operation based on an internal operation of a data storage device (hereinafter referred to as an internal random write operation).

[0082] For example, when the write time T of the internal random write operation WT is 10 seconds, the number B of memory blocks in the preliminary super block is 8, and the erase time E of each memory block is 1 second, the number X of memory blocks of the erase unit of the preliminary super block can be determined to be 1 based on Equation 1.

[0083] Since the idle time I is 2 seconds according to Equation 2, the erasure interval IG can be determined to be, for example, 0.25 seconds.

[0084] For example, since the preliminary super block includes 8 erase units, the erasing process of the preliminary super block can be repeated 8 times. The basic erase process includes erasing the erase unit of 1 memory block for 1 second and stopping the erase operation for 0.25 seconds (TE21->TI21->TE22->TI22->TE23->TI23->TE24->TI24->TE25->TI25->TE26->TI26->TE27->TI27->TE28->TI28). Therefore, the erase ER of the preliminary super block is performed within the internal random write operation WT of 10 seconds.

[0085] If the erasure interval IG is determined to be I / ((B / X)-1), the last erasure interval TI28 may be omitted.

[0086] Figure 7A and Figure 7B is a graph illustrating peak power of an erase operation based on a preliminary super block according to an embodiment of the present disclosure.

[0087] Figure 7A Shows simultaneous erasure Figure 6 Peak power at all 8 memory blocks of the initial superblock. Figure 7B The preliminary super block is grouped into multiple erase units and Figure 6 Peak power when erasing at uniform intervals.

[0088] like Figure 7A As shown, when the erase power of a memory block is 10 mW and 8 memory blocks included in a preliminary super block are erased simultaneously, the peak power per erase operation of the erase unit in the preliminary super block is 80 mW.

[0089] like Figure 7B As shown, when the erase power of the memory block is 10 mW and four erase units, each including one memory block, are sequentially erased with an erase interval (e.g., 0.25 seconds) between erase operations of the erase units, the peak power of each erase operation of the preliminary super block is reduced to 10 mW, which can reduce instantaneous power consumption.

[0090] Figure 8 1 is a diagram illustrating the concept of grouping memory blocks and determining erase intervals based on a write operation mode according to an embodiment of the present disclosure. In this embodiment, the write operation mode is a random write operation based on a request from an external device 100 (hereinafter referred to as an external random write operation).

[0091] For example, when the write time T of the external random write operation WT is 30 seconds, the number B of memory blocks in the preliminary super block is 16, and the erase time E of each memory block is 2 seconds, the number X of memory blocks per erase unit of the preliminary super block can be determined to be 2 based on Equation 1.

[0092] Since the idle time I is 14 seconds according to Equation 2, the erasure interval IG can be determined to be, for example, 1.75 seconds.

[0093] For example, since the preliminary super block includes 8 erase units, the erasing process of the preliminary super block can be repeated 8 times. The basic erase includes erasing the erase unit of 2 memory blocks for 2 seconds and stopping the erase operation for 1.75 seconds (TE31->TI31->TE32->TI32->TE33->TI33->TE34->TI34->TE35->TI35->TE36->TI36->TE37->TI37->TE38->TI38). Therefore, the erase ER of the preliminary super block is performed within the external random write operation WT of 30 seconds.

[0094] If the erasure interval IG is determined to be I / ((B / X)-1), the last erasure interval TI28 may be omitted.

[0095] Figure 9A and Figure 9B is a graph illustrating peak power of an erase operation based on a preliminary super block according to an embodiment of the present disclosure.

[0096] Figure 9A Shows simultaneous erasure Figure 8 Peak power at all 16 memory blocks of the preliminary superblock. Figure 9B The preliminary super block is grouped into multiple erase units and Figure 8 Peak power when erasing at uniform intervals.

[0097] like Figure 9A As shown, when the erase power of a memory block is 10 mW and 16 memory blocks included in a preliminary super block are erased at the same time, the peak power of each erase operation of the preliminary super block is 160 mW.

[0098] like Figure 9B As shown, when the erase power of the memory block is 10 mW, the 16 memory blocks of the preliminary super block are grouped into 8 erase units each including 2 memory blocks, and the 8 erase units are sequentially erased with an erase interval (e.g., 1.75 seconds) between erase operations of the erase units in the preliminary super block, the peak power of each erase operation of the preliminary super block can be reduced to 20 mW, which can reduce instantaneous power consumption.

[0099] Figure 10is a flowchart illustrating a method of operating a data storage device according to an embodiment of the present disclosure.

[0100] The erase management circuit 30 of the memory controller 210 may monitor whether a super block is in a write operation (operation S101 ).

[0101] When the super block is in a write operation ( S101 : Yes), the erase management circuit 30 may determine a write operation mode of the super block currently being processed (operation S103 ).

[0102] When the super block is not in a write operation ( S101 : No), the erase management circuit 30 may repeat operation S101 .

[0103] If the write operation mode of the Super Block is a sequential write operation (S103: Sequential Write), the erase management circuit 30 may set a write time "a" for the sequential write operation (S105). For example, the write time "a" may be the erase time of the preliminary Super Block to be erased for the subsequent write operation.

[0104] When the write operation mode of the super block in the write operation is the external random write operation ( S103 : external random write) as a result of the determination, the erase management circuit 30 may set a write time “b” for the external random write operation ( operation S107 ).

[0105] When the write operation mode of the super block in the write operation is the internal random write operation ( S103 : internal random write) as a result of the determination, the erase management circuit 30 may set a write time “c” for the internal random write operation ( operation S109 ).

[0106] After setting the write time "a", "b" or "c" according to the write operation mode (operation S105, S107 or S109), the erase management circuit 30 can define at least one erase unit in the preliminary super block by grouping the memory blocks in the preliminary super block so as to minimize the number of memory blocks erased simultaneously (operation S111).

[0107] After the number of erase units of the preliminary super block is determined, the erase management circuit 30 may determine erase intervals between erase operations of the erase units so that the erase intervals are uniform (operation S113 ).

[0108] The erase management circuit 30 may control the storage medium 260 to erase the preliminary super block using the erase unit and the erase interval determined in operation S113 (operation S115 ).

[0109] As is well known, peak power consumption increases in proportion to the number of simultaneously erased memory blocks. According to embodiments, because the memory blocks in the preliminary super block are grouped into erase units and erased one by one, the data storage device can achieve stable performance. In particular, each erase unit includes a minimum number of simultaneously erased memory blocks, and the erase intervals between erase units are uniform.

[0110] The performance consistency of the data storage device 200 may be measured by the lowest input / output per second (IOPS) relative to the average IOPS, and the performance consistency may be evaluated based on how evenly the IOPS are measured when the IOPS are measured over a period of time.

[0111] After the data storage device enters the maintenance state, a program time (tPROG) or an erase time of the data storage device changes, and frequent internal operations such as garbage collection may cause IOPS to be uneven, resulting in inconsistent performance.

[0112] According to an embodiment, the memory blocks of a preliminary super block for subsequent write operations are grouped into erase units, and the preliminary super block is erased erase unit by erase unit. In particular, each erase unit includes a minimum number of memory blocks that are erased simultaneously with an erase interval between erase units to minimize peak power and ensure performance consistency.

[0113] Therefore, it will be understood by those skilled in the art to which the embodiments of the present disclosure pertain that, without changing the technical ideas or basic features of the present invention, the present invention may be implemented in other specific forms. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not intended to be limiting. The scope of the present disclosure is indicated by the appended claims rather than the above-described specific description, and all modifications or changes derived from the meaning and scope of the claims and their equivalents will be understood to be within the scope of the present disclosure. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A data storage device comprising: a storage medium, comprising a plurality of storage blocks; as well as A storage controller combines the storage blocks that are accessed simultaneously among the plurality of storage blocks to manage the combined storage blocks as a super block, The storage controller erases a preliminary super block for a subsequent write operation during a write time set according to a write operation mode of a selected super block for performing a write operation, and divides the storage blocks of the preliminary super block into a plurality of erase units, each erase unit including a set number of storage blocks, and the plurality of erase units are sequentially erased with uniform erase intervals between erase operations of the plurality of erase units.

2. The data storage device according to claim 1, wherein The memory controller determines a set number of memory blocks per erase unit, the set number being a minimum number of memory blocks that are simultaneously erased in each erase unit.

3. The data storage device according to claim 1, wherein The storage controller manages the preliminary super block to complete an erase operation of the plurality of erase units within a write operation of the selected super block.

4. The data storage device according to claim 1, wherein The write operation mode is one of a sequential write operation, a random write operation based on an external request, and a random write operation based on an internal operation of the data storage device.

5. The data storage device according to claim 1, wherein The power consumption of the erasing operation of the preliminary super block is determined by the product of the erasing power of each memory block and the number of memory blocks to be erased simultaneously, and The memory controller configures the erase unit to satisfy that power consumption of each of erase operations of the erase unit is less than power consumption consumed when simultaneously erasing all memory blocks of the preliminary super block. The data storage device according to claim 1 , wherein: The memory controller manages a first super block that combines a first number of memory blocks and a second super block that combines a second number of memory blocks, the second number being different from the first number, and For the same write operation mode, the first super block and the second super block have different write times.

7. The data storage device according to claim 1, wherein: The memory controller manages a first super block that combines a first number of memory blocks and a second super block that combines a second number of memory blocks, the second number being different from the first number, and During the erase operation, the first super block and the second super block have different power consumptions.

8. A data storage device comprising: Storage Controller: Combining the storage blocks that are accessed simultaneously among the plurality of storage blocks included in the storage medium to manage the combined storage blocks as a super block, erasing a preliminary Super Block for a subsequent write operation during a write time set according to a write operation mode of a selected Super Block in which a write operation is performed, Grouping the memory blocks of the preliminary super block into a plurality of erase units, and Based on the erase time of each erase unit, the number of memory blocks of each erase unit, and the erase interval between the erase operations of the multiple erase units, it is determined to complete the erase operation of the multiple erase units of the preliminary super block within the write time.

9. The data storage device according to claim 8, wherein: The storage controller manages a plurality of super blocks having different sizes, and For the same write operation mode, the write time of each super block is set differently according to the size of the super block.

10. The data storage device according to claim 8, wherein: The storage controller manages a plurality of super blocks having different sizes, and For the same write operation mode, the write time of each super block is set differently according to the size of the super block. During the erase operation, each super block consumes different amounts of power.

11. A method of operating a data storage device, the method comprising: Combining, by a storage controller, storage blocks that are accessed simultaneously among a plurality of storage blocks, so as to manage the combined storage blocks as a super block; determining, by the storage controller, a write time set according to a write operation mode of a selected super block for performing a write operation; dividing, by the storage controller, a plurality of storage blocks of a preliminary super block for subsequent write operations into a plurality of erase units; as well as The memory controller erases the plurality of erasing units at uniform erasing intervals.

12. The method according to claim 11, wherein Each of the plurality of erase units includes a minimum number of memory blocks that are erased simultaneously.

13. The method according to claim 11, wherein The erasing operation of the plurality of erasing units of the preliminary super block is completed within the writing time.

14. The method according to claim 11, wherein The write operation mode is one of a sequential write operation, a random write operation based on an external request, and a random write operation based on an internal operation of the data storage device.

15. The method according to claim 11, wherein The power consumption of the erasing operation of the preliminary super block is determined by the product of the erasing power of each memory block and the number of memory blocks to be erased simultaneously, and Dividing the plurality of memory blocks of the preliminary super block includes configuring the erase units so that power consumption of an erase operation of each of the erase units is less than power consumption when simultaneously erasing all memory blocks of the preliminary super block.

16. The method according to claim 11, further comprising: managing, by the memory controller, a first super block combining a first number of memory blocks and a second super block combining a second number of memory blocks, the second number being different from the first number, and For the same write operation mode, the first super block and the second super block have different write times.

17. The method according to claim 11, further comprising: managing, by the memory controller, a first super block combining a first number of memory blocks and a second super block combining a second number of memory blocks, the second number being different from the first number, and During the erase operation, the first super block and the second super block have different power consumptions.

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