Packaging structure and packaging method
By forming protruding dividing pillars on the interconnect metal layer, the interconnect via is divided into multiple sub-vias, which solves the warping problem caused by stress imbalance in three-dimensional integrated circuits, improves device yield, and ensures electrical connection performance.
Patent Information
- Application Number
- CN202410331027.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-21
- Publication Date
- 2025-09-23
AI Technical Summary
In existing packaging structures, it is difficult to improve device yield and ensure electrical connection performance. In particular, in three-dimensional integrated circuits, the interconnect metal layer suffers from severe warping problems due to stress imbalance.
Protruding dividing pillars are formed on the interconnect metal layer to divide the interconnect via into multiple sub-vias, and interconnect structures are formed in the sub-vias, so that the interconnect structures are electrically connected to the interconnect metal layer. The dividing pillars are used to balance stress and reduce warping.
The design of the dividing pillars alleviates the warping problem of the interconnect metal layer, improves the device yield, and ensures the electrical connection performance of the package structure.
Smart Images
Figure CN120690752A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a packaging structure and a packaging method. Background Art
[0002] In semiconductor manufacturing, with the development of ultra-large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to decrease. Consequently, the requirements for integrated circuit packaging are also increasing. Building on the two-dimensional packaging within the X and Y planes of multi-chip modules (MCMs), 3D packaging technology stacked along the Z direction has been fully developed, and this 3D packaging technology has higher density.
[0003] Three-Dimensional Integrated Circuits (3D ICs) utilize the Through Silicon Via (TSV) process to form metal pillars within wafers, coupled with metal bumps. This allows for direct three-dimensional interconnection between wafers (chips) or between a chip and a substrate, overcoming the limitations of traditional two-dimensional wiring for semiconductor chips. Compared to traditional stacking technologies such as bonding, this interconnection method offers advantages such as higher three-dimensional stacking density and smaller packaged dimensions, significantly improving chip speed and reducing power consumption. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, which are conducive to ensuring the electrical connection performance of the packaging structure.
[0005] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a wafer, in which an interconnection metal layer is formed; an interconnection through-hole, which passes through the wafer above the interconnection metal layer and exposes the top surface of the interconnection metal layer, and the interconnection through-hole includes a partitioning column protruding from the interconnection metal layer, and the partitioning column divides the interconnection through-hole into multiple sub-through-holes, and the multiple sub-through-holes are connected; an interconnection structure, which is located in the interconnection through-hole and is electrically connected to the interconnection metal layer.
[0006] Optionally, the partition column includes a plurality of sub-partition columns, and the plurality of sub-partition columns intersect or are parallel to each other.
[0007] Optionally, the partitioning pillars partition the interconnection through-hole into a plurality of sub-through-holes evenly distributed in a top-view direction.
[0008] Optionally, the partitioning column includes two sub-partitioning columns that intersect vertically, and the partitioning column divides the interconnection through-hole into four sub-through-holes.
[0009] Optionally, the top surface of the partition column is lower than the top of the interconnection through hole, and the parts of the multiple sub-through holes that are higher than the top surface of the partition column are connected; the parts of the interconnection structure that are higher than the top surface of the partition column are connected.
[0010] Optionally, the ratio of the height of the partition pillar to the total height of the interconnection through hole is 1 / 4 to 4 / 5.
[0011] Optionally, the partitioning post passes through a center point of the interconnecting through hole.
[0012] Optionally, the interconnection via is located at a central position of the interconnection metal layer.
[0013] Correspondingly, an embodiment of the present invention also provides a packaging method, including: providing a wafer, in which an interconnection metal layer is formed; patterning the wafer to form an interconnection through-hole exposing the top surface of the interconnection metal layer, the interconnection through-hole including a partitioning column protruding from the interconnection metal layer, the partitioning column partitioning the interconnection through-hole into multiple sub-through-holes, and the multiple sub-through-holes are connected; forming an interconnection structure in the interconnection through-hole, and the interconnection structure is electrically connected to the interconnection metal layer.
[0014] Optionally, the step of patterning the wafer to form interconnected through-holes exposing the top surface of the interconnected metal layer includes: removing the wafer of a portion of the thickness of multiple preset areas above the interconnected metal layer to form a plurality of separated initial sub-through-holes, retaining the remaining wafer of the multiple separated initial sub-through-holes as initial dividing columns, and the multiple initial sub-through-holes constitute the initial interconnected through-holes; removing the wafer of a portion of the thickness of multiple preset areas above the interconnected metal layer to form a plurality of sub-through-holes; removing the initial dividing columns of a portion of the height, retaining the remaining initial dividing columns as dividing columns, so that the plurality of sub-through-holes are connected through the portion higher than the top surface of the dividing columns, and the plurality of sub-through-holes constitute the interconnected through-holes.
[0015] Optionally, in the same step, the wafer having a remaining thickness in a plurality of preset areas above the interconnect metal layer is removed, and a portion of the height of the initial segmentation pillars is removed.
[0016] Optionally, the step of removing a portion of the wafer having a thickness of multiple preset areas above the interconnect metal layer to form a plurality of separated initial sub-vias includes: forming a first mask layer on the wafer, the first mask layer having a first opening exposing the top surface of the wafer having multiple preset areas; patterning the wafer along the first opening to remove the remaining thickness of the wafer having multiple preset areas above the interconnect metal layer; after forming the initial sub-vias, further including: removing the first mask layer.
[0017] Optionally, the steps of removing the wafer with the remaining thickness of multiple preset areas above the interconnection metal layer and removing a portion of the height of the initial dividing columns include: forming a second mask layer on the wafer, the second mask layer having a second opening exposing the initial interconnection through-hole; patterning the wafer in the initial interconnection through-hole along the second opening, removing the wafer with the remaining thickness of multiple preset areas above the interconnection metal layer and removing a portion of the height of the initial dividing columns; after forming the interconnection through-hole, it also includes: removing the second mask layer.
[0018] Optionally, in the step of removing a portion of the wafer thickness in multiple preset areas above the interconnect metal layer to form a plurality of separated initial sub-vias, the ratio of the depth of the initial sub-vias to the total thickness of the wafer above the interconnect metal layer is 1 / 5 to 3 / 4.
[0019] Optionally, in the step of removing a portion of the height of the initial partition pillars, the ratio of the height of the removed initial partition pillars to the total height of the interconnection through-holes is 1 / 5 to 3 / 4.
[0020] Optionally, in the step of patterning the wafer to form interconnection through holes exposing the top surface of the interconnection metal layer, the segmentation column includes a plurality of sub-segmentation columns, and the plurality of sub-segmentation columns intersect or are parallel to each other.
[0021] Optionally, in the step of patterning the wafer to form an interconnection through-hole exposing the top surface of the interconnection metal layer, the segmentation pillars segment the interconnection through-hole into a plurality of sub-through-holes uniformly distributed in a top-view direction.
[0022] Optionally, in the step of patterning the wafer to form an interconnection through-hole exposing the top surface of the interconnection metal layer, the segmentation column includes two sub-segmentation columns that intersect vertically, and the segmentation column divides the interconnection through-hole into four sub-through-holes.
[0023] Optionally, in the step of patterning the wafer to form an interconnection through hole exposing the top surface of the interconnection metal layer, the segmentation column passes through the center point of the interconnection through hole.
[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0025] In the packaging structure provided by the embodiment of the present invention, the interconnection through-hole includes a partitioning column protruding from the interconnection metal layer, the partitioning column divides the interconnection through-hole into multiple sub-through-holes, the multiple sub-through-holes are connected, and the interconnection structure is located in the interconnection through-hole and electrically connected to the interconnection metal layer. In the embodiment of the present invention, in the step of forming the interconnection structure, it is necessary to first form the interconnection through-hole exposing the interconnection metal layer, and then form the interconnection structure in the interconnection through-hole. In the embodiment of the present invention, the interconnection through-hole includes the partitioning column protruding from the interconnection metal layer. The partitioning column is conducive to balancing the stress effects on the upper and lower sides of the interconnection metal layer, reducing the stress change on the upper side of the interconnection metal layer (located on one side of the interconnection through-hole) caused by the formation of the interconnection through-hole, thereby facilitating the problem of warping of the interconnection metal layer toward the upper side due to the unbalanced stress between the upper and lower sides, and facilitating the improvement of device yield. Moreover, the multiple sub-through-holes are connected, so that the interconnection structure located in the interconnection through-hole remains connected as an integrated structure, so that the packaging structure of the embodiment of the present invention can alleviate the warping problem while still ensuring the electrical connection performance of the packaging structure.
[0026] In the packaging method provided in an embodiment of the present invention, the wafer is patterned to form an interconnection through-hole exposing the top surface of the interconnection metal layer. The interconnection through-hole includes a segmentation column protruding from the interconnection metal layer. The segmentation column divides the interconnection through-hole into a plurality of sub-through-holes. The plurality of sub-through-holes are interconnected, forming an interconnection structure in the interconnection through-hole, and the interconnection structure is electrically connected to the interconnection metal layer. In the embodiment of the present invention, the interconnection through-hole includes the segmentation column protruding from the interconnection metal layer. Then, in the step of forming the interconnection through-hole exposing the interconnection metal layer, the segmentation column helps balance the stress effects on the upper and lower sides of the interconnection metal layer, reducing the stress change on the upper side of the interconnection metal layer (located on one side of the interconnection through-hole) caused by the formation of the interconnection through-hole, thereby facilitating the problem of warping of the interconnection metal layer due to the stress imbalance between the upper and lower sides, thereby improving the device yield. Moreover, the plurality of sub-through-holes are interconnected, so that the interconnection structure located in the interconnection through-hole remains connected as an integrated structure, so that the packaging structure of the embodiment of the present invention can alleviate the warping problem while still ensuring the electrical connection performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figures 1 to 2 It is a structural schematic diagram corresponding to each step of a packaging method;
[0028] Figures 3 and 4 is a schematic diagram corresponding to an embodiment of the packaging structure of the present invention;
[0029] Figures 5 to 13 It is a structural schematic diagram corresponding to each step of an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION
[0030] As can be seen from the background technology, it is difficult to improve the device yield of the current packaging structure and to ensure the electrical connection performance. Now, based on a packaging method, we analyze the reasons why it is difficult to improve the device yield of the packaging structure and to ensure the electrical connection performance.
[0031] Figures 1 to 2 It is a structural schematic diagram corresponding to each step of the packaging method.
[0032] refer to Figure 1 , providing a first wafer 10 and a second wafer 20 bonded to each other, the first wafer 10 includes an interconnection layer 11 and a substrate 12 located on the interconnection layer 11, the interconnection layer 11 faces the second wafer 20, and an interconnection metal layer 13 is formed on the surface of the interconnection layer 11 facing the substrate 12.
[0033] refer to Figure 2 , patterning the substrate 12 to form interconnection through holes 31 exposing the interconnection metal layer 13.
[0034] The interconnection through hole 31 exposes the upper side of the interconnection metal layer 13, causing the stress on the upper side of the interconnection metal layer 13 to suddenly decrease, which can easily lead to stress imbalance between the upper and lower sides of the interconnection metal layer 13, thereby easily causing the interconnection metal layer 13 to warp toward the side of the interconnection through hole 31, affecting the device yield. After the interconnection structure is subsequently formed in the interconnection through hole 31, the electrical connection performance between the interconnection structure and the interconnection metal layer 13 is affected.
[0035] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a wafer, in which an interconnection metal layer is formed; an interconnection through-hole, which passes through the wafer above the interconnection metal layer and exposes the top surface of the interconnection metal layer, and the interconnection through-hole includes a partitioning column protruding from the interconnection metal layer, and the partitioning column divides the interconnection through-hole into multiple sub-through-holes, and the multiple sub-through-holes are connected; an interconnection structure, which is located in the interconnection through-hole and is electrically connected to the interconnection metal layer.
[0036] In an embodiment of the present invention, in the step of forming an interconnection structure, it is necessary to first form an interconnection through-hole exposing the interconnection metal layer, and then form an interconnection structure in the interconnection through-hole. In an embodiment of the present invention, the interconnection through-hole includes a split column protruding from the interconnection metal layer. The split column is beneficial to balancing the stress effects on the upper and lower sides of the interconnection metal layer, reducing the stress changes on the upper side of the interconnection metal layer (located on one side of the interconnection through-hole) due to the formation of the interconnection through-hole, thereby helping to alleviate the problem of warping of the interconnection metal layer toward the upper side due to the imbalance of stress between the upper and lower sides, and helping to improve the device yield. Moreover, when multiple sub-through-holes are connected, the interconnection structure located in the interconnection through-hole remains connected as an integrated structure, so that the packaging structure of the embodiment of the present invention can alleviate the warping problem while still ensuring the electrical connection performance of the packaging structure.
[0037] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0038] Figures 3 and 4 It is a structural schematic diagram corresponding to an embodiment of the packaging structure of the present invention.
[0039] Combined with reference Figure 3 and Figure 4 ,in, Figure 3 (a) is a top view, Figure 3 (b) Yes Figure 3 (a) Cross-sectional view along the AA direction, Figure 3 (c) Yes Figure 3(a) A cross-sectional view along direction BB shows a package structure comprising: a wafer 100 having an interconnect metal layer 130 formed therein; an interconnect via 420 penetrating the wafer 100 above the interconnect metal layer 130 and exposing the top surface of the interconnect metal layer 130; the interconnect via 420 including a segmentation column 510 protruding from the interconnect metal layer 130, the segmentation column 510 segmenting the interconnect via 420 into a plurality of sub-vias 410, the plurality of sub-vias 410 being interconnected; and an interconnect structure 600 located in the interconnect via 420 and electrically connected to the interconnect metal layer 130.
[0040] Wafer 100 is used to implement wafer-level packaging.
[0041] In this embodiment, the wafer 100 includes an interconnection layer 110 and a base layer 120 located on the interconnection layer 110 . The interconnection metal layer 130 is formed on a surface of the interconnection layer 110 facing the base layer 120 .
[0042] In this embodiment, the wafer 100 is used as the first wafer, and the packaging structure further includes: a second wafer 200 bonded to the first wafer. The second wafer 200 is bonded to the first wafer 100 to realize the basic function of the packaging structure.
[0043] The interconnection metal layer 130 is used to electrically connect to the outside through the interconnection structure 600 , thereby realizing electrical connection of the interconnection layer 110 in the vertical direction.
[0044] The interconnection via 420 is used to provide a spatial location for forming the interconnection structure 600 .
[0045] In this embodiment, the interconnection via 420 penetrates the wafer 100 above the interconnection metal layer 130 and exposes the top surface of the interconnection metal layer 130 , so that the interconnection structure 600 and the interconnection metal layer 130 are in contact and electrically connected to each other.
[0046] Specifically, in this embodiment, the interconnection through-hole 420 passes through the base layer 120 on the interconnection metal layer 130 .
[0047] In this embodiment, the interconnection via 420 is a through silicon via (TSV) structure.
[0048] It should be noted that in this embodiment, the shape of the interconnecting through-hole 420 is not limited. The shape of the interconnecting through-hole 420 can be circular, rectangular, diamond, trapezoidal, polygonal, or other closed-loop shapes. As an example, this embodiment is described using the circular shape of the interconnecting through-hole 420 as an example.
[0049] The partition pillars 510 are used to balance the stress on the upper and lower sides of the interconnection metal layer 130 .
[0050] In this embodiment, in the step of forming the interconnect structure 600, it is necessary to first form an interconnect through-hole 420 that exposes the interconnect metal layer 130, and then form the interconnect structure 600 in the interconnect through-hole 420. In this embodiment, the interconnect through-hole 420 includes a partitioning column 510 protruding from the interconnect metal layer 130. The partitioning column 510 is conducive to balancing the stress effects on the upper and lower sides of the interconnect metal layer 130, reducing the stress change on the upper side of the interconnect metal layer 130 (located on the side of the interconnect through-hole 420) due to the formation of the interconnect through-hole 420, thereby relieving the problem of warping of the interconnect metal layer 130 towards the upper side due to the unbalanced stress between the upper and lower sides, and relieving the device yield. Moreover, when multiple sub-through-holes 410 are connected, the interconnect structure 600 located in the interconnect through-hole 420 remains connected as an integrated structure, so that the packaging structure of this embodiment can alleviate the warping problem while still ensuring the electrical connection performance of the packaging structure.
[0051] In this embodiment, the partitioning column 510 includes a plurality of sub-partitioning columns, and the plurality of sub-partitioning columns intersect or are parallel to each other.
[0052] The plurality of sub-segmentation columns constitute the segmentation column 510 . The segmentation column 510 occupies a larger area on the surface of the interconnection metal layer 130 , which is beneficial for further balancing the stress effects on the upper and lower sides of the interconnection metal layer 130 .
[0053] In this embodiment, the partitioning pillars 510 partition the interconnection through-hole 420 into a plurality of sub-through-holes 410 that are evenly distributed in a top-view direction.
[0054] The splitting column 510 splits the interconnection through-hole 420 into a plurality of sub-through-holes 410 uniformly distributed in the top-view direction, which is beneficial for uniform distribution of the interconnection structure 600 formed in each part of the sub-through-hole 410, and is beneficial for better electrical connection performance of the interconnection structure 600. Moreover, the splitting column 510 splits the interconnection through-hole 420 into a plurality of sub-through-holes 410 uniformly distributed in the top-view direction, and the uniform distribution of the plurality of sub-splitting columns representing the splitting column 510 is beneficial for more uniform stress distribution of the splitting column 510 on the surface of the interconnection metal layer 130, and is beneficial for more uniformly balancing the stress effects on the upper and lower sides of the interconnection metal layer 130.
[0055] As an example, in this embodiment, the dividing column 510 includes two sub-dividing columns that intersect vertically. The dividing column 510 divides the interconnection through-hole 420 into four sub-through-holes 410. The distribution of the dividing columns 510 is uniform, and the distribution of the sub-through-holes 410 in the interconnection through-hole 420 is uniform, so that the electrical connection performance of the interconnection structure 600 is better, and the stress on the upper and lower sides of the interconnection metal layer 130 is more evenly balanced.
[0056] In this embodiment, the partition pillar 510 passes through the center point of the interconnection through hole 420 .
[0057] The partition column 510 passes through the center point of the interconnection through hole 420 , which helps to make the stress of the partition column 510 on the surface of the interconnection metal layer 130 exposed by the interconnection through hole 420 diverge from the center and the stress effect is more uniform.
[0058] In this embodiment, the interconnection via 420 is located at the center of the interconnection metal layer 130 .
[0059] The interconnection through hole 420 is located at the center of the interconnection metal layer 130, which is beneficial to ensuring the electrical connection performance between the interconnection structure 600 and the interconnection metal layer 130. Moreover, the dividing column 510 passes through the center point of the interconnection through hole 420. The dividing column 510 passes through the center position of the interconnection metal layer 130, which is beneficial to make the stress effect of the dividing column 510 on the surface of the entire interconnection metal layer 130 diverge from the center, and the stress effect on the entire interconnection metal layer 130 is more uniform.
[0060] In this embodiment, the top surface of the partition pillar 510 is lower than the top of the interconnection through-hole 420 , and portions of the plurality of sub-through-holes 410 that are higher than the top surface of the partition pillar 510 are interconnected.
[0061] The top surface of the partition column 510 is lower than the top of the interconnection through-hole 420, so that the parts of the plurality of sub-through-holes 410 above the top surface of the partition column 510 are connected, thereby making the interconnection structures 600 in the plurality of sub-through-holes 410 connected as an integrated structure.
[0062] It should be noted that, in this embodiment, the ratio of the height h3 of the partition pillar 510 to the total height h of the interconnection through hole 420 should not be too large or too small. If the ratio of the height h3 of the splitting column 510 to the total height h of the interconnection through-hole 420 is too large, the height difference between the splitting column 510 and the top of the interconnection through-hole 420 is too small, that is, the height difference between the splitting column 510 and the top of the interconnection structure 600 is too small, and the interconnection structure 600 is connected through the space above the splitting column 510, which may easily lead to the interconnection structures 600 in the sub-through-holes 410 split by the splitting column 510 being not firmly connected, affecting the formation of the integrated structure of the interconnection structure 600 and affecting the electrical connection performance of the interconnection structure 600; if the ratio of the height h3 of the splitting column 510 to the total height h of the interconnection through-hole 420 is too small, the height of the splitting column 510 is too small, and the stress of the splitting column 510 on the interconnection metal layer 130 is too small, making it difficult to balance the stress effects on the upper and lower sides of the interconnection metal layer 130, thereby making it difficult to alleviate the problem of warping of the interconnection metal layer 130 on the upper side due to the imbalance of stress on the upper and lower sides, and making it difficult to improve the device yield. Therefore, in this embodiment, the height h3 of the partition pillar 510 accounts for 1 / 4 to 4 / 5 of the total height h of the interconnection through hole 420. As an example, the height h3 of the partition pillar 510 accounts for 1 / 3 of the total height h of the interconnection through hole 420.
[0063] The interconnect structure 600 is used to electrically connect to the interconnect metal layer 130 , thereby achieving electrical connection between the interconnect metal layer 130 and the outside.
[0064] Accordingly, in this embodiment, portions of the interconnection structure 600 that are higher than the top surfaces of the partition pillars 510 are connected.
[0065] The portion of the interconnection structure 600 that is higher than the top surface of the segmentation pillar 510 is connected to form an integrated structure, which is beneficial to ensuring the electrical connection performance between the interconnection structure 600 and the interconnection metal layer 130 .
[0066] It should be noted that, in this embodiment, the morphology of the partition pillars 510 in the interconnection through-holes 420 in the top view is not limited. Figure 4 (a)-(d) show the morphologies of four types of segmentation pillars 510 .
[0067] Figures 5 to 13 It is a structural schematic diagram corresponding to each step of an embodiment of a packaging method of the present invention.
[0068] refer to Figure 5 , Figure 5 (a) Yes Figure 5 (b) A cross-sectional view along the AA direction shows a wafer 100 with an interconnection metal layer 130 formed therein.
[0069] Wafer 100 is used to implement wafer-level packaging.
[0070] In this embodiment, in the step of providing the wafer 100 , the wafer 100 includes an interconnection layer 110 and a base layer 120 located on the interconnection layer 110 , and the interconnection metal layer 130 is formed on the surface of the interconnection layer 110 facing the base layer 120 .
[0071] In this embodiment, the wafer 100 is used as the first wafer, and the step of providing the wafer 100 also includes: providing a second wafer 200 bonded to the first wafer, and the second wafer 200 is bonded to the first wafer 100 to realize the basic function of the packaging structure.
[0072] The interconnection metal layer 130 is used to subsequently be electrically connected to the outside through an interconnection structure, thereby realizing electrical connection of the interconnection layer 110 in the longitudinal direction.
[0073] Combined with reference Figures 6 to 10 The wafer 100 is patterned to form an interconnection through-hole 420 exposing the top surface of the interconnection metal layer 130. The interconnection through-hole 420 includes a partitioning column 510 protruding from the interconnection metal layer 130. The partitioning column 510 divides the interconnection through-hole 420 into multiple sub-through-holes 410, and the multiple sub-through-holes 410 are connected.
[0074] The interconnection through-hole 420 is used to provide a spatial location for the subsequent formation of an interconnection structure.
[0075] In this embodiment, the interconnection via 420 penetrates the wafer 100 above the interconnection metal layer 130 and exposes the top surface of the interconnection metal layer 130 , so that the subsequently formed interconnection structure contacts the interconnection metal layer 130 and is electrically connected to each other.
[0076] Specifically, in this embodiment, the interconnection through-hole 420 passes through the base layer 120 on the interconnection metal layer 130 .
[0077] In this embodiment, in the step of patterning the wafer 100 to form the interconnection vias 420 exposing the top surface of the interconnection metal layer 130 , the interconnection vias 420 are through silicon vias (TSV) structures.
[0078] It should be noted that in this embodiment, the shape of the interconnecting through-hole 420 is not limited. The shape of the interconnecting through-hole 420 can be circular, rectangular, diamond, trapezoidal, polygonal, or other closed-loop shapes. As an example, this embodiment is described using the circular shape of the interconnecting through-hole 420 as an example.
[0079] The partition pillars 510 are used to balance the stress on the upper and lower sides of the interconnection metal layer 130 .
[0080] In this embodiment, the interconnection through hole 420 includes a dividing column 510 protruding from the interconnection metal layer 130. The dividing column 510 is conducive to balancing the stress effects on the upper and lower sides of the interconnection metal layer 130, reducing the stress changes on the upper side of the interconnection metal layer 130 (located on the side of the interconnection through hole 420) due to the formation of the interconnection through hole 420, thereby helping to alleviate the problem of warping of the interconnection metal layer 130 towards the upper side due to the imbalance of stress between the upper and lower sides, and helping to improve the device yield. Moreover, when multiple sub-through holes 410 are connected, the interconnection structure located in the interconnection through hole 420 remains connected as an integrated structure, so that the packaging structure of this embodiment can alleviate the warping problem while still ensuring the electrical connection performance of the packaging structure.
[0081] In this embodiment, in the step of patterning the wafer 100 to form the interconnection through-hole 420 exposing the top surface of the interconnection metal layer 130 , the segmentation column 510 includes a plurality of sub-segmentation columns, and the plurality of sub-segmentation columns intersect or are parallel to each other.
[0082] The plurality of sub-segmentation columns constitute the segmentation column 510 . The segmentation column 510 occupies a larger area on the surface of the interconnection metal layer 130 , which is beneficial for further balancing the stress effects on the upper and lower sides of the interconnection metal layer 130 .
[0083] In this embodiment, during the step of patterning the wafer 100 to form the interconnection via 420 exposing the top surface of the interconnection metal layer 130 , the segmentation pillars 510 segment the interconnection via 420 into a plurality of sub-vias 410 evenly distributed in a top view direction.
[0084] The splitting column 510 splits the interconnection through-hole 420 into a plurality of sub-through-holes 410 that are evenly distributed in the top-view direction, which is beneficial for making the subsequently formed interconnection structure evenly distributed in each part of the sub-through-hole 410, and is beneficial for making the electrical connection performance of the interconnection structure better. Moreover, the splitting column 510 splits the interconnection through-hole 420 into a plurality of sub-through-holes 410 that are evenly distributed in the top-view direction, and the uniform distribution of the plurality of sub-splitting columns representing the splitting column 510 is beneficial for making the stress distribution of the splitting column 510 on the surface of the interconnection metal layer 130 more even, and is beneficial for more evenly balancing the stress effects on the upper and lower sides of the interconnection metal layer 130.
[0085] As an example, in this embodiment, in the step of patterning the wafer 100 to form an interconnection through-hole 420 exposing the top surface of the interconnection metal layer 130, the dividing column 510 includes two sub-dividing columns that intersect vertically. The dividing column 510 divides the interconnection through-hole 420 into four sub-through-holes 410. The distribution of the dividing columns 510 is uniform, and the distribution of the sub-through-holes 410 in the interconnection through-hole 420 is uniform, so that the electrical connection performance of the interconnection structure is better, and the stress on the upper and lower sides of the interconnection metal layer 130 is more evenly balanced.
[0086] In this embodiment, in the step of patterning the wafer 100 to form the interconnection through-hole 420 exposing the top surface of the interconnection metal layer 130 , the segmentation pillar 510 passes through the center point of the interconnection through-hole 420 .
[0087] The partition column 510 passes through the center point of the interconnection through hole 420 , which helps to make the stress of the partition column 510 on the surface of the interconnection metal layer 130 exposed by the interconnection through hole 420 diverge from the center and the stress effect is more uniform.
[0088] In this embodiment, in the step of patterning the wafer 100 to form the interconnection through-hole 420 exposing the top surface of the interconnection metal layer 130 , the interconnection through-hole 420 is located at the center of the interconnection metal layer 130 .
[0089] The interconnection through hole 420 is located at the center of the interconnection metal layer 130, which is beneficial to ensuring the electrical connection performance between the interconnection structure and the interconnection metal layer 130. Moreover, the dividing column 510 passes through the center point of the interconnection through hole 420. The dividing column 510 passes through the center position of the interconnection metal layer 130, which is beneficial to make the stress effect of the dividing column 510 on the surface of the entire interconnection metal layer 130 diverge from the center, and the stress effect on the entire interconnection metal layer 130 is more uniform.
[0090] In this embodiment, in the step of patterning the wafer 100 to form the interconnection through hole 420 exposing the top surface of the interconnection metal layer 130, the top surface of the partition column 510 is lower than the top of the interconnection through hole 420, and the parts of the multiple sub-through holes 410 above the top surface of the partition column 510 are connected.
[0091] The top surface of the partition column 510 is lower than the top of the interconnection through-hole 420, so that the parts of the multiple sub-through-holes 410 above the top surface of the partition column 510 are connected, thereby making the interconnection structures in the multiple sub-through-holes 410 connected into an integrated structure.
[0092] Specifically, with reference to Figure 6 and Figure 7 The step of patterning the wafer 100 to form an interconnection through-hole 420 exposing the top surface of the interconnection metal layer 130 includes: removing the wafer 100 with a partial thickness of multiple preset areas above the interconnection metal layer 130 to form a plurality of separated initial sub-through-holes 400, retaining the remaining wafer 100 that separates the plurality of initial sub-through-holes 400 as an initial dividing column 500, and the plurality of initial sub-through-holes 400 constitute an initial interconnection through-hole.
[0093] The preset area is a preset area where the interconnection through-hole 420 needs to be formed.
[0094] First, an initial sub-via 400 is formed in the wafer 100 partially above the interconnection metal layer 130 to position the interconnection via 420 in preparation for further etching to form the interconnection via 420 , and an initial segmentation column 500 is formed in preparation for forming the segmentation column 510 .
[0095] Specifically, in this embodiment, a portion of the thickness of the base layer 120 above the interconnection metal layer 130 is removed, and the initial sub-via 400 is formed in the portion of the thickness of the base layer 120 .
[0096] It should be noted that, in the step of removing a portion of the thickness of the wafer 100 in multiple preset areas above the interconnection metal layer 130 to form a plurality of separated initial sub-vias 400, the ratio of the depth h1 of the initial sub-vias 400 to the total thickness h of the wafer 100 above the interconnection metal layer 130 should not be too large or too small. If the ratio of the depth h1 of the initial sub-through hole 400 to the total thickness h of the wafer 100 above the interconnection metal layer 130 is too large, the depth h1 of the initial sub-through hole 400 is too large, and the thickness of the remaining wafer 100 between the bottom of the initial sub-through hole 400 and the interconnection metal layer 130 is too small. Subsequently, it is necessary to simultaneously remove the remaining wafer 100 between the bottom of the initial sub-through hole 400 and the interconnection metal layer 130, and remove part of the height of the initial dividing column 500. The thickness of the remaining wafer 100 between the bottom of the initial sub-through hole 400 and the interconnection metal layer 130 is too small, which may easily lead to the height of the initial dividing column 500 of the removed part being too small. The sub-through hole 410 is connected through the space above the dividing column 510, that is, the interconnection structure formed subsequently is connected through the space above the dividing column 510, which may easily lead to the interconnection structures in the sub-through hole 410 divided by the dividing column 510 being not firmly connected, affecting the shape of the integrated structure of the interconnection structure. 130 , and the thickness of the wafer 100 remaining between the bottom of the initial sub-through hole 400 and the interconnected metal layer 130 is too large. Subsequently, it is necessary to remove the remaining wafer 100 between the bottom of the initial sub-through hole 400 and the interconnected metal layer 130, and remove part of the height of the initial dividing column 500. Then, the thickness of the remaining wafer 100 between the bottom of the initial sub-through hole 400 and the interconnected metal layer 130 is too large, and the height of the formed dividing column 510 is too small, which easily leads to the stress of the dividing column 510 on the interconnected metal layer 130 being too small, making it difficult to balance the stress effects on the upper and lower sides of the interconnected metal layer 130, thereby making it difficult to alleviate the problem of warping of the interconnected metal layer 130 due to the unbalanced stress on the upper and lower sides, and thus it is difficult to improve the device yield. To this end, in this embodiment, in the step of removing a portion of the thickness of the wafer 100 in multiple predetermined areas above the interconnection metal layer 130 to form a plurality of separated initial sub-vias 400, the ratio of the depth h1 of the initial sub-vias 400 to the total thickness h of the wafer 100 above the interconnection metal layer 130 is 1 / 5 to 3 / 4. As an example, the ratio of the depth h1 of the initial sub-vias 400 to the total thickness h of the wafer 100 above the interconnection metal layer 130 is 1 / 3.
[0097] Specifically, refer to Figure 6 ,in, Figure 6 (a) Yes Figure 6(b) A cross-sectional view along the AA direction shows the step of removing a portion of the thickness of the wafer 100 in multiple predetermined areas above the interconnect metal layer 130 to form a plurality of separated initial sub-vias 400, including forming a first mask layer 300 on the wafer 100, the first mask layer 300 having a first opening 310 exposing the top surface of the wafer 100 in the plurality of predetermined areas.
[0098] The first mask layer 300 is used as an etching mask for forming the initial sub-through hole 400 on the patterned wafer 100 .
[0099] refer to Figure 7 ,in, Figure 7 (a) Yes Figure 7 (b) A cross-sectional view along the AA direction shows that the wafer 100 is patterned along the first opening 310 , and the remaining thickness of the wafer 100 in multiple predetermined areas above the interconnection metal layer 130 is removed.
[0100] refer to Figure 8 ,in, Figure 8 (a) Yes Figure 8 (b) A cross-sectional view along the AA direction, after the initial sub-through hole 400 is formed, the process further includes: removing the first mask layer 300 .
[0101] Combined with reference Figure 9 and Figure 10 , removing the wafer 100 with a remaining thickness in multiple predetermined areas above the interconnect metal layer 130 to form a plurality of sub-vias 410 .
[0102] The wafer 100 with remaining thickness in a plurality of predetermined areas above the interconnection metal layer 130 is removed to form a plurality of sub-vias 410 penetrating the base layer 120 in preparation for forming an interconnection structure.
[0103] In this embodiment, a portion of the initial partition column 500 is removed, and the remaining initial partition column 500 is retained as the partition column 510, so that multiple sub-through holes 410 are connected through the portion higher than the top surface of the partition column 510, and the multiple sub-through holes 410 constitute an interconnected through hole 420.
[0104] Part of the height of the initial partition pillars 500 is removed to obtain partition pillars 510 with a lower top surface, so that the sub-through holes 410 are connected, and accordingly the interconnection structures formed subsequently are connected into an integrated structure.
[0105] In this embodiment, in the same step, the wafer 100 with the remaining thickness in a plurality of predetermined areas above the interconnection metal layer 130 and the initial segmentation pillars 500 with a partial height are removed.
[0106] In the same step, the wafer 100 with the remaining thickness in multiple preset areas above the interconnect metal layer 130 and the initial partitioning columns 500 with a partial height are removed, so that the interconnection through-holes 420 and the partitioning columns 510 can be obtained at the same time, simplifying the process steps and improving the process efficiency.
[0107] It should be noted that, in this embodiment, in the step of removing a portion of the height of the initial partition column 500, the ratio of the height h2 of the removed initial partition column 500 to the total height h of the interconnection through hole 420 should not be too large or too small. If the ratio of the height h2 of the removed initial partition column 500 to the total height h of the interconnection through hole 420 is too large, then too many initial partition columns 500 are removed, and the height of the obtained partition column 510 is too small, which can easily lead to the stress of the partition column 510 on the interconnection metal layer 130 being too small, making it difficult to balance the stress effects on the upper and lower sides of the interconnection metal layer 130, thereby making it difficult to alleviate the problem of the interconnection metal layer 130 warping upward due to the unbalanced stress on the upper and lower sides, and making it difficult to improve the device yield. Moreover, in the same step of this embodiment, the wafer 100 with the remaining thickness of multiple preset areas above the interconnection metal layer 130 and the initial partition column 500 with a portion of the height are removed, so the removed initial partition column 500 If the thickness of the wafer 100 is too large, it may easily lead to over-etching when removing the remaining thickness of the wafer 100 in multiple predetermined areas above the interconnect metal layer 130, causing damage to the interconnect metal layer 130. If the ratio of the height h2 of the removed initial segmentation column 500 to the total height h of the interconnection through hole 420 is too small, the height difference between the formed segmentation column 510 and the top of the interconnection through hole 420 is too small, that is, the height difference between the segmentation column 510 and the top of the subsequently formed interconnection structure is too small. The interconnection structure is connected through the space above the segmentation column 510, which may easily lead to the interconnection structures in the sub-through holes 410 divided by the segmentation column 510 being loosely connected, affecting the formation of the integrated structure of the interconnection structure and affecting the electrical connection performance of the interconnection structure. To this end, in the step of removing a portion of the height of the initial segmentation column 500, the ratio of the height h2 of the removed initial segmentation column 500 to the total height h of the interconnection through hole 420 is 1 / 5 to 3 / 4. As an example, the ratio of the height h2 of the removed initial segmentation column 500 to the total height h of the interconnection through hole 420 is 2 / 3.
[0108] Specifically, refer to Figure 9 ,in, Figure 9 (a) Yes Figure 9 (b) A cross-sectional view along the AA direction shows the steps of removing the wafer 100 with the remaining thickness in multiple predetermined areas above the interconnect metal layer 130 and removing a portion of the height of the initial segmentation pillars 500, including forming a second mask layer 320 on the wafer 100, the second mask layer 320 having a second opening 330 exposing the initial interconnection through-hole 400.
[0109] The second mask layer 320 is used as an etching mask for patterning the wafer 100 to form the sub-through hole 410 .
[0110] refer to Figure 10 ,in, Figure 10 (a) Yes Figure 10 (b) A cross-sectional view along the AA direction shows the wafer 100 in the initial interconnection vias patterned along the second opening 330 , removing the remaining thickness of the wafer 100 in multiple predetermined areas above the interconnection metal layer 130 , and removing a portion of the height of the initial segmentation pillars 500 .
[0111] refer to Figure 11 ,in, Figure 11 (b) Yes Figure 11 (a) Cross-sectional view along the AA direction, Figure 11 (c) Yes Figure 11 (a) is a cross-sectional view along the BB direction. After forming the interconnection through hole 420 , the process further includes: removing the second mask layer 320 .
[0112] Combined with reference Figure 12 and Figure 13 ,in, Figure 12 (b) Yes Figure 12 (a) Cross-sectional view along the AA direction, Figure 12 (c) Yes Figure 12 (a) A cross-sectional view along the BB direction shows an interconnection structure 600 formed in the interconnection via 420 , and the interconnection structure 600 is electrically connected to the interconnection metal layer 130 .
[0113] The interconnect structure 600 is used to electrically connect to the interconnect metal layer 130 , thereby achieving electrical connection between the interconnect metal layer 130 and the outside.
[0114] Accordingly, in this embodiment, portions of the interconnection structure 600 that are higher than the top surfaces of the partition pillars 510 are connected.
[0115] The portion of the interconnection structure 600 that is higher than the top surface of the segmentation pillar 510 is connected to form an integrated structure, which is beneficial to ensuring the electrical connection performance between the interconnection structure 600 and the interconnection metal layer 130 .
[0116] It should be noted that, in this embodiment, the morphology of the partition pillars 510 in the interconnection through-holes 420 in the top view is not limited. Figure 13 (a)-(d) show the morphologies of four types of segmentation pillars 510 .
[0117] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A packaging structure, characterized in that: include: a wafer having an interconnect metal layer formed therein; an interconnection through-hole, penetrating the wafer above the interconnection metal layer and exposing the top surface of the interconnection metal layer, the interconnection through-hole comprising a segmentation column protruding from the interconnection metal layer, the segmentation column segmenting the interconnection through-hole into a plurality of sub-through-holes, the plurality of sub-through-holes being interconnected; An interconnection structure is located in the interconnection through hole and is electrically connected to the interconnection metal layer.
2. The packaging structure according to claim 1, wherein: The partition column includes a plurality of sub-partition columns, and the plurality of sub-partition columns intersect or are parallel to each other.
3. The packaging structure according to claim 2, wherein: The partitioning pillars partition the interconnection through-hole into a plurality of sub-through-holes uniformly distributed in a top-view direction.
4. The packaging structure according to claim 3, wherein: The partition pillar includes two sub-partition pillars that intersect vertically, and the partition pillars partition the interconnection through-hole into four sub-through-holes.
5. The packaging structure according to claim 1, wherein: The top surface of the partition column is lower than the top of the interconnected through hole, and the portions of the plurality of sub-through holes that are higher than the top surface of the partition column are connected; Portions of the interconnection structure that are higher than the top surfaces of the segmentation pillars are connected.
6. The packaging structure according to claim 5, wherein: The ratio of the height of the partition pillar to the total height of the interconnection through hole is 1 / 4 to 4 / 5.
7. The packaging structure according to claim 1, wherein: The partition pillar passes through the center point of the interconnection through hole.
8. The packaging structure according to claim 7, wherein: The interconnection via is located at a central position of the interconnection metal layer.
9. A packaging method, characterized in that: include: providing a wafer having an interconnect metal layer formed therein; Patterning the wafer to form an interconnection through-hole exposing a top surface of the interconnection metal layer, wherein the interconnection through-hole comprises a segmentation column protruding from the interconnection metal layer, the segmentation column segmenting the interconnection through-hole into a plurality of sub-through-holes, and the plurality of sub-through-holes are connected; An interconnection structure is formed in the interconnection through hole, the interconnection structure being electrically connected to the interconnection metal layer.
10. The packaging method according to claim 9, wherein: The step of patterning the wafer to form interconnection through-holes exposing the top surface of the interconnection metal layer comprises: removing a portion of the wafer having a thickness of a plurality of predetermined areas above the interconnection metal layer to form a plurality of separated initial sub-through-holes, retaining the remaining wafer from which the plurality of initial sub-through-holes are separated as initial segmentation columns, and the plurality of initial sub-through-holes forming an initial interconnection through-hole; Removing the wafer of remaining thickness in a plurality of preset areas above the interconnect metal layer to form a plurality of sub-vias; Part of the height of the initial segmentation column is removed, and the remaining initial segmentation column is retained as the segmentation column, so that the multiple sub-through holes are connected through the portion higher than the top surface of the segmentation column, and the multiple sub-through holes constitute the interconnected through hole.
11. The packaging method according to claim 10, wherein: In the same step, the wafer having the remaining thickness in a plurality of preset areas above the interconnection metal layer is removed, and the initial segmentation columns having a partial height are removed.
12. The packaging method according to claim 10, wherein: The step of removing a portion of the wafer thickness of a plurality of preset areas above the interconnect metal layer to form a plurality of separated initial sub-vias comprises: forming a first mask layer on the wafer, the first mask layer having a first opening exposing a top surface of the wafer of the plurality of preset areas; patterning the wafer along the first opening to remove the remaining thickness of the wafer in a plurality of predetermined areas above the interconnect metal layer; After forming the initial sub-through hole, the method further includes: removing the first mask layer.
13. The packaging method according to claim 11, wherein: The steps of removing the wafer having a remaining thickness of a plurality of predetermined areas above the interconnect metal layer and removing a portion of the height of the initial segmentation pillars include: forming a second mask layer on the wafer, the second mask layer having a second opening exposing the initial interconnection through-hole; Patterning the wafer in the initial interconnection through-hole along the second opening, removing the wafer with a remaining thickness in a plurality of predetermined areas above the interconnection metal layer, and removing a portion of the height of the initial segmentation pillars; After forming the interconnection through hole, the method further includes: removing the second mask layer.
14. The packaging method according to claim 10, wherein: In the step of removing a portion of the wafer thickness in multiple preset areas above the interconnect metal layer to form a plurality of separated initial sub-vias, the ratio of the depth of the initial sub-vias to the total thickness of the wafer above the interconnect metal layer is 1 / 5 to 3 / 4.
15. The packaging method according to claim 10, wherein: In the step of removing a portion of the height of the initial partition pillars, the ratio of the height of the removed initial partition pillars to the total height of the interconnection through-holes is 1 / 5 to 3 / 4.
16. The packaging method according to claim 9, wherein: In the step of patterning the wafer to form interconnection through-holes exposing the top surface of the interconnection metal layer, the segmentation column includes a plurality of sub-segmentation columns, and the plurality of sub-segmentation columns intersect or are parallel to each other.
17. The packaging method according to claim 16, wherein: In the step of patterning the wafer to form an interconnection through-hole exposing the top surface of the interconnection metal layer, the segmentation pillars segment the interconnection through-hole into a plurality of sub-through-holes uniformly distributed in a top-view direction.
18. The packaging method according to claim 17, wherein: In the step of patterning the wafer to form an interconnection through-hole exposing the top surface of the interconnection metal layer, the segmentation column includes two sub-segmentation columns that intersect vertically, and the segmentation column divides the interconnection through-hole into four sub-through-holes.
19. The packaging method according to claim 9, wherein: In the step of patterning the wafer to form an interconnection through-hole exposing the top surface of the interconnection metal layer, the segmentation column passes through the center point of the interconnection through-hole.