Integratable distributed dynamic temperature detection system for ferroelectric memory chip

Abstract

The invention relates to an integratable distributed dynamic temperature detection system for a ferroelectric memory chip, and the system comprises distributed temperature sensor groups which are distributed at the periphery of a ferroelectric memory array and are used for detecting the relative temperature gradient information of the ferroelectric memory array; the array temperature detection module is used for generating a secondary array address meeting a preset relative highest temperature condition; the temperature address decoder is used for respectively outputting enable signals of the secondary temperature sensor and the array temperature detection module; the temperature gradient analysis module is used for performing relative temperature analysis on the relative temperature gradient information; and the control module is used for controlling the primary array and the secondary array to perform array temperature dynamic scanning detection according to the enable signal so as to generate a final integratable distributed dynamic temperature detection result. According to the invention, the framework of a ferroelectric memory chip temperature detection system is standardized, the temperature detection power consumption of a large-scale ferroelectric memory array is reduced, and the rapid temperature scanning of the ferroelectric memory array is realized.

Description

Technical Field

[0001] The present application relates to the technical field of ferroelectric memory, and in particular to an integrated distributed dynamic temperature detection system for ferroelectric memory chips. Background Art

[0002] An integrated distributed dynamic temperature detection system for ferroelectric memory chips is a circuit system that improves the temperature detection efficiency of large-scale ferroelectric memories while effectively reducing the static power consumption of ferroelectric memory array temperature detection. As the application of ferroelectric memories continues to expand, a low-power, high-efficiency, real-time ferroelectric memory thermal management system is urgently needed to meet the increasing demand for ferroelectric memory's high-temperature performance.

[0003] Traditional temperature detection solutions typically use non-integrated, off-chip temperature detection chips to build detection systems, which suffer from high power consumption, low accuracy, and high cost. Furthermore, existing integrated ferroelectric memory temperature detection circuits only determine the overtemperature status of the ferroelectric memory chip as a whole, resulting in low temperature detection accuracy and large temperature detection errors. Summary of the Invention

[0004] This application provides an integrated, distributed, dynamic temperature detection system for ferroelectric memory chips. This system addresses the drawbacks of traditional temperature detection solutions, which typically utilize non-integrated, off-chip temperature detection chips to build detection systems. This system suffers from high power consumption, low accuracy, and high cost. Furthermore, existing integrated ferroelectric memory temperature detection circuits only determine the overtemperature status of the ferroelectric memory chip's overall circuitry, resulting in low temperature detection accuracy and large temperature detection errors.

[0005] According to a first aspect of the present application, an embodiment provides an integrable distributed dynamic temperature detection system for a ferroelectric memory chip, comprising: a distributed temperature sensor group, the distributed temperature sensor group being distributed around a ferroelectric memory array and configured to detect relative temperature gradient information of the ferroelectric memory array; an array temperature detection module, the input end of the array temperature detection module being connected to the output end of the temperature sensor group and configured to generate, based on the relative temperature gradient information, a secondary array address that satisfies a preset relative maximum temperature condition; a temperature address decoder, the temperature address decoder being connected to the output end of the array temperature detection module and configured to output enable signals for the secondary temperature sensor and the array temperature detection module, respectively, based on the secondary array address; a temperature gradient analysis module, the input end of the temperature gradient analysis module being connected to the output end of the array temperature detection module and configured to perform relative temperature analysis on the relative temperature gradient information to obtain a sub-array that satisfies the preset maximum temperature condition; and a control module, the control module being connected to the output end of the temperature gradient analysis module and configured to control the primary array and the secondary array to perform array temperature dynamic scanning detection according to the enable signal to generate a final integrable distributed dynamic temperature detection result.

[0006] Optionally, in one embodiment of the present application, the distributed temperature sensor group includes: a location division unit, used to divide the locations of the temperature sensor group into multiple groups; a temperature gradient analysis unit, used to collect temperature information of the multiple groups and analyze the temperature gradient information of the ferroelectric memory array based on the temperature information.

[0007] Optionally, in one embodiment of the present application, the temperature gradient analysis module is further configured to determine the operating state of the ferroelectric memory array by utilizing a relative temperature change between the ferroelectric memory array and a reference temperature.

[0008] Optionally, in one embodiment of the present application, the temperature gradient analysis module is further configured to determine any output signal of the operating temperature, subarray address data, relative temperature or fatigue degree that meets a preset temperature condition by analyzing the temperature data.

[0009] Optionally, in one embodiment of the present application, the control module is further configured to control the temperature sensor group and array temperature detection circuit of the scanned ferroelectric memory sub-array to be in an operating state when dynamically scanning the distributed ferroelectric memory temperature gradient.

[0010] Optionally, in one embodiment of the present application, the distributed temperature sensor group adopts an integrable complementary metal oxide semiconductor (CMOS) temperature sensor.

[0011] The second aspect of the present application provides an integrated distributed dynamic temperature detection method for a ferroelectric memory chip, comprising the following steps: detecting relative temperature gradient information; generating a secondary array address that meets a preset relative maximum temperature condition based on the relative temperature gradient information; outputting enable signals based on the secondary array addresses; performing relative temperature analysis on the relative temperature gradient information; and performing array temperature dynamic scanning detection based on the enable signal to generate a final integrated distributed dynamic temperature detection result.

[0012] Optionally, in one embodiment of the present application, the detecting relative temperature gradient information includes: dividing the locations of the temperature sensor group into multiple groups; collecting temperature information of the multiple groups, and analyzing the temperature gradient information of the ferroelectric memory array based on the temperature information.

[0013] Optionally, in one embodiment of the present application, the performing relative temperature analysis on the relative temperature gradient information includes: determining the working state of the ferroelectric memory array by utilizing the relative temperature change between the ferroelectric memory array and a reference temperature.

[0014] Optionally, in one embodiment of the present application, the performing relative temperature analysis on the relative temperature gradient information further includes: determining any output signal of the operating temperature, subarray address data, relative temperature or fatigue degree that meets the preset temperature condition by analyzing the temperature data.

[0015] Optionally, in one embodiment of the present application, the array temperature dynamic scanning detection is performed according to the enable signal to generate a final integrated distributed dynamic temperature detection result, including: when dynamically scanning the distributed ferroelectric storage temperature gradient, controlling the temperature sensor group and array temperature detection circuit of the scanned ferroelectric memory sub-array to be in a working state.

[0016] The third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored on the memory and runnable on the processor, wherein the processor executes the program to implement the integrated distributed dynamic temperature detection method for ferroelectric memory chips as described in the above embodiment.

[0017] A fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program. When the program is executed by a processor, it implements the above-mentioned integrated distributed dynamic temperature detection method for ferroelectric memory chips.

[0018] A fifth aspect of the present application provides a computer program product, which stores a computer program that, when executed by a processor, implements the above-mentioned integrated distributed dynamic temperature detection method for ferroelectric memory chips.

[0019] The embodiments of the present application reflect the fatigue state of a ferroelectric memory array by detecting the relative temperature change of the memory array. Based on a distributed dynamic temperature detection system, the architecture of the ferroelectric memory chip temperature detection system is standardized, the power consumption of temperature detection of large-scale ferroelectric memory arrays is reduced, and a fast temperature scanning method for ferroelectric memory arrays is realized. This solves the problem that traditional temperature detection solutions generally use non-integrated off-chip temperature detection chips to build detection systems, which has the disadvantages of high power consumption, low accuracy, and high cost. At the same time, existing integrated ferroelectric memory temperature detection circuits only determine the overtemperature state of the entire ferroelectric memory chip circuit, resulting in problems such as low temperature detection accuracy and large temperature detection errors.

[0020] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0022] Figure 1 Schematic diagram of the structure of an integrated distributed dynamic temperature detection system for a ferroelectric memory chip provided in accordance with an embodiment of the present application;

[0023] Figure 2 Schematic diagram of a temperature detection system for a ferroelectric memory chip according to one embodiment of the present application;

[0024] Figure 3 Schematic diagram of an N-th level module according to one embodiment of the present application;

[0025] Figure 4 Schematic diagram of temperature sensors distributed around a ferroelectric memory array according to one embodiment of the present application;

[0026] Figure 5 Schematic diagram of the connection between a ferroelectric memory array temperature sensor and an array temperature detection circuit according to one embodiment of the present application;

[0027] Figure 6 is a detailed schematic diagram of an array temperature detection circuit according to one embodiment of the present application;

[0028] Figure 7A schematic diagram of a flow chart of an integrated distributed dynamic temperature detection method for a ferroelectric memory chip provided according to an embodiment of the present application;

[0029] Figure 8 A schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0031] The following describes an integrated distributed dynamic temperature detection system for ferroelectric memory chips according to an embodiment of the present application with reference to the accompanying drawings. The conventional temperature detection scheme mentioned in the above background technology generally uses a non-integrated off-chip temperature detection chip to build a detection system, which has the disadvantages of high power consumption, low precision, and high cost. At the same time, the existing integrated ferroelectric memory temperature detection circuit only judges the over-temperature state of the ferroelectric memory chip's overall circuit, and has problems such as low temperature detection precision and large temperature detection error. The present application provides an integrated distributed dynamic temperature detection system for ferroelectric memory chips, in which the fatigue state of the ferroelectric memory array is reflected by detecting the relative temperature change of the storage array. Based on the distributed dynamic temperature detection system, the architecture of the ferroelectric memory chip temperature detection system is standardized, the power consumption of temperature detection of large-scale ferroelectric memory arrays is reduced, and a fast temperature scanning method for ferroelectric memory arrays is realized. Thus, the problem that the conventional temperature detection scheme generally uses a non-integrated off-chip temperature detection chip to build a detection system, which has the disadvantages of high power consumption, low precision, and high cost, is solved. Meanwhile, the existing integrated ferroelectric memory temperature detection circuit only determines the over-temperature state of the entire ferroelectric memory chip circuit, and has problems such as low temperature detection accuracy and large temperature detection error.

[0032] Specifically, Figure 1 A schematic structural diagram of an integrated distributed dynamic temperature detection system for a ferroelectric memory chip provided in an embodiment of the present application.

[0033] like Figure 1 As shown, the integrable distributed dynamic temperature detection system 10 for ferroelectric memory chips includes: a distributed temperature sensor group 100, an array temperature detection module 200, a temperature address decoder 300, a temperature gradient analysis module 400 and a control module 500.

[0034] Specifically, the distributed temperature sensor group 100 is distributed around the periphery of the ferroelectric memory array and is used to detect relative temperature gradient information of the ferroelectric memory array.

[0035] During the actual implementation process, the distributed temperature sensor group 100 in the embodiment of the present application is distributed around the periphery of the ferroelectric memory array. The enable end of the temperature sensor group and the array temperature detection circuit at each level is connected to the enable output end of the upper-level module. A distributed temperature sensor group is placed around each ferroelectric memory array at each level, and each temperature sensor group detects and analyzes the relative temperature gradient information of the sub-array in which it is located.

[0036] The ferroelectric memory chip can be divided into multiple levels of sub-memory arrays, and each sub-memory array is provided with a dynamic temperature sensor.

[0037] Optionally, in one embodiment of the present application, the distributed temperature sensor group 100 includes: a location division unit for dividing the location of the temperature sensor group 100 into multiple groups; a temperature gradient analysis unit for collecting temperature information of multiple groups and analyzing the temperature gradient information of the ferroelectric memory array based on the temperature information.

[0038] In the embodiment of the present application, the temperature sensor group 100 of each ferroelectric memory array is divided into multiple groups according to their locations, and the temperature gradient information of each array of the ferroelectric memory is analyzed by collecting the temperature information of each group.

[0039] In one embodiment of the present application, the distributed temperature sensor group 100 uses an integrable complementary metal oxide semiconductor (CMOS) temperature sensor.

[0040] The embodiment of the present application can integrate a CMOS temperature sensor and integrate the temperature sensor into a ferroelectric memory chip, thereby improving temperature detection accuracy and reducing power consumption and area.

[0041] Temperature sensors are distributed around the periphery of each ferroelectric memory array at each level, performing temperature detection from the top module to the secondary modules, and finally transmitting the collected maximum operating temperature and sub-array address data to the control module 500.

[0042] The array temperature detection module 200 has an input end connected to the output end of the temperature sensor group 100 and is used to generate a secondary array address that meets a preset relative maximum temperature condition based on the relative temperature gradient information.

[0043] It can be understood that the array temperature detection module 200 in the embodiment of the present application can be an array temperature detection circuit.

[0044] Specifically, in the embodiment of the present application, the input end of the array temperature detection module 200 is connected to the output end of the temperature sensor group 100, and is used to generate a secondary array address that meets a preset relative maximum temperature condition based on the relative temperature gradient information. After detecting the temperature of a certain array through dynamic temperature detection, the secondary array with the highest temperature is analyzed based on the data of the two horizontal groups and the two vertical groups of temperature sensors, and the temperature data of this secondary array is detected. At the same time, the temperature detection systems of other arrays remain disabled to avoid generating additional static power consumption, improve detection efficiency, and reduce power consumption.

[0045] It should be noted that the preset relative maximum temperature condition can be set by those skilled in the art according to actual conditions and is not specifically limited here.

[0046] The temperature address decoder 300 is connected to the output end of the array temperature detection module 200 and is used to output enable signals of the secondary temperature sensor and the array temperature detection module 200 based on the secondary array address.

[0047] During actual execution, the temperature address decoder 300 in the embodiment of the present application can output enable signals of the secondary temperature sensor and the array temperature detection module 200 respectively based on the secondary array address, providing support for subsequent dynamic scanning detection of array temperature.

[0048] The temperature gradient analysis module 400 has its input end connected to the output end of the array temperature detection module 200 and is used to perform relative temperature analysis on the relative temperature gradient information to obtain a sub-array that meets a preset maximum temperature condition.

[0049] During actual execution, the input end of the temperature gradient analysis module 400 in the embodiment of the present application is connected to the output end of the array temperature detection module 200. The dynamic temperature detection system includes a reference temperature sensor, temperature sensors of each sub-array at each level, and a temperature gradient analysis module 400. The temperature gradient analysis module 400 performs relative temperature analysis on the data collected by each sub-array temperature sensor and the reference temperature sensor to obtain the sub-array with the highest temperature.

[0050] It should be noted that the preset maximum temperature condition can be set by those skilled in the art according to actual conditions and is not specifically limited here.

[0051] Optionally, in one embodiment of the present application, the temperature gradient analysis module 400 is further configured to determine the operating state of the ferroelectric memory array by utilizing the relative temperature change between the ferroelectric memory array and a reference temperature.

[0052] Among them, the embodiment of the present application can use the relative temperature change between the ferroelectric memory array and the reference temperature to judge the working status of the ferroelectric memory array. Through the distributed temperature detection structure, it can scan and detect the temperature status of all arrays for data collection and detect the working status of the ferroelectric memory chip in real time.

[0053] Optionally, in one embodiment of the present application, the temperature gradient analysis module 400 is further configured to determine any output signal of the operating temperature, subarray address data, relative temperature or fatigue degree that meets a preset temperature condition by analyzing the temperature data.

[0054] It can be understood that, in the embodiment of the present application, the operating temperature that meets the preset temperature condition may be the highest operating temperature.

[0055] During actual execution, the output signal of the temperature gradient analysis module 400 in the embodiment of the present application includes the maximum operating temperature and sub-array address data, as well as the relative temperature or fatigue degree. The memory performs real-time fatigue analysis, and the relative temperature change of the storage array reflects the fatigue state of the ferroelectric memory array. While the ferroelectric memory chip is working, the device fatigue degree is quantified based on the dynamic temperature detection results, and real-time fatigue analysis is performed.

[0056] Since capacitor fatigue in the ferroelectric memory array generates additional thermal waste, it can be reflected by the relative temperature change of the array. The present application can reflect the fatigue state of the ferroelectric memory array by detecting the relative temperature change of the memory array.

[0057] It should be noted that the preset temperature conditions can be set by those skilled in the art according to actual conditions and are not specifically limited here.

[0058] The control module 500 is connected to the output end of the temperature gradient analysis module 400 and is used to control the primary array and the secondary array to perform array temperature dynamic scanning detection according to the enable signal to generate the final integrated distributed dynamic temperature detection result.

[0059] It can be understood that the ferroelectric memory sub-array (ferroelectric memory chip sub-array) in the embodiment of the present application is divided into at least two levels of arrays.

[0060] During actual implementation, the control module 500 in the embodiment of the present application is connected to the output of the temperature gradient analysis module 400. After performing array temperature detection and temperature address decoding on each ferroelectric memory subarray, it sends an enable signal to control the primary and secondary arrays to perform dynamic array temperature scanning detection, thereby generating the final integrated distributed dynamic temperature detection results and transmitting the array temperature data to the receiving end. This application standardizes the architecture of the ferroelectric memory chip temperature detection system, reduces the power consumption of temperature detection on large-scale ferroelectric memory arrays, and implements a fast temperature scanning method for ferroelectric memory arrays.

[0061] Among them, the distributed dynamic temperature detection system starts from the top array, measures and analyzes the array temperature gradient. Furthermore, the temperature detection system of the secondary array with the highest temperature works, while the temperature detection systems of other arrays remain closed to avoid generating additional static power consumption.

[0062] Optionally, in one embodiment of the present application, the control module 500 is further configured to control the temperature sensor group and the array temperature detection circuit of the scanned ferroelectric memory sub-array to be in an operating state when dynamically scanning the distributed ferroelectric memory temperature gradient.

[0063] Specifically, the temperature sensors and array temperature detection circuits of other secondary arrays except the scanned array will be in a closed state, that is, when the control module 500 in the embodiment of the present application dynamically scans the distributed ferroelectric storage temperature gradient, the temperature sensor group and array temperature detection circuit of the scanned ferroelectric memory sub-array are in a working state.

[0064] The basic operating principle of the ferroelectric memory temperature detection system is as follows: The ferroelectric memory array to be tested is divided into at least two levels, with each non-minimum array containing at least two sub-arrays. Distributed temperature sensors are placed around each array to detect the relative temperature gradient of the ferroelectric memory array. The collected relative temperature gradient information is transmitted to the array temperature detection circuit. The array temperature detection circuit detects the collected relative temperature gradient information and obtains the address of the sub-array with the highest relative temperature. The array temperature detection circuit inputs the output array address information into a temperature address decoder. The temperature address decoder outputs a control signal that enables the sub-temperature sensors and the array temperature detection circuit to perform temperature detection on a specific sub-array. This detection logic based on distributed temperature sensors ensures that the sub-array to be tested is the one with the highest temperature within the same level, ensuring detection efficiency and real-time performance while also taking into account detection accuracy. The output of the array temperature detection circuit is connected to the input of the temperature gradient analysis module, which in turn is connected to the control module and transmits the array temperature data to the receiver.

[0065] The top-level array's temperature sensors detect temperature under the action of an enable signal. The temperature sensors are divided into four groups based on their location, detecting the temperatures on both sides of the memory array, both horizontally and vertically. The four sets of temperature data, along with reference temperature data, are transmitted to the array temperature detection circuit, which analyzes the relative temperature gradient and determines the address of the sub-array with the highest temperature. The sub-array address is input into the address decoder, which generates an enable signal for the sub-array temperature sensor. The sub-array temperature sensor with the highest temperature detects temperature under the action of an enable signal and transmits the four sets of temperature data to the array temperature detection circuit. If the ferroelectric memory has more array levels, the operation method is similar. After the minimum-level array temperature detection is completed, the temperature data is transmitted to the temperature gradient analysis module. The output signal of the temperature gradient analysis module is transmitted to the control module, which sends the array temperature data to the receiving end, completing the single-shot detection process.

[0066] Specifically, it can be combined Figures 2 to 6 As shown, the working principle of the integrated distributed dynamic temperature detection system for ferroelectric memory chips in the embodiment of the present application is described in detail with a specific embodiment.

[0067] like Figure 2 As shown, the temperature detection system for ferroelectric memory includes primary and secondary modules, a reference temperature detection module, a temperature gradient analysis module, and a control module. Each secondary module is contained within the primary module. The primary and secondary modules include a distributed temperature sensor group outside the ferroelectric memory array, an array temperature detection circuit, and a temperature address decoder. The control module provides control signals to the primary and secondary modules. The primary, secondary, and reference temperature detection modules transmit the detected temperature data to the temperature detection and analysis module. The temperature detection and analysis module processes the temperature data from the primary and secondary modules and the reference temperature data to generate relative temperature gradient data, which is then transmitted to the control module and ultimately sent to the receiving end. As ferroelectric capacitors fatigue, their capacitance decreases and their capacitive reactance increases, leading to an increase in operating temperature. When the overall fatigue of the ferroelectric memory array reaches a certain level, fatigue is reflected in the relative temperature. Therefore, based on the dynamic temperature detection results, the degree of device fatigue can be quantified, allowing for real-time fatigue analysis.

[0068] like Figure 3As shown, the Nth-stage module of a temperature detection system for a ferroelectric memory array includes a distributed temperature sensor group outside the ferroelectric memory array, an array temperature detection circuit, and an address decoder. The ferroelectric memory array is controlled by an external control signal, and its corresponding temperature sensor group and array temperature detection circuit are controlled by an enable signal provided by the N-1th-stage module. When the enable signal is valid, the array's temperature sensor group operates, detecting temperatures at different locations in the array and transmitting temperature gradient data to the array temperature detection circuit. The array temperature detection circuit is also controlled by the enable signal provided by the N-1th-stage module. After receiving the temperature gradient data, it outputs the address of the secondary array with the highest temperature. This address is input into the address decoder, which provides an enable signal for the N+1th-stage module.

[0069] like Figure 4 As shown, the ferroelectric memory chip is divided into a multi-level array. Taking a three-level array as an example, each level is divided into four sub-arrays. Temperature sensors are distributed around the periphery of each level of the ferroelectric memory array. Taking into account power consumption and temperature detection accuracy, this application provides an optimal choice for the number and location of temperature sensors. Each level of the ferroelectric memory array uses eight temperature sensors, four of which are placed at the four corners of the ferroelectric memory array, and the other four are placed at the center of the four sides, thereby being able to detect the temperature of the entire ferroelectric memory array. Furthermore, the temperature sensors at different locations are grouped to perform temperature gradient analysis.

[0070] Figure 5 and Figure 6 This paper demonstrates how temperature sensors on the periphery of a ferroelectric memory array are grouped according to their location. The four ferroelectric memory arrays on the same level are numbered 00, 01, 10, and 11, which also serve as the addresses of the ferroelectric memory arrays. Furthermore, the eight temperature sensors are divided into groups along each edge of the ferroelectric memory array: temperature sensors A1, A2, and A3 form horizontal group 0; temperature sensors A5, A6, and A7 form horizontal group 1; temperature sensors A1, A8, and A7 form vertical group 0; and temperature sensors A3, A4, and A5 form vertical group 1. The temperature data H0 and H1 for horizontal groups 0 and 1, and the temperature data V0 and V1 for vertical groups 0 and 1, are input into the array temperature detection circuit. A reference temperature is also input into the array temperature detection circuit. The array temperature detection circuit determines the relative temperature based on the input temperature data. By comparing the relative temperatures H0 and H1, the first address of the secondary module array is obtained. By comparing the relative temperatures V0 and V1, the second address of the secondary module array is obtained. Combining this information, the address of the secondary array with the highest temperature is determined. The address is decoded to obtain a secondary module enable signal, which enables the secondary module with the highest temperature to continue temperature detection, thus realizing distributed dynamic temperature detection.

[0071] According to the embodiment of the present application, an integrable distributed dynamic temperature detection system for ferroelectric memory chips is proposed to detect the temperature condition of the ferroelectric memory array, which effectively improves the accuracy of the distributed temperature detection of the ferroelectric memory, realizes the real-time performance of the temperature detection of the ferroelectric memory array, and reduces the power consumption of the temperature detection of large-scale ferroelectric memory arrays. On the basis of dynamic temperature detection, the present application also proposes the concept of real-time fatigue analysis of the memory, quantifies the degree of device fatigue, and further optimizes the durability of the ferroelectric memory. Thus, the problem that the traditional temperature detection scheme generally uses non-integrable off-chip temperature detection chips to build the detection system is solved, which has the disadvantages of high power consumption, low accuracy, and high cost. At the same time, the existing integrable ferroelectric memory temperature detection circuit only judges the over-temperature state of the overall circuit of the ferroelectric memory chip, and has problems such as low temperature detection accuracy and large temperature detection error.

[0072] Next, a schematic structural diagram of an integrated distributed dynamic temperature detection method for a ferroelectric memory chip proposed in accordance with an embodiment of the present application will be described with reference to the accompanying drawings.

[0073] Figure 7 It is a flow chart of an integrated distributed dynamic temperature detection method for a ferroelectric memory chip according to an embodiment of the present application.

[0074] like Figure 7 As shown, the integrated distributed dynamic temperature detection method for ferroelectric memory chip includes the following steps:

[0075] In step S701 , relative temperature gradient information is detected.

[0076] In step S702 , a secondary array address that meets a preset relative maximum temperature condition is generated based on the relative temperature gradient information.

[0077] In step S703 , enable signals are outputted based on the secondary array addresses.

[0078] In step S704 , relative temperature analysis is performed on the relative temperature gradient information.

[0079] In step S705 , array temperature dynamic scanning detection is performed according to the enable signal to generate a final integrated distributed dynamic temperature detection result.

[0080] Optionally, in one embodiment of the present application, detecting relative temperature gradient information includes: dividing the locations of the temperature sensor groups into multiple groups; collecting temperature information of the multiple groups, and analyzing temperature gradient information of the ferroelectric memory array based on the temperature information.

[0081] Optionally, in one embodiment of the present application, performing relative temperature analysis on the relative temperature gradient information includes: determining the operating state of the ferroelectric memory array by utilizing the relative temperature change between the ferroelectric memory array and a reference temperature.

[0082] Optionally, in one embodiment of the present application, performing relative temperature analysis on the relative temperature gradient information further includes: determining any output signal of the operating temperature, subarray address data, relative temperature or fatigue degree that meets the preset temperature conditions by analyzing the temperature data.

[0083] Optionally, in one embodiment of the present application, array temperature dynamic scanning detection is performed according to an enable signal to generate a final integrated distributed dynamic temperature detection result, including: when dynamically scanning the distributed ferroelectric storage temperature gradient, controlling the temperature sensor group and array temperature detection circuit of the scanned ferroelectric memory sub-array to be in a working state.

[0084] It should be noted that the above explanation of the embodiment of the integrated distributed dynamic temperature detection system for ferroelectric memory chips is also applicable to the integrated distributed dynamic temperature detection method for ferroelectric memory chips of this embodiment, and will not be repeated here.

[0085] According to the integrated distributed dynamic temperature detection method for ferroelectric memory chips proposed in the embodiment of the present application, the accuracy of distributed temperature detection of ferroelectric memory is effectively improved, the real-time performance of temperature detection of ferroelectric memory array is achieved, and the power consumption of temperature detection of large-scale ferroelectric memory array is reduced. On the basis of dynamic temperature detection, the present application also proposes the concept of real-time fatigue analysis of memory, quantifies the degree of device fatigue, and further optimizes the durability of ferroelectric memory. Thus, the problem that traditional temperature detection schemes generally use non-integrated off-chip temperature detection chips to build detection systems, which has the disadvantages of high power consumption, low accuracy, and high cost, is solved. At the same time, the existing integrated ferroelectric memory temperature detection circuit only judges the over-temperature state of the overall circuit of the ferroelectric memory chip, and has problems such as low temperature detection accuracy and large temperature detection error.

[0086] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0087] A memory 801 , a processor 802 , and a computer program stored in the memory 801 and executable on the processor 802 .

[0088] When the processor 802 executes the program, the integrated distributed dynamic temperature detection method for a ferroelectric memory chip provided in the above embodiment is implemented.

[0089] Furthermore, the electronic device further includes:

[0090] The communication interface 803 is used for communication between the memory 801 and the processor 802 .

[0091] The memory 801 is used to store computer programs that can be run on the processor 802.

[0092] The memory 801 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0093] If the memory 801, processor 802, and communication interface 803 are implemented independently, the communication interface 803, memory 801, and processor 802 can be connected to each other via a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0094] Optionally, in a specific implementation, if the memory 801, the processor 802 and the communication interface 803 are integrated on a chip, the memory 801, the processor 802 and the communication interface 803 can communicate with each other through an internal interface.

[0095] The processor 802 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0096] This embodiment further provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the above-mentioned integrated distributed dynamic temperature detection method for a ferroelectric memory chip is implemented.

[0097] An embodiment of the present application further provides a computer program product on which a computer program is stored. When the program is executed by a processor, the above-mentioned integrated distributed dynamic temperature detection method for a ferroelectric memory chip is implemented.

[0098] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0099] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this application, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0100] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing a custom logical function or process step, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed in a different order than shown or discussed, including performing functions in a substantially simultaneous manner or in a reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application pertain.

[0101] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or N wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program can be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing it in other suitable ways as necessary, and then storing it in a computer memory.

[0102] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0103] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0104] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0105] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. An integrated distributed dynamic temperature detection system for ferroelectric memory chips, characterized in that: include: A distributed temperature sensor group, wherein the distributed temperature sensor group is distributed around the periphery of the ferroelectric memory array and is used to detect relative temperature gradient information of the ferroelectric memory array; an array temperature detection module, the input end of the array temperature detection module being connected to the output end of the temperature sensor group, and being configured to generate a secondary array address that meets a preset relative maximum temperature condition based on the relative temperature gradient information; a temperature address decoder connected to an output terminal of the array temperature detection module and configured to output enable signals of the secondary temperature sensor and the array temperature detection module respectively based on the secondary array address; a temperature gradient analysis module, the input end of which is connected to the output end of the array temperature detection module, for performing relative temperature analysis on the relative temperature gradient information to obtain a subarray that meets a preset maximum temperature condition; A control module is connected to the output end of the temperature gradient analysis module and is used to control the primary array and the secondary array to perform array temperature dynamic scanning detection according to the enable signal to generate a final integrated distributed dynamic temperature detection result.

2. The integrable distributed dynamic temperature detection system for ferroelectric memory chips according to claim 1, characterized in that: The distributed temperature sensor group includes: a position division unit, configured to divide the positions of the temperature sensor groups into a plurality of groups; The temperature gradient analysis unit is configured to collect temperature information of the plurality of groups and analyze temperature gradient information of the ferroelectric memory array according to the temperature information.

3. The integrable distributed dynamic temperature detection system for ferroelectric memory chips according to claim 1, characterized in that: The temperature gradient analysis module is further configured to determine the operating state of the ferroelectric memory array by utilizing the relative temperature change between the ferroelectric memory array and a reference temperature.

4. The integrable distributed dynamic temperature detection system for ferroelectric memory chips according to claim 1, characterized in that: The temperature gradient analysis module is further configured to determine any output signal of the operating temperature, subarray address data, relative temperature or fatigue degree that satisfies a preset temperature condition by analyzing the temperature data.

5. The integrable distributed dynamic temperature detection system for ferroelectric memory chips according to claim 1, characterized in that: The control module is further configured to control the temperature sensor group and array temperature detection circuit of the scanned ferroelectric memory sub-array to be in a working state when dynamically scanning the distributed ferroelectric memory temperature gradient.

6. The integrable distributed dynamic temperature detection system for ferroelectric memory chips according to claim 1, characterized in that: The distributed temperature sensor group adopts an integrable complementary metal oxide semiconductor (CMOS) temperature sensor.

7. An integrated distributed dynamic temperature detection method for ferroelectric memory chips, characterized in that: The following steps are involved: Detect relative temperature gradient information; generating a secondary array address that meets a preset relative maximum temperature condition based on the relative temperature gradient information; outputting enable signals respectively based on the secondary array addresses; performing relative temperature analysis on the relative temperature gradient information; Perform array temperature dynamic scanning detection according to the enable signal to generate a final integrable distributed dynamic temperature detection result.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the integrable distributed dynamic temperature detection method for a ferroelectric memory chip as claimed in claim 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the integrable distributed dynamic temperature detection method for a ferroelectric memory chip as claimed in claim 7 .

10. A computer program product comprising a computer program, characterized in that The computer program is executed to implement the integrable distributed dynamic temperature detection method for a ferroelectric memory chip according to claim 7 .

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