Wafer level integration and digital manufacturing method of vertical micromirror based photo-current chip

Abstract

The application discloses a method for on-chip integration and digital manufacturing of a photovoltaic chip based on a vertical micro-mirror, which comprises the following steps: manufacturing passive optical devices and active optical devices based on a vertical micro-mirror with a roughness of less than 1 nm on a drivable micro-electro-mechanical system structure, and forming an optical chip with adjustable parameters in a horizontal direction, the optical chip having functions of calculation, sensing, communication and the like; manufacturing integrated circuits on at least one surface of a top portion, a bottom portion and a sidewall of a silicon wafer by using a three-dimensional-two-dimensional patterning method, so as to obtain a concave-convex three-dimensional integrated circuit, i.e., an electrical chip; bonding a plurality of pieces of the concave-convex three-dimensional integrated circuit through micro-bumps and bonding rings to form micro-flow channels, connecting the micro-flow channels through through holes, and forming a micro-fluidic unit; and performing on-chip integration of the optical chip, the electrical chip and the micro-fluidic unit to form an on-chip system containing the photovoltaic chip based on the vertical micro-mirror, the on-chip system having complex function processing capabilities of calculation, sensing, communication, signal processing, data storage and the like.

Description

Technical Field

[0001] This invention belongs to the fields of integrated circuits, optoelectronics, advanced packaging and digital manufacturing, and particularly relates to on-chip integration and digital manufacturing methods for photocurrent chips based on vertical micromirrors. Background Technology

[0002] As integrated circuit manufacturing processes enter the sub-10 nanometer range, Moore's Law has gradually slowed down and is even becoming obsolete. How to integrate more transistors on a limited chip area to achieve more powerful functions has become a hot research topic in the integrated circuit field. Advanced packaging technologies, such as 2.5D / 3D packaging and wafer-level packaging, have become effective technical routes to further improve the performance of integrated circuit systems in the post-Moore's Law era. Through advanced packaging technologies, multi-chip systems can achieve high-density, high-bandwidth, low-latency, and low-power wafer-level heterogeneous integrated systems. However, traditional advanced packaging technologies, whether 2.5D / 3D packaging or wafer-level packaging, increase the overall number of transistors by horizontally tiling or vertically stacking them without changing the utilization efficiency per unit area of ​​the chip. Generally, whether it is field-effect transistors manufactured based on processes at 28 nanometer nodes and above, or fin field-effect transistors manufactured based on processes below 28 nanometer nodes, integrated circuits composed of transistors are manufactured on the surface of the wafer, and the internal space of the wafer is not effectively utilized. Even 3D stacking integration technologies, such as Through-Silicon Via (TSV), involve first fabricating integrated circuit chips on a silicon plane and then stacking them together. Essentially, it's a reconstruction of planar integrated circuit chips, rather than directly manufacturing 3D integrated circuit chips. Fabricating 3D integrated circuit chips can fully utilize the internal space of a silicon wafer to integrate more transistors in the same area. However, the manufacturing of such integrated circuit chips is limited by various manufacturing techniques, including fabricating 3D deep trench structures with smooth sidewalls, patterning 3D sidewalls, 3D doping, and 3D thin film deposition. Summary of the Invention

[0003] To address the problems existing in the prior art, the purpose of this application is to provide a method for on-chip integration and digital manufacturing of photocurrent chips based on vertical micromirrors.

[0004] According to a first aspect of the embodiments of this application, a method for on-chip integration of a photocurrent chip based on a vertical micromirror is provided, comprising:

[0005] On a driveable microelectromechanical system structure, passive and active optical devices based on vertical micromirrors are fabricated using deep etching, sidewall smoothing, and three-dimensional-two-dimensional patterning methods to form an optical chip.

[0006] An integrated circuit is fabricated on at least one surface of the top, bottom, or sidewall of a silicon wafer using a three-dimensional-two-dimensional patterning method to obtain a bump-concave three-dimensional integrated circuit, i.e., an electrical chip.

[0007] Several concave-convex three-dimensional integrated circuits are bonded together using microbumps and bonding rings to form microchannels. These microchannels are then connected by vias to form a microfluidic unit.

[0008] The optical chip, electrical chip, and microfluidic unit are integrated on-chip to form a system-on-chip including a photocurrent chip based on a vertical micromirror.

[0009] Furthermore, the manufacturing process of passive optical devices includes:

[0010] Deep etching and sidewall smoothing steps: Deeply etch a vertical structure on a silicon wafer, and smooth the sidewalls of the vertical structure to form a vertical micromirror;

[0011] Three-dimensional to two-dimensional patterning steps: Three-dimensional patterning is performed on the sidewall of the vertical micromirror using two-photon printing, and two-dimensional patterning is performed on the area outside the sidewall using spray adhesive or layered coating of multiple layers of photoresist and exposure and development, so as to achieve patterning of the entire wafer.

[0012] Thin film growth steps: Optical thin films and electrical thin films are grown on the wafer and the sidewall of the vertical micromirror. The optical thin films include antireflection films, anti-reflection films, filter films, polarizing films, and beam splitting films. The electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

[0013] Furthermore, the manufacturing process of active optical devices includes:

[0014] Deep etching and sidewall smoothing steps: Deeply etch a vertical structure on a silicon wafer, and smooth the sidewalls of the vertical structure to form a vertical micromirror;

[0015] Three-dimensional to two-dimensional patterning steps: Three-dimensional patterning is performed on the sidewall of the vertical micromirror using two-photon printing, and two-dimensional patterning is performed on the area outside the sidewall using spray adhesive or layered coating of multiple layers of photoresist and exposure and development, so as to achieve patterning of the entire wafer.

[0016] Doping and activation steps: Ion implantation and heat treatment are performed on the sidewall of the vertical micromirror to achieve sidewall doping activation, ohmic contact formation, and metal electrode alloying.

[0017] Thin film growth steps: Optical thin films and electrical thin films are grown on the wafer and the sidewall of the vertical micromirror. The optical thin films include antireflection films, anti-reflection films, filter films, polarizing films, and beam splitting films. The electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

[0018] Furthermore, in the deep etching and sidewall smoothing steps, the sidewall smoothing methods include, but are not limited to, high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, reducing the alternation cycle of etching and protection processes, gas cluster ion beam etching, focused ion beam etching and milling, ion beam etching, and chemical mechanical polishing of the sidewalls based on hard mask metal protection.

[0019] Furthermore, in the three-dimensional to two-dimensional patterning step, the exposure and development methods include, but are not limited to, contact exposure, deep ultraviolet lithography, and extreme ultraviolet lithography.

[0020] Furthermore, in the doping and activation steps, the sidewall doping methods include, but are not limited to, tilt-angle rotational ion implantation and plasma doping.

[0021] Furthermore, the bonding method for forming microchannels is selected from at least one of transient liquid phase bonding, eutectic bonding, hot-press bonding, mixed bonding, and anodic bonding.

[0022] Furthermore, a three-dimensional integrated circuit with concave and convex shapes is fabricated on both the upper and lower surfaces of a silicon wafer using a double-sided process, and the circuits on the upper and lower surfaces are connected through through-silicon vias. Three double-sided concave and convex three-dimensional integrated circuits are bonded together through microbumps and bonding rings to form microchannels. Coolant flows horizontally through the microchannels formed by bonding and flows vertically between layers through through-silicon vias.

[0023] Furthermore, several of the aforementioned crystal systems are installed in a cabinet, the bottom of which is equipped with a power supply that powers the entire cabinet and a coolant circulation system that integrates a circulating pump and a heat exchanger; the cabinets are connected to each other via cables or optical fibers.

[0024] According to a second aspect of the embodiments of this application, a digital manufacturing method is provided for a system-on-a-chip including a photocurrent chip based on a vertical micromirror, comprising:

[0025] Digital twin modeling steps: System-level digital modeling of the on-chip system is performed by constructing a multiphysics coupling model, a data-driven model library, and a real-time simulation engine;

[0026] Virtual design and digital simulation steps: Based on the established digital model, artificial neural networks and large models are used to automatically lay out the on-chip network interconnection topology, forming a simulator for on-chip system topology algorithms and performance simulation, generating on-chip system layout, and dynamically adjusting the position of power consumption cells and configuring microchannel heat dissipation;

[0027] Digital manufacturing process control steps: Control the micro-nano fabrication equipment to manufacture using the method described in the first aspect. During the manufacturing process, collect error data in the micro-nano fabrication process in real time, predict the optimal process parameters, and feed them back to the equipment control terminal.

[0028] Automated test feedback steps: Several measurement steps are set in the photolithography, etching, thin film and thermal processing processes. After the node process and its measurement steps are completed, the measurement data is automatically extracted. The simulation results are compared with the measurement data to infer the overall processing quality of the wafer-level system. The results are fed back to the simulator to optimize the process conditions.

[0029] The dynamic correction mechanism involves the following steps: Based on the measurement data, the simulator is dynamically corrected. The influence weight of process parameters on the final performance is analyzed by quantifying the parameters. Highly sensitive parameters are corrected first. An adaptive simulation model is established and corrected by combining physical equations, artificial intelligence networks, large models, and measured parameters to improve the generalization ability of process window prediction. Furthermore, the model in the simulator is updated synchronously based on the measured data.

[0030] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0031] As can be seen from the above embodiments, this application utilizes key technologies such as sidewall smoothing, three-dimensional-two-dimensional patterning, sidewall doping, and sidewall thin film growth of deeply etched silicon structures. By using methods such as high temperature, dry, or wet methods to smooth the sidewalls of deeply etched silicon, a vertical micromirror structure with a roughness of less than 1 nanometer can be formed. Based on this, a three-dimensional-two-dimensional patterning method is used to load various passive and active optical devices onto the microelectromechanical structure, forming an on-chip optical system with adjustable parameters and functions such as computing, sensing, and communication in the horizontal direction. At the same time, PN junctions, CMOS, FinFET (Fin Field-Effect Transistor), and GAAFET (Gate-All-Around Field-Effect Transistor) transistor elements can be fabricated on the top, bottom, and sidewalls of the silicon wafer to realize a concave-convex three-dimensional integrated circuit, thereby achieving sidewall integration of the main optoelectronic components. Compared to traditional methods of fabricating micromirrors, silicon photonic devices, or CMOS (Complementary Metal Oxide Semiconductor) integrated circuits on silicon wafer surfaces, this approach not only fully utilizes the three-dimensional space of silicon wafers to increase integration density, but also, for the optical computing portion, vertical micromirrors can form a fully functional on-chip optical system in the horizontal direction. Light propagation loss in air is extremely low, with losses occurring only at the device interface, and these losses can be significantly reduced by growing optical films, making it suitable for large-scale integration. Simultaneously, the integrated microchannels can effectively dissipate heat from the high-density integrated system. Based on this, addressing the challenges of large scale, complex physical field functions, and long manufacturing processes in wafer-level integrated systems, a digital manufacturing method for photocurrent-based on-chip integrated systems based on on-chip system model construction technology is proposed, comprehensively improving the design and manufacturing efficiency of wafer-level systems.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0034] Figure 1 The diagram shows a method for manufacturing a PN junction diode based on a vertical micromirror according to the present invention, wherein (a-1)-(g-1) are the front views of the wafer in each process, and (a-2)-(g-2) are the top views of the wafer in each process.

[0035] Figure 2 The diagram shows a method for manufacturing a PMOS field-effect transistor based on vertical deep etching of the sidewalls according to the present invention, wherein (a-1)-(h-1) are the front views of the wafer in each process, (a-2)-(h-2) are the top views of the wafer in each process, and (a-3)-(h-3) are the cross-sectional views of the wafer in each process.

[0036] Figure 3 The diagram shown is a cross-sectional schematic of the on-chip integrated structure of the three-dimensional integrated circuit chip and microfluidic unit of the present invention, wherein (a)-(c) are schematic diagrams of the wafer in each process;

[0037] Figure 4 The diagram shows a method for manufacturing a PIN photodetector based on vertical deep etching of the sidewalls according to the present invention, where (a-1)-(f-1) are the front views of the wafer in each process, and (a-2)-(f-2) are the cross-sectional views of the wafer in each process.

[0038] Figure 5 The diagram shows a schematic of a three-dimensional optoelectronic on-chip integrated system based on a vertical micromirror, where (a) is the front view and (b) is the top view.

[0039] Figure 6 The diagram shows a large-scale computing cluster composed of high-density integration of light, electricity, and current.

[0040] Figure 7 The diagram shows the logic of wafer-level chip modeling technology and digital manufacturing methods.

[0041] Reference numerals: 1. Vertical structure; 2. Photosensitive resin; 3. N-type semiconductor region; 4. P-type semiconductor region; 5. PN junction; 6. P+ type semiconductor region; 7. P+ type semiconductor region; 8. Ohmic contact electrode; 9. Silicon dioxide layer; 10. Polysilicon layer; 11. Gate patterned photosensitive resin; 12. Gate polysilicon; 13. First photoresist; 14. Gate oxide layer; 15. Source / drain; 16. Metal silicide; 17. Dielectric layer; 18. Interconnect layer; 19. Top integrated circuit; 20. Bottom integrated circuit; 21. Sidewall integrated circuit; 22. First concave-convex 3D integrated circuit; 23. Second concave-convex 3D integrated circuit; 24. Bonding ring; 25. Microchannel; 26. Through-silicon via; 28. 1. First double-sided concave-convex 3D integrated circuit; 29. ​​Second double-sided concave-convex 3D integrated circuit; 30. Third double-sided concave-convex 3D integrated circuit; 31. Gate pattern photosensitive resin; 32. Second photoresist; 33. N+ layer; 34. Silicon dioxide layer; 35. Intrinsic layer; 36. P+ layer; 37. N+ layer electrode; 38. P+ layer electrode; 39. Laser; 40. Spherical lens; 41. Optical computing unit; 42. Photodetector; 43. 3D integrated circuit unit; 44. 3D optoelectronic crystal on-board integrated system; 45. Integrated circuit chip; 46. Circuit board; 47. Power supply board; 48. Cooling plate; 49. Cooling fan; 50. Cabinet; 51. Power supply; 52. Coolant circulation system; 53. Optical cable; Detailed Implementation

[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0043] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0044] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0045] This application provides a method for on-chip integration of photocurrent chips based on vertical micromirrors, including:

[0046] (1) On a driveable microelectromechanical system structure, based on deep etching, sidewall smoothing and three-dimensional-two-dimensional patterning methods, passive optical devices and active optical devices based on vertical micromirrors are fabricated to form an optical chip;

[0047] The passive optical devices include: mirrors, cylindrical mirrors, beam splitters, prisms, gratings, interferometers, etc., manufactured based on vertical deep etching and sidewall smoothing technology; spherical lenses, apertures, polarizers, waveplates, superlenses, optical waveguides, etc., manufactured based on sidewall two-photon printing and focused ion beam grayscale milling sidewall additive and subtractive manufacturing technology; and optical thin films manufactured based on physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

[0048] The active optical devices include lasers, amplifiers, modulators, detectors, etc., manufactured based on three-dimensional-two-dimensional patterning technology and sidewall doping and epitaxial technology;

[0049] Passive and active optical devices based on vertical micromirrors are fabricated on microelectromechanical system structures such as combs, cantilever beams, and springs that can be driven by electrostatics, piezoelectricity, heat, and magnetism, enabling on-chip adjustment of optical parameters such as focal length, optical path, and phase. Passive and active optical devices based on vertical micromirrors are loaded onto microelectromechanical system structures to form on-chip optical systems with adjustable parameters in the horizontal direction, which have functions such as computing, sensing, and communication.

[0050] In specific implementations, the manufacturing process of passive optical devices may include:

[0051] Deep etching and sidewall smoothing steps: Deeply etch a vertical structure on a silicon wafer, and smooth the sidewalls of the vertical structure to form a vertical micromirror. The sidewall smoothing methods include, but are not limited to, high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, reducing the alternation cycle of etching and protection processes, gas cluster ion beam etching, focused ion beam etching and milling, ion beam etching, and chemical mechanical polishing of the sidewalls based on hard mask metal protection.

[0052] Three-dimensional to two-dimensional patterning steps: Three-dimensional patterning is performed on the sidewall of the vertical micromirror using two-photon printing, and two-dimensional patterning is performed on the area outside the sidewall using spray adhesive or layered coating of multiple layers of photoresist and exposure and development, so as to achieve patterning of the entire wafer. The exposure and development methods include, but are not limited to, contact exposure, deep ultraviolet lithography, and extreme ultraviolet lithography.

[0053] Thin film growth steps: Optical thin films and electrical thin films are grown on the wafer and the sidewall of the vertical micromirror. The optical thin films include antireflection films, anti-reflection films, filter films, polarizing films, and beam splitting films. The electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

[0054] For active optical devices, the manufacturing process may include:

[0055] Deep etching and sidewall smoothing steps: Deeply etch a vertical structure on a silicon wafer, and smooth the sidewalls of the vertical structure to form a vertical micromirror;

[0056] 3D-2D patterning steps: 3D patterning is performed on the sidewalls of the vertical micromirror using two-photon printing, and 2D patterning is performed on the areas outside the sidewalls using spray adhesive or multilayer photoresist coating and exposure and development, so as to achieve patterning of the entire wafer.

[0057] Doping and activation steps: Ion implantation and heat treatment are performed on the sidewall of the vertical micromirror to achieve sidewall doping activation, ohmic contact formation, and metal electrode alloying. The sidewall doping methods include, but are not limited to, tilt angle rotational ion implantation and plasma doping.

[0058] Thin film growth steps: Optical thin films and electrical thin films are grown on the wafer and the sidewall of the vertical micromirror. The optical thin films include antireflection films, anti-reflection films, filter films, polarizing films, and beam splitting films. The electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

[0059] It should be noted that for both passive and active optical devices, the manufacturing process does not simply involve executing each step sequentially once. Instead, some steps are selected and executed multiple times based on actual manufacturing requirements.

[0060] (2) An integrated circuit is fabricated on at least one surface of the top, bottom, and sidewall of a silicon wafer using a three-dimensional-two-dimensional patterning method to obtain a concave-convex three-dimensional integrated circuit, i.e., an electrical chip.

[0061] Specifically, by combining 3D-to-2D patterning methods, the top, bottom, and sidewall surfaces of a silicon wafer can be patterned, enabling the fabrication of transistor devices such as PN junctions, CMOS, FinFETs, and GAAFETs on these surfaces, thus realizing bump-and-recessed 3D integrated circuits. It should be noted that the 3D-to-2D patterning method used here is equivalent to the aforementioned 3D-to-2D patterning steps, and will not be elaborated upon further.

[0062] In practice, a bump-type three-dimensional integrated circuit can be fabricated on one surface of a silicon wafer, or a bump-type three-dimensional integrated circuit can be fabricated on both the upper and lower surfaces of the silicon wafer using a double-sided process, with the circuits on the upper and lower surfaces connected through through-silicon vias.

[0063] (3) Several concave-convex three-dimensional integrated circuits are bonded together through microbumps and bonding rings to form microchannels. The microchannels of multiple concave-convex three-dimensional integrated circuits are connected through vias to form microfluidic units.

[0064] Multiple concave-convex three-dimensional integrated circuits are bonded together to form microchannels through microbumps and bonding rings. The microchannels of multiple concave-convex three-dimensional integrated circuits are connected by through holes to form a complete microfluidic unit. Coolant is used to dissipate heat inside the optoelectronic integrated system through the microfluidic unit. The bonding method for forming microchannels is selected from at least one of transient liquid phase bonding, eutectic bonding, thermo-press bonding, hybrid bonding, and anodic bonding.

[0065] For double-sided concave-convex three-dimensional integrated circuits, three double-sided concave-convex three-dimensional integrated circuits can be bonded together with microbumps and bonding rings to form microchannels. Coolant flows horizontally through the bonded microchannels and vertically between layers through through-silicon vias.

[0066] (4) Perform on-chip integration of the optical chip, electrical chip, and microfluidic unit to form an on-chip system;

[0067] Optical units, electrical chips, and microfluidic units are integrated at high density on a wafer to form a system-on-a-chip (SoC) capable of performing complex functions such as computing, sensing, communication, signal processing, and data storage. Multiple SoCs are connected by cables or optical fibers to form a large-scale computing cluster.

[0068] In practice, several of the aforementioned crystal systems are installed in a cabinet. The bottom of the cabinet is equipped with a power supply that powers the entire cabinet and a coolant circulation system that integrates a circulating pump and a heat exchanger. The cabinets are connected to each other by cables or optical fibers.

[0069] Vertical micromirrors are three-dimensional structures fabricated perpendicular to a single-crystal silicon wafer using a deep etching method. Further smoothing techniques are employed to achieve a roughness of 1 nanometer or even lower on the vertical sidewalls, meeting the requirements for manufacturing optical-grade interfaces. Compared to horizontal micromirrors in traditional Micro-Opto-Electro-Mechanical Systems (MOEMS), vertical micromirrors eliminate the need for additional alignment and micro-assembly steps. They allow for the direct fabrication of vertically oriented optical elements on the silicon wafer, forming a complete on-chip optical path in the horizontal direction. Furthermore, the vertical micromirror structure with a roughness of less than 1 nanometer also provides excellent electrical interfaces. Through the key technologies proposed in this invention, such as the 3D-to-2D patterning step and the sidewall doping step, three-dimensional integrated circuits can be fabricated. Additionally, the trench-type structure created by deep vertical etching also serves as an excellent heat dissipation microchannel embedded within the silicon wafer, enabling heat dissipation for high-density integrated optoelectronic systems.

[0070] The following examples further illustrate the on-chip integration method described above. Examples 1 and 2 respectively illustrate the manufacturing methods of the PN junction diode and PMOS field-effect transistor, the most basic units of a vertically structured three-dimensional integrated circuit. Example 3 illustrates the on-chip integration method of the three-dimensional integrated circuit chip and microfluidic unit of the present invention. Example 4 uses a PIN photodetector as an example to illustrate the manufacturing method of on-chip optical elements based on vertical micromirrors. The PIN photodetector is not only an important active optical element but also a link between photoelectric conversion and integration. Based on this, Example 5 illustrates a schematic diagram of a three-dimensional optoelectronic on-chip integrated system based on vertical micromirrors. Examples 6 and 7 illustrate the structure, design method, and digital manufacturing method of high-density integration of light, electricity, and current to form a large-scale computing cluster. This forms a complete and innovative methodological system from underlying component structure, system integration, large-scale clustering, design methods, and digital manufacturing.

[0071] Example 1

[0072] A PN junction is a semiconductor device structure formed by combining P-type and N-type semiconductors. It is not only the most basic unit in integrated circuits but also the fundamental structural unit of many active optical devices. This embodiment takes the PN junction, the most basic unit in integrated circuits, as an example to provide a method for manufacturing integrated circuit chips based on vertical micromirrors. However, the application scenarios of this invention are not limited to the example given, and can also be applied to the manufacturing scenarios of other integrated circuit devices with vertical sidewalls.

[0073] As shown in Figure 1, the fabrication method of the PN junction based on a vertical micromirror includes the following steps:

[0074] S11: Deeply etch vertical structure 1 on a single-crystal silicon wafer and smooth the sidewalls to create a good optical plane and an electrical vertical plane, i.e., a vertical micromirror.

[0075] In single-crystal silicon wafers ( Figure 1 The upper surfaces of (a-1) and (a-2) were etched with a deep etching process to form a vertical structure 1 with a depth greater than 100 micrometers, a verticality better than 90°±0.3°, and an initial sidewall roughness better than 50 nanometers.

[0076] Sidewall smoothing of the vertical structure can be achieved through methods including, but not limited to, high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, reducing the alternation cycle between etching and protection processes, gas cluster ion beam etching, focused ion beam etching and milling, ion beam etching, and chemical mechanical polishing of the sidewalls based on hard mask metal protection. As an embodiment of the invention, it is preferable to use a solution of less than 5 wt.% low-concentration potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), 10 wt.%~30 wt.% isopropanol, and deionized water to etch the aforementioned deep-etched silicon vias, resulting in a vertical structure 1 with a sidewall roughness of less than 1 nanometer, serving as a good optical and electrical vertical plane, i.e., a vertical micromirror. As another embodiment of the invention, it is preferable to use one or more of the following—one or more low-flow sulfur hexafluoride (SF6), argon plasma, oxygen plasma, and xenon difluoride (XeF2)—for post-etching of the vertical structure, with the gas flow rate generally below 30 sccm.

[0077] S12: A thin silicon dioxide layer is deposited on the vertical micromirror as a protective layer for ion implantation; an N-type semiconductor region 3 is lithographically patterned on the surface of the vertical micromirror using a two-photon printer (two-photon grayscale lithography) with photosensitive resin 2 as a mask; N-type ion implantation is performed into the N-type semiconductor region 3. Figure 1 (b-1) and (b-2) in the middle.

[0078] S13: A P-type semiconductor region 4 is photolithographically patterned on the surface of a vertical micromirror using a two-photon printer with photosensitive resin 2 as a mask; P-type ion implantation is performed on the P-type semiconductor region 4; the photosensitive resin 2 is removed, and annealing is performed to activate the implantation and form a PN junction 5. Sidewall doping methods include, but are not limited to, tilt-angle rotational ion implantation, plasma doping (PLAD), etc. Figure 1 (c-1) and (c-2) in the middle.

[0079] S14: First, a P+ type semiconductor region 6 is photolithographically patterned on the surface of a vertical micromirror using a two-photon printer with photosensitive resin 2 as a mask; then, P+ type ion implantation is performed on the P+ type semiconductor region 6. Figure 1(d-1) and (d-2) in the middle.

[0080] S15: First, an N+ type semiconductor region 7 is photolithographically patterned on the surface of a vertical micromirror using a two-photon printer with photosensitive resin 2 as a mask; then, N+ type ion implantation is performed on the N+ type semiconductor region 7; finally, the photosensitive resin 2 is removed, and annealing implantation is performed to activate and form heavily doped regions N+ and P+ as ohmic contacts. Figure 1 (e-1) and (e-2) in the middle.

[0081] S16: Using a two-photon printer, photolithography is performed on the surface of the vertical micromirror using photosensitive resin 2 as a mask, simultaneously exposing the P+ type semiconductor region 6 and the N+ type semiconductor region 7. Figure 1 (f-1) and (f-2) in the middle.

[0082] S17: First, a metal electrode layer is deposited on the surface of the vertical micromirror; then, excess metal is removed using a lift-off process, leaving only the metal electrode layers of the P+ type semiconductor region 6 and the N+ type semiconductor region 7; finally, the metal electrode layers are alloyed to form the ohmic contact electrode 8. Figure 1 (g-1) and (g-2) in the middle.

[0083] Example 2

[0084] Field-effect transistors (FETs) are the basic building blocks of modern integrated circuit chips. MOS FETs are also known as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). MOSFETs can be divided into NMOS and PMOS. NMOS refers to the N-channel type, with N+ source / drain regions formed on a P-type substrate, and conducts when a positive voltage is applied to the gate. PMOS refers to the P-channel type, with P+ source / drain regions formed on an N-type substrate, and conducts when a negative voltage is applied to the gate. NMOS and PMOS can form Complementary Metal Oxide Semiconductor (CMOS), which is the basic building block of digital integrated circuits. This embodiment uses PMOS as an example to illustrate how to fabricate integrated circuit chips on vertical sidewalls. This invention provides a method for manufacturing integrated circuit chips based on vertical micromirrors. However, the application scenarios of this invention are not limited to the PMOS example mentioned above. It can also be applied to the manufacturing scenarios of other integrated circuit devices with vertical sidewalls, such as NMOS, Fin Field-Effect Transistor (FinFET), and Gate-all-around Field-Effect Transistor (GAAFET).

[0085] like Figure 2 As shown, the fabrication method of PMOS based on vertical micromirrors includes the following steps:

[0086] S21: Deeply etch vertical structure 1 on a single-crystal silicon wafer with an N-type substrate and smooth the sidewalls to create a good optical plane and an electrical vertical plane, i.e., a vertical micromirror.

[0087] First, on a single-crystal silicon wafer with an N-type substrate ( Figure 2 The upper surfaces of (a-1) and (a-2) are etched using a deep etching process to create vertical structures with a depth greater than 100 micrometers, a perpendicularity better than 90°±0.3°, and an initial sidewall roughness better than 50 nanometers. Then, the vertical structures are sidewall smoothed to obtain vertical structure 1 with a sidewall roughness less than 1 nm, serving as a good optical and electrical vertical plane.

[0088] S22: First, a silicon dioxide layer 9 is deposited on the vertical micromirror. Figure 2 In (b-1) and (b-2) of the above, the methods include, but are not limited to, chemical vapor deposition (CVD), dry oxidation, wet oxidation, atomic layer deposition (ALD), etc.; then, the polycrystalline silicon layer 10 is preferably deposited using low-pressure chemical vapor deposition (LPCVD).

[0089] S23: Using a two-photon printer (two-photon grayscale lithography), the shape of the gate is photolithographically etched on the surface of the silicon dioxide layer 9 and the polysilicon layer 10 of the vertical micromirror, that is, the gate pattern is protected by a photosensitive resin 11 of the gate pattern printed by two-photon. Figure 2 (c-1) and (c-2) in the middle.

[0090] S24: First, using the gate pattern photosensitive resin 11 as a mask, the polysilicon layer is removed to form the gate polysilicon 12; then, using a spray coating method, the first photoresist 13 is applied to the wafer where the vertical micromirror is located, so that only the process surface of the vertical micromirror is exposed, while the other surfaces are protected by the first photoresist 13. Figure 2 (d-1) and (d-2) in the middle.

[0091] It's important to note that two-photon printing typically uses negative photoresist, meaning the exposed pattern remains after development. This is used to pattern the sidewalls of vertical structures with depths of hundreds of micrometers, representing a three-dimensional patterning process. Spray printing, on the other hand, uses either positive or negative photoresist to pattern areas outside the vertical structure. Since spray printing is usually thicker, this method is suitable for situations where linewidth accuracy requirements are not high. Alternatively, a multi-layer photoresist coating method can be used to pattern areas outside the vertical structure: a low-viscosity negative photoresist is used to cover the stepped areas, forming a protective layer (approximately 1-2 micrometers thick), and then positive photoresist is layered on top for sub-micrometer patterning of the main body areas. Exposure methods include, but are not limited to, contact exposure, deep ultraviolet (DUV) lithography, and extreme ultraviolet (EUV) lithography. This method is suitable for situations requiring high linewidth accuracy. However, both spray printing and multi-layer photoresist coating are two-dimensional patterning methods. In this way, the two-photon printing method for three-dimensional patterning of sidewalls and the spraying or layering of multiple layers of photoresist for two-dimensional patterning of structures other than sidewalls can work together to achieve patterning of the entire wafer.

[0092] S25: First, buffered hydrofluoric acid (BHF) is preferably used as an etching solution to remove the silicon dioxide layer 9 outside the gate pattern; then, the first photoresist 13 and the gate pattern photosensitive resin 11 are removed to obtain the gate oxide layer 14. Figure 2 (e-1) and (e-2) in the middle.

[0093] S26: First, the source / drain regions are patterned using the aforementioned three-dimensional-two-dimensional patterning method; then, P+ doping is performed to form source / drain 15 ( Figure 2 (f-1) and (f-2) in the text. Sidewall doping methods include, but are not limited to, tilt-angle rotational ion implantation, plasma doping (PLAD), etc. Finally, annealing is performed after resist removal to achieve implantation activation.

[0094] S27: First, the ohmic contact region is patterned using the aforementioned three-dimensional-two-dimensional patterning method; then, physical vapor deposition (PVD) is performed on metals such as titanium, nickel, cobalt, and platinum; finally, annealing is used to form a metal silicide ohmic contact 16. Figure 2 (g-1) and (g-2) in the middle.

[0095] S28: First, a silicon dioxide dielectric layer 17 is deposited; then, the dielectric layer 17 is patterned using the aforementioned three-dimensional-two-dimensional patterning method, and the dielectric layer 17 is etched to expose the contact holes; next, a PVD seed layer is applied, and copper is electroplated to fill the contact holes; finally, preferably, the electroplated layer is etched using an ion beam etching (IBE) method to form an interconnect layer 18 and alloyed. Figure 2 (h-1) and (h-2) in the middle.

[0096] Example 3

[0097] By using the combined three-dimensional-two-dimensional patterning method described in Example 2, the top, bottom, and sidewall surfaces of a silicon wafer can be patterned, thereby enabling the fabrication of integrated circuit 19 on the top of the silicon wafer, integrated circuit 20 on the bottom, and integrated circuit 21 on the sidewalls, forming a bump-concave three-dimensional integrated circuit. Figure 3 (a)). Compared to traditional methods of manufacturing integrated circuits only on the wafer surface, the method described in this invention significantly increases the process area, thereby enabling the integration of more MOSFETs and achieving stronger performance.

[0098] Furthermore, the two concave-convex three-dimensional integrated circuits 22 and 23 can be bonded together using microbumps and bonding rings 24 to form microchannels 25, allowing the coolant to dissipate heat from the system composed of 22 and 23. Figure 3 (b) in the middle.

[0099] Furthermore, a double-sided process can be used to fabricate three-dimensional integrated circuits with concave and convex shapes on both the top and bottom surfaces of a silicon wafer. The circuits on the top and bottom surfaces are connected through through-silicon vias (TSVs) 26. Three double-sided concave and convex three-dimensional integrated circuits 28, 29, and 30 are bonded together through microbumps and bonding rings 24 to form microchannels 25. Coolant can flow vertically between layers through the vertical microchannel vias 27 fabricated (deeply etched) on the wafer, and flow horizontally through the bonded microchannels 25, thereby dissipating heat from the entire system. Figure 3 (c) in the middle.

[0100] Example 4

[0101] Example 1 describes a method for fabricating a PN junction diode on the sidewall of a silicon vertically etched structure. The PN junction diode is not only the most basic unit in integrated circuits but also exhibits photoelectric effects and can be used as a photodetector. To achieve photoelectric conversion and integration in the near-infrared band, Example 4 describes a method for fabricating a PIN detector on the sidewall of a silicon vertically etched structure. However, the application scenarios of this invention are not limited to the examples given; it can also be applied to the fabrication of other optical devices with vertical sidewall structures.

[0102] S41: Deeply etch vertical structure 1 on a single-crystal silicon wafer and smooth the sidewalls to create a good optical plane and an electrical vertical plane, i.e., a vertical micromirror.

[0103] First, on a single-crystal silicon wafer ( Figure 4 The upper surfaces of (a-1) and (a-2) are etched using a deep etching process to create vertical structures with a depth greater than 100 micrometers, a perpendicularity better than 90°±0.3°, and an initial sidewall roughness better than 50 nanometers. Then, the vertical structures are sidewall smoothed to obtain vertical micromirrors with a sidewall roughness of less than 1 nm, serving as both good optical and electrical vertical planes.

[0104] S42: Using a two-photon printer (two-photon grayscale lithography), the N+ region pattern is photolithographically patterned on the sidewall surface of the vertical micromirror, i.e., the gate pattern is protected by the photosensitive resin 31 of the two-photon printed gate pattern. Then, using a spray coating method, a second photoresist 32 is applied to the wafer containing the vertical micromirror, and the vertical structure is exposed and developed. Finally, N+ doping is performed to form an N+ layer 33, and the second photoresist 32 is removed. Figure 4 (b-1) and (b-2) in the middle.

[0105] S43: First, a silicon dioxide layer 34 is preferably deposited using PECVD. Then, a combined 3D-2D patterning method is used to pattern the P+ region. Finally, the silicon dioxide layer on the surface of the P+ region is removed using hydrofluoric acid, followed by the removal of the photoresist. Figure 4 (c-1) and (c-2) in the middle.

[0106] S44: First, an intrinsic layer 35 and a P+ layer 36 are sequentially epitaxially grown on the surface of the N+ layer 33. The intrinsic layer 35 is preferably epitaxial silicon or germanium. Then, the silicon dioxide layer and any remaining epitaxial growth on the surface are removed. Figure 4 (d-1) and (d-2) in the middle.

[0107] S45: Combine three-dimensional and two-dimensional graphics methods to graphics the electrode region ( Figure 4 (e-1) and (e-2) in the middle.

[0108] S46: First, the electrode region is patterned using a combined 3D-2D patterning method. Then, N+ layer electrodes 37 and P+ layer electrodes 38 are grown. The preferred electrode layer material is ITO (indium tin oxide). Finally, the PIN detector with sidewalls is formed by stripping and removing the adhesive. Figure 4 (f-1) and (f-2) in the middle.

[0109] Example 5

[0110] In the aforementioned embodiments 1-4, this invention proposes a method for fabricating optoelectronic devices such as PN junctions, PIN detectors, and MOSFETs on vertical sidewalls. Because this invention solves key technologies such as sidewall smoothing, sidewall patterning, sidewall doping, and sidewall thin film growth in silicon vertically etched structures, it can achieve sidewall integration of major optoelectronic components. Its advantages are that, compared to methods of fabricating micromirrors, silicon photonic devices, or CMOS integrated circuits on silicon wafer surfaces, it not only fully utilizes the three-dimensional space of the silicon wafer to increase integration density, but also, for the optical computing part, vertical micromirrors can form a fully functional on-chip optical system in the horizontal direction. Light propagation loss in air is extremely low, with losses only occurring at the component interface, and these losses can be significantly reduced by growing optical films, making it suitable for large-scale integration.

[0111] Figure 5 The diagram illustrates a three-dimensional optoelectronic integrated system based on a vertical micromirror. The horizontally oriented laser emitted by the edge-emitting laser 39 is collimated by a spherical lens 40, manufactured using two-photon printing additive manufacturing or focused ion beam milling on its vertical sidewalls and coated with an anti-reflection film. The laser light is then input to an optical computing unit 41 composed of a Mach-Zehnder interferometer based on the vertical micromirror. The output light from the optical calculation illuminates a photodetector 42 based on the vertical micromirror, converting the optical signal into an electrical signal, which is then input to the three-dimensional integrated circuit unit 43 for further signal processing and data calculation. To achieve higher integration density and better heat dissipation, the double-sided process and technologies from Example 3, such as through-silicon vias, microbumps, bonding rings, and bonding to form microchannels, can be applied to the three-dimensional optoelectronic integrated system based on the vertical micromirror to meet the needs of more application scenarios.

[0112] Example 6

[0113] Three-dimensional optoelectronic on-chip integrated systems based on vertical micromirrors, supported by power supply and heat dissipation systems, can form computing clusters with complex functions, such as... Figure 6 As shown, a three-dimensional optoelectronic on-chip integrated system 44 based on vertical micromirrors is integrated and packaged with other integrated circuit chips 45 on a circuit board 46. The bottom of the circuit board 46 is connected to a power supply board 47 to provide power to the on-chip system 44. Microchannel cooling fins 48 are located at the top and bottom of the on-chip system 44, and inside and at the bottom of the power supply board 47 to dissipate heat from the high-density integrated system and ensure stable operation. Cooling fans 49 are installed on the outside of the microchannel cooling fins 48 to further enhance the system's heat dissipation capacity. Multiple such on-chip system units are installed in a cabinet 50. The bottom of the cabinet houses a power supply 51 that powers the entire cabinet and a coolant circulation system 52 integrating a circulation pump and heat exchanger. Multiple such cabinets 50 are connected to each other via cables or optical fibers 53 to form a computing cluster with complex functions.

[0114] Example 7

[0115] The digital manufacturing method for photocurrent-based on-chip integrated systems proposed in this invention is a digital tool covering the entire process of design, manufacturing, and testing. By constructing a wafer-level digital twin model, it achieves closed-loop optimization and yield improvement throughout the entire lifecycle of integrated circuit manufacturing. For example... Figure 7 As shown, digital manufacturing methods mainly include several aspects such as digital twin modeling, virtual design and digital simulation, digital manufacturing process control, automated testing feedback, and dynamic correction mechanisms.

[0116] S71: Digital twin modeling steps: System-level digital modeling of the on-chip system is performed by constructing a multiphysics coupling model, a data-driven model library, and a real-time simulation engine;

[0117] The multiphysics coupling model includes: an optical / electromagnetic model, which uses FDTD (finite-difference time-domain) simulation to simulate interconnect crosstalk and signal integrity; and an electrical / thermodynamic model, which uses finite element analysis to predict the thermal gradient, TSV stress distribution, parasitic parameters, and microchannel heat dissipation capacity of the 3D stacked chip.

[0118] The data-driven model library includes: a process parameter library for storing historical data from equipment such as lithography, etching, and deposition; and a defect pattern library based on a classification model trained on a large artificial intelligence model for identifying defects on the wafer surface during manufacturing, such as the spectral features of particle contamination and overlay deviation.

[0119] Real-time simulation engine: Real-time simulation is achieved through hardware acceleration and cloud collaboration. Hardware acceleration uses GPU clusters to achieve parallel simulation of wafer-level system functions and performance. Cloud collaboration uses 5G networks to synchronize data from multiple factories with low latency and multiple tasks, supporting production line linkage.

[0120] S72: Virtual Design and Digital Simulation Steps: Based on the mathematical model established by S71, artificial neural networks and large models are used to automatically lay out the on-chip network interconnection topology, forming a simulator for on-chip system topology algorithms and performance simulation, generating on-chip system layout, and dynamically adjusting the position of power consumption cells and configuring microchannel heat dissipation.

[0121] (1) Simulator-driven intelligent layout: Using artificial neural networks and large models, the on-chip network interconnection topology of the photocurrent on-chip integrated system is automatically laid out, and then the wiring is automatically performed to generate the on-chip system layout.

[0122] (2) Optical-electrical-thermal-fluidic joint simulation: The position of the power consumption unit is dynamically adjusted and microfluidic heat dissipation is configured based on the simulation results.

[0123] S73: Digital manufacturing process control steps: Based on the layout generated by the design and simulation results in S72, the micro-nano fabrication equipment is controlled to use the on-chip integration method of the above-mentioned photocurrent chip based on vertical micromirrors for manufacturing. During the manufacturing process, error data in the micro-nano fabrication process is collected in real time, the optimal process parameters are predicted and fed back to the equipment control terminal.

[0124] It collects error data in real time from photolithography, etching, thin film and heat treatment processes in micro and nano fabrication, predicts the optimal process parameters and feeds them back to the equipment control terminal.

[0125] S74: Automated Test Feedback Steps: Multiple measurement steps are set up in the photolithography, etching, thin film, and thermal processing processes, including but not limited to thin film thickness measurement, sheet resistance measurement, etching depth measurement, and structural morphology measurement. Measurement data is automatically extracted after each node process and its measurement steps are completed. The simulation results are compared with automated measurement data such as electron microscope images, sheet resistance, and thin film thickness to infer the overall processing quality of the wafer-level system. The results are fed back to the simulator, making the simulator closer to the actual situation from the ideal model. An incremental learning framework is deployed to continuously train the defect classification model using production line data, assisting in the analysis and optimization of process conditions.

[0126] S75: Dynamic Correction Mechanism Steps: Based on the automated test results in S74, the simulator used for on-chip system topology algorithm and performance simulation in S72 is dynamically corrected. By analyzing the influence weight of process parameters on the final performance, highly sensitive parameters are corrected first. Adaptive simulation models are established and corrected by combining physical equations, artificial neural networks and large models, and measured parameters to improve the generalization ability of process window prediction. Furthermore, the model in the on-chip system simulator is updated synchronously based on measured data.

[0127] (1) Error source tracing and weight allocation: The influence weight of process parameters (such as etching rate, deposition temperature, etching rate, etc.) on the final performance is analyzed by quantifying the factors, and highly sensitive parameters are corrected first. An error propagation chain is established from the atomic level (ALD film growth) to the system level (power delay product) to locate the bottleneck link.

[0128] (2) Adaptive simulation model: Combine physical equations, artificial intelligence networks and large models, and measured parameters to establish and correct adaptive simulation models to improve the generalization ability of process window prediction;

[0129] (3) Digital twin mirror update: After each batch of production, the model in the simulator used for on-chip system topology algorithm and performance simulation is updated synchronously based on the measured data.

[0130] In summary, this invention can form a vertical micromirror structure with a roughness of less than 1 nanometer by smoothing the sidewalls of deeply etched silicon using methods such as high temperature, dry, or wet etching. Based on this, a three-dimensional-two-dimensional patterning method is used to load various passive and active optical devices onto the microelectromechanical structure, forming an on-chip optical system with adjustable parameters and functions such as computing, sensing, and communication in the horizontal direction. This on-chip optical system has only slight optical signal loss at the device interface, and the loss during propagation in air is extremely low, making it suitable for large-scale integration. At the same time, PN junctions, CMOS, FinFET (Fin Field-Effect Transistor), and GAAFET (Gate-All-Around Field-Effect Transistor) transistors can be fabricated on the top, bottom, and sidewalls of the silicon wafer to realize concave-convex three-dimensional integrated circuits and improve integration density. By integrating optical units, electrical chips, and microfluidic units on a wafer at high density, a wafer-level system and a large-scale computing cluster with complex processing capabilities such as computing, sensing, communication, signal processing, and data storage are realized. Furthermore, a wafer-level chip modeling technology and digital manufacturing method are proposed to comprehensively improve the design and manufacturing efficiency of wafer-level systems.

[0131] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0132] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for on-chip integration of a photocurrent chip based on a vertical micromirror, characterized in that, include: On a driveable microelectromechanical system structure, passive and active optical devices based on vertical micromirrors are fabricated using deep etching, sidewall smoothing, and three-dimensional-two-dimensional patterning methods to form an optical chip. An integrated circuit is fabricated on at least one surface of the top, bottom, or sidewall of a silicon wafer using a three-dimensional-two-dimensional patterning method to obtain a bump-concave three-dimensional integrated circuit, i.e., an electrical chip. Several concave-convex three-dimensional integrated circuits are bonded together using microbumps and bonding rings to form microchannels. These microchannels are then connected by vias to form a microfluidic unit. The optical chip, electrical chip, and microfluidic unit are integrated on-chip to form a system-on-chip including a photocurrent chip based on a vertical micromirror.

2. The method according to claim 1, characterized in that, The manufacturing process of passive optical devices includes: Deep etching and sidewall smoothing steps: Deeply etch a vertical structure on a silicon wafer, and smooth the sidewalls of the vertical structure to form a vertical micromirror; Three-dimensional to two-dimensional patterning steps: Three-dimensional patterning is performed on the sidewall of the vertical micromirror using two-photon printing, and two-dimensional patterning is performed on the area outside the sidewall using spray adhesive or layered coating of multiple layers of photoresist and exposure and development, so as to achieve patterning of the entire wafer. Thin film growth steps: Optical thin films and electrical thin films are grown on the wafer and the sidewall of the vertical micromirror. The optical thin films include antireflection films, anti-reflection films, filter films, polarizing films, and beam splitting films. The electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

3. The method according to claim 1, characterized in that, The manufacturing process of active optical devices includes: Deep etching and sidewall smoothing steps: Deeply etch a vertical structure on a silicon wafer, and smooth the sidewalls of the vertical structure to form a vertical micromirror; Three-dimensional to two-dimensional patterning steps: Three-dimensional patterning is performed on the sidewall of the vertical micromirror using two-photon printing, and two-dimensional patterning is performed on the area outside the sidewall using spray adhesive or layered coating of multiple layers of photoresist and exposure and development, so as to achieve patterning of the entire wafer. Doping and activation steps: Ion implantation and heat treatment are performed on the sidewall of the vertical micromirror to achieve sidewall doping activation, ohmic contact formation, and metal electrode alloying. Thin film growth steps: Optical thin films and electrical thin films are grown on the wafer and the sidewall of the vertical micromirror. The optical thin films include antireflection films, anti-reflection films, filter films, polarizing films, and beam splitting films. The electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

4. The method according to claim 2 or 3, characterized in that, In the deep etching and sidewall smoothing steps, sidewall smoothing methods include, but are not limited to, high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, reducing the alternation cycle of etching and protection processes, gas cluster ion beam etching, focused ion beam etching milling, ion beam etching, and chemical mechanical polishing of the sidewalls based on hard mask metal protection.

5. The method according to claim 2 or 3, characterized in that, In the 3D-2D patterning step, the exposure and development methods include, but are not limited to, contact exposure, deep ultraviolet lithography, and extreme ultraviolet lithography.

6. The method according to claim 2 or 3, characterized in that, In the doping and activation steps, the sidewall doping methods include, but are not limited to, tilt-angle rotational ion implantation and plasma doping.

7. The method according to claim 1, characterized in that, The bonding method for forming microchannels is selected from at least one of transient liquid phase bonding, eutectic bonding, hot-pressing bonding, mixed bonding, and anodic bonding.

8. The method according to claim 1, characterized in that, Double-sided three-dimensional integrated circuits with concave and convex shapes are fabricated on both the upper and lower surfaces of a silicon wafer using a double-sided process. The circuits on the upper and lower surfaces are connected through through-silicon vias. Three double-sided concave and convex three-dimensional integrated circuits are bonded together with microbumps and bonding rings to form microchannels. Coolant flows horizontally through the microchannels formed by bonding and flows vertically between layers through through-silicon vias.

9. The method according to claim 1, characterized in that, Several of the aforementioned crystal systems are installed in a cabinet, the bottom of which is equipped with a power supply that powers the entire cabinet and a coolant circulation system that integrates a circulation pump and a heat exchanger; the cabinets are connected to each other by cables or optical fibers.

10. A digital manufacturing method for a system-on-a-chip including a photocurrent chip based on a vertical micromirror, characterized in that, include: Digital twin modeling steps: System-level digital modeling of the on-chip system is performed by constructing a multiphysics coupling model, a data-driven model library, and a real-time simulation engine; Virtual design and digital simulation steps: Based on the established digital model, artificial neural networks and large models are used to automatically lay out the on-chip network interconnection topology, forming a simulator for on-chip system topology algorithms and performance simulation, generating on-chip system layout, and dynamically adjusting the position of power consumption cells and configuring microchannel heat dissipation; Digital manufacturing process control steps: Control the micro-nano fabrication equipment to manufacture using the method described in claim 1. During the manufacturing process, collect error data in the micro-nano fabrication process in real time, predict the optimal process parameters, and feed them back to the equipment control terminal. Automated test feedback steps: Several measurement steps are set in the photolithography, etching, thin film and thermal processing processes. After the node process and its measurement steps are completed, the measurement data is automatically extracted. The simulation results are compared with the measurement data to infer the overall processing quality of the wafer-level system. The results are fed back to the simulator to optimize the process conditions. The dynamic correction mechanism involves the following steps: Based on the measurement data, the simulator is dynamically corrected. The influence weight of process parameters on the final performance is analyzed by quantifying the parameters. Highly sensitive parameters are corrected first. An adaptive simulation model is established and corrected by combining physical equations, artificial intelligence networks, large models, and measured parameters to improve the generalization ability of process window prediction. Furthermore, the model in the simulator is updated synchronously based on the measured data.

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