Electronic device

Abstract

The invention discloses an electronic device which is characterized by comprising a substrate, a first conductive layer, an electronic unit, a sensing unit and a sensing unit driving circuit. The first conductive layer is arranged on the substrate and comprises a first grid electrode and a line segment, and the line segment is connected with the first grid electrode. The electronic unit and the sensing unit are respectively arranged on the substrate. The sensing unit driving circuit is arranged on the substrate and is electrically connected to the electronic unit and the sensing unit. The sensing unit driving circuit comprises a first transistor, the first transistor is provided with a first grid electrode, and the outline of the first grid electrode is different from the outline of the line segment.

Description

Technical Field

[0001] The present invention relates to an electronic device, in particular to an electronic device with display and sensing functions. Background Art

[0002] Some electronic devices require both display and sensing functions. However, current display and sensing circuits are separate circuits, which take up a large amount of space and result in low space utilization. As a result, electronic devices currently on the market cannot achieve both high-resolution display and high-precision sensing functions.

[0003] Therefore, a novel electronic device is needed to improve the above problems. Summary of the Invention

[0004] The present invention provides an electronic device comprising a substrate, a first conductive layer, an electronic unit, a sensing unit, and a sensing unit driving circuit. The first conductive layer is disposed on the substrate and comprises a first gate and a line segment connected to the first gate. The electronic unit and the sensing unit are disposed on the substrate, respectively. The sensing unit driving circuit is disposed on the substrate and electrically connected to the electronic unit and the sensing unit. The sensing unit driving circuit comprises a first transistor having a first gate, wherein the contour of the first gate is different from the contour of the line segment. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A schematic diagram showing an electronic device according to an embodiment of the present invention is shown;

[0006] Figure 2 A schematic diagram showing a corner area of ​​an electronic device according to an embodiment of the present invention;

[0007] Figure 3 A schematic diagram showing a basic driving circuit of an electronic device according to an embodiment of the present invention;

[0008] Figure 4 A detailed circuit diagram of an electronic device according to an embodiment of the present invention is shown;

[0009] Figure 5 The present invention and Figure 4 The signal timing diagram corresponding to the circuit structure;

[0010] Figure 6 A schematic diagram showing a wiring configuration of an electronic device according to an embodiment of the present invention;

[0011] Figure 7 A schematic diagram showing a detailed circuit structure of an electronic device according to another embodiment of the present invention;

[0012] Figure 8The present invention and Figure 7 The signal timing diagram corresponding to the circuit structure;

[0013] Figure 9 A schematic diagram showing a wiring arrangement of a reset transistor of an electronic device according to an embodiment of the present invention;

[0014] Figure 10 A schematic diagram showing a wiring arrangement of a reset transistor of an electronic device according to another embodiment of the present invention;

[0015] Figure 11 A schematic diagram showing a wiring arrangement of a reset transistor of an electronic device according to another embodiment of the present invention;

[0016] Figure 12 A schematic diagram showing a wiring arrangement of a reset transistor of an electronic device according to another embodiment of the present invention;

[0017] Figure 13 shows a cross-sectional view of a reset transistor according to an embodiment of the present invention;

[0018] Figure 14 shows a cross-sectional view of a reset transistor according to another embodiment of the present invention;

[0019] Figure 15 shows a cross-sectional view of a reset transistor according to another embodiment of the present invention;

[0020] Figure 16 A schematic diagram showing a circuit structure of an electronic device according to another embodiment of the present invention;

[0021] Figure 17 A schematic diagram showing a circuit structure of an electronic device according to another embodiment of the present invention.

[0022] Reference numerals:

[0023] electronic device 1;

[0024] Active area AA;

[0025] Main Area A;

[0026] peripheral area B;

[0027] Corner area C;

[0028] peripheral area PA;

[0029] lateral zone Z;

[0030] substrate 10;

[0031] Electronic unit 25;

[0032] Sensing unit 35;

[0033] Electronic unit drive circuit 20;

[0034] Sensing unit driving circuit 30;

[0035] Drive transistor T1;

[0036] Data is written into transistor T2;

[0037] Reset transistor T3;

[0038] Transistors T4 and T5;

[0039] Switching transistor T6;

[0040] Driving transistor ST1;

[0041] Reset transistor ST2;

[0042] Data transmission transistor ST3;

[0043] First ends a1-a8, as1-as3, 67a;

[0044] Second ends b1-b8, bs1-bs3, 67b;

[0045] Control terminals c1 to c8, cs1 to cs3;

[0046] Drive units SN(N), SN_I(NX), SN_I(N), SN(N+Y), SN_I(N+Y), EM(N);

[0047] Data line DL;

[0048] Data reading line RL;

[0049] Transistors T7, T8, SW, CKDR, MD, MR, SW1, SW2, CKI1, CKI2, CKI3, CKIS1, CKIS2, CKIS3, CKL1, CKL2, CKL3, CKLS1, CKLS2, CKLS3;

[0050] Display frame TA;

[0051] Sensing frame TB;

[0052] Sub-periods ta1-ta3, tb1-tb3;

[0053] Open period t11 to t15;

[0054] a first conductive layer 40;

[0055] sub-conductive layers 41, 51, 621, 622, 42, 52, 43, 53;

[0056] Line segments 41a, 42a, 52a, 43a, 53a;

[0057] Gates 41b, 51b, 42b, 52b, 43b, 53b;

[0058] a second conductive layer 50;

[0059] First metal layer 81;

[0060] widths L2-1, Lline, L2-2, W2-1, L1-1, L1-2, W1-1; semiconductor layer 70;

[0061] First semiconductor 71;

[0062] one end 71a, 63a, 72a;

[0063] the other end 71b, 63b, 72b;

[0064] third end 67c;

[0065] extension portion 72c;

[0066] middle part 67d;

[0067] a third conductive layer 61;

[0068] a sixth metal layer 86;

[0069] A third metal layer 83;

[0070] a fourth metal layer 84;

[0071] a fourth conductive layer 62;

[0072] a fifth conductive layer 63;

[0073] seventh metal layer 87;

[0074] an eighth metal layer 88;

[0075] a sixth conductive layer 64;

[0076] First metal layer 81;

[0077] a second semiconductor 72;

[0078] a fifth metal layer 85;

[0079] a seventh conductive layer 65;

[0080] an eighth conductive layer 66;

[0081] a ninth conductive layer 67;

[0082] Channel lengths LT1, LST1, LST3, L2-1, L3-1;

[0083] Channel width WST3, W2-1, W3-1;

[0084] Transistors ST21, ST22;

[0085] Pattern portion 70p;

[0086] Insulation layers 91-99;

[0087] Drain electrodes 101, 111;

[0088] Source electrodes 102, 112;

[0089] First sublayer 711;

[0090] Second sublayer 712;

[0091] Oxide auxiliary semiconductor layers 713 and 714;

[0092] Thickness d1, d2;

[0093] Gate lines SL, SLI, SLL;

[0094] Integrated signal line DR;

[0095] Integrated control-side DRM;

[0096] Multiplexers MI1, MI2, ML1, ML2. DETAILED DESCRIPTION

[0097] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0098] Throughout the present specification and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will appreciate that sensing device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, words such as "including," "comprising," and "comprising" are open-ended and should be interpreted as meaning "including, but not limited to..."

[0099] The terms "about," "substantially," or "approximately" are generally interpreted as within 10% of a given value or range, or within 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0100] The use of ordinal numbers such as "first" and "second" in the specification and claims to modify an element does not, by itself, imply or indicate any prior ordinal number of the element(s), nor does it indicate the order of one element relative to another, or the order of manufacturing methods. Such ordinal numbers are used solely to clearly distinguish one element from another with the same name. The claims and the specification may not use the same terminology; thus, the first element in the specification may be the second element in the claim.

[0101] In the present invention, the phrases “a given range is from a first value to a second value” and “a given range falls within the range from a first value to a second value” mean that the given range includes the first value, the second value and other values ​​therebetween.

[0102] Furthermore, the control method disclosed in the present invention can be used on an electronic device or a vehicle equipped with an electronic device, wherein the electronic device may include, but is not limited to, a vehicle device, an imaging device, an assembly device, a backlight device, an antenna device, a splicing device, a touch display, a curved display, or a freeshape display. The electronic device may, for example, include, but is not limited to, a liquid crystal, a light emitting diode, fluorescence, phosphor, other suitable display media, or a combination thereof. The display device may be a non-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The sensing device may be a sensing device that senses capacitance, light, heat, or ultrasound, but is not limited to such. The splicing device may, for example, include a display splicing device or an antenna splicing device, but is not limited to such. It should be noted that the electronic device may be any combination or permutation of the aforementioned, but is not limited to such. Furthermore, the electronic device may be a bendable or flexible electronic device. It should be noted that the electronic device may be any of the aforementioned arrangements and combinations, but is not limited thereto. Furthermore, the electronic device may be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may include peripheral systems such as a drive system, control system, light source system, and shelf system to support the display device, antenna device, or splicing device.

[0103] It should be noted that the following embodiments may be implemented by replacing, recombining, or combining features from several different embodiments to create other embodiments without departing from the spirit of the present invention. Features from various embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with it.

[0104] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by one skilled in the art to which this invention belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant art and this invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0105] In addition, the term "adjacent" in the specification and claims is used to describe proximity to each other, and the two adjacent entities may or may not be in contact.

[0106] Furthermore, in this disclosure, phrases such as "when" or "when" refer to "at the moment, before, or after," and are not limited to simultaneous occurrences. This is clarified in advance. Phrases such as "disposed on" and similar phrases in this disclosure indicate the corresponding positional relationship between two elements and do not limit whether the two elements are in contact, unless otherwise specified. This is clarified in advance. Furthermore, when describing multiple functions in this disclosure, the use of the word "or" between functions indicates that the functions can exist independently, but does not preclude the simultaneous existence of multiple functions.

[0107] Figure 1 FIG is a schematic diagram of an electronic device 1 according to an embodiment of the present invention. Figure 1 As shown, the electronic device 1 has an active area AA and a peripheral area PA. The active area AA is a region capable of emitting light and includes a main area A, a plurality of peripheral areas B, and a plurality of corner areas C. The peripheral areas B may, for example, surround the main area A. In one embodiment, the corner areas C may, for example, be arc-shaped, but are not limited thereto.

[0108] Figure 2 is a schematic diagram of an enlarged view of an outer area Z of an electronic device 1 according to an embodiment of the present invention, and please refer to Figure 1 .like Figure 2 As shown, the electronic device 1 may include a substrate 10, a plurality of electronic units 25, and a plurality of sensing units 35. The electronic units 25 and the sensing units 35 are respectively disposed on the substrate 10. Furthermore, in the outer region Z of the electronic device 1, the active area AA may include a main area A and a corner area C. The main area A and / or the corner area C may be provided with electronic units 25 and / or sensing units 35 as required. Similarly, the peripheral area B (not shown) may be provided with sensing units 35 as required, or may not be provided with sensing units 35. The corner area C may be located between the main area A and the peripheral area PA.

[0109] In one embodiment, the electronic unit 25 can be used to transmit electromagnetic waves, such as light, but not limited thereto. In one embodiment, the electronic unit 25 is, for example, a light-emitting unit or a display unit. When the electronic unit 25 is a light-emitting unit, the electronic unit 25 can be, for example, an organic light-emitting diode (OLED), but not limited thereto. When the electronic unit 25 is a display unit, the electronic unit 25 can be, for example, a thin film transistor (TFT) or a liquid crystal, but not limited thereto. For ease of explanation, the following examples all take the electronic unit 25 as an organic light-emitting diode.

[0110] In one embodiment, the sensing unit 35 can be used to receive electromagnetic waves, such as, but not limited to, light. In one embodiment, the sensing unit 35 can be a light sensing unit, such as, but not limited to, an organic photodiode (OPD). Multiple sensing units 35 can be used to sense, for example, ambient light or fingerprints, but are not limited to these.

[0111] In one embodiment, the electronic units 25 and the sensing units 35 may be staggered in the main area A and / or the corner area C. However, any arrangement is possible based on actual needs. In one embodiment, the area of ​​the main area A may differ from the area of ​​the corner area C. In one embodiment, the shape of the main area A may differ from the shape of the corner area C. In one embodiment, the size of the electronic units 25 and / or the sensing units 35 in the main area A may differ from the size of the electronic units 25 and / or the sensing units 35 in the corner area C. For example, the electronic units 25 in the main area A may be smaller than the electronic units 25 in the corner area C, and the sensing units 35 in the main area A may be smaller than the sensing units 35 in the corner area C, but the present invention is not limited thereto.

[0112] Please also refer to Figure 1 and Figure 2 In one embodiment, the active area AA of the electronic device 1 (including the main area A and the corner area C) is provided with both the electronic unit 25 and the sensing unit 35, while the peripheral area B of the electronic device 1 (such as multiple side portions) is provided with the sensing unit 35. This allows the effect of simultaneously sensing multiple fingerprints, thereby improving the accuracy of sensing.

[0113] Next, the basic driving method of the electronic unit 25 and the sensor unit 35 is described. Figure 3 is a schematic diagram of a basic driving circuit of an electronic device 1 according to an embodiment of the present invention, and please also refer to Figure 1 and Figure 2 .in, Figure 3The figure shows the basic driving circuit of a single electronic unit 25 and a sensing unit 35. A person skilled in the art can infer the form of multiple electronic units 25 and sensing units 35. In more detail, the electronic device 1 can have multiple scanning columns (not shown), each scanning column having at least one electronic unit, and Figure 3 The electronic units 25 in the CMOS are, for example, electronic units in the Nth group of scanning columns.

[0114] like Figure 3 As shown, in one embodiment, the electronic device 1 may include an electronic unit driving circuit 20 disposed on the substrate 10, and the electronic unit driving circuit 20 is electrically connected to the electronic unit 25. The electronic unit driving circuit 20 may be located, for example, in the active area AA. The electronic unit driving circuit 20 may include, but is not limited to, a driving transistor T1, a data writing transistor T2, a reset transistor T3, a transistor T4, a transistor T5, and a switching transistor T6. At least one of the transistors T1-T6 may be electrically connected to the electronic unit 25. The driving transistor T1 may include a first terminal a1, a second terminal b1, and a control terminal c1. The first terminal a1 may be a drain or a source, the second terminal b1 may be a drain or a source, and the control terminal c1 may be a gate. The data write transistor T2 may include a first terminal a2, a second terminal b2, and a control terminal c2, wherein the first terminal a2 may be a drain or a source, the second terminal b2 may be a drain or a source, and the control terminal c2 may be a gate. The reset transistor T3 may include a first terminal a3, a second terminal b3, and a control terminal c3, wherein the first terminal a3 may be a drain or a source, the second terminal b3 may be a drain or a source, and the control terminal c3 may be a gate. The transistor T4 may include a first terminal a4, a second terminal b4, and a control terminal c4, wherein the first terminal a4 may be a drain or a source, the second terminal b4 may be a drain or a source, and the control terminal c4 may be a gate. The transistor T5 may include a first terminal a5, a second terminal b5, and a control terminal c5, wherein the first terminal a5 may be a drain or a source, the second terminal b5 may be a drain or a source, and the control terminal c5 may be a gate. The switching transistor T6 may include a first terminal a6, a second terminal b6 and a control terminal c6, wherein the first terminal a6 may be a drain or a source, the second terminal b6 may be a drain or a source, and the control terminal c6 may be a gate.

[0115] In one embodiment, the driving transistor T1, the data writing transistor T2, the transistor T4, and the transistor T5 may be made of polysilicon, such as low temperature polysilicon (LTPS), and the reset transistor T3 and the switch transistor T6 may be made of metal oxide, such as indium gallium zinc oxide (IGZO), but are not limited thereto.

[0116] Furthermore, the electronic device 1 may include a sensing unit driving circuit 30 disposed on the substrate 10 and electrically connected to the electronic unit 25 and the sensing unit 35. The sensing unit driving circuit 30 may, for example, be located in the active area AA. The sensing unit driving circuit 30 may include, but is not limited to, a driving transistor ST1, a reset transistor ST2, and a data transmission transistor ST3. The driving transistor ST1 may include a first terminal as1, a second terminal bs1, and a control terminal cs1. The first terminal as1 may be a drain or a source, the second terminal bs1 may be a drain or a source, and the control terminal cs1 may be a gate. The reset transistor ST2 may include a first terminal as2, a second terminal bs2, and a control terminal cs2. The first terminal as2 may be a drain or a source, the second terminal bs2 may be a drain or a source, and the control terminal cs2 may be a gate. The data transmission transistor ST3 may include a first terminal as3, a second terminal bs3 and a control terminal cs3, wherein the first terminal as3 may be a drain or a source, the second terminal bs3 may be a drain or a source, and the control terminal cs3 may be a gate.

[0117] In one embodiment, the material of the amplifying transistor ST1 may include polysilicon, such as LTPS, the material of the reset transistor ST2 may include metal oxide, such as IGZO, and the material of the data transmission transistor ST3 may include polysilicon (such as LTPS) or metal oxide (such as IGZO), but is not limited thereto.

[0118] In addition, in one embodiment, the electronic device 1 may further include a plurality of driver units SN(N), SN_I(NX), SN_I(N), and EM(N), disposed on the substrate 10, wherein SN_I(NX) and SN_I(N) are the same driver unit but drive different scan columns. The driver units SN(N), SN_I(NX), SN_I(N), and EM(N) may be, for example, located in an area outside the active area AA, in an outer region Z, such as the peripheral area PA, but are not limited thereto. In one embodiment, the driver units SN(N), SN_I(NX), SN_I(N), and EM(N) may be, for example, source drivers for the aforementioned transistors T1-T6 or ST1-ST3, but are not limited thereto.

[0119] Furthermore, when Figure 3When the electronic unit driving circuit 20 and the sensing unit driving circuit 30 shown correspond to the Nth group of scan columns of the electronic device 1, generally speaking, the driving unit SN(N) may be, for example, a source driver for driving the LTPS transistors in the Nth group of scan columns to write data, the EM(N) may be, for example, a source driver for driving the LTPS transistors in the Nth group of scan columns to emit light, the driving unit SN_I(N) may be, for example, a source driver for turning on the IGZO transistors in the Nth group of scan columns, the driving unit SN(NX) may be, for example, a source driver for driving the LTPS transistors in the first X groups of scan columns (each group including at least one scan column) to write data, and the driving unit SN_I(NX) may be, for example, a source driver for turning on the IGZO transistors in the first X groups of scan columns, where X may be a positive integer greater than or equal to 1 (X≧1). For convenience of explanation, the following examples all use X as 1. It should be noted that in the present invention, in order to integrate the electronic unit driving circuit 20 and the sensing unit driving circuit 30, the transistors of the electronic unit driving circuit 20 and the sensing unit driving circuit 30 in the Nth group of scanning rows are driven not only by the driving units SN(N), EM(N), and SN_I(N), but may also be driven by the driving units SN(NX) and SN_I(NX) corresponding to the first X groups of scanning rows, and may even be driven by the driving units corresponding to the last Y groups of scanning rows (each group including at least one scanning row) (for example, SN(N+Y), SN_I(N+Y), as shown in FIG. Figure 5 、 7 , 8), where Y can be a positive integer greater than or equal to 0 (Y≧0).

[0120] In addition, in one embodiment, the driving units SN(N), SN_I(NX), SN_I(N) and EM(N) may each include a transistor, or the driving units SN(N), SN_I(NX), SN_I(N) and EM(N) may each be regarded as a transistor.

[0121] Next, the details of the electronic unit driving circuit 20 will be described.

[0122] In one embodiment, the first terminal a1 of the driving transistor T1 can be electrically connected to the second terminal b2 of the data write transistor T2 and the second terminal b4 of the transistor T4. The second terminal b1 of the driving transistor T1 can be electrically connected to the first terminal a5 of the transistor T5, and the control terminal c1 of the driving transistor T1 can be electrically connected to the first terminal a6 of the switching transistor T6. The first terminal a2 of the data write transistor T2 can be electrically connected to a data line DL, and the control terminal c2 of the data write transistor T2 can be electrically connected to the driving unit SN(N). The first terminal a3 of the reset transistor T3 can be electrically connected to the control terminal c1 of the driving transistor T1 and form a capacitor with a high voltage Vdd. The second terminal b3 of the reset transistor T3 can be electrically connected to an initial signal Vini, and the control terminal c3 of the reset transistor T3 can be electrically connected to the driving unit SN_I(NX). The first terminal a4 of the transistor T4 can be electrically connected to the high voltage Vdd, and the control terminal c4 of the transistor T4 can be electrically connected to the driving unit EM(N). The second terminal b5 of transistor T5 can be electrically connected to the electronic unit 25, and the control terminal c5 of transistor T5 can be electrically connected to the driving unit EM(N). The second terminal b6 of switching transistor T6 can be electrically connected to the first terminal a5 of transistor T5, and the control terminal c6 of switching transistor T6 can be electrically connected to the driving unit SN_I(N). In one embodiment, the high voltage Vdd can be used to adjust the brightness of the electronic unit 25. One terminal of the electronic unit 25 is electrically connected to the second terminal b5 of transistor T5, and the other terminal of the electronic unit 25 is electrically connected to a low voltage Vss.

[0123] Next, the details of the sensing unit driving circuit 30 will be described.

[0124] In one embodiment, the first end as1 of the amplifying transistor ST1 can be electrically connected to the high potential Vdd, the second end bs1 of the amplifying transistor ST1 can be electrically connected to the first end as3 of the data transmission transistor ST3, and the control end ac1 of the amplifying transistor ST1 can be electrically connected to the second end bs2 of the reset transistor ST2. The first end as2 of the reset transistor ST2 can be electrically connected to the initial signal Vini, and the control end cs2 of the reset transistor ST2 can be electrically connected to the driving unit SN_I(NX). The second end bs3 of the data transmission transistor ST3 can be electrically connected to a signal readout line RL. In addition, when the material of the data transmission transistor ST3 includes metal oxide, the control end cs3 of the data transmission transistor ST3 can be electrically connected to the driving unit SN_I(N), and when the material of the data transmission transistor ST3 includes polysilicon, the control end cs3 of the data transmission transistor ST3 can be electrically connected to the driving unit SN(N). It should be noted that Figure 3 The data transmission transistor ST3 is shown to be made of polysilicon. Therefore, the control terminal cs3 of the data transmission transistor ST3 can be electrically connected to the driving unit SN(N).

[0125] As can be seen, driver unit SN_I(NX) can be used to control reset transistor T3 and reset transistor ST2. Here, "control" refers to, for example, turning a transistor on or off. In other words, driver unit SN_I(NX) can control a signal SSN_I(NX) to be transmitted to reset transistor T3 and reset transistor ST2. Signal SSN_I(NX) can be considered a reset signal. Driver unit SN_I(N) can be used to control switching transistor T6 and data transfer transistor ST3 (when the material thereof includes IGZO). In other words, driver unit SN_I(N) can control a signal SSN_I(N) to be transmitted to switching transistor T6 and data transfer transistor ST3 (IGZO). Driver unit SN(N) can be used to control data write transistor T2 and data transfer transistor ST3 (when the material thereof includes LTPS). In other words, driver unit SN(N) can control a signal SSN(N) to be transmitted to data write transistor T2 and data transfer transistor ST3 (LTPS). The driving unit EM(N) can be used to control the transistors T4 and T5. In other words, the driving unit EM(N) can control a signal SEM(N) to be transmitted to the transistors T4 and T5. The signal SEM(N) can be regarded as a switching signal.

[0126] Figure 4 This is a detailed circuit diagram of an electronic device according to an embodiment of the present invention. Please also refer to Figures 1 to 3 Since the circuit structures of the electronic unit driving circuit 20 and the sensing unit driving circuit 30 are shown in FIG. Figure 3 To make the diagram clear, Figure 4 The circuit structures of the electronic unit driving circuit 20 and the sensing unit driving circuit 30 are simplified. Figure 4 For example, the material of the data transmission transistor ST3 includes polysilicon, and thus the driving unit SN(N) can be used to control the data transmission transistor ST3 to be turned on or off.

[0127] like Figure 4 As shown, the electronic device 1 may include a driving unit SN(N), a driving unit SN_I(N), a driving unit SN_I(N-1), and a driving unit EM(N). The driving unit SN_I(N-1) may be used to control the reset transistor T3 of the electronic unit driving circuit 20 and the reset transistor ST2 of the sensing unit driving circuit 30. The driving unit SN(N) may be used to control the data write transistor T2 of the electronic unit driving circuit 20 and the data transfer transistor ST3 of the sensing unit driving circuit 30.

[0128] Although the reset transistor T3 and the reset transistor ST2 can share the driving unit SN(NX), the reset transistor T3 and the reset transistor ST2 may need to be turned on at different times. Therefore, in one embodiment, the electronic device 1 may further include a transistor T7 disposed on the substrate 10. Transistor T7 may be electrically connected between the reset transistor ST2 and the reset transistor ST3. For example, a first terminal a7 of transistor T7 may be electrically connected to the driving unit SN_I(NX) and the reset transistor T3, and a second terminal b7 of transistor T7 may be electrically connected to the reset transistor ST2. Furthermore, a control terminal c7 of transistor T7 may be electrically connected to a reset control signal Sreset. Therefore, the potential of the reset control signal Sreset can be used to control whether transistor T7 is turned on or off. Thus, when transistor T7 is off, the signal SSN_I(NX) provided by the driver unit SN_I(NX) can be transmitted to the electronic unit driver circuit 20 but not to the sensing unit driver circuit 30. However, when transistor T7 is on, the signal SSN_I(NX) provided by the driver unit SN_I(NX) can be transmitted to the sensing unit driver circuit 30 through transistor T7. Therefore, the switching timings of the reset transistors T3 and ST2 can be controlled.

[0129] In one embodiment, although the data transmission transistor ST3 and the data write transistor T2 may share the driver unit SN(N), the data write transistor T2 and the data transmission transistor ST3 may need to be turned on at different times. Therefore, the electronic device 1 may further include a transistor T8. A first terminal a8 of the transistor T8 may be electrically connected to the driver unit SN(N) and the data write transistor T2, a second terminal b8 of the transistor T8 may be electrically connected to the data transmission transistor ST3, and a control terminal c8 of the transistor T8 may be electrically connected to a read control signal Sread. The voltage level of the read control signal Sread may be used to control the turning on or off of the transistor T8. Therefore, when the transistor T8 is turned off, the signal SSN(N) provided by the driver unit SN(N) may be transmitted to the electronic unit driving circuit 20 but not to the sensing unit driving circuit 30. When the transistor T8 is turned on, the signal SSN(N) provided by the driver unit SN(N) may be transmitted to the sensing unit driving circuit 30. Thus, the turning on and off timings of the data write transistor T2 and the data transmission transistor ST3 can be controlled.

[0130] It should be noted that, in another embodiment, when the data transmission transistor ST3 is an IGZO transistor, the switching transistor T6 (shown in FIG. Figure 3 ) and the data transmission transistor ST3 can share the driving unit SN_I(N). At this time, the first end a8 of the transistor T8 can be electrically connected to the driving unit SN_I(N) and the switching transistor T6, for example, but is not limited thereto.

[0131] Figure 5 is with Figure 4 The signal timing diagram corresponding to the circuit structure, and please also refer to Figure 3 .

[0132] In one embodiment, the electronic device 1 can execute a display mode and a sensing mode, wherein the duration of one display mode execution is defined as a display frame TA, and the duration of one sensing mode execution is defined as a sensing frame TB. In one embodiment, the display mode can include a reset phase, a data writing phase, and a light emitting phase, while the sensing mode can include a reset phase and a data transmission phase.

[0133] like Figure 5 As shown, the display frame TA may include multiple sub-periods, such as ta1 to ta3, and the sensing frame TB may include multiple sub-periods, such as tb1 to tb2. Figure 5 In this example, the sensing mode is executed later than the display mode. For example, the first sensing frame TB may follow the first display frame TA and at least partially overlap with the second display frame TA.

[0134] In addition, Figure 5 In the example, the signals SSN_I(NX) and SSN_I(N) are set to turn on the transistors at high levels, and the signal SSN(N), the signal SEM(N), the reset control signal Sreset, and the read control signal Sread are set to turn on the transistors at low levels, but the present invention is not limited thereto.

[0135] First, the operation process of the display mode is described, taking the first display frame TA as an example.

[0136] During the first sub-period ta1 of the display frame TA, the signal SSN_I(NX) provided by the driver unit SN_I(NX) transitions from a low level to a high level (which can be considered as the transistor of the driver unit SN_I(NX) turning on. Therefore, the first sub-period ta1 of the display frame TA can be considered as an on-period t11 of the transistor of the driver unit SN_I(NX)). This causes the reset transistor T3 of the electronic unit driving circuit 20 to turn on and receive the initialization signal Vini. During this time, the remaining transistors are off, allowing the reset phase of the display mode to be executed. It should be noted that since the reset control signal Sreset is high at this time, transistor T7 is off. Therefore, the control terminal cs2 of the reset transistor ST2 does not receive the signal SSN_I(NX), and thus the reset transistor ST2 is off.

[0137] During the second sub-period ta2 of the display frame TA, the signal SSN_I(N) provided by the driver unit SN_I(N) transitions from a low voltage level to a high voltage level (which can be considered as the transistor of the driver unit SN_I(N) being turned on. Therefore, the second sub-period ta2 of the display frame TA can be considered as an on-period t12 of the transistor of the driver unit SN_I(N)). This causes the switching transistor T6 of the electronic unit driving circuit 20 to turn on. Simultaneously, the signal SSN(N) provided by the driver unit SN(N) transitions from a high voltage level to a low voltage level (which can be considered as the transistor of the driver unit SN(N) being turned on. Therefore, the second sub-period ta2 of the display frame TA can be considered as an on-period t13 of the transistor of the driver unit SN(N)). This causes the data write transistor T2 of the electronic unit driving circuit 20 to turn on and receive the data signal Data. At this time, the remaining transistors are in a turned-off state, allowing the data write phase of the display mode to be executed. It should be noted that, since the read control signal Sread is at a high level at this time, the transistor T8 is turned off, and thus the control terminal cs3 of the data transmission transistor ST3 does not receive the signal SSN(N), so the data transmission transistor ST3 is also turned off.

[0138] During the third sub-period ta3 of the display frame TA, the signal SEM(N) provided by the driving unit EM(N) changes from a high potential to a low potential (which can be regarded as the transistor of the driving unit EM(N) being turned on. Therefore, the third sub-period ta3 of the display frame TA can be regarded as an on-period t14 of the transistor of the driving unit EM(N)). As a result, the transistors T4 and T5 of the electronic unit driving circuit 20 are turned on. At the same time, the driving transistor T1 is affected by the transistors T4 and T5 and is also turned on. At this time, the remaining transistors are in a turned-off state. Therefore, the light-emitting stage of the display mode can be executed.

[0139] Next, the operation process of the sensing mode is described.

[0140] During the first sub-period tb1 of the sensing frame TB, the signal SSN_I(NX) provided by the driver unit SN_I(NX) transitions from a low voltage level to a high voltage level (which can be considered as the transistor of the driver unit SN_I(NX) turning on. Therefore, the first sub-period tb1 of the sensing frame TB can be considered as an on-period t11 of the transistor of the driver unit SN_I(NX)). Simultaneously, the reset control signal Sreset transitions from a high voltage level to a low voltage level, turning on transistor T7. At this time, the control terminal cs2 of the reset transistor ST2 receives the driver unit signal SSN_I(NX), turning on the reset transistor ST2 and receiving the initial signal Vini. Thus, the reset phase of the sensing mode is executed. Furthermore, the sensing unit 35 can sense the signal, and the amplifier transistor ST1 can be turned on by the reset transistor ST2, thereby amplifying the signal sensed by the sensing unit 35.

[0141] During the second sub-period tb2 of the sensing frame TB, the signal SSN(N) provided by the driver unit SN(N) transitions from a high level to a low level (which can be considered as the transistor of the driver unit SN(N) being turned on. Therefore, the second sub-period tb2 of the sensing frame TB can be considered as an on-period t13 of the transistor of the driver unit SN(N)). Simultaneously, the readout control signal Sread transitions from a high level to a low level, turning on the transistor T8. Consequently, the control terminal cs3 of the data transmission transistor ST3 receives the signal SSN_I(NX) and turns on, thereby transmitting the signal sensed by the sensing unit 35 to the signal readout line RL. Thus, the data transmission phase of the sensing mode is executed.

[0142] In addition, although Figure 5 In the example, transistors T7 and T8 are turned on in different sub-periods of the sensing frame TB. However, in another embodiment, transistors T7 and T8 may be turned on at the same time point. For example, both may be turned on in the first sub-period tb1 of the sensing frame TB. For example, the reset control signal Sreset and the read control signal Sread both change from a high level to a low level in the first sub-period tb1 of the sensing frame TB.

[0143] In addition, although Figure 5 In this example, the sensing mode is executed later than the display mode. However, in another embodiment, the sensing mode and the display mode can be executed simultaneously, that is, the display frame TA and the sensing frame TB can also be synchronized. In this case, during the first display sub-period ta1, the reset control signal Sreset can transition from a high voltage to a low voltage, turning on transistor T7, thereby simultaneously turning on reset transistors T3 and ST2. During the second display sub-period ta2, the read control signal Sread can transition from a high voltage to a low voltage, turning on transistor T8, thereby allowing the data write transistor T2 to receive the data signal Data. The data transmission transistor ST3, the amplifying transistor ST1, the switching transistor T6, and the data write transistor T2 can all be turned on simultaneously, without limitation.

[0144] Next, a description will be given of a wiring layout of the electronic device 1 . Figure 6 is a schematic diagram of the wiring configuration of the electronic device 1 according to an embodiment of the present invention, which may correspond to Figure 3 and Figure 4 The circuit structure of Figure 6 The wiring configuration is presented from a top-down perspective. Figure 6 Taking the case where the material of the data transmission transistor ST3 includes polysilicon as an example, the control terminal cs3 of the data transmission transistor ST3 can be electrically connected to the driving unit SN(N).

[0145] [Reset the wiring configuration of transistors ST2 and T7]

[0146] like Figure 6 As shown, the electronic device 1 includes a first conductive layer 40 disposed on a substrate 10. The first conductive layer 40 may include a sub-conductive layer 41. The sub-conductive layer 41 includes a line segment 41a and a gate 41b. The line segment 41a connects the gate 41b. The gate 41b may, for example, overlap with a semiconductor layer 70. The reset transistor ST2 of the sensing unit driving circuit 30 may have a gate 41b. In one embodiment, the electronic device 1 includes a second conductive layer 50 disposed on the substrate 10. The second conductive layer 50 is disposed on the first conductive layer 40 in the Z direction. The second conductive layer 50 may include a sub-conductive layer 51 disposed on the sub-conductive layer 41 in the Z direction. The sub-conductive layer 51 may include a gate 51b. The gate 51b may, for example, overlap with the semiconductor layer 70. The reset transistor ST2 has a gate 51b. The gate 41b of the sub-conductive layer 41 and the gate 51b of the sub-conductive layer 51 may at least partially overlap in the Z direction. In one embodiment, the sub-conductive layer 41 and the sub-conductive layer 51 can receive the signal SSN_I(NX) from the driving unit SN_I(NX) through a first metal layer 81. In one embodiment, the gate 41b of the sub-conductive layer 41 can be, for example, a bottom gate, and the gate 51b of the sub-conductive layer 51 can be, for example, a top gate, and the gates 41b and 51b can form the gate of the reset transistor ST2 (i.e., Figure 3 control terminal cs2).

[0147] From the top view (e.g. Figure 6In the -Z direction), the contour of the gate 41b of the sub-conductive layer 41 is different from the contour of the line segment 41a. In the present disclosure, "different contours" means, for example, that there is no relationship of being scaled proportionally between the two. Conversely, if there is a relationship of being scaled proportionally between the two, it belongs to "different contours". In one embodiment, the gate 41b has a width L2-1, and the fact that the contour of the gate 41b is different from the contour of the line segment 41a means that the width L2-1 of the gate 41b is different from the width Lline of the line segment 41a. In one embodiment, the width L2-1 of the gate 41b can be greater than the width Lline of the line segment 41a (L2-1 > Lline), so the leakage current of the reset transistor ST2 can be reduced. In one embodiment, the ratio of the width Lline of the line segment 41a to the width L2-1 of the gate 41b can satisfy the equation: 0.3 times the width L2-1 of the gate 41b < this ratio < 0.7 times the width L2-1 of the gate 41b (0.3×L2-1 < Line / L2-1 < 0.7×L2-1), but it is not limited thereto. In addition, in one embodiment, the contour of the gate 41b is different from the contour of the gate 51b. For example, the gate 51b can have a width L2-2, and the width L2-1 of the gate 41b is different from the width L2-2 of the gate 51b. In one embodiment, the width L2-1 of the gate 41b is greater than the width L2-2 of the gate 51b (L2-1 > L2-2), and it is not limited thereto.

[0148] In one embodiment, the electronic device 1 further includes a semiconductor layer 70 disposed on the substrate 10. The material of the semiconductor layer 70 can include metal oxide (such as IGZO) and / or polysilicon (such as LTPS), and it is not limited thereto. The reset transistor ST2 can include a first semiconductor 71, where the first semiconductor 71 can be, for example, at least a part of the semiconductor layer 70, but it is not limited thereto. One end 71a of the first semiconductor 71 can be electrically connected to the initial signal Vini through a third conductive layer 61, and the other end 71b of the first semiconductor 71 can be electrically connected to the amplifying transistor ST1 through a sixth metal layer 86.

[0149] Accordingly, the gate 41b of the sub-conductive layer 41 and the gate 51b of the sub-conductive layer 51 can serve as the control terminal cs2 of the reset transistor ST2. The first semiconductor 71 can overlap at least partially with the gates 41b and 51b to serve as the channel of the reset transistor ST2. One end 71a of the first semiconductor 71 can serve as the first end as2 of the reset transistor ST2, and the other end 71b of the first semiconductor 71 can serve as the second end bs2 of the reset transistor ST2, and it is not limited thereto. In addition, since the first semiconductor 71 can overlap with the gate 41b, the channel length of the reset transistor ST2 can be regarded as equal to the width L2-1 of the gate 41b. The channel width of the reset transistor ST2 can be equal to the width W2-1 of the first semiconductor 71.

[0150] In one embodiment, the sub-conductive layer 41 and the sub-conductive layer 51 can be electrically connected to the transistor T7. In one embodiment, the transistor T7 can be formed by a third metal layer 83 and a fourth metal layer 84, wherein the third metal layer 83 can include an LTPS semiconductor, for example, and the fourth metal layer 84 can be a conductive layer, which can serve as the gate of the transistor T7 (i.e., the control terminal c7). Therefore, whether the signal SSN_I(NX) provided by the driving unit SN_I(NX) enters the sub-conductive layer 41 and the sub-conductive layer 51 can be controlled by turning on or off the transistor T7. In one embodiment, the third metal layer 83 can be electrically connected to the sub-conductive layer 41 and the sub-conductive layer 51 by means of a bridge. In one embodiment, the third metal layer 83 can be electrically connected to the sub-conductive layer 42 and the sub-conductive layer 52 by means of a bridge.

[0151] Therefore, the structure of the reset transistor ST2 can be understood.

[0152] [Wiring configuration of amplifier transistor ST1, data transmission transistor ST3, and transistor T8]

[0153] In one embodiment, the electronic device 1 further includes a fourth conductive layer 62, wherein the fourth conductive layer 62 may include a sub-conductive layer 621 and a sub-conductive layer 622. The fourth conductive layer 62 may be used to receive the signal SSN(N) transmitted by the driving unit SN(N). Furthermore, the electronic device 1 further includes a fifth conductive layer 63. The fifth conductive layer 63 may be located on a different layer from the fourth conductive layer 62 in the Z direction, but is not limited thereto. One end 63a of the fifth conductive layer 63 may be electrically connected to the signal readout line RL, and the other end 63b of the fifth conductive layer 63 may be electrically connected to the high potential Vdd. In one embodiment, the sub-conductive layer 622 of the fourth conductive layer 62 and the fifth conductive layer 63 may form a data transmission transistor ST3, wherein the sub-conductive layer 622 of the fourth conductive layer 62 may serve as the control terminal cs3 of the data transmission transistor ST3, one end 63a of the fifth conductive layer 63 may serve as the second terminal bs3 of the data transmission transistor ST3, and a portion of the fifth conductive layer 63 may serve as the first terminal as3 of the data transmission transistor ST3. In one embodiment, a portion of the fifth conductive layer 63 may serve as a channel of the amplifying transistor ST1 . In one embodiment, another portion of the fifth conductive layer 63 may serve as a channel of the data transmitting transistor ST3 .

[0154] In one embodiment, the sub-conductive layer 622 of the fourth conductive layer 62 can be electrically connected to the transistor T8. In one embodiment, the transistor T8 can be formed by a seventh metal layer 87 and an eighth metal layer 88. The seventh metal layer 87 can include, for example, an LTPS or IGZO semiconductor, and the eighth metal layer 88 can be a conductive layer that serves as the gate of the transistor T8 (i.e., the control terminal c8). Therefore, the turning on or off of the transistor T8 can be used to control whether the signal SSN(N) provided by the driving unit SN(N) enters the sub-conductive layer 622 of the fourth conductive layer 62.

[0155] Furthermore, in one embodiment, the electronic device 1 may further include a sixth conductive layer 64. In the Z direction, the fifth conductive layer 63 and the sixth conductive layer 64 may be located on different layers. The fifth conductive layer 63 may be electrically connected to the reset transistor ST2 via the sixth metal layer 86. The sixth conductive layer 64 and the fifth conductive layer 63 may form an amplifying transistor ST1, wherein the sixth conductive layer 64 may serve as the control terminal cs1 of the amplifying transistor ST1, a portion of the fifth conductive layer 63 may serve as the second terminal bs1 of the amplifying transistor ST1, and the other terminal 63b of the fifth conductive layer 63 may serve as the first terminal as1 of the amplifying transistor ST1.

[0156] Therefore, the structures of the amplifying transistor ST1 and the data transmitting transistor ST3 can be understood.

[0157] [Reset the wiring configuration of transistor T3]

[0158] In one embodiment, the first conductive layer 40 may further include a sub-conductive layer 42. The sub-conductive layer 42 may include a line segment 42a and a gate 42b, with the line segment 42a connected to the gate 42b. The reset transistor T3 of the electronic unit driving circuit 20 has a gate 42b. The second conductive layer 50 may further include a sub-conductive layer 52, which is disposed on the sub-conductive layer 42 in the Z direction. The sub-conductive layer 52 may include a gate 52b. The reset transistor T3 has a gate 52b, and the gate 52b may be electrically connected to the electronic unit 25. In addition, in the Z direction, the gate 42b of the sub-conductive layer 42 and the gate 52b of the sub-conductive layer 52 may at least partially overlap. In one embodiment, the sub-conductive layer 42 and the sub-conductive layer 52 may receive the signal SSN_I(NX) from the driving unit SN_I(NX) through a first metal layer 81. The sub-conductive layer 42 and the sub-conductive layer 52 may be electrically connected to the sub-conductive layer 41 and the sub-conductive layer 51 through the transistor T7. In one embodiment, gate 42b may be, for example, a bottom gate, and gate 52b may be, for example, a top gate, and gates 42b and 52b may form the gate of the reset transistor T3 (i.e., control terminal c3). Furthermore, in one embodiment, line segment 41a may also be connected to gate 42b, but is not limited thereto. Furthermore, in one embodiment, electronic device 1 may further include another conductive layer (not shown) disposed on substrate 10. This other conductive layer may have a connecting portion (not shown), and gates 41b and 52b may be electrically connected via the connecting portion, but is not limited thereto. Furthermore, in the Z direction, this other conductive layer may be located below gate 41b and line segment 41a, but may also be located between gate 41b (or line segment 41a) and gate 52b.

[0159] The lengths of line segment 41a and line segment 42a may be the same. Figure 6In the -Z direction), the contour of the gate 42b is different from the contour of the line segment 42a (or the line segment 41a). For example, the gate 42b may have a width L1-1, the line segment 42a (or the line segment 41a) may have a width Lline, and the width L2-2 of the gate 42b may be different from the width Line of the line segment 42a (or the line segment 41a). In one embodiment, the width L1-1 of the gate 42b may be greater than the width Lline of the line segment 42a (L1-1 > Lline), so the leakage current of the reset transistor T3 can be reduced. In one embodiment, the ratio of the width Lline of the line segment 42a to the width L1-1 of the gate 42b may satisfy the equation: 0.3 times the width L1-1 of the gate 42b < this ratio < 0.7 times the width L1-1 of the gate 42b (0.3×L2-1 < Line / L1-1 < 0.7×L2-1), but is not limited thereto. In addition, in one embodiment, the line segment 42a may have the same width Lline as the line segment 41a, so the width L1-1 of the gate 42b may also be greater than the width Lline of the line segments 41a and 41b. Additionally, in one embodiment, as viewed from the top-down direction (e.g., Figure 6 In the -Z direction), the contour of the gate 42b may also be different from the contour of the gate 52b. For example, the gate 52b may have a width L1-2, and the width L1-1 of the gate 42b is different from the width L1-2 of the gate 52b. In one embodiment, the width L1-1 of the gate 42b may be greater than the width L1-2 of the gate 52b (L1-1 > L1-2). In addition, as viewed from the top-down direction (e.g., Figure 6 In the -Z direction), the contour of the gate 52b may also be different from the line segments 41a, 42a or 52a. In one embodiment, the width L1-1 of the gate 52b may be less than or equal to the width Lline of the line segments 41a, 42a or 52a (L1-1 ≦ Lline), but is not limited thereto.

[0160] In addition, in one embodiment, the reset transistor T3 may include a second semiconductor 72, where the second semiconductor 72 may be, for example, at least a part of the semiconductor layer 70, but is not limited thereto. One end 72a of the second semiconductor 72 may be electrically connected to the initial signal Vini through the third conductive layer 61, and an extended portion 72c of the second semiconductor 72 may be electrically connected to the driving transistor T1 through a fifth metal layer 85.

[0161] Accordingly, the gate 42b of the sub-conductive layer 42 and the gate 52b of the sub-conductive layer 52 can serve as the control terminal c3 of the reset transistor T3. The second semiconductor 72 can at least partially overlap with the gates 42b and 52b to serve as the channel of the reset transistor T3. One end 72a of the second semiconductor 72 can serve as the second end b3 of the reset transistor T3, and the extended portion 72c of the second semiconductor 72 can serve as the first end a3 of the reset transistor T3, without limitation. Furthermore, because the second semiconductor 72 can overlap with the gate 42b, the channel length of the reset transistor T3 can be considered equal to the width L1-1 of the gate 42b. The channel width of the reset transistor T3 can be equal to the width W1-1 of the second semiconductor 72.

[0162] Therefore, the structure of the reset transistor T3 can be understood.

[0163] [Wiring configuration of switching transistor T6]

[0164] In one embodiment, the first conductive layer 40 may further include a sub-conductive layer 43. The sub-conductive layer 41, the sub-conductive layer 42, and the sub-conductive layer 43 may be separated from each other, but are not limited thereto. The sub-conductive layer 43 may include a line segment 43a and a gate 43b, wherein the line segment 43a is connected to the gate 43b. The switching transistor T6 of the electronic unit driving circuit 20 has a gate 43b. The second conductive layer 50 may further include a sub-conductive layer 53, which is disposed on the sub-conductive layer 43 in the Z direction. The sub-conductive layer 53 may include a gate 53b. The switching transistor T6 has a gate 53b. In addition, in the Z direction, the gate 43b of the sub-conductive layer 43 and the gate 53b of the sub-conductive layer 53 may at least partially overlap. In one embodiment, the sub-conductive layer 43 and the sub-conductive layer 53 may receive the signal SSN_I(N) from the driving unit SN_I(N) through a second metal layer 82. In one embodiment, the gate 43b may be, for example, a bottom gate, the gate 53b may be, for example, a top gate, and the gate 43b and the gate 53b may form the gate of the switching transistor T6 (ie, Figure 3 control terminal c6).

[0165] In one embodiment, when viewed from the top (e.g. Figure 6 The relationship between the outline of the gate 43b of the sub-conductive layer 43 and the outline of the line segment 43a can be applied to the description of the relationship between the outline of the gate 41b of the sub-conductive layer 41 and the outline of the line segment 41a, so it will not be described in detail. The line segment 43a and the line segment 41a can have the same width Lline. In addition, as seen from the top view (for example Figure 6 In the -Z direction), the profile of the gate 43b may be different from the profile of the gate 53b.

[0166] In one embodiment, the extended portion 72c of the second semiconductor 72 can serve as the first terminal a6 of the switching transistor T6, and the other terminal 72b of the second semiconductor 72, opposite to the terminal 72a, can serve as the second terminal b6 of the switching transistor T6. The other terminal 72b of the second semiconductor 72 can be electrically connected to the transistor T5 (not shown). The gate 43b of the sub-conductive layer 43 and the gate 53b of the sub-conductive layer 53 can serve as the control terminal c6 of the switching transistor T6, but the present invention is not limited thereto. Therefore, the structure of the switching transistor T6 can be understood.

[0167] Wiring Arrangement of Other Transistors (T1, T2, T4, and T5) in the Electronic Unit Driving Circuit 20

[0168] In one embodiment, the electronic device 1 may further include a seventh conductive layer 65, an eighth conductive layer 66, and a ninth conductive layer 67. The seventh conductive layer 65 may be configured to receive the signal SEM(N) transmitted by the driving unit EM(N). In the Z direction, the eighth conductive layer 66 and the ninth conductive layer 67 may be disposed on different layers. The ninth conductive layer 67 may have a first end 67a, a second end 67b, and a third end 67c. The first end 67a may be electrically connected to the electronic unit 25, the second end 67b may be electrically connected to the high potential 67b, and the third end 67c may be electrically connected to the data line DL. The ninth conductive layer 67 may also have a middle portion 67d, which may at least partially overlap with the eighth conductive layer 66.

[0169] In one embodiment, a portion of the ninth conductive layer 67 and the eighth conductive layer 66 can be used to form a driving transistor T1. In one embodiment, the ninth conductive layer 67 and the seventh conductive layer 61 can be used to form transistors T4 and T5, wherein the second end 67b of the ninth conductive layer 67 can serve as the first end a4 of transistor T4, and the first end 67a of the ninth conductive layer 67 can serve as the second end b5 of transistor T5. In one embodiment, the sub-conductive layer 621 of the fourth conductive layer 62 and the ninth conductive layer 67 can be used to form a data write transistor T2, wherein the third end 67c of the ninth conductive layer 67 can serve as the first end a2 of the data write transistor T2.

[0170] In one embodiment, a portion of the ninth conductive layer 67 can serve as a channel for driving transistor T1 , another portion of the ninth conductive layer 67 can serve as a channel for transistor T4 , and yet another portion of the ninth conductive layer 67 can serve as a channel for transistor T5 .

[0171] Therefore, the structures of the driving transistors T1 , T2 , T4 and T5 can be understood.

[0172] Next, the size relationship between the transistors is described.

[0173] In one embodiment, the materials of the amplifying transistor ST1 and the data transfer transistor ST3 may include LTPS, the material of the reset transistor ST2 may include IGZO, the driving transistor T1 may have a channel length LT1, and the amplifying transistor ST1 may have a channel length LST1. In one embodiment, the driving transistor T1 and the amplifying transistor ST1 may be electrically connected to different high potentials Vdd. In one embodiment, when the driving transistor T1 and the amplifying transistor ST1 are electrically connected to the same high potential Vdd, the channel length LT1 of the driving transistor T1 may be equal to the channel length LST1 of the amplifying transistor ST1 (LT1 = LST1). In one embodiment, when the driving transistor T1 and the amplifying transistor ST1 are electrically connected to different high potentials Vdd, the channel length LT1 of the driving transistor T1 may be greater than the channel length LST1 of the amplifying transistor ST1 (LT1 > LST1), thereby reducing the leakage current of the sensing unit driving circuit 30. In addition, in one embodiment, the channel length LST1 of the amplifying transistor ST1 may be greater than the channel length L2-1 of the reset transistor ST2 (LST1 > L2-1), thereby reducing the leakage current of the sensing unit driving circuit 30.

[0174] In one embodiment, the materials of the amplifying transistor ST1 and the data transfer transistor ST3 may include LTPS, the material of the reset transistor ST2 may include IGZO, and the data transfer transistor ST3 may have a channel length LST3 and a channel width WST3. In one embodiment, the channel length LST3 of the data transfer transistor ST3 may be greater than the channel length L2-1 of the reset transistor ST2 (LST3 > L2-1). In one embodiment, the channel width WST3 of the data transfer transistor ST3 may be less than the channel width W2-1 of the reset transistor ST2 (WST3 < W2-1). Therefore, the leakage current of the sensing unit driving circuit 30 can be reduced.

[0175] In one embodiment, the material of the amplifying transistor ST1 may include LTPS, the materials of the reset transistor ST2 and the data transfer transistor ST3 may include IGZO, and the data transfer transistor ST3 may have a channel length LST3 and a channel width WST3. In one embodiment, the channel length LST3 of the data transfer transistor ST3 may be greater than the channel length L2-1 of the reset transistor ST2 (LST3 > L2-1). In one embodiment, the channel width WST3 of the data transfer transistor ST3 may be less than the channel width W2-1 of the reset transistor ST2 (WST3 < W2-1). Therefore, the leakage current of the sensing unit driving circuit 30 can be reduced.

[0176] Therefore, the wiring configuration of the electronic device 1 can be understood.

[0177] In the present invention, when the materials of the amplifying transistor ST1, the reset transistor ST2, and / or the data transmission transistor ST3 of the sensing unit driving circuit 30 are changed, the circuit structure between the sensing unit driving circuit 30 and the driving unit will also change. The following will describe different circuit structures.

[0178] Figure 7 A schematic diagram showing a detailed circuit structure of an electronic device 1 according to another embodiment of the present invention is shown. Figures 1 to 6 .because Figure 7 The features of the examples are generally applicable Figure 4 The following mainly describes the differences.

[0179] exist Figure 7 In this example, the material of the amplifying transistor ST1 includes LTPS, the material of the resetting transistor ST2 includes IGZO, the material of the data transmission transistor ST3 includes LTPS, and the part of the electronic unit driving circuit 20 is the same as Figure 4 In addition, the reset transistor ST2 is driven by the driving unit SN_I(NX).

[0180] Figure 7 Example with Figure 4 The difference in this example is that the electronic device 1 further includes a driver unit SN(N+Y) disposed in the peripheral area B, where Y can be, for example, 1. The driver unit SN(N+Y) can be electrically connected to the first terminal a8 of the transistor T8, while the second terminal b8 of the transistor T8 can be electrically connected to the data transmission transistor ST3. Therefore, the transistor T8 is driven by the driver unit SN(N+Y). For example, the driver unit SN(N+Y) can provide a signal SSN(N+Y). When the transistor T8 is turned on, the signal SSN(N+Y) can enter the control terminal cs3 of the data transmission transistor ST3, thereby turning on the data transmission transistor ST3. In one embodiment, the driver unit SN(N+Y) can include a transistor, or can itself be a transistor. In other words, the driver unit SN(N+Y) can control the signal SSN(N+Y) transmitted to the data transmission transistor ST3, where the signal SSN(N+Y) can be considered a read signal.

[0181] Figure 8 is with Figure 7 The signal timing diagram corresponding to the circuit structure. Figure 8 In this example, the display mode works just like Figure 5 The examples are the same, so the following description focuses on the induction mode.

[0182] like Figure 8As shown, during the first sub-period tb1 of the sensing frame TB, the signal SSN_I(NX) provided by the driver unit SN_I(NX) transitions from a low level to a high level, while the reset control signal Sreset transitions from a high level to a low level. Consequently, transistor T7 turns on, and the control terminal cs2 of the reset transistor ST2 receives the driver unit signal SSN_I(NX) and turns on, thereby enabling the reset phase to be executed. Furthermore, the amplifier transistor ST1 is also turned on by the reset transistor ST2, thereby amplifying the signal sensed by the sensing unit 35. At this time, the readout control signal Sread remains high, turning off transistor T8.

[0183] During the second sub-period tb2 of the sensing frame TB, the signal SSN_I(NX) provided by the driver unit SN_I(NX) transitions from high to low, turning off the reset transistor ST2. At this time, the signal SSN(N+Y) provided by the driver unit SN(N+Y) remains low, and the read control signal Sread remains high, thus keeping transistor T8 off. During the third sub-period tb3 of the sensing frame TB, the signal SSN(N+Y) provided by the driver unit SN(N+Y) transitions from low to high (which can be considered as turning on the transistor of the driver unit SN(N+Y). Therefore, the third sub-period tb3 of the sensing frame TB can be considered as an on-period t15 of the transistor of the driver unit SN(N+Y)). Simultaneously, the read control signal Sread transitions from high to low, turning on transistor T8. This, in turn, allows the control terminal cs3 of the data transmission transistor ST3 to receive the signal SSN(N+Y) and turn on, thereby enabling the data transmission phase of the sensing mode to begin. It should be noted that at least one turn-on period t15 of the transistor of the driving unit SN(N+Y) and at least one turn-on period t14 of the transistor of the driving unit EM(N) may not overlap, but the present invention is not limited thereto.

[0184] In one embodiment, the duration of a sensing frame TB may be greater than that of a display frame TA (TB>TA), but the present invention is not limited thereto. In one embodiment, when the duration of a sensing frame TB is greater than that of a display frame TA (TB>TA), the sensing frame TB may at least partially overlap with the next sensing frame TB, but the present invention is not limited thereto.

[0185] In another embodiment, the duration of a display frame TA may be greater than the duration of a sensing frame TB (TA>TB), and one display frame TA may at least partially overlap with multiple sensing frames TB.

[0186] In another embodiment, the duration of a sensing frame TB may be greater than the duration of a sensing frame TA (TB>TA), and a sensing frame TB may at least partially overlap with a plurality of display frames TA.

[0187] therefore, Figure 7 and Figure 8 The example is understandable.

[0188] Apart from Figure 7 In addition to the examples, the circuit structure of the electronic device 1 of the present invention can also have different implementation forms, which will be described in detail below (please refer to the following examples). Figure 4 or Figure 7 Examples are provided for reference only).

[0189] In one embodiment, the amplifying transistor ST1 of the sensing unit driving circuit 30 may be made of LTPS, while the reset transistor ST2 and the data transmission transistor ST3 may be made of IGZO. In this case, the driver unit SN_I(NX) is electrically connected to the control terminal cs2 of the reset transistor ST2 via transistor T7, and the driver unit SN_I(N) is electrically connected to the control terminal cs3 of the data transmission transistor ST3 via transistor T8. Therefore, the reset transistor ST2 can be driven by the driver unit SN_I(NX), while the data transmission transistor ST3 can be driven by the driver unit SN_I(N).

[0190] In one embodiment, the material of the amplifying transistor ST1 of the sensing unit driving circuit 30 may include LTPS, and the material of the reset transistor ST2 and the data transmission transistor ST3 may include IGZO. The electronic device 1 further includes a driving unit SN_I(N+Y). In this case, the driving unit SN_I(NX) can be electrically connected to the control terminal cs2 of the reset transistor ST2 via transistor T7, and the driving unit SN_I(N+Y) can be electrically connected to the control terminal cs3 of the data transmission transistor ST3 via transistor T8. Therefore, the reset transistor ST2 can be driven by the driving unit SN_I(NX), and the data transmission transistor ST3 can be driven by the driving unit SN_I(N+Y).

[0191] In one embodiment, the amplifying transistor ST1, reset transistor ST2, and data transmission transistor ST3 of the sensing unit driving circuit 30 are all made of LTPS. Therefore, in this embodiment, the material of the reset transistor ST2 can be different from that of the reset transistor T3. In this case, the driver unit SN(NX) can be electrically connected to the control terminal cs2 of the reset transistor ST2 via transistor T7, and the driver unit SN(N) can be electrically connected to the control terminal cs3 of the data transmission transistor ST3 via transistor T8. Therefore, the reset transistor ST2 can be driven by the driver unit SN(N), and the data transmission transistor ST3 can be driven by the driver unit SN_I(N).

[0192] In one embodiment, the amplifying transistor ST1 and the data transmission transistor ST3 of the sensing unit driving circuit 30 are made of LTPS, the reset transistor ST2 is made of IGZO, and the electronic device 1 may not include transistors T7 and T8. In this case, the electronic device 1 may include at least two driver units SN_I(NX), one of which drives the reset transistor T3 in the electronic unit driving circuit 20 and the other drives the reset transistor ST2 in the sensing unit driving circuit 30. Furthermore, the electronic device 1 may also include at least two driver units SN(N), one of which drives the data write transistor T2 in the electronic unit driving circuit 20 and the other drives the data transmission transistor ST3 in the sensing unit driving circuit 30.

[0193] In one embodiment, the amplifying transistor ST1, reset transistor ST2, and data transmission transistor ST3 of the sensing unit driving circuit 30 are all made of LTPS, and the electronic device 1 may not include transistors T7 and T8. In this case, the electronic device 1 may include a driver unit SN(NX) (not shown) for driving the reset transistor ST2 in the sensing unit driving circuit 30. Furthermore, the electronic device 1 may also include at least two driver units SN(N), one for driving the data write transistor T2 in the electronic unit driving circuit 20, and the other for driving the data transmission transistor ST3 in the sensing unit driving circuit 30.

[0194] Therefore, various implementation forms of the circuit structure of the electronic device 1 can be understood. It should be noted that the circuit structure of the present invention is not limited thereto.

[0195] The wiring arrangement of the reset transistors T2 and ST2 of the electronic device 1 of the present invention is Figure 6 In addition to the embodiment of the present invention, other changes may be provided, which will be described below.

[0196] Figure 9 is a schematic diagram of the wiring arrangement of the reset transistors T3 and ST2 of the electronic device 1 according to an embodiment of the present invention, and please also refer to Figures 1 to 8 To make the features clear, Figure 9 Only the wiring configuration of reset transistors T3 and ST2 is shown. The wiring configuration of other transistors can be referred to as Figure 6 The content of the example.

[0197] like Figure 9As shown, in one embodiment, the channel width W1-1 of the reset transistor T3 is different from the channel width W2-1 of the reset transistor ST2. In one embodiment, the channel width W1-1 of the reset transistor T3 may be greater than the channel width W2-1 of the reset transistor ST2 (W1-1>W2-1), but is not limited to this. In one embodiment, the channel length L1-1 of the reset transistor T3 is different from the channel length L2-1 of the reset transistor ST2. In one embodiment, the channel width L2-1 of the reset transistor ST2 may be greater than the channel length L1-1 of the reset transistor T3 (L2-1>L1-1), but is not limited to this. With the above configuration, the sensing unit driving circuit 30 of the present invention can have lower leakage current or improve sensing accuracy.

[0198] Figure 10 is a schematic diagram of the wiring arrangement of the reset transistors T3 and ST2 of the electronic device 1 according to another embodiment of the present invention, and please refer to Figures 1 to 9 To make the features clear, Figure 10 Only the wiring configuration of reset transistors T3 and ST2 is shown. The wiring configuration of other transistors can be referred to as Figure 6 The content of the example.

[0199] like Figure 10 As shown, the reset transistor ST2 may include a plurality of sub-transistors, such as a sub-transistor ST21 and a sub-transistor ST22, wherein the sub-transistor ST21 and the sub-transistor ST22 may be electrically connected, for example, connected in series. In one embodiment, the sub-conductive layer 41 may further include a gate 41c, wherein the sub-transistor ST21 may include gates 41b and 51, and ST22 may include gates 41c and 51. In addition, a portion of the first semiconductor 71 may serve as a channel for the sub-transistor ST21, and another portion of the first semiconductor 71 may serve as a channel for the sub-transistor ST22.

[0200] In one embodiment, the sub-transistor ST21 may have a channel length L2-1 and a channel width W2-1, and the sub-transistor ST22 may have a channel length L3-1 and a channel width W3-1. In one embodiment, at least one of the channel length L2-1 of the sub-transistor ST21 and the channel length L3-1 of the sub-transistor ST22 may be greater than the channel length L1-1 of the reset transistor T3 (L2-1 > L1-1, or L3-1 > L1-1, or L2-1 > L1-1 and L3-1 > L1-1). In one embodiment, at least one of the channel width W2-1 of the sub-transistor ST21 and the channel width W3-1 of the sub-transistor ST22 may be less than the channel width W1-1 of the reset transistor T3 (W2-1 < W1-1, or W3-1 < W1-1, or W2-1 < W1-1 and W3-1 < W1-1). With the above configuration, the sensing unit driving circuit 30 of the present invention may have a lower leakage current.

[0201] Figure 11 is a schematic diagram of the wiring configuration of the reset transistors T3 and ST2 of the electronic device 1 according to another embodiment of the present invention, and please also refer to Figures 1 to 10 . To make the features clear, Figure 11 only the wiring configuration of the reset transistors T3 and ST2 is shown, and the wiring configurations of the other transistors can be referred to Figure 6 the content of the example.

[0202] As Figure 11 shown, the semiconductor layer 70 may include a patterned portion 70p, and the first semiconductor 71 of the reset transistor ST2 and the second semiconductor 72 of the reset transistor T3 may share the patterned portion Figure 11 p. For example, when the materials of the first semiconductor 71 and the second semiconductor 72 are the same, such as both being IGZO, the first semiconductor 71 and the second semiconductor 72 may be connected together. In one embodiment, the reset transistor ST2 and the reset transistor T3 may share the same end, for example, may share the source electrode, and the other ends (such as the drain electrodes) of the reset transistor ST2 and the reset transistor T3 are respectively disposed in the sensing unit driving circuit 30 and the electronic unit driving circuit 20. In addition, the patterned portion 70p may extend to the sensing unit driving circuit 30 and be connected to the first semiconductor 71, and the patterned portion 70p may extend to the electronic unit driving circuit 20 and be connected to the second semiconductor 72.

[0203] Figure 12 is a schematic diagram of the wiring configuration of the reset transistors T3 and ST2 of the electronic device 1 according to another embodiment of the present invention, and please also refer to Figures 1 to 11 . To make the features clear, Figure 12 only the wiring configuration of the reset transistors T3 and ST2 is shown, and the wiring configurations of the other transistors can be referred to Figure 6 the content of the example.

[0204] like Figure 11 As shown, the semiconductor layer 70 may include a pattern portion 70p. The first semiconductor layer 71 of the reset transistor ST2 and the second semiconductor layer 72 of the reset transistor T3 may share the pattern portion 70p. In one embodiment, the reset transistor ST2 and the reset transistor T3 may share a common end, such as a source, while the other ends (e.g., drains) of the reset transistor ST2 and the reset transistor T3 are disposed in the sensing unit driving circuit 30 and the electronic unit driving circuit 20, respectively. Furthermore, a portion of the pattern portion 70p may extend into the sensing unit driving circuit 30 to form the first semiconductor layer 71, and a portion of the pattern portion 70p may extend into the electronic unit driving circuit 20 to form the second semiconductor layer 72. Thus, the reset transistor ST2 and the reset transistor T3 may share the same channel.

[0205] Therefore, various wiring configurations of the reset transistors T3 and ST2 are contemplated, and the present invention is not limited thereto.

[0206] Next, the structures of the reset transistors T3 and ST2 will be described.

[0207] Figure 13 1 is a cross-sectional view of reset transistors T3 and ST2 according to an embodiment of the present invention, wherein the left half is used to present at least a portion of the cross-sectional structure of the reset transistor T3, and the right half is used to present at least a portion of the cross-sectional structure of the reset transistor ST2.

[0208] like Figure 13 As shown, the electronic device 1 may include a plurality of insulating layers, such as insulating layers 91 to 99. The electronic device 1 may also include a drain electrode 101 and a source electrode 102. Figure 13 The positions of the drain electrode 101 and the source electrode 102 are merely examples, and in practice, their positions can be interchanged. In addition, the electronic device 1 may further include a drain electrode 111 and a source electrode 112. Figure 13 The positions of the drain electrode 111 and the source electrode 112 are merely examples, and their positions can actually be interchanged. In addition, the first semiconductor 71 can include a first sub-layer 711 and a second sub-layer 712 .

[0209] Regarding the reset transistor T3, in one embodiment, in the Z direction, the insulating layer 92 may be disposed on the insulating layer 91, the insulating layer 93 may be disposed on the insulating layer 92, the insulating layer 94 may be disposed on the insulating layer 93, the gate 42b and the insulating layer 95 may be disposed on the insulating layer 94, the second semiconductor 72 and the insulating layer 96 may be disposed on the gate 42b and the insulating layer 95, the gate 52b and the insulating layer 97 may be disposed on the second semiconductor 72 and the insulating layer 96, the drain electrode 101, the source electrode 102, and the insulating layer 98 may be disposed on the gate 52b and the insulating layer 97, and the insulating layer 99 may be disposed on the drain electrode 101, the source electrode 102, and the insulating layer 98. Furthermore, the drain electrode 101 may be electrically connected to the second semiconductor 72 via a conductive material 103, and the source electrode 102 may be electrically connected to the second semiconductor 72 via a conductive material 104.

[0210] Regarding the reset transistor ST2, in one embodiment, in the Z direction, the gate 41b and the insulating layer 95 may be disposed on the insulating layer 94; the first sublayer 711 of the first semiconductor 71, the second sublayer 712 of the first semiconductor 71, and the insulating layer 96 may be disposed on the gate 41b and the insulating layer 95; the second sublayer 712 may be disposed on the first sublayer 711; the gate 51b and the insulating layer 97 may be disposed on the first sublayer 711, the second sublayer 712, and the insulating layer 96; the drain electrode 111, the source electrode 112, and the insulating layer 98 may be disposed on the gate 51b and the insulating layer 97; and the insulating layer 99 may be disposed on the drain electrode 111, the source electrode 112, and the insulating layer 98. Furthermore, the drain electrode 111 may be electrically connected to the second sublayer 712 via a conductive material 113, and the source electrode 112 may be electrically connected to the second sublayer 712 via a conductive material 114.

[0211] In one embodiment, the material of the first semiconductor 71 and the second semiconductor 72 may include IGZO, wherein the electron mobility of the first sublayer 711 of the first semiconductor 71 is higher than the electron mobility of the second sublayer 712, but the present invention is not limited thereto. In one embodiment, the electron mobility of the first sublayer 711 of the first semiconductor 71 is higher than the electron mobility of the second semiconductor 72, but the present invention is not limited thereto.

[0212] In addition, in one embodiment, compared to Figure 13 For example, the first semiconductor 71 may also be adjusted to include another second sub-layer 712 (not shown), wherein in the Z direction, the first sub-layer 711 may be disposed between the two second sub-layers 712. The electron mobility of the first sub-layer 711 may be higher than the electron mobility of the two second sub-layers 712.

[0213] In addition, in one embodiment, compared to Figure 13For example, the first semiconductor 71 can also be adjusted such that in the Z direction, the first sub-layer 711 with higher electron mobility is disposed above the second sub-layer 712 with lower electron mobility.

[0214] Furthermore, in one embodiment, according to requirements, the second semiconductor 72 can also have multiple sub-layers similar to the aforementioned first semiconductor 71, and the electron mobility between these multiple sub-layers can be different. Alternatively, it can also be designed such that the second semiconductor 72 has multiple sub-layers while the first semiconductor 71 has a single layer.

[0215] Figure 14 It is a cross-sectional view of the reset transistors T3 and ST2 of another embodiment of the present invention. Figure 14 Some features of Figure 13 can be applied, so the following mainly focuses on the differences for description.

[0216] As Figure 14 shown, the reset transistor ST2 can further include an oxide-assisted semiconductor layer 713. In one embodiment, in the Z direction, the gate 41b, the oxide-assisted semiconductor layer 713, and the insulating layer 95 can be disposed above the insulating layer 94, where the oxide-assisted semiconductor layer 713 can be disposed above the insulating layer 95, and the first semiconductor 71 and the insulating layer 96 can be disposed above the gate 41b, the oxide-assisted semiconductor layer 713, and the insulating layer 95.

[0217] In one embodiment, in the Z direction, the oxide-assisted semiconductor layer 713 has a thickness d1, and the first semiconductor 71 has a thickness d2, where the thickness d1 of the oxide-assisted semiconductor layer 713 can be less than the thickness d2 of the first semiconductor 71 (d1 < d2), and it is not limited thereto. In one embodiment, the oxide component (such as concentration) of the oxide-assisted semiconductor layer 713 can be less than that of the first semiconductor 71, but it is not limited thereto. The oxide-assisted semiconductor layer 713 can supplement oxygen vacancies to the first semiconductor 71, so that the threshold voltage of the reset transistor ST2 can be more accurate, and thus leakage can be reduced.

[0218] In one embodiment, compared with Figure 14 the example, the oxide-assisted semiconductor layer 713 can also be adjusted to be disposed at the gate 51b, for example, it can be disposed below the gate 51b in the Z direction, but it is not limited thereto.

[0219] In one embodiment, according to requirements, it can also be designed such that the second semiconductor 72 has an oxide-assisted semiconductor layer while the first semiconductor 71 does not have an oxide-assisted semiconductor layer.

[0220] Figure 15 It is a cross-sectional view of the reset transistors T3 and ST2 of another embodiment of the present invention. Figure 15 Some features of Figure 14 Therefore, the following mainly describes the differences.

[0221] like Figure 15 As shown, the electronic device 1 may further include another oxide-assisted semiconductor layer 714. In the Z direction, the oxide-assisted semiconductor layer 713 may be disposed above the gate 41b, facing upward toward the first semiconductor 71, while the oxide-assisted semiconductor layer 714 may be disposed below the gate 51, facing downward toward the first semiconductor 71. Therefore, the threshold voltage of the reset transistor ST2 can be more accurately determined.

[0222] In one embodiment, according to needs, the second semiconductor 72 may be designed to include an oxide auxiliary semiconductor layer while the first semiconductor 71 may not include an oxide auxiliary semiconductor layer.

[0223] Therefore, the structures of the reset transistors T3 and ST2 are already understood. The present invention is not limited to the above-mentioned embodiment.

[0224] The electronic device 1 of the present invention may also have different circuit structures. For example, the data line DL and the data readout line RL may be integrated together. For example, the same signal line may be used to transmit a data signal or a sensing signal.

[0225] Figure 16 is a schematic diagram of the circuit structure of an electronic device 1 according to another embodiment of the present invention, and please refer to Figures 1 to 15 .

[0226] like Figure 16 As shown, the electronic device 1 may include a plurality of array units p, each of which may be, for example, an electronic unit driving circuit 20 or a sensing unit driving circuit 30 .

[0227] The electronic device 1 may further include a plurality of gate lines SL, each gate line SL being configured to transmit a driving signal, wherein a portion of the driving signal may be configured to drive the IGZO transistors in the electronic unit driving circuit 20 or the sensing unit driving circuit 30, such as, but not limited to, driving signals SSN_I(N-1), SSN_I(N), SSN_I(N+1), and SSN_I(N+2), and another portion of the driving signal may be configured to drive the LTPS transistors in the electronic unit driving circuit 20 or the sensing unit driving circuit 30, such as, but not limited to, driving signals SSN(N-1), SSN(N), SSN(N+1), and SSN(N+2). In one embodiment, each scan line SL can be electrically connected to one of the driving electronic unit driving circuits 20 and one of the sensing unit driving circuits 30 via one end of a transistor SW. For example, the scan line SL can be electrically connected to a first end of the transistor SW, and the first end of the transistor SW can be further electrically connected to one of the driving electronic unit driving circuit 20 and the sensing unit driving circuit 30, while the second end of the transistor SW can be electrically connected to the other of the driving electronic unit driving circuit 20 and the sensing unit driving circuit 30. Therefore, by turning the transistor SW on or off, it is possible to control whether the driving signal is transmitted to the driving electronic unit driving circuit 20 or the sensing unit driving circuit 30, but the present invention is not limited thereto.

[0228] The electronic device 1 may further include a plurality of integrated signal lines DR. Each integrated signal line DR may be used to transmit a data signal Data to the electronic unit driving circuit 20 and may be used to transmit a sensing signal from the sensing unit driving circuit 30. Therefore, each integrated signal line DR may be electrically connected to the plurality of electronic unit driving circuits 20 and the sensing unit driving circuit 30. In one embodiment, each integrated signal line DR may be electrically connected to a first terminal (e.g., drain / source) of a transistor CKDR, while the other terminal (e.g., source / drain) of the transistor CKDR may be electrically connected to an integrated control terminal DRM. Therefore, when the transistor CKDR is turned on, the data signal Data provided by the integrated control terminal DRM may be transmitted to the electronic unit driving circuit 20 via the transistor CKDR and the integrated signal line DR, or the sensing signal transmitted by the sensing unit driving circuit 30 may be transmitted to the integrated control terminal DRM via the integrated signal line DR and the transistor CKDR. The present invention is not limited thereto.

[0229] Furthermore, in one embodiment, the electronic unit driving circuit 20 may include a transistor MD, and the sensing unit driving circuit 30 may include a transistor MR. One end (e.g., drain or source) of transistor MD and one end (e.g., drain or source) of MR may be electrically connected to the integrated signal line DR, respectively. Therefore, in display mode, transistor MD can be turned on, allowing the electronic unit driving circuit 20 to receive the data signal Data from the integrated signal line DR, while transistor MR can be turned off, preventing the sensing unit driving circuit 30 from receiving the data signal Data. In sensing mode, transistor MR can be turned on, allowing the sensing unit driving circuit 30 to transmit the sensing signal via the integrated signal line DR, while transistor MD can be turned off, preventing the electronic unit driving circuit 20 from receiving the sensing signal. This allows for an integrated design of the data line DL and the data readout line RL. In one embodiment, the material of transistor MD or MR may include, but is not limited to, LTPS, IGZO, or holmium manganese oxide (HoMnO3, HMO).

[0230] Furthermore, in one embodiment, multiple integrated signal lines DR may share a single integrated control terminal DRM. For example, the integrated control terminal DRM may include a multiplexer (not shown) to simultaneously electrically connect to multiple integrated signal lines DR. In one embodiment, three integrated signal lines DR may share a single integrated control terminal DRM, but the present invention is not limited thereto. In one embodiment, the operating timing of each integrated control terminal DRM may be staggered through timing control, but the present invention is not limited thereto. In one embodiment, each integrated control terminal DRM may include at least one transistor (not shown). The material of the at least one transistor may include, but is not limited to, LTPS or HMO.

[0231] Figure 17 FIG. 1 is a schematic diagram of a circuit structure of an electronic device 1 according to another embodiment of the present invention. Figure 17 Some features of the example are applicable Figure 16 The following mainly describes the differences.

[0232] like Figure 17 As shown, each gate line SL of the electronic device 1 can be electrically connected to multiple electronic unit driving circuits 20 and sensing unit driving circuits 30 through a multiplexing method. For example, the gate line SLI corresponding to the IGZO transistor can be electrically connected to the multiple electronic unit driving circuits 20 through a multiplexer MI1, and can be electrically connected to the multiple sensing unit driving circuits 30 through a multiplexer MI2. The gate line SLL corresponding to the LTPS transistor can be electrically connected to the multiple electronic unit driving circuits 20 through a multiplexer ML1, and can be electrically connected to the multiple sensing unit driving circuits 30 through a multiplexer ML2.

[0233] In one embodiment, each gate line SL_I corresponding to an IGZO transistor can be electrically connected to a first end (e.g., drain or source) of a transistor SW1 and multiplexer MI1, while a second end of transistor SW1 can be electrically connected to multiplexer MI2. Therefore, by controlling the on / off state of transistor SW1, it is possible to determine whether the driving signal transmitted by gate line SLI enters multiplexer MI1 or multiplexer MI2, thereby driving the electronic unit driving circuit 20 or the sensing unit driving circuit 30. In one embodiment, multiplexer MI1 can include multiple transistors (e.g., CKI1, CKI2, and CKI3, but not limited thereto), each electrically connected to a different electronic unit driving circuit 20. In one embodiment, multiplexer MI2 can include multiple transistors (e.g., CKIS1, CKIS2, and CKIS3, but not limited thereto), each electrically connected to a different sensing unit driving circuit 30.

[0234] In one embodiment, each gate line SLL corresponding to a LTPS transistor can be electrically connected to a first end (e.g., drain or source) of a transistor SW2 and multiplexer ML1, while a second end (e.g., source or drain) of transistor SW2 can be electrically connected to multiplexer ML2. Therefore, by controlling the on / off state of transistor SW2, it is possible to determine whether the driving signal transmitted by gate line SLL enters multiplexer ML1 or multiplexer ML2, thereby driving the electronic unit driving circuit 20 or the sensing unit driving circuit 30, but the present invention is not limited thereto. In one embodiment, multiplexer ML1 can include multiple transistors (e.g., CKL1, CKL2, CKL3, but the present invention is not limited thereto), each electrically connected to a different electronic unit driving circuit 20. In one embodiment, multiplexer ML2 can include multiple transistors (e.g., CKLS1, CKLS2, CKLS3, but the present invention is not limited thereto), each electrically connected to a different sensing unit driving circuit 30.

[0235] In one embodiment, the material of transistor SW1 or SW2 may include LTPS, IGZO or HMO, but is not limited thereto. In one embodiment, multiplexer MI1, MI2, ML1 or ML2 may include multiple transistors, wherein the material of the transistors may include LTPS or HMO, but is not limited thereto.

[0236] In addition, in this embodiment, the electronic unit driving circuit 20 can be electrically connected to the data line DL, and the sensing unit driving circuit 30 can be electrically connected to the data readout line RL. However, in other embodiments, the electronic unit driving circuit 20 can be electrically connected to the data line DL, and the sensing unit driving circuit 30 can be electrically connected to the data readout line RL. Figure 16 The structure allows the data line DL and the data readout line RL to be integrated into the integrated signal line DR, but is not limited thereto.

[0237] Therefore, different implementations of the circuit structure of the electronic device 1 of the present invention have been understood. It should be noted that the present invention is not limited thereto.

[0238] In one embodiment, the present invention can at least determine whether the product in question falls within the scope of protection of the present invention by observing the presence or absence of components, component configuration, mechanism observation and / or operation mode, but is not limited thereto.

[0239] The details or features of the various embodiments of the present invention may be mixed and matched as desired as long as they do not violate the spirit of the invention or conflict with each other.

[0240] Therefore, the present invention can provide an electronic device with display function and sensing function. Since the display circuit and the sensing circuit can be integrated together, the electronic device of the present invention can provide a high-resolution display function and a high-precision sensing function.

[0241] The above embodiments are merely examples for the convenience of explanation. The scope of rights claimed by the present invention shall be based on the scope of the patent application, and shall not be limited to the above embodiments.

Claims

1. An electronic device, characterized in that: include: a substrate; A first conductive layer is disposed on the substrate and includes a first gate and a line segment, wherein the line segment is connected to the first gate; an electronic unit and a sensing unit, respectively disposed on the substrate; and a sensing unit driving circuit, disposed on the substrate and electrically connected to the electronic unit and the sensing unit; The sensing unit driving circuit includes a first transistor having the first gate, and a contour of the first gate is different from a contour of the line segment.

2. The electronic device according to claim 1, wherein: The difference between the outline of the first gate and the outline of the line segment means that a width of the first gate is different from a width of the line segment.

3. The electronic device according to claim 2, wherein: A ratio of the width of the line segment to the width of the first gate satisfies the equation: 0.3 times the width of the first gate<the ratio<0.7 times the width of the first gate.

4. The electronic device according to claim 1, wherein: Also includes: A semiconductor layer and an electronic unit driving circuit are respectively arranged on the substrate, and the electronic unit driving circuit includes a second transistor, which is electrically connected to the electronic unit, wherein the semiconductor layer includes a pattern portion, the first transistor includes a first semiconductor, the second transistor includes a second semiconductor, and the first semiconductor and the second semiconductor share the pattern portion.

5. The electronic device according to claim 4, wherein: The material of the semiconductor layer includes metal oxide.

6. The electronic device according to claim 1, wherein: Also includes: A second conductive layer is disposed on the first conductive layer, wherein the second conductive layer includes a second gate, and the first transistor has the second gate, and the second gate of the first transistor at least partially overlaps with the first gate of the first transistor.

7. The electronic device according to claim 6, wherein: The profile of the first gate is different from a profile of the second gate.

8. The electronic device according to claim 7, wherein: The difference between the profile of the first gate and the profile of the second gate means that a width of the first gate is different from a width of the second gate.

9. The electronic device according to claim 1, wherein: Also includes: An electronic unit driving circuit is disposed on the substrate, wherein the first conductive layer includes a second gate, and the electronic driving circuit includes a second transistor having the second gate, and a contour of the second gate is different from the contour of the line segment.

10. The electronic device according to claim 9, wherein: Also includes: A third transistor is disposed on the substrate, wherein the electronic device further includes an active region and a peripheral region, the peripheral region is adjacent to the active region, the sensing unit driving circuit and the electronic unit driving circuit are disposed in the active region, the third transistor is disposed in the peripheral region, and the third transistor controls a signal to the first transistor and the second transistor.

11. The electronic device according to claim 10, wherein: Also includes: A fourth transistor is disposed on the substrate, wherein the fourth transistor is electrically connected between the first transistor and the second transistor, and the signal is transmitted to the first transistor through the fourth transistor.

12. The electronic device according to claim 9, wherein: The line segment is connected to the second gate.

13. The electronic device according to claim 1, wherein: Also includes: An electronic unit driving circuit is disposed on the substrate. The electronic unit driving circuit includes a second transistor electrically connected to the electronic unit. The electronic device further includes a third transistor and a fourth transistor, each disposed on the substrate. The electronic device further includes an active region and a peripheral region. The sensing unit driving circuit and the electronic unit driving circuit are disposed in the active region. The third transistor and the fourth transistor are disposed in the peripheral region. The third transistor controls a first signal to the first transistor, and the fourth transistor controls a second signal to the second transistor.

14. The electronic device according to claim 13, wherein: The first signal is a reset signal, and the second signal is a switch signal.

15. The electronic device according to claim 14, wherein: Also includes: A fifth transistor is disposed on the substrate and located in the peripheral area, wherein the sensing unit driving circuit includes a sixth transistor, the fifth transistor controls a readout signal to the sixth transistor during a plurality of first turn-on periods, and the fourth transistor controls the switching signal to the second transistor during a plurality of second turn-on periods, and at least one of the plurality of first turn-on periods does not overlap with at least one of the plurality of second turn-on periods.

16. The electronic device according to claim 1, wherein: Also includes: A second conductive layer and an electronic unit driving circuit are respectively disposed on the substrate. The second conductive layer includes a second gate. The electronic unit driving circuit includes a second transistor. The second transistor has the second gate. The second gate is electrically connected to the electronic unit.

17. The electronic device according to claim 16, wherein: A profile of the second gate is different from the profile of the line segment.

18. The electronic device according to claim 17, wherein: The fact that a profile of the second gate is different from the profile of the line segment means that a width of the second gate is smaller than a width of the line segment.

19. The electronic device according to claim 16, wherein: The first transistor and the second transistor include semiconductors of different materials.

20. The electronic device according to claim 16, wherein: Also includes: Another conductive layer is disposed on the substrate, wherein the other conductive layer includes a connecting portion, and the first grid and the second grid are electrically connected through the connecting portion.

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