Calculation instruction execution method and device, electronic equipment, medium and product

Abstract

The invention provides a calculation instruction execution method and device, electronic equipment, a medium and a product, and relates to the field of artificial intelligence, in particular to the field of chips. According to the specific implementation scheme, a to-be-executed target calculation instruction is obtained; when the target calculation instruction meets a read-after-write condition for the target single-bit register, continuously constructing two target transmission instructions according to a current bit value in the target single-bit register; and respectively transmitting the two target transmitting instructions to an arithmetic logic unit to carry out calculation to obtain two calculation results, so that a target register in the target calculation instruction selects a correct calculation result from the two calculation results to complete data writing operation. When the read-after-write condition is met, two target transmitting instructions are constructed according to the current value of the target single-bit register and transmitted to the arithmetic logic unit for calculation, and a correct result is selected and written by the target register, so that the degree of dependence on the single-bit register is reduced, and the parallelism and efficiency of instruction execution are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence, in particular to the field of chip technology, and specifically to a method for executing a computing instruction, a device for executing a computing instruction, an electronic device, a non-transitory computer-readable storage medium, and a computer program product. Background Art

[0002] With the development of artificial intelligence, big data analysis and high-performance computing, computing-intensive applications and complex data processing scenarios continue to emerge, and data computing needs are becoming increasingly large and complex, which puts higher requirements on the execution efficiency of computing instructions.

[0003] During operations, processors often have single-bit registers that are frequently used as source registers to provide data or as destination registers to receive new data. However, when a read-after-write condition occurs, that is, after a register is used as a destination register, subsequent instructions requiring that register as a source operand must passively wait for the previous operation to complete and write the correct value before proceeding.

[0004] In the process of implementing the present disclosure, the inventors discovered that the related technology has the following defects: the related technology can only detect registers that meet the write-after-read condition, and cannot fundamentally avoid the performance overhead caused by the write-after-read of single-bit registers, thereby reducing processor performance and instruction execution efficiency. Summary of the Invention

[0005] The present disclosure provides a method for executing a computing instruction, an apparatus for executing a computing instruction, an electronic device, a non-transitory computer-readable storage medium, and a computer program product.

[0006] According to one aspect of the present disclosure, a method for executing a computing instruction is provided, the method being executed by an instruction buffer, the method comprising:

[0007] Obtain target computing instructions to be executed;

[0008] When the target computation instruction satisfies a read-after-write condition for a target single-bit register, constructing two target emission instructions consecutively according to a current bit value in the target single-bit register;

[0009] Wherein, the two target transmission instructions respectively include a current bit value and a negated value of the current bit value;

[0010] The two target issuance instructions are respectively issued to the arithmetic logic unit to perform calculations, and two calculation results are obtained, so that the destination register in the target calculation instruction selects a correct calculation result from the two calculation results to complete the data writing operation.

[0011] According to another aspect of the present disclosure, a method for executing a computing instruction is provided, the method being executed by an arithmetic logic unit, the method comprising:

[0012] receiving two target-issue instructions from an instruction buffer for the same target-compute instruction;

[0013] The source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register;

[0014] Calculation is performed on the two target emission instructions respectively to obtain two calculation results, so that the destination register in the target calculation instruction selects a correct calculation result from the two calculation results to complete the data writing operation.

[0015] According to another aspect of the present disclosure, a method for executing a computing instruction is provided, wherein the method is executed by a general register, and the method comprises:

[0016] receiving two calculation results obtained by the arithmetic logic unit from two target transmission instructions for the same target calculation instruction;

[0017] The general register is a destination register in the target calculation instruction, and the source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register;

[0018] A correct calculation result is selected from the two calculation results according to the current bit value of the target single-bit register.

[0019] According to another aspect of the present disclosure, there is provided instruction execution hardware, comprising an instruction buffer, a general register, a single-bit register, a scoreboard module, and an arithmetic logic unit, wherein:

[0020] The instruction buffer is used to execute the method for executing a computing instruction executed by the instruction buffer according to any one of the embodiments of the present disclosure;

[0021] The general register is used to store operands and execute the execution method of the computing instruction executed by the general register according to any one of the embodiments of the present disclosure;

[0022] The single-bit register is used to store a single-bit value;

[0023] The scoreboard module is used to set whether the general register and the single-bit register are in a dependent state;

[0024] The arithmetic logic unit is used to execute the execution method of the calculation instruction executed by the arithmetic logic unit as described in any one of the embodiments of the present disclosure.

[0025] According to another aspect of the present disclosure, an electronic device is provided, comprising the instruction execution hardware described in any one of the embodiments of the present disclosure.

[0026] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable a computer to execute the method for executing the computing instructions described in any one of the embodiments of the present disclosure.

[0027] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0029] Figure 1 is a schematic diagram of a method for executing a computing instruction provided according to an embodiment of the present disclosure;

[0030] Figure 2 is a schematic diagram of another method for executing a computing instruction provided according to an embodiment of the present disclosure;

[0031] Figure 3 is a schematic diagram of another method for executing a computing instruction provided according to an embodiment of the present disclosure;

[0032] Figure 4 is a schematic diagram of another method for executing a computing instruction provided according to an embodiment of the present disclosure;

[0033] Figure 5 is a schematic diagram of another method for executing a computing instruction provided according to an embodiment of the present disclosure;

[0034] Figure 6 is a schematic diagram of another method for executing a computing instruction provided according to an embodiment of the present disclosure;

[0035] Figure 7 is a schematic diagram of a device for executing a computing instruction according to an embodiment of the present disclosure;

[0036] Figure 8 is a schematic diagram of another device for executing computing instructions provided according to an embodiment of the present disclosure;

[0037] Figure 9 is a schematic diagram of another device for executing a computing instruction provided according to an embodiment of the present disclosure;

[0038] Figure 10 is a schematic diagram of instruction execution hardware provided according to an embodiment of the present disclosure;

[0039] Figure 11 The block diagram is a block diagram of an electronic device used to implement the method for executing computing instructions according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0041] Figure 1 This is a schematic diagram of a method for executing a computing instruction according to an embodiment of the present disclosure. This embodiment of the present disclosure is applicable to executing computing instructions when a read-after-write condition is met. The method can be performed by a computing instruction execution device, which can be implemented in hardware and generally configured in an instruction buffer. Specifically, an instruction buffer can be understood as a hardware component located at the front end of a processor's instruction pipeline that temporarily stores instructions and provides a continuous instruction stream for the instruction decoding and execution stages.

[0042] Correspondingly, such as Figure 1 As shown, the method may specifically include:

[0043] S110: Obtain target computing instructions to be executed.

[0044] Specifically, when an instruction is needed during the execution of the instruction pipeline, the instruction buffer obtains the target computing instruction to be executed, ensuring the smooth progress of the instruction pipeline. There is no need to obtain the instruction from the memory every time, which improves the access speed of the instruction and ensures the continuity of instruction execution.

[0045] S120. When the target computing instruction satisfies a read-after-write condition for a target single-bit register, continuously construct two target issuing instructions according to a current bit value in the target single-bit register.

[0046] The two target transmission instructions respectively include a current bit value and an inverse value of the current bit value.

[0047] In the disclosed embodiments, read-after-write can be specifically understood as a situation where the data required by one instruction involves reading data written by another instruction but not yet written. Generally speaking, in a read-after-write situation, a subsequent read instruction must wait for the previous write instruction to complete before obtaining the correct data.

[0048] The method for judging the read-after-write condition can be: since the processor monitors the usage status of registers through the register allocator and the tracking unit, the processor can obtain the usage status between registers, judge the dependency, and identify the read-after-write status; since the instruction scheduler considers the dependency between instructions when arranging the instruction execution order and marks it, the dependency between instructions can be identified by obtaining the mark, and the read-after-write status can be judged; since the execution unit also provides feedback information on the usage status of registers to the control unit when executing instructions, the usage status of registers can be identified by obtaining the feedback information, the dependency can be identified, and it can be judged whether the read-after-write condition is met.

[0049] A single-bit register can be specifically understood as a register that can store a single binary bit, that is, it can only store 0 or 1. It can include: a 0 value judgment register, a negative value judgment calculator, a carry flag register, an overflow flag register, an interrupt enable flag register, a direction flag register, and a task priority flag register, etc.

[0050] Specifically, when a target computation instruction needs to read the value of a target single-bit register that was written by a previous instruction but has not yet been written, the system determines whether the write-after-read condition for the target single-bit register is met. Based on the current bit value stored in the target single-bit register (assuming it is b), the system constructs two target emission instructions. The first instruction uses the current bit value b for computation, while the second instruction uses the inverse of b (i.e., 1-b) for computation.

[0051] S130, respectively transmit the two target transmit instructions to the arithmetic logic unit to perform calculations, and obtain two calculation results, so that the destination register in the target calculation instruction can select the correct calculation result from the two calculation results to complete the data writing operation.

[0052] Specifically, the two constructed instructions are respectively sent to the arithmetic logic unit for calculation. These two instructions can respectively assume that the values ​​of the single-bit register are 0 and 1 (the single-bit register has only these two possible values), ensuring that no matter what the actual value of the single-bit register is, two possible results can be calculated. The arithmetic logic unit calculates these two instructions and obtains two different results. One result is a calculation result based on the value of the single-bit register being 0, and the other result is a calculation result based on the value of the single-bit register being 1. The destination register in the target calculation instruction selects the correct calculation result from the two calculation results based on the actual value of the single-bit register, and performs a data write operation.

[0053] Based on this, the technical solution of the embodiment of the present disclosure obtains the target calculation instruction to be executed; when the target calculation instruction meets the write-after-read condition for the target single-bit register, two target emission instructions are continuously constructed according to the current bit value in the target single-bit register; the two target emission instructions are respectively emitted to the arithmetic logic unit to perform calculations, and two calculation results are obtained, so that the destination register in the target calculation instruction can select the correct calculation result from the two calculation results to complete the data writing operation. When the write-after-read condition is met, two target emission instructions are constructed according to the current value of the target single-bit register, and are emitted to the arithmetic logic unit for calculation, and the correct result is selected by the destination register to be written, thereby avoiding the instruction execution delay caused by waiting for the register write to be completed, reducing the dependence on the single-bit register, and enabling instructions that were originally executed serially due to the dependency relationship to be processed in parallel, thereby improving the parallelism of instruction execution, improving processor performance and instruction execution efficiency, and without adding too much new calculation logic, and will not increase hardware resource costs such as transistor area.

[0054] Figure 2 This is a schematic diagram of another method for executing a computing instruction provided according to an embodiment of the present disclosure. This embodiment refines the "target computing instruction satisfies the write-after-read condition for the target single-bit register" in the above embodiment, and specifically may include: identifying the source register and the destination register in the target computing instruction, and detecting the dependent status of the source register and the destination register in real time; when the source register includes the target single-bit register, and it is detected in real time that only the target single-bit register is in the dependent state, determining that the target computing instruction satisfies the write-after-read condition for the target single-bit register.

[0055] Correspondingly, such as Figure 2 As shown, the method may specifically include:

[0056] S210: Obtain target computing instructions to be executed.

[0057] S220 , identifying a source register and a destination register in the target computing instruction, and detecting dependency states of the source register and the destination register in real time.

[0058] In the disclosed embodiments, a source register can be specifically understood as a register that stores data required for instruction execution and is used to provide operands in the instruction. A destination register can be specifically understood as a register used to store the result of instruction execution in the instruction. A dependent state can be specifically understood as the state in which a register's value needs to be written but has not yet been written.

[0059] Specifically, the target computing instruction is parsed, the source register and the destination register in the instruction are identified, and the usage status of the source register and the destination register is obtained through the processor to determine the dependency relationship. Alternatively, the dependency relationship between the source register and the destination register can be identified by obtaining the mark added by the instruction scheduler, or the usage status of the source register and the destination register can be identified by obtaining feedback information to identify the dependency relationship.

[0060] Optionally, based on the above embodiments, detecting the dependency status of the source register and the destination register in real time may include:

[0061] The dependent registers set in the scoreboard module are detected in real time to obtain the dependent states of the source register and the destination register.

[0062] In the embodiment of the present disclosure, the scoreboard module can be specifically understood as: a module for tracking and recording the usage status of each register, such as the dependent state of the register. Among them, a state table can be maintained in the scoreboard module, and one or more state bits are set for each register in the state table. The dependent state of the register is identified by setting a set status bit for the register in the data write state, that is, when the register is in the data write state (that is, its value is about to be updated), the corresponding status bit will be set to a specific value (for example, set to 1) to indicate that the register is currently in the dependent state. Conversely, when the value of the register has been updated and can be read, the status bit will be reset to another value (for example, reset to 0), indicating that the register is no longer in the dependent state. During the execution of instructions, this state table will be updated and queried in real time.

[0063] Specifically, at different stages of instruction execution, the processor will query the status bits in the scoreboard module in real time to determine the current status of the source register and the destination register, and perform a read-after-write condition judgment operation. By setting the status bit of the register when it is in the data write state, the dependent state is identified. And by monitoring the set status bits of the source register and the destination register in the scoreboard module in real time to detect the dependent state, it is possible to timely grasp the usage of the registers and perform a read-after-write condition judgment operation. When the read-after-write condition is met, the instructions that were originally executed serially due to the dependency relationship can be processed in parallel, reducing the delay caused by the dependency relationship, optimizing instruction scheduling, improving the execution efficiency of the processor, and ensuring data consistency and correctness.

[0064] S230. When the source register includes a target single-bit register and it is detected in real time that only the target single-bit register is in a dependent state, when it is determined that the target calculation instruction meets the write-after-read condition for the target single-bit register, two target emission instructions are continuously constructed according to the current bit value in the target single-bit register.

[0065] The two target transmission instructions respectively include a current bit value and an inverse value of the current bit value.

[0066] Specifically, if the source register includes the target single-bit register, and only this register is in a dependent state, that is, the subsequent instruction needs to read the unwritten value of this register, it is determined that the target computing instruction has a write-after-read dependency. In order to reduce the delay caused by waiting for the target single-bit register value to be determined, two target emission instructions are constructed continuously based on the current bit value of the target single-bit register. One instruction uses the current bit value (assuming it is b), and the other instruction uses the inverted value of this bit value (i.e., 1-b).

[0067] Optionally, based on the above embodiments, continuously constructing two target transmit instructions according to the current bit value in the target single-bit register may include:

[0068] Obtaining a current bit value from the target single-bit register and obtaining other operands from at least one general register included in the target computation instruction;

[0069] A first target issue instruction is constructed according to the current bit value and the other operands, and a second target issue instruction is constructed according to the inverted value of the current bit value and the other operands.

[0070] Specifically, the currently stored bit value of the target single-bit register is read, and other operands are obtained from at least one general register specified in the target calculation instruction. The other operands can be used to perform calculations together with the current bit value. A first target emission instruction is constructed using the obtained current bit value and other operands. The first target emission instruction causes the arithmetic logic unit to perform calculations based on the current bit value. A second target emission instruction is constructed using the inverted value of the current bit value and other operands. The second target emission instruction causes the arithmetic logic unit to perform calculations based on the inverted bit value.

[0071] In a specific example, assume that the current value of the target single-bit register is 0 and the other operand is 5 (from the general register specified in the target calculation instruction). Two target-issue instructions are constructed: the first target-issue instruction uses the bit value 0 and the operand 5 to perform a calculation, such as "5+0". The second target-issue instruction uses the inverted value of the bit value 1 and the operand 5 to perform a calculation, such as "5+1".

[0072] By constructing two target-issue instructions simultaneously, possible calculation results can be prepared in advance. Regardless of the final value of the target single-bit register, the correct result can be obtained immediately, avoiding instruction execution delays caused by waiting for register writes to complete. This reduces the reliance on single-bit registers and enables parallel processing of instructions that were originally executed serially due to dependencies, thereby improving the parallelism of instruction execution and enhancing processor performance and instruction execution efficiency.

[0073] Optionally, based on the above embodiments, constructing a first target emission instruction according to the current bit value and the other operands, and constructing a second target emission instruction according to the inverted value of the current bit value and the other operands, further includes:

[0074] In the first target transmit instruction, a first flag bit that matches the current bit value is added, and in the second target transmit instruction, a second flag bit that matches the inverse value of the current bit value is added;

[0075] When the arithmetic logic unit obtains a first calculation result by issuing an instruction for the first target, the arithmetic logic unit adds the first identification bit to the first calculation result; when the arithmetic logic unit obtains a second calculation result by issuing an instruction for the second target, the arithmetic logic unit adds the second identification bit to the second calculation result;

[0076] The first flag bit and the second flag bit are used for the destination register to select a correct calculation result from the first calculation result and the second calculation result.

[0077] Specifically, when constructing the first target emission instruction, a first identification bit that matches the current bit value is added (for example, if the current bit value is 0, the first identification bit can be a specific tag value, such as 0). Correspondingly, when constructing the second target emission instruction, a second identification bit that matches the inverted value of the current bit value is added (for example, if the current bit value is 0, then the inverted value is 1, and the second identification bit can be another specific tag value, such as 1).

[0078] Accordingly, when the arithmetic logic unit executes these two target-issue instructions, for the first target-issue instruction, the arithmetic logic unit adds a first flag to the calculation result, and for the second target-issue instruction, the arithmetic logic unit adds a second flag to the calculation result. The flag is used to select the correct calculation result for the subsequent destination register. When the result needs to be written to the destination register, the flag is matched against the actual current value of the target single-bit register, thereby selecting the correct calculation result for writing.

[0079] By adding identification bits that match the current bit value and its inverted value when constructing two target emission instructions, the arithmetic logic unit can add the corresponding identification bits to the result when obtaining the calculation result, so that when the destination register selects the correct calculation result, it can select the result by judging whether the identification bit matches the current actual value of the target single-bit register, thereby ensuring the correctness of the written calculation result, avoiding the instruction execution delay caused by waiting for the register write to be completed, reducing the dependence on the single-bit register, improving the instruction execution efficiency, and simplifying the correct result selection mechanism.

[0080] S240. The two target transmit instructions are respectively transmitted to the arithmetic logic unit for performing calculations to obtain two calculation results, so that the destination register in the target calculation instruction can select a correct calculation result from the two calculation results to complete the data writing operation.

[0081] Optionally, based on the above embodiments, the two target transmit instructions are respectively transmitted to an arithmetic logic unit for calculation, further comprising:

[0082] Setting the dependent state of the destination register in the scoreboard module;

[0083] The two target issuance instructions are issued sequentially to the arithmetic logic unit for calculation.

[0084] Specifically, when two target-issue instructions need to be sent to the ALU for calculation, the scoreboard module sets the destination register's dependent state, indicating that a new value is about to be written to the destination register. Subsequent instructions that need to read the register's value must wait for the destination register to select the correct result from the two calculation results before completing the write operation. After setting the destination register's dependent state, the two target-issue instructions are sequentially sent to the ALU for calculation.

[0085] By setting the dependent state of the destination register in the scoreboard module, it is ensured that subsequent instructions will not read the value of the register before the current instruction completes the write operation, thereby ensuring the consistency and correctness of the data. Two target emission instructions are sent to the arithmetic logic unit in sequence, ensuring the orderly execution of instruction calculations and avoiding conflicts and confusion between instructions.

[0086] Based on this, the technical solution of the embodiment of the present disclosure obtains the target calculation instruction to be executed; identifies the source register and the destination register in the target calculation instruction, and detects the dependent status of the source register and the destination register in real time; when the source register includes the target single-bit register, and it is detected in real time that only the target single-bit register is in the dependent state, when it is determined that the target calculation instruction meets the write-after-read condition for the target single-bit register, two target emission instructions are continuously constructed according to the current bit value in the target single-bit register; the two target emission instructions are respectively emitted to the arithmetic logic unit to perform calculations, and two calculation results are obtained, so that the destination register in the target calculation instruction can select the correct calculation result from the two calculation results to complete the data write operation. By identifying the source register and the destination register and detecting their dependent states in real time, it is determined whether only the target single-bit register is in the dependent state, thereby determining whether the write-after-read condition is met, and taking optimization measures for the write-after-read situation of the single-bit register, reducing the impact on the execution of subsequent instructions, and improving processing efficiency. When the write-after-read condition is met, two target emission instructions are constructed according to the current value of the target single-bit register and emitted to the arithmetic logic unit for calculation. The correct result is selected by the destination register and written, thereby avoiding the instruction execution delay caused by waiting for the register write to be completed, reducing the dependence on the single-bit register, and allowing instructions that were originally executed serially due to dependencies to be processed in parallel, thereby improving the parallelism of instruction execution, enhancing processor performance and instruction execution efficiency, without adding too much new calculation logic, and not increasing hardware resource costs such as transistor area.

[0087] Figure 3This is a schematic diagram of another method for executing a computation instruction according to an embodiment of the present disclosure. This embodiment of the present disclosure is applicable to executing a computation instruction when a read-after-write condition is met. This method can be performed by a computation instruction execution device, which can be implemented in hardware and generally configured in an arithmetic logic unit (ALU). Specifically, the ALU can be understood as a component within a processor that performs arithmetic and logical operations.

[0088] Correspondingly, such as Figure 3 As shown, the method may specifically include:

[0089] S310: Receive two target transmit instructions sent by the instruction buffer for the same target compute instruction.

[0090] The source register in the target calculation instruction includes a target single-bit register; and the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register.

[0091] S320 , respectively performing calculations on the two target transmit instructions to obtain two calculation results, so that the destination register in the target calculation instruction can select a correct calculation result from the two calculation results to complete the data writing operation.

[0092] Specifically, the arithmetic logic unit receives two instructions sent by the instruction buffer for the same target computing instruction. Both instructions are generated based on the same target computing instruction, and the source register of the target computing instruction includes a single-bit register. The two instructions cause the arithmetic logic unit to perform a calculation using two possible values ​​(0 and 1) of the target single-bit register, thereby obtaining two calculation results. The destination register in the target computing instruction selects the correct calculation result from the two calculation results based on the actual value of the single-bit register and performs a data write operation.

[0093] Based on this, the technical solution of the embodiment of the present disclosure receives two target emission instructions sent by the instruction buffer for the same target calculation instruction; performs calculations on the two target emission instructions respectively to obtain two calculation results, so that the destination register in the target calculation instruction can select the correct calculation result from the two calculation results to complete the data write operation. The arithmetic logic unit performs calculations on the two received target emission instructions respectively to obtain two calculation results, and the destination register selects the correct result to complete the data write operation. It can continue to execute subsequent instructions without waiting for the previous instruction to complete the write operation, avoiding the instruction execution delay under the write-after-read condition, reducing the dependence on single-bit registers, and allowing instructions that were originally executed serially due to dependencies to be processed in parallel, thereby improving the parallelism of instruction execution, improving processor performance and instruction execution efficiency, and without adding too much new calculation logic, and will not increase hardware resource costs such as transistor area.

[0094] Figure 4 It is a schematic diagram of another method for executing a calculation instruction provided according to an embodiment of the present disclosure. This embodiment refines the "performing calculations on two target launch instructions respectively to obtain two calculation results" in the above embodiment, and can specifically include: performing calculations on the first target launch instruction of the two target launch instructions to obtain a first calculation result, and performing calculations on the second target launch instruction of the two target launch instructions to obtain a second calculation result; extracting a first identification bit from the first target launch instruction, and adding the first identification bit to the first calculation result; extracting a second identification bit from the second target launch instruction, and adding the second identification bit to the second calculation result; wherein, the first identification bit is used to identify a bit value of the target single-bit register used in the first target launch instruction, and the second identification bit is used to identify another bit value of the target single-bit register used in the second target launch instruction.

[0095] Correspondingly, such as Figure 4 As shown, the method may specifically include:

[0096] S410: Receive two target transmit instructions sent by the instruction buffer for the same target compute instruction.

[0097] The source register in the target calculation instruction includes a target single-bit register; and the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register.

[0098] S420. Calculate the first target launch instruction of the two target launch instructions to obtain a first calculation result, and calculate the second target launch instruction of the two target launch instructions to obtain a second calculation result.

[0099] S430: Extract a first identification bit from the first target transmission instruction, and add the first identification bit to the first calculation result.

[0100] S440. Extract a second identification bit from the second target transmit instruction, and add the second identification bit to the second calculation result, so that the destination register in the target calculation instruction selects a correct calculation result from the two calculation results to complete the data write operation.

[0101] The first identification bit is used to identify a bit value of the target single-bit register used in the first target emission instruction, and the second identification bit is used to identify another bit value of the target single-bit register used in the second target emission instruction.

[0102] Specifically, the arithmetic logic unit calculates the first target transmit instruction to obtain a first calculation result, and calculates the second target transmit instruction to obtain a second calculation result. A first identification bit is extracted from the first target transmit instruction, and the first identification bit indicates which specific value of the target single-bit register is used for the calculation by the first target transmit instruction. Similarly, another second identification bit is extracted from the second target transmit instruction, indicating that the second target transmit instruction uses another bit value of the inverted value of the target single-bit register for calculation.

[0103] The extracted first identification bit is added to the first calculation result, so that the first calculation result includes not only the numerical result of the calculation, but also a mark used to indicate which value of the target single-bit register the calculation result is calculated based on. Similarly, the second identification bit is added to the second calculation result, so that the second calculation result includes not only the numerical result of the calculation, but also a mark used to indicate which value of the target single-bit register the calculation result is calculated based on, so that the destination register can decide which result to select by comparing the identification bit in the calculation result with the actual current value of the target single-bit register. If the actual value of the target single-bit register matches the first identification bit, the first calculation result is selected; if it matches the second identification bit, the second calculation result is selected.

[0104] Based on this, the technical solution of the embodiment of the present disclosure receives two target emission instructions sent by the instruction buffer for the same target calculation instruction; performs calculation on the first target emission instruction of the two target emission instructions to obtain a first calculation result, and performs calculation on the second target emission instruction of the two target emission instructions to obtain a second calculation result; extracts the first identification bit from the first target emission instruction and adds the first identification bit to the first calculation result; extracts the second identification bit from the second target emission instruction and adds the second identification bit to the second calculation result, so that the destination register in the target calculation instruction selects the correct calculation result from the two calculation results to complete the data write operation. The arithmetic logic unit calculates the two received target transmission instructions separately to obtain two calculation results, and adds an identification bit to each result to distinguish the value of the single-bit register used. This can ensure that the destination register selects the accurate result according to the correct identification to complete the data write operation, thereby ensuring data correctness. The processor can continue to execute subsequent instructions without waiting for the previous instruction to complete the write operation of the single-bit register, avoiding the instruction execution delay under the write-after-read condition, reducing the dependence on the single-bit register, and allowing instructions that were originally executed serially due to dependencies to be processed in parallel, thereby improving the parallelism of instruction execution, improving processor performance and instruction execution efficiency, and without adding too much new calculation logic, and will not increase hardware resource costs such as transistor area.

[0105] Figure 5 This is a schematic diagram of another method for executing a computation instruction according to an embodiment of the present disclosure. This embodiment of the present disclosure is applicable to situations where a computation instruction is executed when a read-after-write condition is met. This method can be performed by a computation instruction execution device, which can be implemented in hardware and generally configured in a general-purpose register. Specifically, a general-purpose register can be understood as a component used to temporarily store data and operands to support operations such as arithmetic operations, logical operations, and data movement. For example, it stores the calculation results of an arithmetic logic unit.

[0106] Correspondingly, such as Figure 5 As shown, the method may specifically include:

[0107] S510 , receiving two calculation results obtained by the arithmetic logic unit for two target transmission instructions of the same target calculation instruction.

[0108] The general register is the destination register in the target calculation instruction, and the source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register.

[0109] S520 . Select a correct calculation result from the two calculation results according to the current bit value of the target single-bit register.

[0110] In an embodiment of the present invention, in a target computation instruction, a general register is designated as a destination register for writing the final computation result. The arithmetic logic unit performs computations on two target issue instructions for the same target computation instruction, obtaining two computation results. These two results are calculated based on the two possible values ​​(e.g., 0 and 1) of the source register in the target computation instruction, i.e., the target single-bit register.

[0111] Specifically, a general register receives two calculation results obtained by the arithmetic logic unit for two target-issued instructions for the same target calculation instruction. Based on the current bit value of the target single-bit register (e.g., 0 or 1), the general register selects the correct result from the two calculation results and writes it. If the current value of the target single-bit register is 0, the result calculated based on 0 is selected and written; if it is 1, the other result calculated based on 1 is selected and written.

[0112] Based on this, the technical solution of the embodiment of the present disclosure obtains two calculation results by receiving the two target emission instructions for the same target calculation instruction by the arithmetic logic unit; and selects the correct calculation result from the two calculation results according to the current bit value of the target single-bit register. The general register receives the two calculation results obtained by the arithmetic logic unit based on the two possible bit values ​​of the target single-bit register, and selects the correct calculation result from the two calculation results and writes it into the general register according to the current bit value of the target single-bit register. This can ensure the accuracy of the data result, avoid the instruction execution delay caused by waiting for the register write to be completed, reduce the dependence on the single-bit register, and enable instructions that were originally executed serially due to the dependency relationship to be processed in parallel, thereby improving the parallelism of instruction execution, improving processor performance and instruction execution efficiency, and without adding too much new calculation logic, and will not increase the hardware resource cost such as transistor area.

[0113] Figure 6is a schematic diagram of another method for executing a calculation instruction provided according to an embodiment of the present disclosure. This embodiment refines the "selecting a correct calculation result from the two calculation results based on the current bit value of the target single-bit register" in the above embodiment, and specifically may include: extracting a first identification bit from the first of the two calculation results, and extracting a second identification bit from the second of the two calculation results; wherein the two target transmit instructions include a first target transmit instruction and a second target transmit instruction; the first identification bit is extracted by the arithmetic logic unit from the first target transmit instruction and added to the first calculation result, and the second identification bit is extracted by the arithmetic logic unit from the second target transmit instruction and added to the second calculation result; the first identification bit is used to identify a bit value of the target single-bit register used in the first target transmit instruction, and the second identification bit is used to identify another bit value of the target single-bit register used in the second target transmit instruction; if it is determined that the first identification bit matches the current bit value of the target single-bit register, then the first calculation result is selected for data writing; if it is determined that the second identification bit matches the current bit value of the target single-bit register, then the second calculation result is selected for data writing.

[0114] Correspondingly, such as Figure 6 As shown, the method may specifically include:

[0115] S610 , receiving two calculation results obtained by the arithmetic logic unit for two target transmission instructions of the same target calculation instruction.

[0116] The general register is the destination register in the target calculation instruction, and the source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register.

[0117] S620: Extract a first flag from a first calculation result of the two calculation results, and extract a second flag from a second calculation result of the two calculation results.

[0118] Among them, the two target launch instructions include a first target launch instruction and a second target launch instruction; the first identification bit is extracted by the arithmetic logic unit from the first target launch instruction and added to the first calculation result, and the second identification bit is extracted by the arithmetic logic unit from the second target launch instruction and added to the second calculation result; the first identification bit is used to identify a bit value of the target single-bit register used in the first target launch instruction, and the second identification bit is used to identify another bit value of the target single-bit register used in the second target launch instruction.

[0119] S630: If it is determined that the first flag matches the current bit value of the target single-bit register, select the first calculation result for data writing.

[0120] S640: If it is determined that the second flag matches the current bit value of the target single-bit register, select the second calculation result for data writing.

[0121] Specifically, each of the two calculation results received by the general register includes, in addition to the actual calculation result, an identification bit for indicating the target single-bit register value used in the calculation process. The first calculation result includes a first identification bit, and the second calculation result includes a second identification bit. The general register checks which of the two identification bits matches the actual current value of the target single-bit register. If it is determined that the first identification bit matches the current bit value of the target single-bit register, the first calculation result is selected for data writing. Correspondingly, if it is determined that the second identification bit matches the current bit value of the target single-bit register, the second calculation result is selected for data writing.

[0122] Based on this, the technical solution of the embodiment of the present disclosure is to receive two calculation results obtained by the arithmetic logic unit for two target emission instructions for the same target calculation instruction; extract the first flag bit from the first calculation result of the two calculation results, and extract the second flag bit from the second calculation result of the two calculation results; if it is determined that the first flag bit matches the current bit value of the target single-bit register, the first calculation result is selected for data writing; if it is determined that the second flag bit matches the current bit value of the target single-bit register, the second calculation result is selected for data writing. The general register receives the arithmetic logic unit to calculate two calculation results based on the two possible bit values ​​of the target single-bit register, extract the flag bit from each of the two calculation results, and select the correct calculation result to write to the destination register based on the matching between the flag bit and the current bit value of the target single-bit register. This can ensure the accuracy of the data result, avoid the instruction execution delay caused by waiting for the register write to be completed, reduce the dependence on the single-bit register, enable instructions that were originally executed serially due to the dependency to be processed in parallel, improve the parallelism of instruction execution, improve processor performance and instruction execution efficiency, and do not add too much new calculation logic, and will not increase hardware resource costs such as transistor area.

[0123] Furthermore, based on the above embodiments, after selecting a correct calculation result from the two calculation results according to the current bit value of the target single-bit register, the method may further include:

[0124] The dependent state of the destination register in the scoreboard module is canceled.

[0125] Specifically, during the execution of an instruction, the destination register is in a dependent state before a new value is written to it, that is, if other subsequent instructions need to read the value of the register, they need to wait for the current instruction to complete the write operation. After the correct calculation result is selected and written into the destination register, the dependent state of the register needs to be canceled. By canceling the dependent state of the destination register in the scoreboard module, the scoreboard module indicates to other components of the processor that the data of the register has been updated and can be used for subsequent instructions. By updating the scoreboard module after selecting the correct calculation result and writing it into the destination register, and canceling the dependent state of the register, it is ensured that subsequent instructions can access the latest data in a timely manner, thereby improving the execution efficiency of the processor.

[0126] As an implementation of the above-mentioned execution method of each computing instruction executed by the instruction buffer, the present disclosure also provides an optional embodiment of an execution device for implementing the above-mentioned execution method of each computing instruction executed by the instruction buffer.

[0127] Figure 7is a schematic diagram of a device for executing a computing instruction according to an embodiment of the present disclosure, such as Figure 7 As shown, the apparatus includes: an instruction acquisition module 710, an instruction construction module 720 and an instruction transmission module 730, wherein:

[0128] An instruction acquisition module 710 is used to acquire a target computing instruction to be executed;

[0129] an instruction construction module 720 for constructing two target transmit instructions in succession according to a current bit value in the target single-bit register when the target computation instruction satisfies a read-after-write condition for the target single-bit register;

[0130] Wherein, the two target transmission instructions respectively include a current bit value and a negated value of the current bit value;

[0131] The instruction transmitting module 730 is used to transmit the two target transmitting instructions to the arithmetic logic unit respectively to perform calculations and obtain two calculation results, so that the destination register in the target calculation instruction can select the correct calculation result from the two calculation results to complete the data writing operation.

[0132] Based on this, the technical solution of the embodiment of the present disclosure obtains the target calculation instruction to be executed; when the target calculation instruction meets the write-after-read condition for the target single-bit register, two target emission instructions are continuously constructed according to the current bit value in the target single-bit register; the two target emission instructions are respectively emitted to the arithmetic logic unit to perform calculations, and two calculation results are obtained, so that the destination register in the target calculation instruction can select the correct calculation result from the two calculation results to complete the data writing operation. When the write-after-read condition is met, two target emission instructions are constructed according to the current value of the target single-bit register, and are emitted to the arithmetic logic unit for calculation, and the correct result is selected by the destination register to be written, thereby avoiding the instruction execution delay caused by waiting for the register write to be completed, reducing the dependence on the single-bit register, and enabling instructions that were originally executed serially due to the dependency relationship to be processed in parallel, thereby improving the parallelism of instruction execution, improving processor performance and instruction execution efficiency, and without adding too much new calculation logic, and will not increase hardware resource costs such as transistor area.

[0133] Based on the above embodiments, the instruction construction module 720 is specifically configured to:

[0134] Identifying a source register and a destination register in the target computing instruction, and detecting dependency states of the source register and the destination register in real time;

[0135] When the source registers include a target single-bit register and it is detected in real time that only the target single-bit register is in a dependent state, it is determined that the target computing instruction satisfies a write-after-read condition for the target single-bit register.

[0136] Based on the above embodiments, the instruction construction module 720 is further configured to:

[0137] The dependent registers set in the scoreboard module are detected in real time to obtain the dependent states of the source register and the destination register.

[0138] Based on the above embodiments, the instruction construction module 720 is further configured to:

[0139] Obtaining a current bit value from the target single-bit register and obtaining other operands from at least one general register included in the target computation instruction;

[0140] A first target issue instruction is constructed according to the current bit value and the other operands, and a second target issue instruction is constructed according to the inverted value of the current bit value and the other operands.

[0141] Based on the above embodiments, the instruction construction module 720 is further configured to:

[0142] In the first target transmit instruction, a first flag bit that matches the current bit value is added, and in the second target transmit instruction, a second flag bit that matches the inverse value of the current bit value is added;

[0143] When the arithmetic logic unit obtains a first calculation result by issuing an instruction for the first target, the arithmetic logic unit adds the first identification bit to the first calculation result; when the arithmetic logic unit obtains a second calculation result by issuing an instruction for the second target, the arithmetic logic unit adds the second identification bit to the second calculation result;

[0144] The first flag bit and the second flag bit are used for the destination register to select a correct calculation result from the first calculation result and the second calculation result.

[0145] Based on the above embodiments, the instruction transmitting module 730 is specifically configured to:

[0146] Setting the dependent state of the destination register in the scoreboard module;

[0147] The two target issuance instructions are issued sequentially to the arithmetic logic unit for calculation.

[0148] The above-mentioned product can execute the method provided by the instruction buffer in any embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method.

[0149] As an implementation of the above-mentioned execution method of each calculation instruction executed by the arithmetic logic unit, the present disclosure also provides an optional embodiment of an execution device for implementing the above-mentioned execution method of each calculation instruction executed by the arithmetic logic unit.

[0150] Figure 8 is a schematic diagram of another device for executing a computing instruction according to an embodiment of the present disclosure, such as Figure 8 As shown, the apparatus includes: an instruction receiving module 810 and a calculation module 820, wherein:

[0151] An instruction receiving module 810 is configured to receive two target transmit instructions sent by an instruction buffer for the same target compute instruction;

[0152] The source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register;

[0153] The calculation module 820 is used to perform calculations on the two target transmit instructions respectively to obtain two calculation results, so that the destination register in the target calculation instruction can select the correct calculation result from the two calculation results to complete the data writing operation.

[0154] Based on this, the technical solution of the embodiment of the present disclosure receives two target emission instructions sent by the instruction buffer for the same target calculation instruction; performs calculations on the two target emission instructions respectively to obtain two calculation results, so that the destination register in the target calculation instruction can select the correct calculation result from the two calculation results to complete the data write operation. The arithmetic logic unit performs calculations on the two received target emission instructions respectively to obtain two calculation results, and the destination register selects the correct result to complete the data write operation. The processor can continue to execute subsequent instructions without waiting for the previous instruction to complete the write operation, avoiding the instruction execution delay under the write-after-read condition, reducing the dependence on single-bit registers, and enabling instructions that were originally executed serially due to dependencies to be processed in parallel, thereby improving the parallelism of instruction execution, improving processor performance and instruction execution efficiency, and without adding too much new calculation logic, and will not increase hardware resource costs such as transistor area.

[0155] Based on the above embodiments, the calculation module 820 is specifically configured to:

[0156] Performing calculation on a first target launch instruction of the two target launch instructions to obtain a first calculation result, and performing calculation on a second target launch instruction of the two target launch instructions to obtain a second calculation result;

[0157] Extracting a first identification bit from the first target launch instruction, and adding the first identification bit to the first calculation result;

[0158] Extracting a second flag from the second target launch instruction, and adding the second flag to the second calculation result;

[0159] The first identification bit is used to identify a bit value of the target single-bit register used in the first target emission instruction, and the second identification bit is used to identify another bit value of the target single-bit register used in the second target emission instruction.

[0160] The above-mentioned product can execute the method performed by the arithmetic logic unit provided in any embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method.

[0161] As an implementation of the above-mentioned execution method of each computing instruction executed by a general register, the present disclosure also provides an optional embodiment of an execution device for implementing the above-mentioned execution method of each computing instruction executed by a general register.

[0162] Figure 9 is a schematic diagram of another device for executing a computing instruction according to an embodiment of the present disclosure, such as Figure 9 As shown, the apparatus includes: a result receiving module 910 and a result selecting module 920, wherein:

[0163] A result receiving module 910 is configured to receive two calculation results obtained by the arithmetic logic unit for two target emission instructions for the same target calculation instruction;

[0164] The general register is a destination register in the target calculation instruction, and the source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register;

[0165] The result selection module 920 is configured to select a correct calculation result from the two calculation results according to the current bit value of the target single-bit register.

[0166] Based on this, the technical solution of the embodiment of the present disclosure obtains two calculation results by receiving the two target emission instructions for the same target calculation instruction by the arithmetic logic unit; and selects the correct calculation result from the two calculation results according to the current bit value of the target single-bit register. The general register receives the two calculation results obtained by the arithmetic logic unit based on the two possible bit values ​​of the target single-bit register, and selects the correct calculation result from the two calculation results and writes it into the general register according to the current bit value of the target single-bit register. This can ensure the accuracy of the data result, avoid the instruction execution delay caused by waiting for the register write to be completed, reduce the dependence on the single-bit register, and enable instructions that were originally executed serially due to the dependency relationship to be processed in parallel, thereby improving the parallelism of instruction execution, improving processor performance and instruction execution efficiency, and without adding too much new calculation logic, and will not increase the hardware resource cost such as transistor area.

[0167] Based on the above embodiments, the result selection module 920 is specifically configured to:

[0168] Extracting a first flag bit from a first calculation result of the two calculation results, and extracting a second flag bit from a second calculation result of the two calculation results;

[0169] The two target launch instructions include a first target launch instruction and a second target launch instruction; the first identification bit is extracted by the arithmetic logic unit from the first target launch instruction and added to the first calculation result, and the second identification bit is extracted by the arithmetic logic unit from the second target launch instruction and added to the second calculation result; the first identification bit is used to identify a bit value of the target single-bit register used in the first target launch instruction, and the second identification bit is used to identify another bit value of the target single-bit register used in the second target launch instruction;

[0170] If it is determined that the first flag bit matches the current bit value of the target single-bit register, selecting the first calculation result for data writing;

[0171] If it is determined that the second flag bit matches the current bit value of the target single-bit register, the second calculation result is selected for data writing.

[0172] Furthermore, based on the above embodiments, the computing instruction execution device may further include a dependency cancellation module, wherein:

[0173] The dependency cancellation module is configured to cancel the dependent state of the destination register in the scoreboard module after a correct calculation result is selected from the two calculation results according to the current bit value of the target single-bit register.

[0174] The above-mentioned product can execute the method provided by any embodiment of the present disclosure and executed by a general register, and has the corresponding functional modules and beneficial effects of the execution method.

[0175] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0176] Figure 10 is a schematic diagram of an instruction execution hardware provided according to an embodiment of the present disclosure, such as Figure 10 As shown, the instruction execution hardware includes an instruction buffer 1010, a general register 1020, a single-bit register 1030, a scoreboard module 1040, and an arithmetic logic unit 1050, wherein:

[0177] The instruction buffer 1010 is used to execute the method for executing a computing instruction executed by the instruction buffer according to any one of the embodiments of the present disclosure;

[0178] The general register 1020 is used to store operands and execute the execution method of the computing instruction executed by the general register according to any one of the embodiments of the present disclosure;

[0179] The single-bit register 1030 is used to store a single-bit value;

[0180] The scoreboard module 1040 is used to set whether the general register 1020 and the single-bit register 1030 are in a dependent state;

[0181] The arithmetic logic unit 1050 is used to execute the execution method of the calculation instruction executed by the arithmetic logic unit as described in any one of the embodiments of the present disclosure.

[0182] Generally speaking, the instruction execution hardware is part of the processor, and the instruction buffer stores all instructions to be issued. When all instructions are issued, they will check the scoreboard module to check whether there is a register in the current instruction that is in a dependent state. If so, they cannot be issued. If no register in the current instruction is in a dependent state, the data of the relevant register in the current instruction can be obtained and the instruction can be issued to the arithmetic logic unit. When issuing, the corresponding register in the scoreboard module will be set, indicating that the current register dependency has not been released. After the instruction issued to the arithmetic logic unit is completed, the scoreboard module will be modified to release the corresponding register dependency, and the calculation result of the instruction will also be written to the general register.

[0183] For instructions that use a single-bit register as a source register, the instruction buffer performs a scoreboard module check when selecting an instruction to be emitted. If the current instruction has only a dependency on the single-bit register that has not been released, the emission will not be paused. Instead, two target emission instructions will be continuously constructed and marked for emission respectively. After obtaining the values ​​of other source operands, the value of the original single-bit register will be used to mark the instruction during the first emission; during the second emission, the value in the original single-bit register will be inverted to mark the instruction.

[0184] Since the current arithmetic logic unit is a fixed-length pipeline, the value of the corresponding single-bit register must have been updated when the marked instruction is written back. When the marked and repeatedly issued instruction is completed in the arithmetic logic unit and the scoreboard module needs to be modified and the general register needs to be updated, it is first necessary to detect whether the value of the single-bit register remains unchanged or is inverted. If it remains unchanged, the calculation result based on the first issued instruction is correct. At this time, the scoreboard module can be updated and the corresponding general register can be updated, and the calculation result based on the second issued instruction can be ignored; if the true value of the single-bit register is inverted, then the calculation result based on the first issued instruction is ignored, and the scoreboard module and the corresponding general register are updated using the calculation result based on the second issued instruction.

[0185] In a specific example, for the instructions in the instruction buffer, assume that the value of the single-bit register is 0 initially, and the instruction sequence is: I0: add the values ​​in the r1 and r0 registers, and then store the result in the r2 register, and update the single-bit register according to the operation result; I1: add the value in the r1 register and the value in the single-bit register, and then store the result in the r3 register.

[0186] Before issuing the I0 instruction, the instruction checks whether there are any dependencies between the r0, r1, and r2 registers in the scoreboard module and the single-bit registers. If not, the instruction can be issued from the instruction buffer. During issuance, the states of the single-bit register and the r2 register in the scoreboard module are modified to indicate that the current registers have not been written back and a dependency exists. Before issuing the I1 instruction, since the current instruction requires a single-bit register as a source operand, the present disclosure only needs to check whether there are any dependencies between the r1 and r3 registers in the scoreboard module, without checking the dependency between the single-bit registers. After detecting that there are no dependencies between the r1 and r3 registers, the instruction is repeatedly issued twice. During the first issuance, the state of the r3 register in the scoreboard module is modified to indicate that the current register has not been written back and a dependency exists. The values ​​of the r1 register and the single-bit register are obtained, and the original value of the current single-bit register is used to mark the instruction issued for the first time. During the second issuance, the scoreboard module is not updated, and the value of the r1 register and the inverted value of the original single-bit register are obtained, and the inverted value is used to mark the instruction issued for the second time.

[0187] Since the current arithmetic logic unit is a fixed-length pipeline, the I0 instruction must have been completed when the I1 instruction is written back. Since the I1 instruction is repeatedly issued twice, the write back of the I1 instruction will also occur twice. During the first write back, it will be checked whether the value of the current single-bit register is the same as the source operand used when the current instruction is executed. If they are the same, the current instruction can update the scoreboard module to release the dependency state and update the value of the first write back to the general register r3. Otherwise, the write back of the current instruction will be ignored and the second instruction will be used to update the scoreboard module to release the dependency state, and the value of the second write back will be updated to the general register r3.

[0188] Specifically, single-bit registers in the instruction execution hardware store single-bit values ​​for state management. The scoreboard module manages register dependencies to avoid conflicting operations and ensure data consistency. The instruction buffer receives instructions and, in conjunction with the scoreboard module, determines whether a write-after-read condition exists. The corresponding execution flow is optimized, and two target-issued instructions are sequentially constructed and sent to the arithmetic logic unit for computation. The arithmetic logic unit then computes the two target-issued instructions, generating two calculation results. The general register receives two calculation results obtained by the arithmetic logic unit for two target emission instructions for the same target calculation instruction, and selects the correct calculation result from the two calculation results according to the current bit value of the target single-bit register. When the write-after-read condition is met, two target emission instructions are constructed according to the current value of the target single-bit register, and are emitted to the arithmetic logic unit for calculation. The correct result is selected by the destination register for writing, avoiding the instruction execution delay caused by waiting for the register write to be completed, reducing the dependence on the single-bit register, and enabling instructions that were originally executed serially due to the dependency to be processed in parallel, thereby improving the parallelism of instruction execution, improving processor performance and instruction execution efficiency, and without adding too much new calculation logic, and will not increase hardware resource costs such as transistor area.

[0189] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0190] Figure 11 A schematic block diagram of an example electronic device that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0191] like Figure 11 As shown, the electronic device includes the instruction execution hardware 1110 described in any one of the embodiments of the present disclosure. The instruction execution hardware 1110 performs the various methods and processes described above, such as the execution method of the computing instructions executed by the instruction buffer, that is:

[0192] Obtain target computing instructions to be executed;

[0193] When the target computation instruction satisfies a read-after-write condition for a target single-bit register, constructing two target emission instructions consecutively according to a current bit value in the target single-bit register;

[0194] Wherein, the two target transmission instructions respectively include a current bit value and a negated value of the current bit value;

[0195] The two target issuance instructions are respectively issued to the arithmetic logic unit to perform calculations, and two calculation results are obtained, so that the destination register in the target calculation instruction selects a correct calculation result from the two calculation results to complete the data writing operation.

[0196] Another example is the execution method of the calculation instruction executed by the arithmetic logic unit, that is:

[0197] receiving two target-issue instructions from an instruction buffer for the same target-compute instruction;

[0198] The source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register;

[0199] Calculation is performed on the two target emission instructions respectively to obtain two calculation results, so that the destination register in the target calculation instruction selects a correct calculation result from the two calculation results to complete the data writing operation.

[0200] Another example is the execution method of a calculation instruction executed by a general register, that is:

[0201] receiving two calculation results obtained by the arithmetic logic unit from two target transmission instructions for the same target calculation instruction;

[0202] The general register is a destination register in the target calculation instruction, and the source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register;

[0203] A correct calculation result is selected from the two calculation results according to the current bit value of the target single-bit register.

[0204] For example, in some embodiments, the execution method of the computing instruction can be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit. In some embodiments, part or all of the computer program can be loaded and / or installed on the device via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by the computing unit, one or more steps of the execution method of the computing instruction described above can be performed. Alternatively, in other embodiments, the computing unit can be configured to execute the execution method of the computing instruction by any other appropriate means (e.g., by means of firmware).

[0205] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0206] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0207] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can include or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0208] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0209] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0210] A computer system may include a client and a server. The client and server are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services. The server may also be a server in a distributed system or a server integrated with blockchain.

[0211] Artificial intelligence (AI) is the study of how computers can simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, specialized AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily encompass computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graphs.

[0212] Cloud computing refers to a technology system that provides network access to elastically scalable shared pools of physical or virtual resources. These resources can include servers, operating systems, networks, software, applications, and storage devices, and can be deployed and managed on-demand in a self-service manner. Cloud computing technology provides efficient and powerful data processing capabilities for the application of technologies such as artificial intelligence and blockchain, as well as for model training.

[0213] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions provided by this disclosure can be achieved. This is not limited herein.

[0214] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A method for executing a computing instruction, executed by an instruction buffer, the method comprising: Obtain target computing instructions to be executed; When the target computation instruction satisfies a read-after-write condition for a target single-bit register, constructing two target emission instructions consecutively according to a current bit value in the target single-bit register; Wherein, the two target transmission instructions respectively include a current bit value and a negated value of the current bit value; The two target issuance instructions are respectively issued to the arithmetic logic unit to perform calculations, and two calculation results are obtained, so that the destination register in the target calculation instruction selects a correct calculation result from the two calculation results to complete the data writing operation.

2. The method according to claim 1, wherein The target computing instruction satisfies a read-after-write condition for a target single-bit register, including: Identifying a source register and a destination register in the target computing instruction, and detecting dependency states of the source register and the destination register in real time; When the source registers include a target single-bit register and it is detected in real time that only the target single-bit register is in a dependent state, it is determined that the target computing instruction satisfies a write-after-read condition for the target single-bit register.

3. The method according to claim 2, wherein: The real-time detection of the dependency status of the source register and the destination register includes: The dependent registers set in the scoreboard module are detected in real time to obtain the dependent states of the source register and the destination register.

4. The method according to claim 1, wherein The continuously constructing two target transmit instructions according to the current bit value in the target single-bit register includes: Obtaining a current bit value from the target single-bit register and obtaining other operands from at least one general register included in the target computation instruction; A first target issue instruction is constructed according to the current bit value and the other operands, and a second target issue instruction is constructed according to the inverted value of the current bit value and the other operands.

5. The method according to claim 4, wherein The constructing a first target emission instruction according to the current bit value and the other operands, and constructing a second target emission instruction according to the inverted value of the current bit value and the other operands, further includes: In the first target transmit instruction, a first flag bit that matches the current bit value is added, and in the second target transmit instruction, a second flag bit that matches the inverse value of the current bit value is added; When the arithmetic logic unit obtains a first calculation result by issuing an instruction for the first target, the arithmetic logic unit adds the first identification bit to the first calculation result; when the arithmetic logic unit obtains a second calculation result by issuing an instruction for the second target, the arithmetic logic unit adds the second identification bit to the second calculation result; The first flag bit and the second flag bit are used for the destination register to select a correct calculation result from the first calculation result and the second calculation result.

6. The method according to claim 1, wherein The step of transmitting the two target transmit instructions to the arithmetic logic unit to perform calculations further includes: Setting the dependent state of the destination register in the scoreboard module; The two target issuance instructions are issued sequentially to the arithmetic logic unit for calculation.

7. A method for executing a calculation instruction, executed by an arithmetic logic unit, the method comprising: receiving two target-issue instructions from an instruction buffer for the same target-compute instruction; The source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register; Calculation is performed on the two target emission instructions respectively to obtain two calculation results, so that the destination register in the target calculation instruction selects a correct calculation result from the two calculation results to complete the data writing operation.

8. The method according to claim 7, wherein: Calculate the two target launch instructions respectively and obtain two calculation results, including: Performing calculation on a first target launch instruction of the two target launch instructions to obtain a first calculation result, and performing calculation on a second target launch instruction of the two target launch instructions to obtain a second calculation result; Extracting a first identification bit from the first target launch instruction, and adding the first identification bit to the first calculation result; Extracting a second flag from the second target launch instruction, and adding the second flag to the second calculation result; The first identification bit is used to identify a bit value of the target single-bit register used in the first target emission instruction, and the second identification bit is used to identify another bit value of the target single-bit register used in the second target emission instruction.

9. A method for executing a computing instruction using a general register, the method comprising: receiving two calculation results obtained by the arithmetic logic unit from two target transmission instructions for the same target calculation instruction; The general register is a destination register in the target calculation instruction, and the source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register; A correct calculation result is selected from the two calculation results according to the current bit value of the target single-bit register.

10. The method according to claim 9, wherein: The selecting a correct calculation result from the two calculation results according to the current bit value of the target single-bit register includes: Extracting a first flag bit from a first calculation result of the two calculation results, and extracting a second flag bit from a second calculation result of the two calculation results; The two target launch instructions include a first target launch instruction and a second target launch instruction; the first identification bit is extracted by the arithmetic logic unit from the first target launch instruction and added to the first calculation result, and the second identification bit is extracted by the arithmetic logic unit from the second target launch instruction and added to the second calculation result; the first identification bit is used to identify a bit value of the target single-bit register used in the first target launch instruction, and the second identification bit is used to identify another bit value of the target single-bit register used in the second target launch instruction; If it is determined that the first flag bit matches the current bit value of the target single-bit register, selecting the first calculation result for data writing; If it is determined that the second flag bit matches the current bit value of the target single-bit register, the second calculation result is selected for data writing.

11. The method according to claim 9, wherein After selecting a correct calculation result from the two calculation results according to the current bit value of the target single-bit register, the method further includes: The dependent state of the destination register in the scoreboard module is canceled.

12. A device for executing a computing instruction, configured in an instruction buffer, the device comprising: An instruction acquisition module, used to acquire target computing instructions to be executed; an instruction construction module, configured to construct two target transmit instructions successively according to a current bit value in the target single-bit register when the target computation instruction satisfies a read-after-write condition for the target single-bit register; Wherein, the two target transmission instructions respectively include a current bit value and a negated value of the current bit value; The instruction emission module is used to emit the two target emission instructions to the arithmetic logic unit respectively to perform calculations and obtain two calculation results, so that the destination register in the target calculation instruction can select the correct calculation result from the two calculation results to complete the data writing operation.

13. A device for executing a computation instruction, configured in an arithmetic logic unit, comprising: An instruction receiving module, configured to receive two target emission instructions sent by an instruction buffer for the same target computing instruction; The source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register; The calculation module is used to respectively perform calculations on two target emission instructions to obtain two calculation results, so that the destination register in the target calculation instruction can select a correct calculation result from the two calculation results to complete the data writing operation.

14. A device for executing a computing instruction, configured in a general register, comprising: A result receiving module is used to receive two calculation results obtained by the arithmetic logic unit for two target emission instructions of the same target calculation instruction; The general register is a destination register in the target calculation instruction, and the source register in the target calculation instruction includes a target single-bit register; the two calculation results are respectively calculated using two bit values ​​that can be used by the target single-bit register; The result selection module is used to select a correct calculation result from the two calculation results according to the current bit value of the target single-bit register.

15. An instruction execution hardware comprising an instruction buffer, a general register, a single-bit register, a scoreboard module, and an arithmetic logic unit, wherein: The instruction buffer is used to execute the method according to any one of claims 1 to 6; The general register is used to store operands and execute the method according to any one of claims 9 to 11; The single-bit register is used to store a single-bit value; The scoreboard module is used to set whether the general register and the single-bit register are in a dependent state; The arithmetic logic unit is used to execute the method according to any one of claims 7 to 8.

16. An electronic device comprising the instruction execution hardware according to claim 15.

17. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to enable a computer to execute the method according to any one of claims 1-11.

18. A computer program product comprising computer instructions, wherein when the computer instructions are executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

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